1 2019-10-04 Jan Beulich <jbeulich@suse.com>
4 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
6 * i386-tbl.h: Re-generate.
8 2019-09-30 Phil Blundell <pb@pbcl.net>
11 * configure, Makefile.in, po/opcodes.pot: Regenerate.
13 2019-09-16 Phil Blundell <pb@pbcl.net>
15 * configure: Regenerated.
17 2019-09-09 Phil Blundell <pb@pbcl.net>
19 binutils 2.33 branch created.
21 2019-09-03 Nick Clifton <nickc@redhat.com>
24 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
25 greater than zero before indexing via (bufcnt -1).
27 2019-09-03 Nick Clifton <nickc@redhat.com>
30 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
31 (MAX_SPEC_REG_NAME_LEN): Define.
32 (struct mmix_dis_info): Use defined constants for array lengths.
33 (get_reg_name): New function.
34 (get_sprec_reg_name): New function.
35 (print_insn_mmix): Use new functions.
37 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
39 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
40 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
41 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
43 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
45 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
46 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
47 (aarch64_sys_reg_supported_p): Update checks for the above.
49 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
51 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
52 cases MVE_SQRSHRL and MVE_UQRSHLL.
53 (print_insn_mve): Add case for specifier 'k' to check
54 specific bit of the instruction.
56 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
59 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
60 encountering an unknown machine type.
61 (print_insn_arc): Handle arc_insn_length returning 0. In error
62 cases return -1 rather than calling abort.
64 2019-08-07 Jan Beulich <jbeulich@suse.com>
66 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
67 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
69 * i386-tbl.h: Re-generate.
71 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
73 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
76 2019-07-30 Mel Chen <mel.chen@sifive.com>
78 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
79 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
81 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
84 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
86 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
87 and MPY class instructions.
88 (parse_option): Add nps400 option.
89 (print_arc_disassembler_options): Add nps400 info.
91 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
93 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
96 * arc-opc.c (RAD_CHK): Add.
97 * arc-tbl.h: Regenerate.
99 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
101 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
102 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
104 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
106 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
107 instructions as UNPREDICTABLE.
109 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
111 * bpf-desc.c: Regenerated.
113 2019-07-17 Jan Beulich <jbeulich@suse.com>
115 * i386-gen.c (static_assert): Define.
117 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
118 (Opcode_Modifier_Num): ... this.
121 2019-07-16 Jan Beulich <jbeulich@suse.com>
123 * i386-gen.c (operand_types): Move RegMem ...
124 (opcode_modifiers): ... here.
125 * i386-opc.h (RegMem): Move to opcode modifer enum.
126 (union i386_operand_type): Move regmem field ...
127 (struct i386_opcode_modifier): ... here.
128 * i386-opc.tbl (RegMem): Define.
129 (mov, movq): Move RegMem on segment, control, debug, and test
131 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
132 to non-SSE2AVX flavor.
133 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
134 Move RegMem on register only flavors. Drop IgnoreSize from
135 legacy encoding flavors.
136 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
138 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
139 register only flavors.
140 (vmovd): Move RegMem and drop IgnoreSize on register only
141 flavor. Change opcode and operand order to store form.
142 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
144 2019-07-16 Jan Beulich <jbeulich@suse.com>
146 * i386-gen.c (operand_type_init, operand_types): Replace SReg
148 * i386-opc.h (SReg2, SReg3): Replace by ...
150 (union i386_operand_type): Replace sreg fields.
151 * i386-opc.tbl (mov, ): Use SReg.
152 (push, pop): Likewies. Drop i386 and x86-64 specific segment
154 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
155 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
157 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
159 * bpf-desc.c: Regenerate.
160 * bpf-opc.c: Likewise.
161 * bpf-opc.h: Likewise.
163 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
165 * bpf-desc.c: Regenerate.
166 * bpf-opc.c: Likewise.
168 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
170 * arm-dis.c (print_insn_coprocessor): Rename index to
173 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
175 * riscv-opc.c (riscv_insn_types): Add r4 type.
177 * riscv-opc.c (riscv_insn_types): Add b and j type.
179 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
180 format for sb type and correct s type.
182 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
184 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
185 SVE FMOV alias of FCPY.
187 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
189 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
190 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
192 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
194 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
195 registers in an instruction prefixed by MOVPRFX.
197 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
199 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
200 sve_size_13 icode to account for variant behaviour of
202 * aarch64-dis-2.c: Regenerate.
203 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
204 sve_size_13 icode to account for variant behaviour of
206 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
207 (OP_SVE_VVV_Q_D): Add new qualifier.
208 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
209 (struct aarch64_opcode): Split pmull{t,b} into those requiring
212 2019-07-01 Jan Beulich <jbeulich@suse.com>
214 * opcodes/i386-gen.c (operand_type_init): Remove
215 OPERAND_TYPE_VEC_IMM4 entry.
216 (operand_types): Remove Vec_Imm4.
217 * opcodes/i386-opc.h (Vec_Imm4): Delete.
218 (union i386_operand_type): Remove vec_imm4.
219 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
220 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
222 2019-07-01 Jan Beulich <jbeulich@suse.com>
224 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
225 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
226 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
227 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
228 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
229 monitorx, mwaitx): Drop ImmExt from operand-less forms.
230 * i386-tbl.h: Re-generate.
232 2019-07-01 Jan Beulich <jbeulich@suse.com>
234 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
236 * i386-tbl.h: Re-generate.
238 2019-07-01 Jan Beulich <jbeulich@suse.com>
240 * i386-opc.tbl (C): New.
241 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
242 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
243 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
244 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
245 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
246 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
247 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
248 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
249 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
250 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
251 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
252 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
253 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
254 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
255 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
256 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
257 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
258 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
259 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
260 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
261 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
262 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
263 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
264 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
265 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
266 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
268 * i386-tbl.h: Re-generate.
270 2019-07-01 Jan Beulich <jbeulich@suse.com>
272 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
274 * i386-tbl.h: Re-generate.
276 2019-07-01 Jan Beulich <jbeulich@suse.com>
278 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
279 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
280 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
281 * i386-tbl.h: Re-generate.
283 2019-07-01 Jan Beulich <jbeulich@suse.com>
285 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
286 Disp8MemShift from register only templates.
287 * i386-tbl.h: Re-generate.
289 2019-07-01 Jan Beulich <jbeulich@suse.com>
291 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
292 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
293 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
294 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
295 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
296 EVEX_W_0F11_P_3_M_1): Delete.
297 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
298 EVEX_W_0F11_P_3): New.
299 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
300 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
301 MOD_EVEX_0F11_PREFIX_3 table entries.
302 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
303 PREFIX_EVEX_0F11 table entries.
304 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
305 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
306 EVEX_W_0F11_P_3_M_{0,1} table entries.
308 2019-07-01 Jan Beulich <jbeulich@suse.com>
310 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
313 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
316 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
317 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
318 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
319 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
320 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
321 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
322 EVEX_LEN_0F38C7_R_6_P_2_W_1.
323 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
324 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
325 PREFIX_EVEX_0F38C6_REG_6 entries.
326 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
327 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
328 EVEX_W_0F38C7_R_6_P_2 entries.
329 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
330 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
331 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
332 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
333 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
334 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
335 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
337 2019-06-27 Jan Beulich <jbeulich@suse.com>
339 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
340 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
341 VEX_LEN_0F2D_P_3): Delete.
342 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
343 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
344 (prefix_table): ... here.
346 2019-06-27 Jan Beulich <jbeulich@suse.com>
348 * i386-dis.c (Iq): Delete.
350 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
352 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
353 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
354 (OP_E_memory): Also honor needindex when deciding whether an
355 address size prefix needs printing.
356 (OP_I): Remove handling of q_mode. Add handling of d_mode.
358 2019-06-26 Jim Wilson <jimw@sifive.com>
361 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
362 Set info->display_endian to info->endian_code.
364 2019-06-25 Jan Beulich <jbeulich@suse.com>
366 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
367 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
368 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
369 OPERAND_TYPE_ACC64 entries.
370 * i386-init.h: Re-generate.
372 2019-06-25 Jan Beulich <jbeulich@suse.com>
374 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
376 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
378 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
380 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
381 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
383 2019-06-25 Jan Beulich <jbeulich@suse.com>
385 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
388 2019-06-25 Jan Beulich <jbeulich@suse.com>
390 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
391 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
393 * i386-opc.tbl (movnti): Add IgnoreSize.
394 * i386-tbl.h: Re-generate.
396 2019-06-25 Jan Beulich <jbeulich@suse.com>
398 * i386-opc.tbl (and): Mark Imm8S form for optimization.
399 * i386-tbl.h: Re-generate.
401 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
403 * i386-dis-evex.h: Break into ...
404 * i386-dis-evex-len.h: New file.
405 * i386-dis-evex-mod.h: Likewise.
406 * i386-dis-evex-prefix.h: Likewise.
407 * i386-dis-evex-reg.h: Likewise.
408 * i386-dis-evex-w.h: Likewise.
409 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
410 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
413 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
416 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
417 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
419 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
420 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
421 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
422 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
423 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
424 EVEX_LEN_0F385B_P_2_W_1.
425 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
426 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
427 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
428 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
429 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
430 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
431 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
432 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
433 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
434 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
436 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
439 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
440 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
441 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
442 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
443 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
444 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
445 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
446 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
447 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
448 EVEX_LEN_0F3A43_P_2_W_1.
449 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
450 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
451 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
452 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
453 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
454 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
455 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
456 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
457 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
458 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
459 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
460 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
462 2019-06-14 Nick Clifton <nickc@redhat.com>
464 * po/fr.po; Updated French translation.
466 2019-06-13 Stafford Horne <shorne@gmail.com>
468 * or1k-asm.c: Regenerated.
469 * or1k-desc.c: Regenerated.
470 * or1k-desc.h: Regenerated.
471 * or1k-dis.c: Regenerated.
472 * or1k-ibld.c: Regenerated.
473 * or1k-opc.c: Regenerated.
474 * or1k-opc.h: Regenerated.
475 * or1k-opinst.c: Regenerated.
477 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
479 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
481 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
484 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
485 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
486 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
487 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
488 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
489 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
490 EVEX_LEN_0F3A1B_P_2_W_1.
491 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
492 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
493 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
494 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
495 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
496 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
497 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
498 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
500 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
503 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
504 EVEX.vvvv when disassembling VEX and EVEX instructions.
505 (OP_VEX): Set vex.register_specifier to 0 after readding
506 vex.register_specifier.
507 (OP_Vex_2src_1): Likewise.
508 (OP_Vex_2src_2): Likewise.
509 (OP_LWP_E): Likewise.
510 (OP_EX_Vex): Don't check vex.register_specifier.
511 (OP_XMM_Vex): Likewise.
513 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
514 Lili Cui <lili.cui@intel.com>
516 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
517 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
519 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
520 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
521 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
522 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
523 (i386_cpu_flags): Add cpuavx512_vp2intersect.
524 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
525 * i386-init.h: Regenerated.
526 * i386-tbl.h: Likewise.
528 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
529 Lili Cui <lili.cui@intel.com>
531 * doc/c-i386.texi: Document enqcmd.
532 * testsuite/gas/i386/enqcmd-intel.d: New file.
533 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
534 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
535 * testsuite/gas/i386/enqcmd.d: Likewise.
536 * testsuite/gas/i386/enqcmd.s: Likewise.
537 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
538 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
539 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
540 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
541 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
542 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
543 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
546 2019-06-04 Alan Hayward <alan.hayward@arm.com>
548 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
550 2019-06-03 Alan Modra <amodra@gmail.com>
552 * ppc-dis.c (prefix_opcd_indices): Correct size.
554 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
557 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
559 * i386-tbl.h: Regenerated.
561 2019-05-24 Alan Modra <amodra@gmail.com>
563 * po/POTFILES.in: Regenerate.
565 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
566 Alan Modra <amodra@gmail.com>
568 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
569 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
570 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
571 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
572 XTOP>): Define and add entries.
573 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
574 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
575 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
576 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
578 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
579 Alan Modra <amodra@gmail.com>
581 * ppc-dis.c (ppc_opts): Add "future" entry.
582 (PREFIX_OPCD_SEGS): Define.
583 (prefix_opcd_indices): New array.
584 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
585 (lookup_prefix): New function.
586 (print_insn_powerpc): Handle 64-bit prefix instructions.
587 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
588 (PMRR, POWERXX): Define.
589 (prefix_opcodes): New instruction table.
590 (prefix_num_opcodes): New constant.
592 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
594 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
595 * configure: Regenerated.
596 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
598 (HFILES): Add bpf-desc.h and bpf-opc.h.
599 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
600 bpf-ibld.c and bpf-opc.c.
602 * Makefile.in: Regenerated.
603 * disassemble.c (ARCH_bpf): Define.
604 (disassembler): Add case for bfd_arch_bpf.
605 (disassemble_init_for_target): Likewise.
606 (enum epbf_isa_attr): Define.
607 * disassemble.h: extern print_insn_bpf.
608 * bpf-asm.c: Generated.
609 * bpf-opc.h: Likewise.
610 * bpf-opc.c: Likewise.
611 * bpf-ibld.c: Likewise.
612 * bpf-dis.c: Likewise.
613 * bpf-desc.h: Likewise.
614 * bpf-desc.c: Likewise.
616 2019-05-21 Sudakshina Das <sudi.das@arm.com>
618 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
619 and VMSR with the new operands.
621 2019-05-21 Sudakshina Das <sudi.das@arm.com>
623 * arm-dis.c (enum mve_instructions): New enum
624 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
626 (mve_opcodes): New instructions as above.
627 (is_mve_encoding_conflict): Add cases for csinc, csinv,
629 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
631 2019-05-21 Sudakshina Das <sudi.das@arm.com>
633 * arm-dis.c (emun mve_instructions): Updated for new instructions.
634 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
635 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
636 uqshl, urshrl and urshr.
637 (is_mve_okay_in_it): Add new instructions to TRUE list.
638 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
639 (print_insn_mve): Updated to accept new %j,
640 %<bitfield>m and %<bitfield>n patterns.
642 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
644 * mips-opc.c (mips_builtin_opcodes): Change source register
647 2019-05-20 Nick Clifton <nickc@redhat.com>
649 * po/fr.po: Updated French translation.
651 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
652 Michael Collison <michael.collison@arm.com>
654 * arm-dis.c (thumb32_opcodes): Add new instructions.
655 (enum mve_instructions): Likewise.
656 (enum mve_undefined): Add new reasons.
657 (is_mve_encoding_conflict): Handle new instructions.
658 (is_mve_undefined): Likewise.
659 (is_mve_unpredictable): Likewise.
660 (print_mve_undefined): Likewise.
661 (print_mve_size): Likewise.
663 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
664 Michael Collison <michael.collison@arm.com>
666 * arm-dis.c (thumb32_opcodes): Add new instructions.
667 (enum mve_instructions): Likewise.
668 (is_mve_encoding_conflict): Handle new instructions.
669 (is_mve_undefined): Likewise.
670 (is_mve_unpredictable): Likewise.
671 (print_mve_size): Likewise.
673 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
674 Michael Collison <michael.collison@arm.com>
676 * arm-dis.c (thumb32_opcodes): Add new instructions.
677 (enum mve_instructions): Likewise.
678 (is_mve_encoding_conflict): Likewise.
679 (is_mve_unpredictable): Likewise.
680 (print_mve_size): Likewise.
682 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
683 Michael Collison <michael.collison@arm.com>
685 * arm-dis.c (thumb32_opcodes): Add new instructions.
686 (enum mve_instructions): Likewise.
687 (is_mve_encoding_conflict): Handle new instructions.
688 (is_mve_undefined): Likewise.
689 (is_mve_unpredictable): Likewise.
690 (print_mve_size): Likewise.
692 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
693 Michael Collison <michael.collison@arm.com>
695 * arm-dis.c (thumb32_opcodes): Add new instructions.
696 (enum mve_instructions): Likewise.
697 (is_mve_encoding_conflict): Handle new instructions.
698 (is_mve_undefined): Likewise.
699 (is_mve_unpredictable): Likewise.
700 (print_mve_size): Likewise.
701 (print_insn_mve): Likewise.
703 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
704 Michael Collison <michael.collison@arm.com>
706 * arm-dis.c (thumb32_opcodes): Add new instructions.
707 (print_insn_thumb32): Handle new instructions.
709 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
710 Michael Collison <michael.collison@arm.com>
712 * arm-dis.c (enum mve_instructions): Add new instructions.
713 (enum mve_undefined): Add new reasons.
714 (is_mve_encoding_conflict): Handle new instructions.
715 (is_mve_undefined): Likewise.
716 (is_mve_unpredictable): Likewise.
717 (print_mve_undefined): Likewise.
718 (print_mve_size): Likewise.
719 (print_mve_shift_n): Likewise.
720 (print_insn_mve): Likewise.
722 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
723 Michael Collison <michael.collison@arm.com>
725 * arm-dis.c (enum mve_instructions): Add new instructions.
726 (is_mve_encoding_conflict): Handle new instructions.
727 (is_mve_unpredictable): Likewise.
728 (print_mve_rotate): Likewise.
729 (print_mve_size): Likewise.
730 (print_insn_mve): Likewise.
732 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
733 Michael Collison <michael.collison@arm.com>
735 * arm-dis.c (enum mve_instructions): Add new instructions.
736 (is_mve_encoding_conflict): Handle new instructions.
737 (is_mve_unpredictable): Likewise.
738 (print_mve_size): Likewise.
739 (print_insn_mve): Likewise.
741 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
742 Michael Collison <michael.collison@arm.com>
744 * arm-dis.c (enum mve_instructions): Add new instructions.
745 (enum mve_undefined): Add new reasons.
746 (is_mve_encoding_conflict): Handle new instructions.
747 (is_mve_undefined): Likewise.
748 (is_mve_unpredictable): Likewise.
749 (print_mve_undefined): Likewise.
750 (print_mve_size): Likewise.
751 (print_insn_mve): Likewise.
753 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
754 Michael Collison <michael.collison@arm.com>
756 * arm-dis.c (enum mve_instructions): Add new instructions.
757 (is_mve_encoding_conflict): Handle new instructions.
758 (is_mve_undefined): Likewise.
759 (is_mve_unpredictable): Likewise.
760 (print_mve_size): Likewise.
761 (print_insn_mve): Likewise.
763 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
764 Michael Collison <michael.collison@arm.com>
766 * arm-dis.c (enum mve_instructions): Add new instructions.
767 (enum mve_unpredictable): Add new reasons.
768 (enum mve_undefined): Likewise.
769 (is_mve_okay_in_it): Handle new isntructions.
770 (is_mve_encoding_conflict): Likewise.
771 (is_mve_undefined): Likewise.
772 (is_mve_unpredictable): Likewise.
773 (print_mve_vmov_index): Likewise.
774 (print_simd_imm8): Likewise.
775 (print_mve_undefined): Likewise.
776 (print_mve_unpredictable): Likewise.
777 (print_mve_size): Likewise.
778 (print_insn_mve): Likewise.
780 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
781 Michael Collison <michael.collison@arm.com>
783 * arm-dis.c (enum mve_instructions): Add new instructions.
784 (enum mve_unpredictable): Add new reasons.
785 (enum mve_undefined): Likewise.
786 (is_mve_encoding_conflict): Handle new instructions.
787 (is_mve_undefined): Likewise.
788 (is_mve_unpredictable): Likewise.
789 (print_mve_undefined): Likewise.
790 (print_mve_unpredictable): Likewise.
791 (print_mve_rounding_mode): Likewise.
792 (print_mve_vcvt_size): Likewise.
793 (print_mve_size): Likewise.
794 (print_insn_mve): Likewise.
796 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
797 Michael Collison <michael.collison@arm.com>
799 * arm-dis.c (enum mve_instructions): Add new instructions.
800 (enum mve_unpredictable): Add new reasons.
801 (enum mve_undefined): Likewise.
802 (is_mve_undefined): Handle new instructions.
803 (is_mve_unpredictable): Likewise.
804 (print_mve_undefined): Likewise.
805 (print_mve_unpredictable): Likewise.
806 (print_mve_size): Likewise.
807 (print_insn_mve): Likewise.
809 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
810 Michael Collison <michael.collison@arm.com>
812 * arm-dis.c (enum mve_instructions): Add new instructions.
813 (enum mve_undefined): Add new reasons.
814 (insns): Add new instructions.
815 (is_mve_encoding_conflict):
816 (print_mve_vld_str_addr): New print function.
817 (is_mve_undefined): Handle new instructions.
818 (is_mve_unpredictable): Likewise.
819 (print_mve_undefined): Likewise.
820 (print_mve_size): Likewise.
821 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
822 (print_insn_mve): Handle new operands.
824 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
825 Michael Collison <michael.collison@arm.com>
827 * arm-dis.c (enum mve_instructions): Add new instructions.
828 (enum mve_unpredictable): Add new reasons.
829 (is_mve_encoding_conflict): Handle new instructions.
830 (is_mve_unpredictable): Likewise.
831 (mve_opcodes): Add new instructions.
832 (print_mve_unpredictable): Handle new reasons.
833 (print_mve_register_blocks): New print function.
834 (print_mve_size): Handle new instructions.
835 (print_insn_mve): Likewise.
837 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
838 Michael Collison <michael.collison@arm.com>
840 * arm-dis.c (enum mve_instructions): Add new instructions.
841 (enum mve_unpredictable): Add new reasons.
842 (enum mve_undefined): Likewise.
843 (is_mve_encoding_conflict): Handle new instructions.
844 (is_mve_undefined): Likewise.
845 (is_mve_unpredictable): Likewise.
846 (coprocessor_opcodes): Move NEON VDUP from here...
847 (neon_opcodes): ... to here.
848 (mve_opcodes): Add new instructions.
849 (print_mve_undefined): Handle new reasons.
850 (print_mve_unpredictable): Likewise.
851 (print_mve_size): Handle new instructions.
852 (print_insn_neon): Handle vdup.
853 (print_insn_mve): Handle new operands.
855 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
856 Michael Collison <michael.collison@arm.com>
858 * arm-dis.c (enum mve_instructions): Add new instructions.
859 (enum mve_unpredictable): Add new values.
860 (mve_opcodes): Add new instructions.
861 (vec_condnames): New array with vector conditions.
862 (mve_predicatenames): New array with predicate suffixes.
863 (mve_vec_sizename): New array with vector sizes.
864 (enum vpt_pred_state): New enum with vector predication states.
865 (struct vpt_block): New struct type for vpt blocks.
866 (vpt_block_state): Global struct to keep track of state.
867 (mve_extract_pred_mask): New helper function.
868 (num_instructions_vpt_block): Likewise.
869 (mark_outside_vpt_block): Likewise.
870 (mark_inside_vpt_block): Likewise.
871 (invert_next_predicate_state): Likewise.
872 (update_next_predicate_state): Likewise.
873 (update_vpt_block_state): Likewise.
874 (is_vpt_instruction): Likewise.
875 (is_mve_encoding_conflict): Add entries for new instructions.
876 (is_mve_unpredictable): Likewise.
877 (print_mve_unpredictable): Handle new cases.
878 (print_instruction_predicate): Likewise.
879 (print_mve_size): New function.
880 (print_vec_condition): New function.
881 (print_insn_mve): Handle vpt blocks and new print operands.
883 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
885 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
886 8, 14 and 15 for Armv8.1-M Mainline.
888 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
889 Michael Collison <michael.collison@arm.com>
891 * arm-dis.c (enum mve_instructions): New enum.
892 (enum mve_unpredictable): Likewise.
893 (enum mve_undefined): Likewise.
894 (struct mopcode32): New struct.
895 (is_mve_okay_in_it): New function.
896 (is_mve_architecture): Likewise.
897 (arm_decode_field): Likewise.
898 (arm_decode_field_multiple): Likewise.
899 (is_mve_encoding_conflict): Likewise.
900 (is_mve_undefined): Likewise.
901 (is_mve_unpredictable): Likewise.
902 (print_mve_undefined): Likewise.
903 (print_mve_unpredictable): Likewise.
904 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
905 (print_insn_mve): New function.
906 (print_insn_thumb32): Handle MVE architecture.
907 (select_arm_features): Force thumb for Armv8.1-m Mainline.
909 2019-05-10 Nick Clifton <nickc@redhat.com>
912 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
913 end of the table prematurely.
915 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
917 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
920 2019-05-11 Alan Modra <amodra@gmail.com>
922 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
923 when -Mraw is in effect.
925 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
927 * aarch64-dis-2.c: Regenerate.
928 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
929 (OP_SVE_BBB): New variant set.
930 (OP_SVE_DDDD): New variant set.
931 (OP_SVE_HHH): New variant set.
932 (OP_SVE_HHHU): New variant set.
933 (OP_SVE_SSS): New variant set.
934 (OP_SVE_SSSU): New variant set.
935 (OP_SVE_SHH): New variant set.
936 (OP_SVE_SBBU): New variant set.
937 (OP_SVE_DSS): New variant set.
938 (OP_SVE_DHHU): New variant set.
939 (OP_SVE_VMV_HSD_BHS): New variant set.
940 (OP_SVE_VVU_HSD_BHS): New variant set.
941 (OP_SVE_VVVU_SD_BH): New variant set.
942 (OP_SVE_VVVU_BHSD): New variant set.
943 (OP_SVE_VVV_QHD_DBS): New variant set.
944 (OP_SVE_VVV_HSD_BHS): New variant set.
945 (OP_SVE_VVV_HSD_BHS2): New variant set.
946 (OP_SVE_VVV_BHS_HSD): New variant set.
947 (OP_SVE_VV_BHS_HSD): New variant set.
948 (OP_SVE_VVV_SD): New variant set.
949 (OP_SVE_VVU_BHS_HSD): New variant set.
950 (OP_SVE_VZVV_SD): New variant set.
951 (OP_SVE_VZVV_BH): New variant set.
952 (OP_SVE_VZV_SD): New variant set.
953 (aarch64_opcode_table): Add sve2 instructions.
955 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
957 * aarch64-asm-2.c: Regenerated.
958 * aarch64-dis-2.c: Regenerated.
959 * aarch64-opc-2.c: Regenerated.
960 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
961 for SVE_SHLIMM_UNPRED_22.
962 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
963 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
966 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
968 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
969 sve_size_tsz_bhs iclass encode.
970 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
971 sve_size_tsz_bhs iclass decode.
973 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
975 * aarch64-asm-2.c: Regenerated.
976 * aarch64-dis-2.c: Regenerated.
977 * aarch64-opc-2.c: Regenerated.
978 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
979 for SVE_Zm4_11_INDEX.
980 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
981 (fields): Handle SVE_i2h field.
982 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
983 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
985 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
987 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
988 sve_shift_tsz_bhsd iclass encode.
989 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
990 sve_shift_tsz_bhsd iclass decode.
992 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
994 * aarch64-asm-2.c: Regenerated.
995 * aarch64-dis-2.c: Regenerated.
996 * aarch64-opc-2.c: Regenerated.
997 * aarch64-asm.c (aarch64_ins_sve_shrimm):
998 (aarch64_encode_variant_using_iclass): Handle
999 sve_shift_tsz_hsd iclass encode.
1000 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1001 sve_shift_tsz_hsd iclass decode.
1002 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1003 for SVE_SHRIMM_UNPRED_22.
1004 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1005 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1008 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1010 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1011 sve_size_013 iclass encode.
1012 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1013 sve_size_013 iclass decode.
1015 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1017 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1018 sve_size_bh iclass encode.
1019 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1020 sve_size_bh iclass decode.
1022 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1024 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1025 sve_size_sd2 iclass encode.
1026 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1027 sve_size_sd2 iclass decode.
1028 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1029 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1031 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1033 * aarch64-asm-2.c: Regenerated.
1034 * aarch64-dis-2.c: Regenerated.
1035 * aarch64-opc-2.c: Regenerated.
1036 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1038 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1039 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1041 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1043 * aarch64-asm-2.c: Regenerated.
1044 * aarch64-dis-2.c: Regenerated.
1045 * aarch64-opc-2.c: Regenerated.
1046 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1047 for SVE_Zm3_11_INDEX.
1048 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1049 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1050 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1052 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1054 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1056 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1057 sve_size_hsd2 iclass encode.
1058 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1059 sve_size_hsd2 iclass decode.
1060 * aarch64-opc.c (fields): Handle SVE_size field.
1061 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1063 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1065 * aarch64-asm-2.c: Regenerated.
1066 * aarch64-dis-2.c: Regenerated.
1067 * aarch64-opc-2.c: Regenerated.
1068 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1070 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1071 (fields): Handle SVE_rot3 field.
1072 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1073 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1075 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1077 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1080 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1083 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1084 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1085 aarch64_feature_sve2bitperm): New feature sets.
1086 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1087 for feature set addresses.
1088 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1089 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1091 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1092 Faraz Shahbazker <fshahbazker@wavecomp.com>
1094 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1095 argument and set ASE_EVA_R6 appropriately.
1096 (set_default_mips_dis_options): Pass ISA to above.
1097 (parse_mips_dis_option): Likewise.
1098 * mips-opc.c (EVAR6): New macro.
1099 (mips_builtin_opcodes): Add llwpe, scwpe.
1101 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1103 * aarch64-asm-2.c: Regenerated.
1104 * aarch64-dis-2.c: Regenerated.
1105 * aarch64-opc-2.c: Regenerated.
1106 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1107 AARCH64_OPND_TME_UIMM16.
1108 (aarch64_print_operand): Likewise.
1109 * aarch64-tbl.h (QL_IMM_NIL): New.
1112 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1114 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1116 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1118 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1119 Faraz Shahbazker <fshahbazker@wavecomp.com>
1121 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1123 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1125 * s12z-opc.h: Add extern "C" bracketing to help
1126 users who wish to use this interface in c++ code.
1128 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1130 * s12z-opc.c (bm_decode): Handle bit map operations with the
1133 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1135 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1136 specifier. Add entries for VLDR and VSTR of system registers.
1137 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1138 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1139 of %J and %K format specifier.
1141 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1143 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1144 Add new entries for VSCCLRM instruction.
1145 (print_insn_coprocessor): Handle new %C format control code.
1147 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1149 * arm-dis.c (enum isa): New enum.
1150 (struct sopcode32): New structure.
1151 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1152 set isa field of all current entries to ANY.
1153 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1154 Only match an entry if its isa field allows the current mode.
1156 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1158 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1160 (print_insn_thumb32): Add logic to print %n CLRM register list.
1162 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1164 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1167 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1169 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1170 (print_insn_thumb32): Edit the switch case for %Z.
1172 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1174 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1176 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1178 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1180 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1182 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1184 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1186 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1187 Arm register with r13 and r15 unpredictable.
1188 (thumb32_opcodes): New instructions for bfx and bflx.
1190 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1192 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1194 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1196 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1198 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1200 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1202 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1204 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1206 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1208 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1209 "optr". ("operator" is a reserved word in c++).
1211 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1213 * aarch64-opc.c (aarch64_print_operand): Add case for
1215 (verify_constraints): Likewise.
1216 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1217 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1218 to accept Rt|SP as first operand.
1219 (AARCH64_OPERANDS): Add new Rt_SP.
1220 * aarch64-asm-2.c: Regenerated.
1221 * aarch64-dis-2.c: Regenerated.
1222 * aarch64-opc-2.c: Regenerated.
1224 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1226 * aarch64-asm-2.c: Regenerated.
1227 * aarch64-dis-2.c: Likewise.
1228 * aarch64-opc-2.c: Likewise.
1229 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1231 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1233 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1235 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1237 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1238 * i386-init.h: Regenerated.
1240 2019-04-07 Alan Modra <amodra@gmail.com>
1242 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1243 op_separator to control printing of spaces, comma and parens
1244 rather than need_comma, need_paren and spaces vars.
1246 2019-04-07 Alan Modra <amodra@gmail.com>
1249 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1250 (print_insn_neon, print_insn_arm): Likewise.
1252 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1254 * i386-dis-evex.h (evex_table): Updated to support BF16
1256 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1257 and EVEX_W_0F3872_P_3.
1258 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1259 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1260 * i386-opc.h (enum): Add CpuAVX512_BF16.
1261 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1262 * i386-opc.tbl: Add AVX512 BF16 instructions.
1263 * i386-init.h: Regenerated.
1264 * i386-tbl.h: Likewise.
1266 2019-04-05 Alan Modra <amodra@gmail.com>
1268 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1269 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1270 to favour printing of "-" branch hint when using the "y" bit.
1271 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1273 2019-04-05 Alan Modra <amodra@gmail.com>
1275 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1276 opcode until first operand is output.
1278 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1281 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1282 (valid_bo_post_v2): Add support for 'at' branch hints.
1283 (insert_bo): Only error on branch on ctr.
1284 (get_bo_hint_mask): New function.
1285 (insert_boe): Add new 'branch_taken' formal argument. Add support
1286 for inserting 'at' branch hints.
1287 (extract_boe): Add new 'branch_taken' formal argument. Add support
1288 for extracting 'at' branch hints.
1289 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1290 (BOE): Delete operand.
1291 (BOM, BOP): New operands.
1293 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1294 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1295 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1296 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1297 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1298 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1299 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1300 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1301 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1302 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1303 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1304 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1305 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1306 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1307 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1308 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1309 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1310 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1311 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1312 bttarl+>: New extended mnemonics.
1314 2019-03-28 Alan Modra <amodra@gmail.com>
1317 * ppc-opc.c (BTF): Define.
1318 (powerpc_opcodes): Use for mtfsb*.
1319 * ppc-dis.c (print_insn_powerpc): Print fields with both
1320 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1322 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1324 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1325 (mapping_symbol_for_insn): Implement new algorithm.
1326 (print_insn): Remove duplicate code.
1328 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1330 * aarch64-dis.c (print_insn_aarch64):
1333 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1335 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1338 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1340 * aarch64-dis.c (last_stop_offset): New.
1341 (print_insn_aarch64): Use stop_offset.
1343 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1346 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1348 * i386-init.h: Regenerated.
1350 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1353 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1354 vmovdqu16, vmovdqu32 and vmovdqu64.
1355 * i386-tbl.h: Regenerated.
1357 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1359 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1360 from vstrszb, vstrszh, and vstrszf.
1362 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1364 * s390-opc.txt: Add instruction descriptions.
1366 2019-02-08 Jim Wilson <jimw@sifive.com>
1368 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1371 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1373 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1375 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1378 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1379 * aarch64-opc.c (verify_elem_sd): New.
1380 (fields): Add FLD_sz entr.
1381 * aarch64-tbl.h (_SIMD_INSN): New.
1382 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1383 fmulx scalar and vector by element isns.
1385 2019-02-07 Nick Clifton <nickc@redhat.com>
1387 * po/sv.po: Updated Swedish translation.
1389 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1391 * s390-mkopc.c (main): Accept arch13 as cpu string.
1392 * s390-opc.c: Add new instruction formats and instruction opcode
1394 * s390-opc.txt: Add new arch13 instructions.
1396 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1398 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1399 (aarch64_opcode): Change encoding for stg, stzg
1401 * aarch64-asm-2.c: Regenerated.
1402 * aarch64-dis-2.c: Regenerated.
1403 * aarch64-opc-2.c: Regenerated.
1405 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1407 * aarch64-asm-2.c: Regenerated.
1408 * aarch64-dis-2.c: Likewise.
1409 * aarch64-opc-2.c: Likewise.
1410 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1412 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1413 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1415 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1416 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1417 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1418 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1419 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1420 case for ldstgv_indexed.
1421 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1422 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1423 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1424 * aarch64-asm-2.c: Regenerated.
1425 * aarch64-dis-2.c: Regenerated.
1426 * aarch64-opc-2.c: Regenerated.
1428 2019-01-23 Nick Clifton <nickc@redhat.com>
1430 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1432 2019-01-21 Nick Clifton <nickc@redhat.com>
1434 * po/de.po: Updated German translation.
1435 * po/uk.po: Updated Ukranian translation.
1437 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1438 * mips-dis.c (mips_arch_choices): Fix typo in
1439 gs464, gs464e and gs264e descriptors.
1441 2019-01-19 Nick Clifton <nickc@redhat.com>
1443 * configure: Regenerate.
1444 * po/opcodes.pot: Regenerate.
1446 2018-06-24 Nick Clifton <nickc@redhat.com>
1448 2.32 branch created.
1450 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1452 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1454 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1457 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1459 * configure: Regenerate.
1461 2019-01-07 Alan Modra <amodra@gmail.com>
1463 * configure: Regenerate.
1464 * po/POTFILES.in: Regenerate.
1466 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1468 * s12z-opc.c: New file.
1469 * s12z-opc.h: New file.
1470 * s12z-dis.c: Removed all code not directly related to display
1471 of instructions. Used the interface provided by the new files
1473 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1474 * Makefile.in: Regenerate.
1475 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1476 * configure: Regenerate.
1478 2019-01-01 Alan Modra <amodra@gmail.com>
1480 Update year range in copyright notice of all files.
1482 For older changes see ChangeLog-2018
1484 Copyright (C) 2019 Free Software Foundation, Inc.
1486 Copying and distribution of this file, with or without modification,
1487 are permitted in any medium without royalty provided the copyright
1488 notice and this notice are preserved.
1494 version-control: never