1 2013-08-28 Nick Clifton <nickc@redhat.com>
3 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
4 immediate is not suitable for the 32-bit ABI.
6 2013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
8 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
11 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
14 * aarch64-asm.c: Fix typos.
15 * aarch64-dis.c: Likewise.
16 * msp430-dis.c: Likewise.
18 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
20 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
21 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
22 Use +H rather than +C for the real "dext".
23 * mips-opc.c (mips_builtin_opcodes): Likewise.
25 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
27 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
28 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
29 and OPTIONAL_MAPPED_REG.
30 * mips-opc.c (decode_mips_operand): Likewise.
31 * mips16-opc.c (decode_mips16_operand): Likewise.
32 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
34 2013-08-19 H.J. Lu <hongjiu.lu@intel.com>
36 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
37 (PREFIX_EVEX_0F3A3F): Likewise.
38 * i386-dis-evex.h (evex_table): Updated.
40 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
42 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
45 2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
46 Konrad Eisele <konrad@gaisler.com>
48 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
50 * sparc-opc.c (MASK_LEON): Define.
51 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
52 (letandleon): New macro.
53 (v9andleon): Likewise.
54 (sparc_opc): Add leon.
55 (umac): Enable for letandleon.
57 (casa): Enable for v9andleon.
61 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
62 Richard Sandiford <rdsandiford@googlemail.com>
64 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
65 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
66 (print_vu0_channel): New function.
67 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
68 (print_insn_args): Handle '#'.
69 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
70 * mips-opc.c (mips_vu0_channel_mask): New constant.
71 (decode_mips_operand): Handle new VU0 operand types.
72 (VU0, VU0CH): New macros.
73 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
74 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
75 Use "+6" rather than "G" for QMFC2 and QMTC2.
77 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
79 * mips-formats.h (PCREL): Reorder parameters and update the definition
80 to match new mips_pcrel_operand layout.
81 (JUMP, JALX, BRANCH): Update accordingly.
82 * mips16-opc.c (decode_mips16_operand): Likewise.
84 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
86 * micromips-opc.c (WR_s): Delete.
88 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
90 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
92 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
93 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
94 (mips_builtin_opcodes): Use the new position-based read-write flags
95 instead of field-based ones. Use UDI for "udi..." instructions.
96 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
98 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
99 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
100 (WR_SP, RD_16): New macros.
101 (RD_SP): Redefine as an INSN2_* flag.
102 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
103 (mips16_opcodes): Use the new position-based read-write flags
104 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
106 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
108 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
109 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
110 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
111 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
112 (micromips_opcodes): Use the new position-based read-write flags
113 instead of field-based ones.
114 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
115 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
116 of field-based flags.
118 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
120 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
121 (WR_SP): Replace with...
123 (mips16_opcodes): Update accordingly.
124 * mips-dis.c (print_insn_mips16): Likewise.
126 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
128 * mips16-opc.c (mips16_opcodes): Reformat.
130 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
132 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
133 for operands that are hard-coded to $0.
134 * micromips-opc.c (micromips_opcodes): Likewise.
136 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
138 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
139 for the single-operand forms of JALR and JALR.HB.
140 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
143 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
145 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
146 instructions. Fix them to use WR_MACC instead of WR_CC and
147 add missing RD_MACCs.
149 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
151 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
153 2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
155 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
157 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
158 Alexander Ivchenko <alexander.ivchenko@intel.com>
159 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
160 Sergey Lega <sergey.s.lega@intel.com>
161 Anna Tikhonova <anna.tikhonova@intel.com>
162 Ilya Tocar <ilya.tocar@intel.com>
163 Andrey Turetskiy <andrey.turetskiy@intel.com>
164 Ilya Verbin <ilya.verbin@intel.com>
165 Kirill Yukhin <kirill.yukhin@intel.com>
166 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
168 * i386-dis-evex.h: New.
169 * i386-dis.c (OP_Rounding): New.
176 (EXEvexHalfBcstXmmq): New.
179 (EXEvexXNoBcst): New.
188 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
189 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
190 evex_rounding_mode, evex_sae_mode, mask_mode.
191 (USE_EVEX_TABLE): New.
194 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
196 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
197 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
198 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
199 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
200 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
201 MOD_EVEX_0F38C7_REG_6.
202 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
203 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
204 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
205 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
206 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
207 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
208 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
209 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
210 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
211 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
212 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
213 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
214 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
215 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
216 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
217 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
218 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
219 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
220 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
221 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
222 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
223 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
224 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
225 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
226 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
227 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
228 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
229 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
230 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
231 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
232 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
233 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
234 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
235 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
236 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
237 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
238 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
239 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
240 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
241 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
242 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
243 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
244 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
245 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
246 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
247 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
248 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
249 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
250 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
251 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
252 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
253 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
254 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
255 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
256 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
257 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
258 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
259 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
260 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
261 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
262 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
263 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
264 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
265 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
266 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
267 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
268 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
269 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
270 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
271 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
272 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
273 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
274 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
275 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
276 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
277 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
279 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
280 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
281 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
282 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
283 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
284 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
285 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
286 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
287 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
288 VEX_W_0F3A32_P_2_LEN_0.
289 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
290 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
291 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
292 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
293 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
294 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
295 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
296 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
297 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
298 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
299 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
300 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
301 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
302 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
303 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
304 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
305 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
306 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
307 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
308 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
309 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
310 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
311 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
312 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
313 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
314 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
315 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
316 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
317 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
318 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
319 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
320 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
321 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
322 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
323 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
324 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
325 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
326 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
327 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
328 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
329 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
330 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
331 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
332 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
333 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
334 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
335 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
336 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
337 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
338 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
339 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
340 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
341 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
342 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
343 (struct vex): Add fields evex, r, v, mask_register_specifier,
345 (intel_names_xmm): Add upper 16 registers.
346 (att_names_xmm): Ditto.
347 (intel_names_ymm): Ditto.
348 (att_names_ymm): Ditto.
350 (intel_names_zmm): Ditto.
351 (att_names_zmm): Ditto.
353 (intel_names_mask): Ditto.
354 (att_names_mask): Ditto.
355 (names_rounding): Ditto.
356 (names_broadcast): Ditto.
357 (x86_64_table): Add escape to evex-table.
358 (reg_table): Include reg_table evex-entries from
359 i386-dis-evex.h. Fix prefetchwt1 instruction.
360 (prefix_table): Add entries for new instructions.
362 (vex_len_table): Ditto.
363 (vex_w_table): Ditto.
365 (get_valid_dis386): Properly handle new instructions.
366 (print_insn): Handle zmm and mask registers, print mask operand.
367 (intel_operand_size): Support EVEX, new modes and sizes.
368 (OP_E_register): Handle new modes.
369 (OP_E_memory): Ditto.
374 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
375 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
376 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
377 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
378 CpuAVX512PF and CpuVREX.
379 (operand_type_init): Add OPERAND_TYPE_REGZMM,
380 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
381 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
382 StaticRounding, SAE, Disp8MemShift, NoDefMask.
383 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
384 * i386-init.h: Regenerate.
385 * i386-opc.h (CpuAVX512F): New.
390 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
391 cpuavx512pf and cpuvrex fields.
392 (VecSIB): Add VecSIB512.
397 (StaticRounding): New.
399 (Disp8MemShift): New.
401 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
402 staticrounding, sae, disp8memshift and nodefmask.
406 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
409 * i386-opc.tbl: Add AVX512 instructions.
410 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
411 registers, mask registers.
412 * i386-tbl.h: Regenerate.
414 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
417 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
418 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
420 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
422 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
423 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
425 (prefix_table): Updated.
426 (three_byte_table): Likewise.
427 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
428 (cpu_flags): Add CpuSHA.
429 (i386_cpu_flags): Add cpusha.
430 * i386-init.h: Regenerate.
431 * i386-opc.h (CpuSHA): New.
432 (CpuUnused): Restored.
433 (i386_cpu_flags): Add cpusha.
434 * i386-opc.tbl: Add SHA instructions.
435 * i386-tbl.h: Regenerate.
437 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
438 Kirill Yukhin <kirill.yukhin@intel.com>
439 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
441 * i386-dis.c (BND_Fixup): New.
448 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
450 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
451 (dis tables): Replace XX with BND for near branch and call
453 (prefix_table): Add new entries.
454 (mod_table): Likewise.
456 (intel_names_bnd): New.
457 (att_names_bnd): New.
459 (prefix_name): Handle BND_PREFIX.
460 (print_insn): Initialize names_bnd.
461 (intel_operand_size): Handle new modes.
462 (OP_E_register): Likewise.
463 (OP_E_memory): Likewise.
465 * i386-gen.c (cpu_flag_init): Add CpuMPX.
466 (cpu_flags): Add CpuMPX.
467 (operand_type_init): Add RegBND.
468 (opcode_modifiers): Add BNDPrefixOk.
469 (operand_types): Add RegBND.
470 * i386-init.h: Regenerate.
471 * i386-opc.h (CpuMPX): New.
472 (CpuUnused): Comment out.
473 (i386_cpu_flags): Add cpumpx.
475 (i386_opcode_modifier): Add bndprefixok.
477 (i386_operand_type): Add regbnd.
478 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
479 Add MPX instructions and bnd prefix.
480 * i386-reg.tbl: Add bnd0-bnd3 registers.
481 * i386-tbl.h: Regenerate.
483 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
485 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
488 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
490 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
492 * Makefile.in: Regenerate.
493 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
494 all fields. Reformat.
496 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
498 * mips16-opc.c: Include mips-formats.h.
499 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
501 (decode_mips16_operand): New function.
502 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
503 (print_insn_arg): Handle OP_ENTRY_EXIT list.
504 Abort for OP_SAVE_RESTORE_LIST.
505 (print_mips16_insn_arg): Change interface. Use mips_operand
506 structures. Delete GET_OP_S. Move GET_OP definition to...
507 (print_insn_mips16): ...here. Call init_print_arg_state.
508 Update the call to print_mips16_insn_arg.
510 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
512 * mips-formats.h: New file.
513 * mips-opc.c: Include mips-formats.h.
514 (reg_0_map): New static array.
515 (decode_mips_operand): New function.
516 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
517 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
518 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
519 (int_c_map): New static arrays.
520 (decode_micromips_operand): New function.
521 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
522 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
523 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
524 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
525 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
526 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
527 (micromips_imm_b_map, micromips_imm_c_map): Delete.
528 (print_reg): New function.
529 (mips_print_arg_state): New structure.
530 (init_print_arg_state, print_insn_arg): New functions.
531 (print_insn_args): Change interface and use mips_operand structures.
532 Delete GET_OP_S. Move GET_OP definition to...
533 (print_insn_mips): ...here. Update the call to print_insn_args.
534 (print_insn_micromips): Use print_insn_args.
536 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
538 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
541 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
543 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
544 ADDA.S, MULA.S and SUBA.S.
546 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
549 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
550 * i386-tbl.h: Regenerated.
552 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
554 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
555 and SD A(B) macros up.
556 * micromips-opc.c (micromips_opcodes): Likewise.
558 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
560 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
563 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
565 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
566 MDMX-like instructions.
567 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
568 printing "Q" operands for INSN_5400 instructions.
570 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
572 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
574 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
577 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
579 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
581 * mips16-opc.c (mips16_opcodes): Likewise.
582 * micromips-opc.c (micromips_opcodes): Likewise.
583 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
584 (print_insn_mips16): Handle "+i".
585 (print_insn_micromips): Likewise. Conditionally preserve the
586 ISA bit for "a" but not for "+i".
588 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
590 * micromips-opc.c (WR_mhi): Rename to..
592 (micromips_opcodes): Update "movep" entry accordingly. Replace
594 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
595 (micromips_to_32_reg_h_map1): ...this.
596 (micromips_to_32_reg_i_map): Rename to...
597 (micromips_to_32_reg_h_map2): ...this.
598 (print_micromips_insn): Remove "mi" case. Print both registers
599 in the pair for "mh".
601 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
603 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
604 * micromips-opc.c (micromips_opcodes): Likewise.
605 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
606 and "+T" handling. Check for a "0" suffix when deciding whether to
607 use coprocessor 0 names. In that case, also check for ",H" selectors.
609 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
611 * s390-opc.c (J12_12, J24_24): New macros.
612 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
613 (MASK_MII_UPI): Rename to MASK_MII_UPP.
614 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
616 2013-07-04 Alan Modra <amodra@gmail.com>
618 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
620 2013-06-26 Nick Clifton <nickc@redhat.com>
622 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
623 field when checking for type 2 nop.
624 * rx-decode.c: Regenerate.
626 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
628 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
631 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
633 * mips-dis.c (is_mips16_plt_tail): New function.
634 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
636 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
638 2013-06-21 DJ Delorie <dj@redhat.com>
640 * msp430-decode.opc: New.
641 * msp430-decode.c: New/generated.
642 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
643 (MAINTAINER_CLEANFILES): Likewise.
644 Add rule to build msp430-decode.c frommsp430decode.opc
645 using the opc2c program.
646 * Makefile.in: Regenerate.
647 * configure.in: Add msp430-decode.lo to msp430 architecture files.
648 * configure: Regenerate.
650 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
652 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
653 (SYMTAB_AVAILABLE): Removed.
654 (#include "elf/aarch64.h): Ditto.
656 2013-06-17 Catherine Moore <clm@codesourcery.com>
657 Maciej W. Rozycki <macro@codesourcery.com>
658 Chao-Ying Fu <fu@mips.com>
660 * micromips-opc.c (EVA): Define.
662 (micromips_opcodes): Add EVA opcodes.
663 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
664 (print_insn_args): Handle EVA offsets.
665 (print_insn_micromips): Likewise.
666 * mips-opc.c (EVA): Define.
668 (mips_builtin_opcodes): Add EVA opcodes.
670 2013-06-17 Alan Modra <amodra@gmail.com>
672 * Makefile.am (mips-opc.lo): Add rules to create automatic
673 dependency files. Pass archdefs.
674 (micromips-opc.lo, mips16-opc.lo): Likewise.
675 * Makefile.in: Regenerate.
677 2013-06-14 DJ Delorie <dj@redhat.com>
679 * rx-decode.opc (rx_decode_opcode): Bit operations on
680 registers are 32-bit operations, not 8-bit operations.
681 * rx-decode.c: Regenerate.
683 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
685 * micromips-opc.c (IVIRT): New define.
686 (IVIRT64): New define.
687 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
688 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
690 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
691 dmtgc0 to print cp0 names.
693 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
695 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
698 2013-06-08 Catherine Moore <clm@codesourcery.com>
699 Richard Sandiford <rdsandiford@googlemail.com>
701 * micromips-opc.c (D32, D33, MC): Update definitions.
702 (micromips_opcodes): Initialize ase field.
703 * mips-dis.c (mips_arch_choice): Add ase field.
704 (mips_arch_choices): Initialize ase field.
705 (set_default_mips_dis_options): Declare and setup mips_ase.
706 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
707 MT32, MC): Update definitions.
708 (mips_builtin_opcodes): Initialize ase field.
710 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
712 * s390-opc.txt (flogr): Require a register pair destination.
714 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
716 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
719 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
721 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
723 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
725 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
726 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
727 XLS_MASK, PPCVSX2): New defines.
728 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
729 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
730 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
731 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
732 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
733 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
734 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
735 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
736 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
737 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
738 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
739 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
740 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
741 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
742 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
743 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
744 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
745 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
746 <lxvx, stxvx>: New extended mnemonics.
748 2013-05-17 Alan Modra <amodra@gmail.com>
750 * ia64-raw.tbl: Replace non-ASCII char.
751 * ia64-waw.tbl: Likewise.
752 * ia64-asmtab.c: Regenerate.
754 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
756 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
757 * i386-init.h: Regenerated.
759 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
761 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
762 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
763 check from [0, 255] to [-128, 255].
765 2013-05-09 Andrew Pinski <apinski@cavium.com>
767 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
768 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
769 (parse_mips_dis_option): Handle the virt option.
770 (print_insn_args): Handle "+J".
771 (print_mips_disassembler_options): Print out message about virt64.
772 * mips-opc.c (IVIRT): New define.
773 (IVIRT64): New define.
774 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
775 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
776 Move rfe to the bottom as it conflicts with tlbgp.
778 2013-05-09 Alan Modra <amodra@gmail.com>
780 * ppc-opc.c (extract_vlesi): Properly sign extend.
781 (extract_vlensi): Likewise. Comment reason for setting invalid.
783 2013-05-02 Nick Clifton <nickc@redhat.com>
785 * msp430-dis.c: Add support for MSP430X instructions.
787 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
789 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
792 2013-04-17 Wei-chen Wang <cole945@gmail.com>
795 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
797 (hash_insns_list): Likewise.
799 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
801 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
804 2013-04-08 Jan Beulich <jbeulich@suse.com>
806 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
807 * i386-tbl.h: Re-generate.
809 2013-04-06 David S. Miller <davem@davemloft.net>
811 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
812 of an opcode, prefer the one with F_PREFERRED set.
813 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
814 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
815 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
816 mark existing mnenomics as aliases. Add "cc" suffix to edge
817 instructions generating condition codes, mark existing mnenomics
818 as aliases. Add "fp" prefix to VIS compare instructions, mark
819 existing mnenomics as aliases.
821 2013-04-03 Nick Clifton <nickc@redhat.com>
823 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
824 destination address by subtracting the operand from the current
826 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
827 a positive value in the insn.
828 (extract_u16_loop): Do not negate the returned value.
829 (D16_LOOP): Add V850_INVERSE_PCREL flag.
831 (ceilf.sw): Remove duplicate entry.
832 (cvtf.hs): New entry.
838 (maddf.s): Restrict to E3V5 architectures.
840 (nmaddf.s): Likewise.
841 (nmsubf.s): Likewise.
843 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
845 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
847 (print_insn): Pass sizeflag to get_sib.
849 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
852 * tic6x-dis.c: Add support for displaying 16-bit insns.
854 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
857 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
858 individual msb and lsb halves in src1 & src2 fields. Discard the
859 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
860 follow what Ti SDK does in that case as any value in the src1
861 field yields the same output with SDK disassembler.
863 2013-03-12 Michael Eager <eager@eagercon.com>
865 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
867 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
869 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
871 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
873 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
875 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
877 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
879 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
881 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
882 (thumb32_opcodes): Likewise.
883 (print_insn_thumb32): Handle 'S' control char.
885 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
887 * lm32-desc.c: Regenerate.
889 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
891 * i386-reg.tbl (riz): Add RegRex64.
892 * i386-tbl.h: Regenerated.
894 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
896 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
897 (aarch64_feature_crc): New static.
899 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
900 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
901 * aarch64-asm-2.c: Re-generate.
902 * aarch64-dis-2.c: Ditto.
903 * aarch64-opc-2.c: Ditto.
905 2013-02-27 Alan Modra <amodra@gmail.com>
907 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
908 * rl78-decode.c: Regenerate.
910 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
912 * rl78-decode.opc: Fix encoding of DIVWU insn.
913 * rl78-decode.c: Regenerate.
915 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
918 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
920 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
921 (cpu_flags): Add CpuSMAP.
923 * i386-opc.h (CpuSMAP): New.
924 (i386_cpu_flags): Add cpusmap.
926 * i386-opc.tbl: Add clac and stac.
928 * i386-init.h: Regenerated.
929 * i386-tbl.h: Likewise.
931 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
933 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
934 which also makes the disassembler output be in little
935 endian like it should be.
937 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
939 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
941 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
943 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
945 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
946 section disassembled.
948 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
950 * arm-dis.c: Update strht pattern.
952 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
954 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
955 single-float. Disable ll, lld, sc and scd for EE. Disable the
956 trunc.w.s macro for EE.
958 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
959 Andrew Jenner <andrew@codesourcery.com>
961 Based on patches from Altera Corporation.
963 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
965 * Makefile.in: Regenerated.
966 * configure.in: Add case for bfd_nios2_arch.
967 * configure: Regenerated.
968 * disassemble.c (ARCH_nios2): Define.
969 (disassembler): Add case for bfd_arch_nios2.
970 * nios2-dis.c: New file.
971 * nios2-opc.c: New file.
973 2013-02-04 Alan Modra <amodra@gmail.com>
975 * po/POTFILES.in: Regenerate.
976 * rl78-decode.c: Regenerate.
977 * rx-decode.c: Regenerate.
979 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
981 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
982 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
983 * aarch64-asm.c (convert_xtl_to_shll): New function.
984 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
985 calling convert_xtl_to_shll.
986 * aarch64-dis.c (convert_shll_to_xtl): New function.
987 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
988 calling convert_shll_to_xtl.
989 * aarch64-gen.c: Update copyright year.
990 * aarch64-asm-2.c: Re-generate.
991 * aarch64-dis-2.c: Re-generate.
992 * aarch64-opc-2.c: Re-generate.
994 2013-01-24 Nick Clifton <nickc@redhat.com>
996 * v850-dis.c: Add support for e3v5 architecture.
997 * v850-opc.c: Likewise.
999 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1001 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1002 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1003 * aarch64-opc.c (operand_general_constraint_met_p): For
1004 AARCH64_MOD_LSL, move the range check on the shift amount before the
1005 alignment check; change to call set_sft_amount_out_of_range_error
1006 instead of set_imm_out_of_range_error.
1007 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1008 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1009 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1012 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1014 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1016 * i386-init.h: Regenerated.
1017 * i386-tbl.h: Likewise.
1019 2013-01-15 Nick Clifton <nickc@redhat.com>
1021 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1023 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1025 2013-01-14 Will Newton <will.newton@imgtec.com>
1027 * metag-dis.c (REG_WIDTH): Increase to 64.
1029 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1031 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1032 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1033 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1035 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1036 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1037 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1038 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1040 2013-01-10 Will Newton <will.newton@imgtec.com>
1042 * Makefile.am: Add Meta.
1043 * configure.in: Add Meta.
1044 * disassemble.c: Add Meta support.
1045 * metag-dis.c: New file.
1046 * Makefile.in: Regenerate.
1047 * configure: Regenerate.
1049 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1051 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1052 (match_opcode): Rename to cr16_match_opcode.
1054 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1056 * mips-dis.c: Add names for CP0 registers of r5900.
1057 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1058 instructions sq and lq.
1059 Add support for MIPS r5900 CPU.
1060 Add support for 128 bit MMI (Multimedia Instructions).
1061 Add support for EE instructions (Emotion Engine).
1062 Disable unsupported floating point instructions (64 bit and
1063 undefined compare operations).
1064 Enable instructions of MIPS ISA IV which are supported by r5900.
1065 Disable 64 bit co processor instructions.
1066 Disable 64 bit multiplication and division instructions.
1067 Disable instructions for co-processor 2 and 3, because these are
1068 not supported (preparation for later VU0 support (Vector Unit)).
1069 Disable cvt.w.s because this behaves like trunc.w.s and the
1070 correct execution can't be ensured on r5900.
1071 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1072 will confuse less developers and compilers.
1074 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1076 * aarch64-opc.c (aarch64_print_operand): Change to print
1077 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1079 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1080 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1083 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1085 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1086 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1088 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1090 * i386-gen.c (process_copyright): Update copyright year to 2013.
1092 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1094 * cr16-dis.c (match_opcode,make_instruction): Remove static
1096 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1097 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1099 For older changes see ChangeLog-2012
1101 Copyright (C) 2013 Free Software Foundation, Inc.
1103 Copying and distribution of this file, with or without modification,
1104 are permitted in any medium without royalty provided the copyright
1105 notice and this notice are preserved.
1111 version-control: never