1 2011-09-26 David S. Miller <davem@davemloft.net>
3 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
6 2011-09-21 David S. Miller <davem@davemloft.net>
8 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
9 bits. Fix "fchksm16" mnemonic.
11 2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
13 The changes below bring 'mov' and 'ticc' instructions into line
14 with the V8 SPARC Architecture Manual.
15 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
16 * sparc-opc.c (sparc_opcodes): Add alias entries for
17 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
18 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
19 * sparc-opc.c (sparc_opcodes): Move/Change entries for
20 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
22 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
25 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
26 This has been reported as being accepted by the Sun assmebler.
28 2011-09-08 David S. Miller <davem@davemloft.net>
30 * sparc-opc.c (pdistn): Destination is integer not float register.
32 2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
35 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
37 2011-08-26 Nick Clifton <nickc@redhat.com>
39 * po/es.po: Updated Spanish translation.
41 2011-08-22 Nick Clifton <nickc@redhat.com>
43 * Makefile.am (CPUDIR): Redfine to point to top level cpu
45 (stamp-frv): Use CPUDIR.
46 (stamp-iq2000): Likewise.
47 (stamp-lm32): Likewise.
48 (stamp-m32c): Likewise.
50 (stamp-xc16x): Likewise.
51 * Makefile.in: Regenerate.
53 2011-08-09 Chao-ying Fu <fu@mips.com>
54 Maciej W. Rozycki <macro@codesourcery.com>
56 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
58 (print_insn_args, print_insn_micromips): Handle MCU.
59 * micromips-opc.c (MC): New macro.
60 (micromips_opcodes): Add "aclr", "aset" and "iret".
61 * mips-opc.c (MC): New macro.
62 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
64 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
66 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
67 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
68 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
69 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
70 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
71 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
73 (micromips_opcodes): Update register use flags of: "addiu",
74 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
75 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
76 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
77 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
78 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
79 "swm" and "xor" instructions.
81 2011-08-05 David S. Miller <davem@davemloft.net>
83 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
85 (print_insn_sparc): Handle '4', '5', and '(' format codes.
86 Accept %asr numbers below 28.
87 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
90 2011-08-02 Quentin Neill <quentin.neill@amd.com>
92 * i386-dis.c (xop_table): Remove spurious bextr insn.
94 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
97 * i386-dis.c (print_insn): Optimize info->mach check.
99 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
102 * i386-opc.tbl: Add Disp32S to 64bit call.
103 * i386-tbl.h: Regenerated.
105 2011-07-24 Chao-ying Fu <fu@mips.com>
106 Maciej W. Rozycki <macro@codesourcery.com>
108 * micromips-opc.c: New file.
109 * mips-dis.c (micromips_to_32_reg_b_map): New array.
110 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
111 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
112 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
113 (micromips_to_32_reg_q_map): Likewise.
114 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
115 (micromips_ase): New variable.
116 (is_micromips): New function.
117 (set_default_mips_dis_options): Handle microMIPS ASE.
118 (print_insn_micromips): New function.
119 (is_compressed_mode_p): Likewise.
120 (_print_insn_mips): Handle microMIPS instructions.
121 * Makefile.am (CFILES): Add micromips-opc.c.
122 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
123 * Makefile.in: Regenerate.
124 * configure: Regenerate.
126 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
127 (micromips_to_32_reg_i_map): Likewise.
128 (micromips_to_32_reg_m_map): Likewise.
129 (micromips_to_32_reg_n_map): New macro.
131 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
133 * mips-opc.c (NODS): New macro.
134 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
135 (DSP_VOLA): Likewise.
136 (mips_builtin_opcodes): Add NODS annotation to "deret" and
137 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
138 place of TRAP for "wait", "waiti" and "yield".
139 * mips16-opc.c (NODS): New macro.
140 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
141 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
142 "restore" and "save".
144 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
146 * configure.in: Handle bfd_k1om_arch.
147 * configure: Regenerated.
149 * disassemble.c (disassembler): Handle bfd_k1om_arch.
151 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
152 bfd_mach_k1om_intel_syntax.
154 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
155 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
156 (cpu_flags): Add CpuK1OM.
158 * i386-opc.h (CpuK1OM): New.
159 (i386_cpu_flags): Add cpuk1om.
161 * i386-init.h: Regenerated.
162 * i386-tbl.h: Likewise.
164 2011-07-12 Nick Clifton <nickc@redhat.com>
166 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
169 2011-07-01 Nick Clifton <nickc@redhat.com>
172 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
173 insns using post-increment addressing.
175 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
177 * i386-dis.c (vex_len_table): Update rorxS.
179 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
181 AVX Programming Reference (June, 2011)
182 * i386-dis.c (vex_len_table): Correct rorxS.
184 * i386-opc.tbl: Correct rorx.
185 * i386-tbl.h: Regenerated.
187 2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
189 * tilegx-opc.c (find_opcode): Replace "index" with "i".
190 * tilepro-opc.c (find_opcode): Likewise.
192 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
194 * mips16-opc.c (jalrc, jrc): Move earlier in file.
196 2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
198 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
201 2011-06-17 Andreas Schwab <schwab@redhat.com>
203 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
204 (MOSTLYCLEANFILES): ... here.
205 * Makefile.in: Regenerate.
207 2011-06-14 Alan Modra <amodra@gmail.com>
209 * Makefile.in: Regenerate.
211 2011-06-13 Walter Lee <walt@tilera.com>
213 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
214 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
215 * Makefile.in: Regenerate.
216 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
217 * configure: Regenerate.
218 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
219 * po/POTFILES.in: Regenerate.
220 * tilegx-dis.c: New file.
221 * tilegx-opc.c: New file.
222 * tilepro-dis.c: New file.
223 * tilepro-opc.c: New file.
225 2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
227 AVX Programming Reference (June, 2011)
228 * i386-dis.c (XMGatherQ): New.
229 * i386-dis.c (EXxmm_mb): New.
230 (EXxmm_mb): Likewise.
231 (EXxmm_mw): Likewise.
232 (EXxmm_md): Likewise.
233 (EXxmm_mq): Likewise.
236 (VexGatherQ): Likewise.
237 (MVexVSIBDWpX): Likewise.
238 (MVexVSIBQWpX): Likewise.
239 (xmm_mb_mode): Likewise.
240 (xmm_mw_mode): Likewise.
241 (xmm_md_mode): Likewise.
242 (xmm_mq_mode): Likewise.
243 (xmmdw_mode): Likewise.
244 (xmmqd_mode): Likewise.
245 (ymmxmm_mode): Likewise.
246 (vex_vsib_d_w_dq_mode): Likewise.
247 (vex_vsib_q_w_dq_mode): Likewise.
248 (MOD_VEX_0F385A_PREFIX_2): Likewise.
249 (MOD_VEX_0F388C_PREFIX_2): Likewise.
250 (MOD_VEX_0F388E_PREFIX_2): Likewise.
251 (PREFIX_0F3882): Likewise.
252 (PREFIX_VEX_0F3816): Likewise.
253 (PREFIX_VEX_0F3836): Likewise.
254 (PREFIX_VEX_0F3845): Likewise.
255 (PREFIX_VEX_0F3846): Likewise.
256 (PREFIX_VEX_0F3847): Likewise.
257 (PREFIX_VEX_0F3858): Likewise.
258 (PREFIX_VEX_0F3859): Likewise.
259 (PREFIX_VEX_0F385A): Likewise.
260 (PREFIX_VEX_0F3878): Likewise.
261 (PREFIX_VEX_0F3879): Likewise.
262 (PREFIX_VEX_0F388C): Likewise.
263 (PREFIX_VEX_0F388E): Likewise.
264 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
265 (PREFIX_VEX_0F38F5): Likewise.
266 (PREFIX_VEX_0F38F6): Likewise.
267 (PREFIX_VEX_0F3A00): Likewise.
268 (PREFIX_VEX_0F3A01): Likewise.
269 (PREFIX_VEX_0F3A02): Likewise.
270 (PREFIX_VEX_0F3A38): Likewise.
271 (PREFIX_VEX_0F3A39): Likewise.
272 (PREFIX_VEX_0F3A46): Likewise.
273 (PREFIX_VEX_0F3AF0): Likewise.
274 (VEX_LEN_0F3816_P_2): Likewise.
275 (VEX_LEN_0F3819_P_2): Likewise.
276 (VEX_LEN_0F3836_P_2): Likewise.
277 (VEX_LEN_0F385A_P_2_M_0): Likewise.
278 (VEX_LEN_0F38F5_P_0): Likewise.
279 (VEX_LEN_0F38F5_P_1): Likewise.
280 (VEX_LEN_0F38F5_P_3): Likewise.
281 (VEX_LEN_0F38F6_P_3): Likewise.
282 (VEX_LEN_0F38F7_P_1): Likewise.
283 (VEX_LEN_0F38F7_P_2): Likewise.
284 (VEX_LEN_0F38F7_P_3): Likewise.
285 (VEX_LEN_0F3A00_P_2): Likewise.
286 (VEX_LEN_0F3A01_P_2): Likewise.
287 (VEX_LEN_0F3A38_P_2): Likewise.
288 (VEX_LEN_0F3A39_P_2): Likewise.
289 (VEX_LEN_0F3A46_P_2): Likewise.
290 (VEX_LEN_0F3AF0_P_3): Likewise.
291 (VEX_W_0F3816_P_2): Likewise.
292 (VEX_W_0F3818_P_2): Likewise.
293 (VEX_W_0F3819_P_2): Likewise.
294 (VEX_W_0F3836_P_2): Likewise.
295 (VEX_W_0F3846_P_2): Likewise.
296 (VEX_W_0F3858_P_2): Likewise.
297 (VEX_W_0F3859_P_2): Likewise.
298 (VEX_W_0F385A_P_2_M_0): Likewise.
299 (VEX_W_0F3878_P_2): Likewise.
300 (VEX_W_0F3879_P_2): Likewise.
301 (VEX_W_0F3A00_P_2): Likewise.
302 (VEX_W_0F3A01_P_2): Likewise.
303 (VEX_W_0F3A02_P_2): Likewise.
304 (VEX_W_0F3A38_P_2): Likewise.
305 (VEX_W_0F3A39_P_2): Likewise.
306 (VEX_W_0F3A46_P_2): Likewise.
307 (MOD_VEX_0F3818_PREFIX_2): Removed.
308 (MOD_VEX_0F3819_PREFIX_2): Likewise.
309 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
310 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
311 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
312 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
313 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
314 (VEX_LEN_0F3A0E_P_2): Likewise.
315 (VEX_LEN_0F3A0F_P_2): Likewise.
316 (VEX_LEN_0F3A42_P_2): Likewise.
317 (VEX_LEN_0F3A4C_P_2): Likewise.
318 (VEX_W_0F3818_P_2_M_0): Likewise.
319 (VEX_W_0F3819_P_2_M_0): Likewise.
320 (prefix_table): Updated.
321 (three_byte_table): Likewise.
322 (vex_table): Likewise.
323 (vex_len_table): Likewise.
324 (vex_w_table): Likewise.
325 (mod_table): Likewise.
326 (putop): Handle "LW".
327 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
328 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
329 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
331 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
332 vex_vsib_q_w_dq_mode.
333 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
336 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
337 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
338 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
339 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
340 (opcode_modifiers): Add VecSIB.
342 * i386-opc.h (CpuAVX2): New.
344 (CpuLZCNT): Likewise.
345 (CpuINVPCID): Likewise.
346 (VecSIB128): Likewise.
347 (VecSIB256): Likewise.
349 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
350 (i386_opcode_modifier): Add vecsib.
352 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
353 * i386-init.h: Regenerated.
354 * i386-tbl.h: Likewise.
356 2011-06-03 Quentin Neill <quentin.neill@amd.com>
358 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
359 * i386-init.h: Regenerated.
361 2011-06-03 Nick Clifton <nickc@redhat.com>
364 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
365 computing address offsets.
366 (print_arm_address): Likewise.
367 (print_insn_arm): Likewise.
368 (print_insn_thumb16): Likewise.
369 (print_insn_thumb32): Likewise.
371 2011-06-02 Jie Zhang <jie@codesourcery.com>
372 Nathan Sidwell <nathan@codesourcery.com>
373 Maciej Rozycki <macro@codesourcery.com>
375 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
377 (print_arm_address): Likewise. Elide positive #0 appropriately.
378 (print_insn_arm): Likewise.
380 2011-06-02 Nick Clifton <nickc@redhat.com>
383 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
384 passed to print_address_func.
386 2011-06-02 Nick Clifton <nickc@redhat.com>
388 * arm-dis.c: Fix spelling mistakes.
389 * op/opcodes.pot: Regenerate.
391 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
393 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
394 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
395 * s390-opc.txt: Fix cxr instruction type.
397 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
399 * s390-opc.c: Add new instruction types marking register pair
401 * s390-opc.txt: Match instructions having register pair operands
402 to the new instruction types.
404 2011-05-19 Nick Clifton <nickc@redhat.com>
406 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
409 2011-05-10 Quentin Neill <quentin.neill@amd.com>
411 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
412 * i386-init.h: Regenerated.
414 2011-04-27 Nick Clifton <nickc@redhat.com>
416 * po/da.po: Updated Danish translation.
418 2011-04-26 Anton Blanchard <anton@samba.org>
420 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
422 2011-04-21 DJ Delorie <dj@redhat.com>
424 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
425 * rx-decode.c: Regenerate.
427 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
429 * i386-init.h: Regenerated.
431 2011-04-19 Quentin Neill <quentin.neill@amd.com>
433 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
436 2011-04-13 Nick Clifton <nickc@redhat.com>
438 * v850-dis.c (disassemble): Always print a closing square brace if
439 an opening square brace was printed.
441 2011-04-12 Nick Clifton <nickc@redhat.com>
444 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
446 (print_insn_thumb32): Handle %L.
448 2011-04-11 Julian Brown <julian@codesourcery.com>
450 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
451 (print_insn_thumb32): Add APSR bitmask support.
453 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
455 * arm-dis.c (print_insn): init vars moved into private_data structure.
457 2011-03-24 Mike Frysinger <vapier@gentoo.org>
459 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
461 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
463 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
464 post-increment to support LPM Z+ instruction. Add support for 'E'
465 constraint for DES instruction.
466 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
468 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
470 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
472 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
474 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
475 Use branch types instead.
476 (print_insn): Likewise.
478 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
480 * mips-opc.c (mips_builtin_opcodes): Correct register use
481 annotation of "alnv.ps".
483 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
485 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
487 2011-02-22 Mike Frysinger <vapier@gentoo.org>
489 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
491 2011-02-22 Mike Frysinger <vapier@gentoo.org>
493 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
495 2011-02-19 Mike Frysinger <vapier@gentoo.org>
497 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
498 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
499 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
500 exception, end_of_registers, msize, memory, bfd_mach.
501 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
502 LB0REG, LC1REG, LT1REG, LB1REG): Delete
503 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
504 (get_allreg): Change to new defines. Fallback to abort().
506 2011-02-14 Mike Frysinger <vapier@gentoo.org>
508 * bfin-dis.c: Add whitespace/parenthesis where needed.
510 2011-02-14 Mike Frysinger <vapier@gentoo.org>
512 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
515 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
517 * configure: Regenerate.
519 2011-02-13 Mike Frysinger <vapier@gentoo.org>
521 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
523 2011-02-13 Mike Frysinger <vapier@gentoo.org>
525 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
526 dregs only when P is set, and dregs_lo otherwise.
528 2011-02-13 Mike Frysinger <vapier@gentoo.org>
530 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
532 2011-02-12 Mike Frysinger <vapier@gentoo.org>
534 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
536 2011-02-12 Mike Frysinger <vapier@gentoo.org>
538 * bfin-dis.c (machine_registers): Delete REG_GP.
539 (reg_names): Delete "GP".
540 (decode_allregs): Change REG_GP to REG_LASTREG.
542 2011-02-12 Mike Frysinger <vapier@gentoo.org>
544 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
547 2011-02-11 Mike Frysinger <vapier@gentoo.org>
549 * bfin-dis.c (reg_names): Add const.
550 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
551 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
552 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
553 decode_counters, decode_allregs): Likewise.
555 2011-02-09 Michael Snyder <msnyder@vmware.com>
557 * i386-dis.c (OP_J): Parenthesize expression to prevent
559 (print_insn): Fix indentation off-by-one.
561 2011-02-01 Nick Clifton <nickc@redhat.com>
563 * po/da.po: Updated Danish translation.
565 2011-01-21 Dave Murphy <davem@devkitpro.org>
567 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
569 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
571 * i386-dis.c (sIbT): New.
572 (b_T_mode): Likewise.
573 (dis386): Replace sIb with sIbT on "pushT".
574 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
575 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
577 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
579 * i386-init.h: Regenerated.
580 * i386-tbl.h: Regenerated
582 2011-01-17 Quentin Neill <quentin.neill@amd.com>
584 * i386-dis.c (REG_XOP_TBM_01): New.
585 (REG_XOP_TBM_02): New.
586 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
587 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
588 entries, and add bextr instruction.
590 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
591 (cpu_flags): Add CpuTBM.
593 * i386-opc.h (CpuTBM) New.
594 (i386_cpu_flags): Add bit cputbm.
596 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
597 blcs, blsfill, blsic, t1mskc, and tzmsk.
599 2011-01-12 DJ Delorie <dj@redhat.com>
601 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
603 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
605 * mips-dis.c (print_insn_args): Adjust the value to print the real
606 offset for "+c" argument.
608 2011-01-10 Nick Clifton <nickc@redhat.com>
610 * po/da.po: Updated Danish translation.
612 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
614 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
616 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
618 * i386-dis.c (REG_VEX_38F3): New.
619 (PREFIX_0FBC): Likewise.
620 (PREFIX_VEX_38F2): Likewise.
621 (PREFIX_VEX_38F3_REG_1): Likewise.
622 (PREFIX_VEX_38F3_REG_2): Likewise.
623 (PREFIX_VEX_38F3_REG_3): Likewise.
624 (PREFIX_VEX_38F7): Likewise.
625 (VEX_LEN_38F2_P_0): Likewise.
626 (VEX_LEN_38F3_R_1_P_0): Likewise.
627 (VEX_LEN_38F3_R_2_P_0): Likewise.
628 (VEX_LEN_38F3_R_3_P_0): Likewise.
629 (VEX_LEN_38F7_P_0): Likewise.
630 (dis386_twobyte): Use PREFIX_0FBC.
631 (reg_table): Add REG_VEX_38F3.
632 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
633 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
634 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
635 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
637 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
638 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
641 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
642 (cpu_flags): Add CpuBMI.
644 * i386-opc.h (CpuBMI): New.
645 (i386_cpu_flags): Add cpubmi.
647 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
648 * i386-init.h: Regenerated.
649 * i386-tbl.h: Likewise.
651 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
653 * i386-dis.c (VexGdq): New.
654 (OP_VEX): Handle dq_mode.
656 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
658 * i386-gen.c (process_copyright): Update copyright to 2011.
660 For older changes see ChangeLog-2010
666 version-control: never