1 2004-11-19 Alan Modra <amodra@bigpond.net.au>
3 * or32-opc.c (debug): Warning fix.
4 * po/POTFILES.in: Regenerate.
6 * maxq-dis.c: Formatting.
7 (print_insn): Warning fix.
9 2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
11 * arm-dis.c (WORD_ADDRESS): Define.
12 (print_insn): Use it. Correct big-endian end-of-section handling.
14 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
15 Vineet Sharma <vineets@noida.hcltech.com>
17 * maxq-dis.c: New file.
18 * disassemble.c (ARCH_maxq): Define.
19 (disassembler): Add 'print_insn_maxq_little' for handling maxq
21 * configure.in: Add case for bfd_maxq_arch.
22 * configure: Regenerate.
23 * Makefile.am: Add support for maxq-dis.c
24 * Makefile.in: Regenerate.
25 * aclocal.m4: Regenerate.
27 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
29 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
31 * crx-dis.c: Likewise.
33 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
35 Generally, handle CRISv32.
36 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
37 (struct cris_disasm_data): New type.
38 (format_reg, format_hex, cris_constraint, print_flags)
39 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
41 (format_sup_reg, print_insn_crisv32_with_register_prefix)
42 (print_insn_crisv32_without_register_prefix)
43 (print_insn_crisv10_v32_with_register_prefix)
44 (print_insn_crisv10_v32_without_register_prefix)
45 (cris_parse_disassembler_options): New functions.
46 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
47 parameter. All callers changed.
48 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
50 (cris_constraint) <case 'Y', 'U'>: New cases.
51 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
53 (print_with_operands) <case 'Y'>: New case.
54 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
55 <case 'N', 'Y', 'Q'>: New cases.
56 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
57 (print_insn_cris_with_register_prefix)
58 (print_insn_cris_without_register_prefix): Call
59 cris_parse_disassembler_options.
60 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
61 for CRISv32 and the size of immediate operands. New v32-only
62 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
63 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
64 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
65 Change brp to be v3..v10.
66 (cris_support_regs): New vector.
67 (cris_opcodes): Update head comment. New format characters '[',
68 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
69 Add new opcodes for v32 and adjust existing opcodes to accommodate
70 differences to earlier variants.
71 (cris_cond15s): New vector.
73 2004-11-04 Jan Beulich <jbeulich@novell.com>
75 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
77 (Mp): Use f_mode rather than none at all.
78 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
79 replaces what previously was x_mode; x_mode now means 128-bit SSE
81 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
82 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
83 pinsrw's second operand is Edqw.
84 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
85 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
86 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
87 mode when an operand size override is present or always suffixing.
88 More instructions will need to be added to this group.
89 (putop): Handle new macro chars 'C' (short/long suffix selector),
90 'I' (Intel mode override for following macro char), and 'J' (for
91 adding the 'l' prefix to far branches in AT&T mode). When an
92 alternative was specified in the template, honor macro character when
93 specified for Intel mode.
94 (OP_E): Handle new *_mode values. Correct pointer specifications for
95 memory operands. Consolidate output of index register.
96 (OP_G): Handle new *_mode values.
97 (OP_I): Handle const_1_mode.
98 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
99 respective opcode prefix bits have been consumed.
100 (OP_EM, OP_EX): Provide some default handling for generating pointer
103 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
105 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
108 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
110 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
111 (getregliststring): Support HI/LO and user registers.
112 * crx-opc.c (crx_instruction): Update data structure according to the
113 rearrangement done in CRX opcode header file.
114 (crx_regtab): Likewise.
115 (crx_optab): Likewise.
116 (crx_instruction): Reorder load/stor instructions, remove unsupported
118 support new Co-Processor instruction 'cpi'.
120 2004-10-27 Nick Clifton <nickc@redhat.com>
122 * opcodes/iq2000-asm.c: Regenerate.
123 * opcodes/iq2000-desc.c: Regenerate.
124 * opcodes/iq2000-desc.h: Regenerate.
125 * opcodes/iq2000-dis.c: Regenerate.
126 * opcodes/iq2000-ibld.c: Regenerate.
127 * opcodes/iq2000-opc.c: Regenerate.
128 * opcodes/iq2000-opc.h: Regenerate.
130 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
132 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
133 us4, us5 (respectively).
134 Remove unsupported 'popa' instruction.
135 Reverse operands order in store co-processor instructions.
137 2004-10-15 Alan Modra <amodra@bigpond.net.au>
139 * Makefile.am: Run "make dep-am"
140 * Makefile.in: Regenerate.
142 2004-10-12 Bob Wilson <bob.wilson@acm.org>
144 * xtensa-dis.c: Use ISO C90 formatting.
146 2004-10-09 Alan Modra <amodra@bigpond.net.au>
148 * ppc-opc.c: Revert 2004-09-09 change.
150 2004-10-07 Bob Wilson <bob.wilson@acm.org>
152 * xtensa-dis.c (state_names): Delete.
153 (fetch_data): Use xtensa_isa_maxlength.
154 (print_xtensa_operand): Replace operand parameter with opcode/operand
155 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
156 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
157 instruction bundles. Use xmalloc instead of malloc.
159 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
161 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
164 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
166 * crx-opc.c (crx_instruction): Support Co-processor insns.
167 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
168 (getregliststring): Change function to use the above enum.
169 (print_arg): Handle CO-Processor insns.
170 (crx_cinvs): Add 'b' option to invalidate the branch-target
173 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
175 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
176 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
177 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
178 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
179 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
181 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
183 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
186 2004-09-30 Paul Brook <paul@codesourcery.com>
188 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
189 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
191 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
193 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
194 (CONFIG_STATUS_DEPENDENCIES): New.
196 (config.status): Likewise.
197 * Makefile.in: Regenerated.
199 2004-09-17 Alan Modra <amodra@bigpond.net.au>
201 * Makefile.am: Run "make dep-am".
202 * Makefile.in: Regenerate.
203 * aclocal.m4: Regenerate.
204 * configure: Regenerate.
205 * po/POTFILES.in: Regenerate.
206 * po/opcodes.pot: Regenerate.
208 2004-09-11 Andreas Schwab <schwab@suse.de>
210 * configure: Rebuild.
212 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
214 * ppc-opc.c (L): Make this field not optional.
216 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
218 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
219 Fix parameter to 'm[t|f]csr' insns.
221 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
223 * configure.in: Autoupdate to autoconf 2.59.
224 * aclocal.m4: Rebuild with aclocal 1.4p6.
225 * configure: Rebuild with autoconf 2.59.
226 * Makefile.in: Rebuild with automake 1.4p6 (picking up
227 bfd changes for autoconf 2.59 on the way).
228 * config.in: Rebuild with autoheader 2.59.
230 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
232 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
234 2004-07-30 Michal Ludvig <mludvig@suse.cz>
236 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
237 (GRPPADLCK2): New define.
238 (twobyte_has_modrm): True for 0xA6.
239 (grps): GRPPADLCK2 for opcode 0xA6.
241 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
243 Introduce SH2a support.
244 * sh-opc.h (arch_sh2a_base): Renumber.
245 (arch_sh2a_nofpu_base): Remove.
246 (arch_sh_base_mask): Adjust.
247 (arch_opann_mask): New.
248 (arch_sh2a, arch_sh2a_nofpu): Adjust.
249 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
250 (sh_table): Adjust whitespace.
251 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
252 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
253 instruction list throughout.
254 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
255 of arch_sh2a in instruction list throughout.
256 (arch_sh2e_up): Accomodate above changes.
257 (arch_sh2_up): Ditto.
258 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
259 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
260 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
261 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
262 * sh-opc.h (arch_sh2a_nofpu): New.
263 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
264 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
266 2004-01-20 DJ Delorie <dj@redhat.com>
267 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
268 2003-12-29 DJ Delorie <dj@redhat.com>
269 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
270 sh_opcode_info, sh_table): Add sh2a support.
271 (arch_op32): New, to tag 32-bit opcodes.
272 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
273 2003-12-02 Michael Snyder <msnyder@redhat.com>
274 * sh-opc.h (arch_sh2a): Add.
275 * sh-dis.c (arch_sh2a): Handle.
276 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
278 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
280 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
282 2004-07-22 Nick Clifton <nickc@redhat.com>
285 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
286 insns - this is done by objdump itself.
287 * h8500-dis.c (print_insn_h8500): Likewise.
289 2004-07-21 Jan Beulich <jbeulich@novell.com>
291 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
292 regardless of address size prefix in effect.
293 (ptr_reg): Size or address registers does not depend on rex64, but
294 on the presence of an address size override.
295 (OP_MMX): Use rex.x only for xmm registers.
296 (OP_EM): Use rex.z only for xmm registers.
298 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
300 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
301 move/branch operations to the bottom so that VR5400 multimedia
302 instructions take precedence in disassembly.
304 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
306 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
307 ISA-specific "break" encoding.
309 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
311 * arm-opc.h: Fix typo in comment.
313 2004-07-11 Andreas Schwab <schwab@suse.de>
315 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
317 2004-07-09 Andreas Schwab <schwab@suse.de>
319 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
321 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
323 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
324 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
325 (crx-dis.lo): New target.
326 (crx-opc.lo): Likewise.
327 * Makefile.in: Regenerate.
328 * configure.in: Handle bfd_crx_arch.
329 * configure: Regenerate.
330 * crx-dis.c: New file.
331 * crx-opc.c: New file.
332 * disassemble.c (ARCH_crx): Define.
333 (disassembler): Handle ARCH_crx.
335 2004-06-29 James E Wilson <wilson@specifixinc.com>
337 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
338 * ia64-asmtab.c: Regnerate.
340 2004-06-28 Alan Modra <amodra@bigpond.net.au>
342 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
343 (extract_fxm): Don't test dialect.
344 (XFXFXM_MASK): Include the power4 bit.
345 (XFXM): Add p4 param.
346 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
348 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
350 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
351 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
353 2004-06-26 Alan Modra <amodra@bigpond.net.au>
355 * ppc-opc.c (BH, XLBH_MASK): Define.
356 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
358 2004-06-24 Alan Modra <amodra@bigpond.net.au>
360 * i386-dis.c (x_mode): Comment.
361 (two_source_ops): File scope.
362 (float_mem): Correct fisttpll and fistpll.
363 (float_mem_mode): New table.
365 (OP_E): Correct intel mode PTR output.
366 (ptr_reg): Use open_char and close_char.
367 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
368 operands. Set two_source_ops.
370 2004-06-15 Alan Modra <amodra@bigpond.net.au>
372 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
373 instead of _raw_size.
375 2004-06-08 Jakub Jelinek <jakub@redhat.com>
377 * ia64-gen.c (in_iclass): Handle more postinc st
379 * ia64-asmtab.c: Rebuilt.
381 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
383 * s390-opc.txt: Correct architecture mask for some opcodes.
384 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
385 in the esa mode as well.
387 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
389 * sh-dis.c (target_arch): Make unsigned.
390 (print_insn_sh): Replace (most of) switch with a call to
391 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
392 * sh-opc.h: Redefine architecture flags values.
393 Add sh3-nommu architecture.
394 Reorganise <arch>_up macros so they make more visual sense.
395 (SH_MERGE_ARCH_SET): Define new macro.
396 (SH_VALID_BASE_ARCH_SET): Likewise.
397 (SH_VALID_MMU_ARCH_SET): Likewise.
398 (SH_VALID_CO_ARCH_SET): Likewise.
399 (SH_VALID_ARCH_SET): Likewise.
400 (SH_MERGE_ARCH_SET_VALID): Likewise.
401 (SH_ARCH_SET_HAS_FPU): Likewise.
402 (SH_ARCH_SET_HAS_DSP): Likewise.
403 (SH_ARCH_UNKNOWN_ARCH): Likewise.
404 (sh_get_arch_from_bfd_mach): Add prototype.
405 (sh_get_arch_up_from_bfd_mach): Likewise.
406 (sh_get_bfd_mach_from_arch_set): Likewise.
407 (sh_merge_bfd_arc): Likewise.
409 2004-05-24 Peter Barada <peter@the-baradas.com>
411 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
412 into new match_insn_m68k function. Loop over canidate
413 matches and select first that completely matches.
414 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
415 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
416 to verify addressing for MAC/EMAC.
417 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
418 reigster halves since 'fpu' and 'spl' look misleading.
419 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
420 * m68k-opc.c: Rearragne mac/emac cases to use longest for
421 first, tighten up match masks.
422 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
423 'size' from special case code in print_insn_m68k to
424 determine decode size of insns.
426 2004-05-19 Alan Modra <amodra@bigpond.net.au>
428 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
429 well as when -mpower4.
431 2004-05-13 Nick Clifton <nickc@redhat.com>
433 * po/fr.po: Updated French translation.
435 2004-05-05 Peter Barada <peter@the-baradas.com>
437 * m68k-dis.c(print_insn_m68k): Add new chips, use core
438 variants in arch_mask. Only set m68881/68851 for 68k chips.
439 * m68k-op.c: Switch from ColdFire chips to core variants.
441 2004-05-05 Alan Modra <amodra@bigpond.net.au>
444 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
446 2004-04-29 Ben Elliston <bje@au.ibm.com>
448 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
449 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
451 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
453 * sh-dis.c (print_insn_sh): Print the value in constant pool
454 as a symbol if it looks like a symbol.
456 2004-04-22 Peter Barada <peter@the-baradas.com>
458 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
459 appropriate ColdFire architectures.
460 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
462 Add EMAC instructions, fix MAC instructions. Remove
463 macmw/macml/msacmw/msacml instructions since mask addressing now
466 2004-04-20 Jakub Jelinek <jakub@redhat.com>
468 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
469 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
470 suffix. Use fmov*x macros, create all 3 fpsize variants in one
471 macro. Adjust all users.
473 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
475 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
478 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
480 * m32r-asm.c: Regenerate.
482 2004-03-29 Stan Shebs <shebs@apple.com>
484 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
487 2004-03-19 Alan Modra <amodra@bigpond.net.au>
489 * aclocal.m4: Regenerate.
490 * config.in: Regenerate.
491 * configure: Regenerate.
492 * po/POTFILES.in: Regenerate.
493 * po/opcodes.pot: Regenerate.
495 2004-03-16 Alan Modra <amodra@bigpond.net.au>
497 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
499 * ppc-opc.c (RA0): Define.
500 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
501 (RAOPT): Rename from RAO. Update all uses.
502 (powerpc_opcodes): Use RA0 as appropriate.
504 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
506 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
508 2004-03-15 Alan Modra <amodra@bigpond.net.au>
510 * sparc-dis.c (print_insn_sparc): Update getword prototype.
512 2004-03-12 Michal Ludvig <mludvig@suse.cz>
514 * i386-dis.c (GRPPLOCK): Delete.
515 (grps): Delete GRPPLOCK entry.
517 2004-03-12 Alan Modra <amodra@bigpond.net.au>
519 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
521 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
523 (dis386): Use NOP_Fixup on "nop".
524 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
525 (twobyte_has_modrm): Set for 0xa7.
526 (padlock_table): Delete. Move to..
527 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
529 (print_insn): Revert PADLOCK_SPECIAL code.
530 (OP_E): Delete sfence, lfence, mfence checks.
532 2004-03-12 Jakub Jelinek <jakub@redhat.com>
534 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
535 (INVLPG_Fixup): New function.
536 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
538 2004-03-12 Michal Ludvig <mludvig@suse.cz>
540 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
541 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
542 (padlock_table): New struct with PadLock instructions.
543 (print_insn): Handle PADLOCK_SPECIAL.
545 2004-03-12 Alan Modra <amodra@bigpond.net.au>
547 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
548 (OP_E): Twiddle clflush to sfence here.
550 2004-03-08 Nick Clifton <nickc@redhat.com>
552 * po/de.po: Updated German translation.
554 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
556 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
557 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
558 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
561 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
563 * frv-asm.c: Regenerate.
564 * frv-desc.c: Regenerate.
565 * frv-desc.h: Regenerate.
566 * frv-dis.c: Regenerate.
567 * frv-ibld.c: Regenerate.
568 * frv-opc.c: Regenerate.
569 * frv-opc.h: Regenerate.
571 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
573 * frv-desc.c, frv-opc.c: Regenerate.
575 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
577 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
579 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
581 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
582 Also correct mistake in the comment.
584 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
586 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
587 ensure that double registers have even numbers.
588 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
589 that reserved instruction 0xfffd does not decode the same
591 * sh-opc.h: Add REG_N_D nibble type and use it whereever
592 REG_N refers to a double register.
593 Add REG_N_B01 nibble type and use it instead of REG_NM
595 Adjust the bit patterns in a few comments.
597 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
599 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
601 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
603 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
605 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
607 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
609 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
611 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
612 mtivor32, mtivor33, mtivor34.
614 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
616 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
618 2004-02-10 Petko Manolov <petkan@nucleusys.com>
620 * arm-opc.h Maverick accumulator register opcode fixes.
622 2004-02-13 Ben Elliston <bje@wasabisystems.com>
624 * m32r-dis.c: Regenerate.
626 2004-01-27 Michael Snyder <msnyder@redhat.com>
628 * sh-opc.h (sh_table): "fsrra", not "fssra".
630 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
632 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
635 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
637 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
639 2004-01-19 Alan Modra <amodra@bigpond.net.au>
641 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
642 1. Don't print scale factor on AT&T mode when index missing.
644 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
646 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
647 when loaded into XR registers.
649 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
651 * frv-desc.h: Regenerate.
652 * frv-desc.c: Regenerate.
653 * frv-opc.c: Regenerate.
655 2004-01-13 Michael Snyder <msnyder@redhat.com>
657 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
659 2004-01-09 Paul Brook <paul@codesourcery.com>
661 * arm-opc.h (arm_opcodes): Move generic mcrr after known
664 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
666 * Makefile.am (libopcodes_la_DEPENDENCIES)
667 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
668 comment about the problem.
669 * Makefile.in: Regenerate.
671 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
673 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
674 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
675 cut&paste errors in shifting/truncating numerical operands.
676 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
677 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
678 (parse_uslo16): Likewise.
679 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
680 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
681 (parse_s12): Likewise.
682 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
683 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
684 (parse_uslo16): Likewise.
685 (parse_uhi16): Parse gothi and gotfuncdeschi.
686 (parse_d12): Parse got12 and gotfuncdesc12.
687 (parse_s12): Likewise.
689 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
691 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
692 instruction which looks similar to an 'rla' instruction.
694 For older changes see ChangeLog-0203
700 version-control: never