1 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
3 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
5 * aarch64-asm.h (ins_fpimm): New inserter.
6 * aarch64-asm.c (aarch64_ins_fpimm): New function.
7 * aarch64-asm-2.c: Regenerate.
8 * aarch64-dis.h (ext_fpimm): New extractor.
9 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
10 (aarch64_ext_fpimm): New function.
11 * aarch64-dis-2.c: Regenerate.
13 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
15 * aarch64-asm.c: Include libiberty.h.
16 (insert_fields): New function.
17 (aarch64_ins_imm): Use it.
18 * aarch64-dis.c (extract_fields): New function.
19 (aarch64_ext_imm): Use it.
21 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
23 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
24 with an esize parameter.
25 (operand_general_constraint_met_p): Update accordingly.
27 * aarch64-asm.c (aarch64_ins_limm): Update call to
28 aarch64_logical_immediate_p.
30 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
32 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
34 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
36 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
38 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
40 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
42 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
44 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
45 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
46 xor3>: Delete mnemonics.
47 <cp_abort>: Rename mnemonic from ...
48 <cpabort>: ...to this.
49 <setb>: Change to a X form instruction.
50 <sync>: Change to 1 operand form.
51 <copy>: Delete mnemonic.
52 <copy_first>: Rename mnemonic from ...
54 <paste, paste.>: Delete mnemonics.
55 <paste_last>: Rename mnemonic from ...
58 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
60 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
62 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
64 * s390-mkopc.c (main): Support alternate arch strings.
66 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
68 * s390-opc.txt: Fix kmctr instruction type.
70 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
72 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
73 * i386-init.h: Regenerated.
75 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
77 * opcodes/arc-dis.c (print_insn_arc): Changed.
79 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
81 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
84 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
86 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
87 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
88 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
90 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
92 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
93 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
94 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
95 PREFIX_MOD_3_0FAE_REG_4.
96 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
97 PREFIX_MOD_3_0FAE_REG_4.
98 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
99 (cpu_flags): Add CpuPTWRITE.
100 * i386-opc.h (CpuPTWRITE): New.
101 (i386_cpu_flags): Add cpuptwrite.
102 * i386-opc.tbl: Add ptwrite instruction.
103 * i386-init.h: Regenerated.
104 * i386-tbl.h: Likewise.
106 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
108 * arc-dis.h: Wrap around in extern "C".
110 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
112 * aarch64-tbl.h (V8_2_INSN): New macro.
113 (aarch64_opcode_table): Use it.
115 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
117 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
118 CORE_INSN, __FP_INSN and SIMD_INSN.
120 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
122 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
123 (aarch64_opcode_table): Update uses accordingly.
125 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
126 Kwok Cheung Yeung <kcy@codesourcery.com>
129 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
130 'e_cmplwi' to 'e_cmpli' instead.
131 (OPVUPRT, OPVUPRT_MASK): Define.
132 (powerpc_opcodes): Add E200Z4 insns.
133 (vle_opcodes): Add context save/restore insns.
135 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
137 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
138 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
141 2016-07-27 Graham Markall <graham.markall@embecosm.com>
143 * arc-nps400-tbl.h: Change block comments to GNU format.
144 * arc-dis.c: Add new globals addrtypenames,
145 addrtypenames_max, and addtypeunknown.
146 (get_addrtype): New function.
147 (print_insn_arc): Print colons and address types when
149 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
150 define insert and extract functions for all address types.
151 (arc_operands): Add operands for colon and all address
153 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
154 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
155 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
156 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
157 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
158 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
160 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
162 * configure: Regenerated.
164 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
166 * arc-dis.c (skipclass): New structure.
167 (decodelist): New variable.
168 (is_compatible_p): New function.
169 (new_element): Likewise.
170 (skip_class_p): Likewise.
171 (find_format_from_table): Use skip_class_p function.
172 (find_format): Decode first the extension instructions.
173 (print_insn_arc): Select either ARCEM or ARCHS based on elf
175 (parse_option): New function.
176 (parse_disassembler_options): Likewise.
177 (print_arc_disassembler_options): Likewise.
178 (print_insn_arc): Use parse_disassembler_options function. Proper
179 select ARCv2 cpu variant.
180 * disassemble.c (disassembler_usage): Add ARC disassembler
183 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
185 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
186 annotation from the "nal" entry and reorder it beyond "bltzal".
188 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
190 * sparc-opc.c (ldtxa): New macro.
191 (sparc_opcodes): Use the macro defined above to add entries for
192 the LDTXA instructions.
193 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
196 2016-07-07 James Bowman <james.bowman@ftdichip.com>
198 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
201 2016-07-01 Jan Beulich <jbeulich@suse.com>
203 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
204 (movzb): Adjust to cover all permitted suffixes.
206 * i386-tbl.h: Re-generate.
208 2016-07-01 Jan Beulich <jbeulich@suse.com>
210 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
211 (lgdt): Remove Tbyte from non-64-bit variant.
212 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
213 xsaves64, xsavec64): Remove Disp16.
214 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
215 Remove Disp32S from non-64-bit variants. Remove Disp16 from
217 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
218 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
219 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
221 * i386-tbl.h: Re-generate.
223 2016-07-01 Jan Beulich <jbeulich@suse.com>
225 * i386-opc.tbl (xlat): Remove RepPrefixOk.
226 * i386-tbl.h: Re-generate.
228 2016-06-30 Yao Qi <yao.qi@linaro.org>
230 * arm-dis.c (print_insn): Fix typo in comment.
232 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
234 * aarch64-opc.c (operand_general_constraint_met_p): Check the
235 range of ldst_elemlist operands.
236 (print_register_list): Use PRIi64 to print the index.
237 (aarch64_print_operand): Likewise.
239 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
241 * mcore-opc.h: Remove sentinal.
242 * mcore-dis.c (print_insn_mcore): Adjust.
244 2016-06-23 Graham Markall <graham.markall@embecosm.com>
246 * arc-opc.c: Correct description of availability of NPS400
249 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
251 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
252 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
253 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
254 xor3>: New mnemonics.
255 <setb>: Change to a VX form instruction.
256 (insert_sh6): Add support for rldixor.
257 (extract_sh6): Likewise.
259 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
261 * arc-ext.h: Wrap in extern C.
263 2016-06-21 Graham Markall <graham.markall@embecosm.com>
265 * arc-dis.c (arc_insn_length): Add comment on instruction length.
266 Use same method for determining instruction length on ARC700 and
268 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
269 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
270 with the NPS400 subclass.
271 * arc-opc.c: Likewise.
273 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
275 * sparc-opc.c (rdasr): New macro.
281 (sparc_opcodes): Use the macros above to fix and expand the
282 definition of read/write instructions from/to
283 asr/privileged/hyperprivileged instructions.
284 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
285 %hva_mask_nz. Prefer softint_set and softint_clear over
286 set_softint and clear_softint.
287 (print_insn_sparc): Support %ver in Rd.
289 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
291 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
292 architecture according to the hardware capabilities they require.
294 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
296 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
297 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
298 bfd_mach_sparc_v9{c,d,e,v,m}.
299 * sparc-opc.c (MASK_V9C): Define.
300 (MASK_V9D): Likewise.
301 (MASK_V9E): Likewise.
302 (MASK_V9V): Likewise.
303 (MASK_V9M): Likewise.
304 (v6): Add MASK_V9{C,D,E,V,M}.
305 (v6notlet): Likewise.
309 (v9andleon): Likewise.
317 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
319 2016-06-15 Nick Clifton <nickc@redhat.com>
321 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
322 constants to match expected behaviour.
323 (nds32_parse_opcode): Likewise. Also for whitespace.
325 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
327 * arc-opc.c (extract_rhv1): Extract value from insn.
329 2016-06-14 Graham Markall <graham.markall@embecosm.com>
331 * arc-nps400-tbl.h: Add ldbit instruction.
332 * arc-opc.c: Add flag classes required for ldbit.
334 2016-06-14 Graham Markall <graham.markall@embecosm.com>
336 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
337 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
338 support the above instructions.
340 2016-06-14 Graham Markall <graham.markall@embecosm.com>
342 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
343 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
344 csma, cbba, zncv, and hofs.
345 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
346 support the above instructions.
348 2016-06-06 Graham Markall <graham.markall@embecosm.com>
350 * arc-nps400-tbl.h: Add andab and orab instructions.
352 2016-06-06 Graham Markall <graham.markall@embecosm.com>
354 * arc-nps400-tbl.h: Add addl-like instructions.
356 2016-06-06 Graham Markall <graham.markall@embecosm.com>
358 * arc-nps400-tbl.h: Add mxb and imxb instructions.
360 2016-06-06 Graham Markall <graham.markall@embecosm.com>
362 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
365 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
367 * s390-dis.c (option_use_insn_len_bits_p): New file scope
369 (init_disasm): Handle new command line option "insnlength".
370 (print_s390_disassembler_options): Mention new option in help
372 (print_insn_s390): Use the encoded insn length when dumping
373 unknown instructions.
375 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
377 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
378 to the address and set as symbol address for LDS/ STS immediate operands.
380 2016-06-07 Alan Modra <amodra@gmail.com>
382 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
383 cpu for "vle" to e500.
384 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
385 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
386 (PPCNONE): Delete, substitute throughout.
387 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
388 except for major opcode 4 and 31.
389 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
391 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
393 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
394 ARM_EXT_RAS in relevant entries.
396 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
399 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
402 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
405 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
407 Add comments for '&'.
408 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
410 (intel_operand_size): Handle indir_v_mode.
411 (OP_E_register): Likewise.
412 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
413 64-bit indirect call/jmp for AMD64.
414 * i386-tbl.h: Regenerated
416 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
418 * arc-dis.c (struct arc_operand_iterator): New structure.
419 (find_format_from_table): All the old content from find_format,
420 with some minor adjustments, and parameter renaming.
421 (find_format_long_instructions): New function.
422 (find_format): Rewritten.
423 (arc_insn_length): Add LSB parameter.
424 (extract_operand_value): New function.
425 (operand_iterator_next): New function.
426 (print_insn_arc): Use new functions to find opcode, and iterator
428 * arc-opc.c (insert_nps_3bit_dst_short): New function.
429 (extract_nps_3bit_dst_short): New function.
430 (insert_nps_3bit_src2_short): New function.
431 (extract_nps_3bit_src2_short): New function.
432 (insert_nps_bitop1_size): New function.
433 (extract_nps_bitop1_size): New function.
434 (insert_nps_bitop2_size): New function.
435 (extract_nps_bitop2_size): New function.
436 (insert_nps_bitop_mod4_msb): New function.
437 (extract_nps_bitop_mod4_msb): New function.
438 (insert_nps_bitop_mod4_lsb): New function.
439 (extract_nps_bitop_mod4_lsb): New function.
440 (insert_nps_bitop_dst_pos3_pos4): New function.
441 (extract_nps_bitop_dst_pos3_pos4): New function.
442 (insert_nps_bitop_ins_ext): New function.
443 (extract_nps_bitop_ins_ext): New function.
444 (arc_operands): Add new operands.
445 (arc_long_opcodes): New global array.
446 (arc_num_long_opcodes): New global.
447 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
449 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
451 * nds32-asm.h: Add extern "C".
452 * sh-opc.h: Likewise.
454 2016-06-01 Graham Markall <graham.markall@embecosm.com>
456 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
457 0,b,limm to the rflt instruction.
459 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
461 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
464 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
467 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
468 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
469 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
470 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
471 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
472 * i386-init.h: Regenerated.
474 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
477 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
478 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
479 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
480 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
481 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
482 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
483 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
484 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
485 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
486 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
487 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
488 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
489 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
490 CpuRegMask for AVX512.
491 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
493 (set_bitfield_from_cpu_flag_init): New function.
494 (set_bitfield): Remove const on f. Call
495 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
496 * i386-opc.h (CpuRegMMX): New.
497 (CpuRegXMM): Likewise.
498 (CpuRegYMM): Likewise.
499 (CpuRegZMM): Likewise.
500 (CpuRegMask): Likewise.
501 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
503 * i386-init.h: Regenerated.
504 * i386-tbl.h: Likewise.
506 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
509 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
510 (opcode_modifiers): Add AMD64 and Intel64.
511 (main): Properly verify CpuMax.
512 * i386-opc.h (CpuAMD64): Removed.
513 (CpuIntel64): Likewise.
514 (CpuMax): Set to CpuNo64.
515 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
518 (i386_opcode_modifier): Add amd64 and intel64.
519 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
521 * i386-init.h: Regenerated.
522 * i386-tbl.h: Likewise.
524 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
527 * i386-gen.c (main): Fail if CpuMax is incorrect.
528 * i386-opc.h (CpuMax): Set to CpuIntel64.
529 * i386-tbl.h: Regenerated.
531 2016-05-27 Nick Clifton <nickc@redhat.com>
534 * msp430-dis.c (msp430dis_read_two_bytes): New function.
535 (msp430dis_opcode_unsigned): New function.
536 (msp430dis_opcode_signed): New function.
537 (msp430_singleoperand): Use the new opcode reading functions.
538 Only disassenmble bytes if they were successfully read.
539 (msp430_doubleoperand): Likewise.
540 (msp430_branchinstr): Likewise.
541 (msp430x_callx_instr): Likewise.
542 (print_insn_msp430): Check that it is safe to read bytes before
543 attempting disassembly. Use the new opcode reading functions.
545 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
547 * ppc-opc.c (CY): New define. Document it.
548 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
550 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
552 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
553 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
554 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
555 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
557 * i386-init.h: Regenerated.
559 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
562 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
563 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
564 * i386-init.h: Regenerated.
566 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
568 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
569 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
570 * i386-init.h: Regenerated.
572 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
574 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
576 (print_insn_arc): Set insn_type information.
577 * arc-opc.c (C_CC): Add F_CLASS_COND.
578 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
579 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
580 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
581 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
582 (brne, brne_s, jeq_s, jne_s): Likewise.
584 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
586 * arc-tbl.h (neg): New instruction variant.
588 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
590 * arc-dis.c (find_format, find_format, get_auxreg)
591 (print_insn_arc): Changed.
592 * arc-ext.h (INSERT_XOP): Likewise.
594 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
596 * tic54x-dis.c (sprint_mmr): Adjust.
597 * tic54x-opc.c: Likewise.
599 2016-05-19 Alan Modra <amodra@gmail.com>
601 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
603 2016-05-19 Alan Modra <amodra@gmail.com>
605 * ppc-opc.c: Formatting.
606 (NSISIGNOPT): Define.
607 (powerpc_opcodes <subis>): Use NSISIGNOPT.
609 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
611 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
612 replacing references to `micromips_ase' throughout.
613 (_print_insn_mips): Don't use file-level microMIPS annotation to
614 determine the disassembly mode with the symbol table.
616 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
618 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
620 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
622 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
624 * mips-opc.c (D34): New macro.
625 (mips_builtin_opcodes): Define bposge32c for DSPr3.
627 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
629 * i386-dis.c (prefix_table): Add RDPID instruction.
630 * i386-gen.c (cpu_flag_init): Add RDPID flag.
631 (cpu_flags): Add RDPID bitfield.
632 * i386-opc.h (enum): Add RDPID element.
633 (i386_cpu_flags): Add RDPID field.
634 * i386-opc.tbl: Add RDPID instruction.
635 * i386-init.h: Regenerate.
636 * i386-tbl.h: Regenerate.
638 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
640 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
641 branch type of a symbol.
642 (print_insn): Likewise.
644 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
646 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
647 Mainline Security Extensions instructions.
648 (thumb_opcodes): Add entries for narrow ARMv8-M Security
649 Extensions instructions.
650 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
652 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
655 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
657 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
659 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
661 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
662 (arcExtMap_genOpcode): Likewise.
663 * arc-opc.c (arg_32bit_rc): Define new variable.
664 (arg_32bit_u6): Likewise.
665 (arg_32bit_limm): Likewise.
667 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
669 * aarch64-gen.c (VERIFIER): Define.
670 * aarch64-opc.c (VERIFIER): Define.
671 (verify_ldpsw): Use static linkage.
672 * aarch64-opc.h (verify_ldpsw): Remove.
673 * aarch64-tbl.h: Use VERIFIER for verifiers.
675 2016-04-28 Nick Clifton <nickc@redhat.com>
678 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
679 * aarch64-opc.c (verify_ldpsw): New function.
680 * aarch64-opc.h (verify_ldpsw): New prototype.
681 * aarch64-tbl.h: Add initialiser for verifier field.
682 (LDPSW): Set verifier to verify_ldpsw.
684 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
688 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
689 smaller than address size.
691 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
693 * alpha-dis.c: Regenerate.
694 * crx-dis.c: Likewise.
695 * disassemble.c: Likewise.
696 * epiphany-opc.c: Likewise.
697 * fr30-opc.c: Likewise.
698 * frv-opc.c: Likewise.
699 * ip2k-opc.c: Likewise.
700 * iq2000-opc.c: Likewise.
701 * lm32-opc.c: Likewise.
702 * lm32-opinst.c: Likewise.
703 * m32c-opc.c: Likewise.
704 * m32r-opc.c: Likewise.
705 * m32r-opinst.c: Likewise.
706 * mep-opc.c: Likewise.
707 * mt-opc.c: Likewise.
708 * or1k-opc.c: Likewise.
709 * or1k-opinst.c: Likewise.
710 * tic80-opc.c: Likewise.
711 * xc16x-opc.c: Likewise.
712 * xstormy16-opc.c: Likewise.
714 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
716 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
717 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
718 calcsd, and calcxd instructions.
719 * arc-opc.c (insert_nps_bitop_size): Delete.
720 (extract_nps_bitop_size): Delete.
721 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
722 (extract_nps_qcmp_m3): Define.
723 (extract_nps_qcmp_m2): Define.
724 (extract_nps_qcmp_m1): Define.
725 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
726 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
727 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
728 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
729 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
732 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
734 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
736 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
738 * Makefile.in: Regenerated with automake 1.11.6.
739 * aclocal.m4: Likewise.
741 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
743 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
745 * arc-opc.c (insert_nps_cmem_uimm16): New function.
746 (extract_nps_cmem_uimm16): New function.
747 (arc_operands): Add NPS_XLDST_UIMM16 operand.
749 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
751 * arc-dis.c (arc_insn_length): New function.
752 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
753 (find_format): Change insnLen parameter to unsigned.
755 2016-04-13 Nick Clifton <nickc@redhat.com>
758 * v850-opc.c (v850_opcodes): Correct masks for long versions of
759 the LD.B and LD.BU instructions.
761 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
763 * arc-dis.c (find_format): Check for extension flags.
764 (print_flags): New function.
765 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
767 * arc-ext.c (arcExtMap_coreRegName): Use
768 LAST_EXTENSION_CORE_REGISTER.
769 (arcExtMap_coreReadWrite): Likewise.
770 (dump_ARC_extmap): Update printing.
771 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
772 (arc_aux_regs): Add cpu field.
773 * arc-regs.h: Add cpu field, lower case name aux registers.
775 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
777 * arc-tbl.h: Add rtsc, sleep with no arguments.
779 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
781 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
783 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
784 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
785 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
786 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
787 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
788 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
789 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
790 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
791 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
792 (arc_opcode arc_opcodes): Null terminate the array.
793 (arc_num_opcodes): Remove.
794 * arc-ext.h (INSERT_XOP): Define.
795 (extInstruction_t): Likewise.
796 (arcExtMap_instName): Delete.
797 (arcExtMap_insn): New function.
798 (arcExtMap_genOpcode): Likewise.
799 * arc-ext.c (ExtInstruction): Remove.
800 (create_map): Zero initialize instruction fields.
801 (arcExtMap_instName): Remove.
802 (arcExtMap_insn): New function.
803 (dump_ARC_extmap): More info while debuging.
804 (arcExtMap_genOpcode): New function.
805 * arc-dis.c (find_format): New function.
806 (print_insn_arc): Use find_format.
807 (arc_get_disassembler): Enable dump_ARC_extmap only when
810 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
812 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
813 instruction bits out.
815 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
817 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
818 * arc-opc.c (arc_flag_operands): Add new flags.
819 (arc_flag_classes): Add new classes.
821 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
823 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
825 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
827 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
828 encode1, rflt, crc16, and crc32 instructions.
829 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
830 (arc_flag_classes): Add C_NPS_R.
831 (insert_nps_bitop_size_2b): New function.
832 (extract_nps_bitop_size_2b): Likewise.
833 (insert_nps_bitop_uimm8): Likewise.
834 (extract_nps_bitop_uimm8): Likewise.
835 (arc_operands): Add new operand entries.
837 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
839 * arc-regs.h: Add a new subclass field. Add double assist
840 accumulator register values.
841 * arc-tbl.h: Use DPA subclass to mark the double assist
842 instructions. Use DPX/SPX subclas to mark the FPX instructions.
843 * arc-opc.c (RSP): Define instead of SP.
844 (arc_aux_regs): Add the subclass field.
846 2016-04-05 Jiong Wang <jiong.wang@arm.com>
848 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
850 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
852 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
855 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
857 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
858 issues. No functional changes.
860 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
862 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
863 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
864 (RTT): Remove duplicate.
865 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
866 (PCT_CONFIG*): Remove.
867 (D1L, D1H, D2H, D2L): Define.
869 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
871 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
873 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
875 * arc-tbl.h (invld07): Remove.
876 * arc-ext-tbl.h: New file.
877 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
878 * arc-opc.c (arc_opcodes): Add ext-tbl include.
880 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
882 Fix -Wstack-usage warnings.
883 * aarch64-dis.c (print_operands): Substitute size.
884 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
886 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
888 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
889 to get a proper diagnostic when an invalid ASR register is used.
891 2016-03-22 Nick Clifton <nickc@redhat.com>
893 * configure: Regenerate.
895 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
897 * arc-nps400-tbl.h: New file.
898 * arc-opc.c: Add top level comment.
899 (insert_nps_3bit_dst): New function.
900 (extract_nps_3bit_dst): New function.
901 (insert_nps_3bit_src2): New function.
902 (extract_nps_3bit_src2): New function.
903 (insert_nps_bitop_size): New function.
904 (extract_nps_bitop_size): New function.
905 (arc_flag_operands): Add nps400 entries.
906 (arc_flag_classes): Add nps400 entries.
907 (arc_operands): Add nps400 entries.
908 (arc_opcodes): Add nps400 include.
910 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
912 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
913 the new class enum values.
915 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
917 * arc-dis.c (print_insn_arc): Handle nps400.
919 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
921 * arc-opc.c (BASE): Delete.
923 2016-03-18 Nick Clifton <nickc@redhat.com>
926 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
927 of MOV insn that aliases an ORR insn.
929 2016-03-16 Jiong Wang <jiong.wang@arm.com>
931 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
933 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
935 * mcore-opc.h: Add const qualifiers.
936 * microblaze-opc.h (struct op_code_struct): Likewise.
937 * sh-opc.h: Likewise.
938 * tic4x-dis.c (tic4x_print_indirect): Likewise.
939 (tic4x_print_op): Likewise.
941 2016-03-02 Alan Modra <amodra@gmail.com>
943 * or1k-desc.h: Regenerate.
944 * fr30-ibld.c: Regenerate.
945 * rl78-decode.c: Regenerate.
947 2016-03-01 Nick Clifton <nickc@redhat.com>
950 * rl78-dis.c (print_insn_rl78_common): Fix typo.
952 2016-02-24 Renlin Li <renlin.li@arm.com>
954 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
955 (print_insn_coprocessor): Support fp16 instructions.
957 2016-02-24 Renlin Li <renlin.li@arm.com>
959 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
962 2016-02-24 Renlin Li <renlin.li@arm.com>
964 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
965 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
967 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
969 * i386-dis.c (print_insn): Parenthesize expression to prevent
973 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
974 Janek van Oirschot <jvanoirs@synopsys.com>
976 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
979 2016-02-04 Nick Clifton <nickc@redhat.com>
982 * msp430-dis.c (print_insn_msp430): Add a special case for
983 decoding an RRC instruction with the ZC bit set in the extension
986 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
988 * cgen-ibld.in (insert_normal): Rework calculation of shift.
989 * epiphany-ibld.c: Regenerate.
990 * fr30-ibld.c: Regenerate.
991 * frv-ibld.c: Regenerate.
992 * ip2k-ibld.c: Regenerate.
993 * iq2000-ibld.c: Regenerate.
994 * lm32-ibld.c: Regenerate.
995 * m32c-ibld.c: Regenerate.
996 * m32r-ibld.c: Regenerate.
997 * mep-ibld.c: Regenerate.
998 * mt-ibld.c: Regenerate.
999 * or1k-ibld.c: Regenerate.
1000 * xc16x-ibld.c: Regenerate.
1001 * xstormy16-ibld.c: Regenerate.
1003 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1005 * epiphany-dis.c: Regenerated from latest cpu files.
1007 2016-02-01 Michael McConville <mmcco@mykolab.com>
1009 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1012 2016-01-25 Renlin Li <renlin.li@arm.com>
1014 * arm-dis.c (mapping_symbol_for_insn): New function.
1015 (find_ifthen_state): Call mapping_symbol_for_insn().
1017 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1019 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1020 of MSR UAO immediate operand.
1022 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1024 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1025 instruction support.
1027 2016-01-17 Alan Modra <amodra@gmail.com>
1029 * configure: Regenerate.
1031 2016-01-14 Nick Clifton <nickc@redhat.com>
1033 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1034 instructions that can support stack pointer operations.
1035 * rl78-decode.c: Regenerate.
1036 * rl78-dis.c: Fix display of stack pointer in MOVW based
1039 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1041 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1042 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1043 erxtatus_el1 and erxaddr_el1.
1045 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1047 * arm-dis.c (arm_opcodes): Add "esb".
1048 (thumb_opcodes): Likewise.
1050 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1052 * ppc-opc.c <xscmpnedp>: Delete.
1053 <xvcmpnedp>: Likewise.
1054 <xvcmpnedp.>: Likewise.
1055 <xvcmpnesp>: Likewise.
1056 <xvcmpnesp.>: Likewise.
1058 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1061 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1064 2016-01-01 Alan Modra <amodra@gmail.com>
1066 Update year range in copyright notice of all files.
1068 For older changes see ChangeLog-2015
1070 Copyright (C) 2016 Free Software Foundation, Inc.
1072 Copying and distribution of this file, with or without modification,
1073 are permitted in any medium without royalty provided the copyright
1074 notice and this notice are preserved.
1080 version-control: never