1 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips16-opc.c (mips16_opcodes): Reformat.
5 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
7 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
8 for operands that are hard-coded to $0.
9 * micromips-opc.c (micromips_opcodes): Likewise.
11 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
13 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
14 for the single-operand forms of JALR and JALR.HB.
15 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
18 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
20 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
21 instructions. Fix them to use WR_MACC instead of WR_CC and
24 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
26 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
28 2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
30 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
32 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
33 Alexander Ivchenko <alexander.ivchenko@intel.com>
34 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
35 Sergey Lega <sergey.s.lega@intel.com>
36 Anna Tikhonova <anna.tikhonova@intel.com>
37 Ilya Tocar <ilya.tocar@intel.com>
38 Andrey Turetskiy <andrey.turetskiy@intel.com>
39 Ilya Verbin <ilya.verbin@intel.com>
40 Kirill Yukhin <kirill.yukhin@intel.com>
41 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
43 * i386-dis-evex.h: New.
44 * i386-dis.c (OP_Rounding): New.
51 (EXEvexHalfBcstXmmq): New.
63 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
64 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
65 evex_rounding_mode, evex_sae_mode, mask_mode.
66 (USE_EVEX_TABLE): New.
69 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
71 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
72 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
73 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
74 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
75 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
76 MOD_EVEX_0F38C7_REG_6.
77 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
78 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
79 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
80 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
81 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
82 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
83 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
84 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
85 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
86 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
87 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
88 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
89 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
90 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
91 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
92 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
93 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
94 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
95 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
96 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
97 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
98 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
99 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
100 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
101 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
102 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
103 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
104 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
105 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
106 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
107 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
108 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
109 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
110 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
111 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
112 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
113 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
114 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
115 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
116 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
117 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
118 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
119 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
120 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
121 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
122 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
123 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
124 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
125 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
126 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
127 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
128 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
129 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
130 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
131 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
132 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
133 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
134 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
135 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
136 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
137 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
138 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
139 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
140 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
141 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
142 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
143 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
144 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
145 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
146 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
147 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
148 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
149 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
150 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
151 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
152 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
154 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
155 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
156 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
157 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
158 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
159 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
160 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
161 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
162 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
163 VEX_W_0F3A32_P_2_LEN_0.
164 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
165 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
166 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
167 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
168 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
169 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
170 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
171 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
172 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
173 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
174 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
175 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
176 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
177 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
178 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
179 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
180 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
181 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
182 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
183 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
184 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
185 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
186 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
187 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
188 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
189 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
190 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
191 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
192 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
193 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
194 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
195 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
196 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
197 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
198 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
199 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
200 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
201 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
202 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
203 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
204 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
205 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
206 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
207 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
208 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
209 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
210 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
211 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
212 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
213 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
214 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
215 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
216 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
217 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
218 (struct vex): Add fields evex, r, v, mask_register_specifier,
220 (intel_names_xmm): Add upper 16 registers.
221 (att_names_xmm): Ditto.
222 (intel_names_ymm): Ditto.
223 (att_names_ymm): Ditto.
225 (intel_names_zmm): Ditto.
226 (att_names_zmm): Ditto.
228 (intel_names_mask): Ditto.
229 (att_names_mask): Ditto.
230 (names_rounding): Ditto.
231 (names_broadcast): Ditto.
232 (x86_64_table): Add escape to evex-table.
233 (reg_table): Include reg_table evex-entries from
234 i386-dis-evex.h. Fix prefetchwt1 instruction.
235 (prefix_table): Add entries for new instructions.
237 (vex_len_table): Ditto.
238 (vex_w_table): Ditto.
240 (get_valid_dis386): Properly handle new instructions.
241 (print_insn): Handle zmm and mask registers, print mask operand.
242 (intel_operand_size): Support EVEX, new modes and sizes.
243 (OP_E_register): Handle new modes.
244 (OP_E_memory): Ditto.
249 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
250 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
251 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
252 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
253 CpuAVX512PF and CpuVREX.
254 (operand_type_init): Add OPERAND_TYPE_REGZMM,
255 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
256 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
257 StaticRounding, SAE, Disp8MemShift, NoDefMask.
258 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
259 * i386-init.h: Regenerate.
260 * i386-opc.h (CpuAVX512F): New.
265 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
266 cpuavx512pf and cpuvrex fields.
267 (VecSIB): Add VecSIB512.
272 (StaticRounding): New.
274 (Disp8MemShift): New.
276 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
277 staticrounding, sae, disp8memshift and nodefmask.
281 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
284 * i386-opc.tbl: Add AVX512 instructions.
285 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
286 registers, mask registers.
287 * i386-tbl.h: Regenerate.
289 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
292 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
293 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
295 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
297 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
298 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
300 (prefix_table): Updated.
301 (three_byte_table): Likewise.
302 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
303 (cpu_flags): Add CpuSHA.
304 (i386_cpu_flags): Add cpusha.
305 * i386-init.h: Regenerate.
306 * i386-opc.h (CpuSHA): New.
307 (CpuUnused): Restored.
308 (i386_cpu_flags): Add cpusha.
309 * i386-opc.tbl: Add SHA instructions.
310 * i386-tbl.h: Regenerate.
312 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
313 Kirill Yukhin <kirill.yukhin@intel.com>
314 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
316 * i386-dis.c (BND_Fixup): New.
323 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
325 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
326 (dis tables): Replace XX with BND for near branch and call
328 (prefix_table): Add new entries.
329 (mod_table): Likewise.
331 (intel_names_bnd): New.
332 (att_names_bnd): New.
334 (prefix_name): Handle BND_PREFIX.
335 (print_insn): Initialize names_bnd.
336 (intel_operand_size): Handle new modes.
337 (OP_E_register): Likewise.
338 (OP_E_memory): Likewise.
340 * i386-gen.c (cpu_flag_init): Add CpuMPX.
341 (cpu_flags): Add CpuMPX.
342 (operand_type_init): Add RegBND.
343 (opcode_modifiers): Add BNDPrefixOk.
344 (operand_types): Add RegBND.
345 * i386-init.h: Regenerate.
346 * i386-opc.h (CpuMPX): New.
347 (CpuUnused): Comment out.
348 (i386_cpu_flags): Add cpumpx.
350 (i386_opcode_modifier): Add bndprefixok.
352 (i386_operand_type): Add regbnd.
353 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
354 Add MPX instructions and bnd prefix.
355 * i386-reg.tbl: Add bnd0-bnd3 registers.
356 * i386-tbl.h: Regenerate.
358 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
360 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
363 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
365 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
367 * Makefile.in: Regenerate.
368 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
369 all fields. Reformat.
371 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
373 * mips16-opc.c: Include mips-formats.h.
374 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
376 (decode_mips16_operand): New function.
377 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
378 (print_insn_arg): Handle OP_ENTRY_EXIT list.
379 Abort for OP_SAVE_RESTORE_LIST.
380 (print_mips16_insn_arg): Change interface. Use mips_operand
381 structures. Delete GET_OP_S. Move GET_OP definition to...
382 (print_insn_mips16): ...here. Call init_print_arg_state.
383 Update the call to print_mips16_insn_arg.
385 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
387 * mips-formats.h: New file.
388 * mips-opc.c: Include mips-formats.h.
389 (reg_0_map): New static array.
390 (decode_mips_operand): New function.
391 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
392 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
393 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
394 (int_c_map): New static arrays.
395 (decode_micromips_operand): New function.
396 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
397 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
398 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
399 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
400 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
401 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
402 (micromips_imm_b_map, micromips_imm_c_map): Delete.
403 (print_reg): New function.
404 (mips_print_arg_state): New structure.
405 (init_print_arg_state, print_insn_arg): New functions.
406 (print_insn_args): Change interface and use mips_operand structures.
407 Delete GET_OP_S. Move GET_OP definition to...
408 (print_insn_mips): ...here. Update the call to print_insn_args.
409 (print_insn_micromips): Use print_insn_args.
411 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
413 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
416 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
418 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
419 ADDA.S, MULA.S and SUBA.S.
421 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
424 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
425 * i386-tbl.h: Regenerated.
427 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
429 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
430 and SD A(B) macros up.
431 * micromips-opc.c (micromips_opcodes): Likewise.
433 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
435 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
438 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
440 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
441 MDMX-like instructions.
442 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
443 printing "Q" operands for INSN_5400 instructions.
445 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
447 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
449 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
452 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
454 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
456 * mips16-opc.c (mips16_opcodes): Likewise.
457 * micromips-opc.c (micromips_opcodes): Likewise.
458 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
459 (print_insn_mips16): Handle "+i".
460 (print_insn_micromips): Likewise. Conditionally preserve the
461 ISA bit for "a" but not for "+i".
463 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
465 * micromips-opc.c (WR_mhi): Rename to..
467 (micromips_opcodes): Update "movep" entry accordingly. Replace
469 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
470 (micromips_to_32_reg_h_map1): ...this.
471 (micromips_to_32_reg_i_map): Rename to...
472 (micromips_to_32_reg_h_map2): ...this.
473 (print_micromips_insn): Remove "mi" case. Print both registers
474 in the pair for "mh".
476 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
478 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
479 * micromips-opc.c (micromips_opcodes): Likewise.
480 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
481 and "+T" handling. Check for a "0" suffix when deciding whether to
482 use coprocessor 0 names. In that case, also check for ",H" selectors.
484 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
486 * s390-opc.c (J12_12, J24_24): New macros.
487 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
488 (MASK_MII_UPI): Rename to MASK_MII_UPP.
489 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
491 2013-07-04 Alan Modra <amodra@gmail.com>
493 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
495 2013-06-26 Nick Clifton <nickc@redhat.com>
497 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
498 field when checking for type 2 nop.
499 * rx-decode.c: Regenerate.
501 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
503 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
506 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
508 * mips-dis.c (is_mips16_plt_tail): New function.
509 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
511 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
513 2013-06-21 DJ Delorie <dj@redhat.com>
515 * msp430-decode.opc: New.
516 * msp430-decode.c: New/generated.
517 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
518 (MAINTAINER_CLEANFILES): Likewise.
519 Add rule to build msp430-decode.c frommsp430decode.opc
520 using the opc2c program.
521 * Makefile.in: Regenerate.
522 * configure.in: Add msp430-decode.lo to msp430 architecture files.
523 * configure: Regenerate.
525 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
527 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
528 (SYMTAB_AVAILABLE): Removed.
529 (#include "elf/aarch64.h): Ditto.
531 2013-06-17 Catherine Moore <clm@codesourcery.com>
532 Maciej W. Rozycki <macro@codesourcery.com>
533 Chao-Ying Fu <fu@mips.com>
535 * micromips-opc.c (EVA): Define.
537 (micromips_opcodes): Add EVA opcodes.
538 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
539 (print_insn_args): Handle EVA offsets.
540 (print_insn_micromips): Likewise.
541 * mips-opc.c (EVA): Define.
543 (mips_builtin_opcodes): Add EVA opcodes.
545 2013-06-17 Alan Modra <amodra@gmail.com>
547 * Makefile.am (mips-opc.lo): Add rules to create automatic
548 dependency files. Pass archdefs.
549 (micromips-opc.lo, mips16-opc.lo): Likewise.
550 * Makefile.in: Regenerate.
552 2013-06-14 DJ Delorie <dj@redhat.com>
554 * rx-decode.opc (rx_decode_opcode): Bit operations on
555 registers are 32-bit operations, not 8-bit operations.
556 * rx-decode.c: Regenerate.
558 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
560 * micromips-opc.c (IVIRT): New define.
561 (IVIRT64): New define.
562 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
563 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
565 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
566 dmtgc0 to print cp0 names.
568 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
570 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
573 2013-06-08 Catherine Moore <clm@codesourcery.com>
574 Richard Sandiford <rdsandiford@googlemail.com>
576 * micromips-opc.c (D32, D33, MC): Update definitions.
577 (micromips_opcodes): Initialize ase field.
578 * mips-dis.c (mips_arch_choice): Add ase field.
579 (mips_arch_choices): Initialize ase field.
580 (set_default_mips_dis_options): Declare and setup mips_ase.
581 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
582 MT32, MC): Update definitions.
583 (mips_builtin_opcodes): Initialize ase field.
585 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
587 * s390-opc.txt (flogr): Require a register pair destination.
589 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
591 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
594 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
596 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
598 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
600 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
601 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
602 XLS_MASK, PPCVSX2): New defines.
603 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
604 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
605 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
606 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
607 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
608 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
609 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
610 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
611 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
612 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
613 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
614 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
615 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
616 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
617 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
618 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
619 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
620 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
621 <lxvx, stxvx>: New extended mnemonics.
623 2013-05-17 Alan Modra <amodra@gmail.com>
625 * ia64-raw.tbl: Replace non-ASCII char.
626 * ia64-waw.tbl: Likewise.
627 * ia64-asmtab.c: Regenerate.
629 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
631 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
632 * i386-init.h: Regenerated.
634 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
636 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
637 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
638 check from [0, 255] to [-128, 255].
640 2013-05-09 Andrew Pinski <apinski@cavium.com>
642 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
643 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
644 (parse_mips_dis_option): Handle the virt option.
645 (print_insn_args): Handle "+J".
646 (print_mips_disassembler_options): Print out message about virt64.
647 * mips-opc.c (IVIRT): New define.
648 (IVIRT64): New define.
649 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
650 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
651 Move rfe to the bottom as it conflicts with tlbgp.
653 2013-05-09 Alan Modra <amodra@gmail.com>
655 * ppc-opc.c (extract_vlesi): Properly sign extend.
656 (extract_vlensi): Likewise. Comment reason for setting invalid.
658 2013-05-02 Nick Clifton <nickc@redhat.com>
660 * msp430-dis.c: Add support for MSP430X instructions.
662 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
664 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
667 2013-04-17 Wei-chen Wang <cole945@gmail.com>
670 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
672 (hash_insns_list): Likewise.
674 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
676 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
679 2013-04-08 Jan Beulich <jbeulich@suse.com>
681 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
682 * i386-tbl.h: Re-generate.
684 2013-04-06 David S. Miller <davem@davemloft.net>
686 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
687 of an opcode, prefer the one with F_PREFERRED set.
688 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
689 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
690 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
691 mark existing mnenomics as aliases. Add "cc" suffix to edge
692 instructions generating condition codes, mark existing mnenomics
693 as aliases. Add "fp" prefix to VIS compare instructions, mark
694 existing mnenomics as aliases.
696 2013-04-03 Nick Clifton <nickc@redhat.com>
698 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
699 destination address by subtracting the operand from the current
701 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
702 a positive value in the insn.
703 (extract_u16_loop): Do not negate the returned value.
704 (D16_LOOP): Add V850_INVERSE_PCREL flag.
706 (ceilf.sw): Remove duplicate entry.
707 (cvtf.hs): New entry.
713 (maddf.s): Restrict to E3V5 architectures.
715 (nmaddf.s): Likewise.
716 (nmsubf.s): Likewise.
718 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
720 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
722 (print_insn): Pass sizeflag to get_sib.
724 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
727 * tic6x-dis.c: Add support for displaying 16-bit insns.
729 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
732 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
733 individual msb and lsb halves in src1 & src2 fields. Discard the
734 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
735 follow what Ti SDK does in that case as any value in the src1
736 field yields the same output with SDK disassembler.
738 2013-03-12 Michael Eager <eager@eagercon.com>
740 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
742 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
744 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
746 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
748 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
750 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
752 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
754 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
756 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
757 (thumb32_opcodes): Likewise.
758 (print_insn_thumb32): Handle 'S' control char.
760 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
762 * lm32-desc.c: Regenerate.
764 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
766 * i386-reg.tbl (riz): Add RegRex64.
767 * i386-tbl.h: Regenerated.
769 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
771 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
772 (aarch64_feature_crc): New static.
774 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
775 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
776 * aarch64-asm-2.c: Re-generate.
777 * aarch64-dis-2.c: Ditto.
778 * aarch64-opc-2.c: Ditto.
780 2013-02-27 Alan Modra <amodra@gmail.com>
782 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
783 * rl78-decode.c: Regenerate.
785 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
787 * rl78-decode.opc: Fix encoding of DIVWU insn.
788 * rl78-decode.c: Regenerate.
790 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
793 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
795 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
796 (cpu_flags): Add CpuSMAP.
798 * i386-opc.h (CpuSMAP): New.
799 (i386_cpu_flags): Add cpusmap.
801 * i386-opc.tbl: Add clac and stac.
803 * i386-init.h: Regenerated.
804 * i386-tbl.h: Likewise.
806 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
808 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
809 which also makes the disassembler output be in little
810 endian like it should be.
812 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
814 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
816 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
818 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
820 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
821 section disassembled.
823 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
825 * arm-dis.c: Update strht pattern.
827 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
829 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
830 single-float. Disable ll, lld, sc and scd for EE. Disable the
831 trunc.w.s macro for EE.
833 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
834 Andrew Jenner <andrew@codesourcery.com>
836 Based on patches from Altera Corporation.
838 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
840 * Makefile.in: Regenerated.
841 * configure.in: Add case for bfd_nios2_arch.
842 * configure: Regenerated.
843 * disassemble.c (ARCH_nios2): Define.
844 (disassembler): Add case for bfd_arch_nios2.
845 * nios2-dis.c: New file.
846 * nios2-opc.c: New file.
848 2013-02-04 Alan Modra <amodra@gmail.com>
850 * po/POTFILES.in: Regenerate.
851 * rl78-decode.c: Regenerate.
852 * rx-decode.c: Regenerate.
854 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
856 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
857 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
858 * aarch64-asm.c (convert_xtl_to_shll): New function.
859 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
860 calling convert_xtl_to_shll.
861 * aarch64-dis.c (convert_shll_to_xtl): New function.
862 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
863 calling convert_shll_to_xtl.
864 * aarch64-gen.c: Update copyright year.
865 * aarch64-asm-2.c: Re-generate.
866 * aarch64-dis-2.c: Re-generate.
867 * aarch64-opc-2.c: Re-generate.
869 2013-01-24 Nick Clifton <nickc@redhat.com>
871 * v850-dis.c: Add support for e3v5 architecture.
872 * v850-opc.c: Likewise.
874 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
876 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
877 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
878 * aarch64-opc.c (operand_general_constraint_met_p): For
879 AARCH64_MOD_LSL, move the range check on the shift amount before the
880 alignment check; change to call set_sft_amount_out_of_range_error
881 instead of set_imm_out_of_range_error.
882 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
883 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
884 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
887 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
889 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
891 * i386-init.h: Regenerated.
892 * i386-tbl.h: Likewise.
894 2013-01-15 Nick Clifton <nickc@redhat.com>
896 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
898 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
900 2013-01-14 Will Newton <will.newton@imgtec.com>
902 * metag-dis.c (REG_WIDTH): Increase to 64.
904 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
906 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
907 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
908 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
910 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
911 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
912 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
913 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
915 2013-01-10 Will Newton <will.newton@imgtec.com>
917 * Makefile.am: Add Meta.
918 * configure.in: Add Meta.
919 * disassemble.c: Add Meta support.
920 * metag-dis.c: New file.
921 * Makefile.in: Regenerate.
922 * configure: Regenerate.
924 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
926 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
927 (match_opcode): Rename to cr16_match_opcode.
929 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
931 * mips-dis.c: Add names for CP0 registers of r5900.
932 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
933 instructions sq and lq.
934 Add support for MIPS r5900 CPU.
935 Add support for 128 bit MMI (Multimedia Instructions).
936 Add support for EE instructions (Emotion Engine).
937 Disable unsupported floating point instructions (64 bit and
938 undefined compare operations).
939 Enable instructions of MIPS ISA IV which are supported by r5900.
940 Disable 64 bit co processor instructions.
941 Disable 64 bit multiplication and division instructions.
942 Disable instructions for co-processor 2 and 3, because these are
943 not supported (preparation for later VU0 support (Vector Unit)).
944 Disable cvt.w.s because this behaves like trunc.w.s and the
945 correct execution can't be ensured on r5900.
946 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
947 will confuse less developers and compilers.
949 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
951 * aarch64-opc.c (aarch64_print_operand): Change to print
952 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
954 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
955 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
958 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
960 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
961 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
963 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
965 * i386-gen.c (process_copyright): Update copyright year to 2013.
967 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
969 * cr16-dis.c (match_opcode,make_instruction): Remove static
971 (dwordU,wordU): Moved typedefs to opcode/cr16.h
972 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
974 For older changes see ChangeLog-2012
976 Copyright (C) 2013 Free Software Foundation, Inc.
978 Copying and distribution of this file, with or without modification,
979 are permitted in any medium without royalty provided the copyright
980 notice and this notice are preserved.
986 version-control: never