1 2018-09-13 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
5 * i386-tbl.h: Re-generate.
7 2018-09-13 Jan Beulich <jbeulich@suse.com>
9 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
11 * i386-tbl.h: Re-generate.
13 2018-09-13 Jan Beulich <jbeulich@suse.com>
15 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
16 * i386-tbl.h: Re-generate.
18 2018-09-13 Jan Beulich <jbeulich@suse.com>
20 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
21 * i386-tbl.h: Re-generate.
23 2018-09-13 Jan Beulich <jbeulich@suse.com>
25 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
27 * i386-tbl.h: Re-generate.
29 2018-09-13 Jan Beulich <jbeulich@suse.com>
31 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
33 * i386-tbl.h: Re-generate.
35 2018-09-13 Jan Beulich <jbeulich@suse.com>
37 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
38 * i386-tbl.h: Re-generate.
40 2018-09-13 Jan Beulich <jbeulich@suse.com>
42 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
43 * i386-tbl.h: Re-generate.
45 2018-09-13 Jan Beulich <jbeulich@suse.com>
47 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
48 * i386-tbl.h: Re-generate.
50 2018-09-13 Jan Beulich <jbeulich@suse.com>
52 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
54 * i386-tbl.h: Re-generate.
56 2018-09-13 Jan Beulich <jbeulich@suse.com>
58 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
60 * i386-tbl.h: Re-generate.
62 2018-09-13 Jan Beulich <jbeulich@suse.com>
64 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
66 * i386-tbl.h: Re-generate.
68 2018-09-13 Jan Beulich <jbeulich@suse.com>
70 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
71 * i386-tbl.h: Re-generate.
73 2018-09-13 Jan Beulich <jbeulich@suse.com>
75 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
76 * i386-tbl.h: Re-generate.
78 2018-09-13 Jan Beulich <jbeulich@suse.com>
80 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
81 * i386-tbl.h: Re-generate.
83 2018-09-13 Jan Beulich <jbeulich@suse.com>
85 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
86 (vpbroadcastw, rdpid): Drop NoRex64.
87 * i386-tbl.h: Re-generate.
89 2018-09-13 Jan Beulich <jbeulich@suse.com>
91 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
92 store templates, adding D.
93 * i386-tbl.h: Re-generate.
95 2018-09-13 Jan Beulich <jbeulich@suse.com>
97 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
98 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
99 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
100 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
101 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
102 Fold load and store templates where possible, adding D. Drop
103 IgnoreSize where it was pointlessly present. Drop redundant
105 * i386-tbl.h: Re-generate.
107 2018-09-13 Jan Beulich <jbeulich@suse.com>
109 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
110 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
111 (intel_operand_size): Handle v_bndmk_mode.
112 (OP_E_memory): Likewise. Produce (bad) when also riprel.
114 2018-09-08 John Darrington <john@darrington.wattle.id.au>
116 * disassemble.c (ARCH_s12z): Define if ARCH_all.
118 2018-08-31 Kito Cheng <kito@andestech.com>
120 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
121 compressed floating point instructions.
123 2018-08-30 Kito Cheng <kito@andestech.com>
125 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
126 riscv_opcode.xlen_requirement.
127 * riscv-opc.c (riscv_opcodes): Update for struct change.
129 2018-08-29 Martin Aberg <maberg@gaisler.com>
131 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
132 psr (PWRPSR) instruction.
134 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
136 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
138 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
140 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
142 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
144 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
145 loongson3a as an alias of gs464 for compatibility.
146 * mips-opc.c (mips_opcodes): Change Comments.
148 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
150 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
152 (print_mips_disassembler_options): Document -M loongson-ext.
153 * mips-opc.c (LEXT2): New macro.
154 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
156 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
158 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
160 (parse_mips_ase_option): Handle -M loongson-ext option.
161 (print_mips_disassembler_options): Document -M loongson-ext.
162 * mips-opc.c (IL3A): Delete.
163 * mips-opc.c (LEXT): New macro.
164 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
167 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
169 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
171 (parse_mips_ase_option): Handle -M loongson-cam option.
172 (print_mips_disassembler_options): Document -M loongson-cam.
173 * mips-opc.c (LCAM): New macro.
174 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
177 2018-08-21 Alan Modra <amodra@gmail.com>
179 * ppc-dis.c (operand_value_powerpc): Init "invalid".
180 (skip_optional_operands): Count optional operands, and update
181 ppc_optional_operand_value call.
182 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
183 (extract_vlensi): Likewise.
184 (extract_fxm): Return default value for missing optional operand.
185 (extract_ls, extract_raq, extract_tbr): Likewise.
186 (insert_sxl, extract_sxl): New functions.
187 (insert_esync, extract_esync): Remove Power9 handling and simplify.
188 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
189 flag and extra entry.
190 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
193 2018-08-20 Alan Modra <amodra@gmail.com>
195 * sh-opc.h (MASK): Simplify.
197 2018-08-18 John Darrington <john@darrington.wattle.id.au>
199 * s12z-dis.c (bm_decode): Deal with cases where the mode is
200 BM_RESERVED0 or BM_RESERVED1
201 (bm_rel_decode, bm_n_bytes): Ditto.
203 2018-08-18 John Darrington <john@darrington.wattle.id.au>
207 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
209 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
210 address with the addr32 prefix and without base nor index
213 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
215 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
216 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
217 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
218 (cpu_flags): Add CpuCMOV and CpuFXSR.
219 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
220 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
221 * i386-init.h: Regenerated.
222 * i386-tbl.h: Likewise.
224 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
226 * arc-regs.h: Update auxiliary registers.
228 2018-08-06 Jan Beulich <jbeulich@suse.com>
230 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
231 (RegIP, RegIZ): Define.
232 * i386-reg.tbl: Adjust comments.
233 (rip): Use Qword instead of BaseIndex. Use RegIP.
234 (eip): Use Dword instead of BaseIndex. Use RegIP.
235 (riz): Add Qword. Use RegIZ.
236 (eiz): Add Dword. Use RegIZ.
237 * i386-tbl.h: Re-generate.
239 2018-08-03 Jan Beulich <jbeulich@suse.com>
241 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
242 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
243 vpmovzxdq, vpmovzxwd): Remove NoRex64.
244 * i386-tbl.h: Re-generate.
246 2018-08-03 Jan Beulich <jbeulich@suse.com>
248 * i386-gen.c (operand_types): Remove Mem field.
249 * i386-opc.h (union i386_operand_type): Remove mem field.
250 * i386-init.h, i386-tbl.h: Re-generate.
252 2018-08-01 Alan Modra <amodra@gmail.com>
254 * po/POTFILES.in: Regenerate.
256 2018-07-31 Nick Clifton <nickc@redhat.com>
258 * po/sv.po: Updated Swedish translation.
260 2018-07-31 Jan Beulich <jbeulich@suse.com>
262 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
263 * i386-init.h, i386-tbl.h: Re-generate.
265 2018-07-31 Jan Beulich <jbeulich@suse.com>
267 * i386-opc.h (ZEROING_MASKING) Rename to ...
268 (DYNAMIC_MASKING): ... this. Adjust comment.
269 * i386-opc.tbl (MaskingMorZ): Define.
270 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
271 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
272 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
273 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
274 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
275 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
276 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
277 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
278 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
280 2018-07-31 Jan Beulich <jbeulich@suse.com>
282 * i386-opc.tbl: Use element rather than vector size for AVX512*
283 scatter/gather insns.
284 * i386-tbl.h: Re-generate.
286 2018-07-31 Jan Beulich <jbeulich@suse.com>
288 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
289 (cpu_flags): Drop CpuVREX.
290 * i386-opc.h (CpuVREX): Delete.
291 (union i386_cpu_flags): Remove cpuvrex.
292 * i386-init.h, i386-tbl.h: Re-generate.
294 2018-07-30 Jim Wilson <jimw@sifive.com>
296 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
298 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
300 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
302 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
303 * Makefile.in: Regenerated.
304 * configure.ac: Add C-SKY.
305 * configure: Regenerated.
306 * csky-dis.c: New file.
307 * csky-opc.h: New file.
308 * disassemble.c (ARCH_csky): Define.
309 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
310 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
312 2018-07-27 Alan Modra <amodra@gmail.com>
314 * ppc-opc.c (insert_sprbat): Correct function parameter and
316 (extract_sprbat): Likewise, variable too.
318 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
319 Alan Modra <amodra@gmail.com>
321 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
322 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
323 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
324 support disjointed BAT.
325 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
326 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
327 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
329 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
330 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
332 * i386-gen.c (adjust_broadcast_modifier): New function.
333 (process_i386_opcode_modifier): Add an argument for operands.
334 Adjust the Broadcast value based on operands.
335 (output_i386_opcode): Pass operand_types to
336 process_i386_opcode_modifier.
337 (process_i386_opcodes): Pass NULL as operands to
338 process_i386_opcode_modifier.
339 * i386-opc.h (BYTE_BROADCAST): New.
340 (WORD_BROADCAST): Likewise.
341 (DWORD_BROADCAST): Likewise.
342 (QWORD_BROADCAST): Likewise.
343 (i386_opcode_modifier): Expand broadcast to 3 bits.
344 * i386-tbl.h: Regenerated.
346 2018-07-24 Alan Modra <amodra@gmail.com>
349 * or1k-desc.h: Regenerate.
351 2018-07-24 Jan Beulich <jbeulich@suse.com>
353 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
354 vcvtusi2ss, and vcvtusi2sd.
355 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
356 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
357 * i386-tbl.h: Re-generate.
359 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
361 * arc-opc.c (extract_w6): Fix extending the sign.
363 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
365 * arc-tbl.h (vewt): Allow it for ARC EM family.
367 2018-07-23 Alan Modra <amodra@gmail.com>
370 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
371 opcode variants for mtspr/mfspr encodings.
373 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
374 Maciej W. Rozycki <macro@mips.com>
376 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
377 loongson3a descriptors.
378 (parse_mips_ase_option): Handle -M loongson-mmi option.
379 (print_mips_disassembler_options): Document -M loongson-mmi.
380 * mips-opc.c (LMMI): New macro.
381 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
384 2018-07-19 Jan Beulich <jbeulich@suse.com>
386 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
387 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
388 IgnoreSize and [XYZ]MMword where applicable.
389 * i386-tbl.h: Re-generate.
391 2018-07-19 Jan Beulich <jbeulich@suse.com>
393 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
394 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
395 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
396 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
397 * i386-tbl.h: Re-generate.
399 2018-07-19 Jan Beulich <jbeulich@suse.com>
401 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
402 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
403 VPCLMULQDQ templates into their respective AVX512VL counterparts
404 where possible, using Disp8ShiftVL and CheckRegSize instead of
405 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
406 * i386-tbl.h: Re-generate.
408 2018-07-19 Jan Beulich <jbeulich@suse.com>
410 * i386-opc.tbl: Fold AVX512DQ templates into their respective
411 AVX512VL counterparts where possible, using Disp8ShiftVL and
412 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
413 IgnoreSize) as appropriate.
414 * i386-tbl.h: Re-generate.
416 2018-07-19 Jan Beulich <jbeulich@suse.com>
418 * i386-opc.tbl: Fold AVX512BW templates into their respective
419 AVX512VL counterparts where possible, using Disp8ShiftVL and
420 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
421 IgnoreSize) as appropriate.
422 * i386-tbl.h: Re-generate.
424 2018-07-19 Jan Beulich <jbeulich@suse.com>
426 * i386-opc.tbl: Fold AVX512CD templates into their respective
427 AVX512VL counterparts where possible, using Disp8ShiftVL and
428 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
429 IgnoreSize) as appropriate.
430 * i386-tbl.h: Re-generate.
432 2018-07-19 Jan Beulich <jbeulich@suse.com>
434 * i386-opc.h (DISP8_SHIFT_VL): New.
435 * i386-opc.tbl (Disp8ShiftVL): Define.
436 (various): Fold AVX512VL templates into their respective
437 AVX512F counterparts where possible, using Disp8ShiftVL and
438 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
439 IgnoreSize) as appropriate.
440 * i386-tbl.h: Re-generate.
442 2018-07-19 Jan Beulich <jbeulich@suse.com>
444 * Makefile.am: Change dependencies and rule for
445 $(srcdir)/i386-init.h.
446 * Makefile.in: Re-generate.
447 * i386-gen.c (process_i386_opcodes): New local variable
448 "marker". Drop opening of input file. Recognize marker and line
450 * i386-opc.tbl (OPCODE_I386_H): Define.
451 (i386-opc.h): Include it.
454 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
457 * i386-opc.h (Byte): Update comments.
466 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
468 * i386-tbl.h: Regenerated.
470 2018-07-12 Sudakshina Das <sudi.das@arm.com>
472 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
473 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
474 * aarch64-asm-2.c: Regenerate.
475 * aarch64-dis-2.c: Regenerate.
476 * aarch64-opc-2.c: Regenerate.
478 2018-07-12 Tamar Christina <tamar.christina@arm.com>
481 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
482 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
483 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
484 sqdmulh, sqrdmulh): Use Em16.
486 2018-07-11 Sudakshina Das <sudi.das@arm.com>
488 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
489 csdb together with them.
490 (thumb32_opcodes): Likewise.
492 2018-07-11 Jan Beulich <jbeulich@suse.com>
494 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
495 requiring 32-bit registers as operands 2 and 3. Improve
497 (mwait, mwaitx): Fold templates. Improve comments.
498 OPERAND_TYPE_INOUTPORTREG.
499 * i386-tbl.h: Re-generate.
501 2018-07-11 Jan Beulich <jbeulich@suse.com>
503 * i386-gen.c (operand_type_init): Remove
504 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
505 OPERAND_TYPE_INOUTPORTREG.
506 * i386-init.h: Re-generate.
508 2018-07-11 Jan Beulich <jbeulich@suse.com>
510 * i386-opc.tbl (wrssd, wrussd): Add Dword.
511 (wrssq, wrussq): Add Qword.
512 * i386-tbl.h: Re-generate.
514 2018-07-11 Jan Beulich <jbeulich@suse.com>
516 * i386-opc.h: Rename OTMax to OTNum.
517 (OTNumOfUints): Adjust calculation.
518 (OTUnused): Directly alias to OTNum.
520 2018-07-09 Maciej W. Rozycki <macro@mips.com>
522 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
524 (lea_reg_xys): Likewise.
525 (print_insn_loop_primitive): Rename `reg' local variable to
528 2018-07-06 Tamar Christina <tamar.christina@arm.com>
531 * aarch64-tbl.h (ldarh): Fix disassembly mask.
533 2018-07-06 Tamar Christina <tamar.christina@arm.com>
536 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
537 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
539 2018-07-02 Maciej W. Rozycki <macro@mips.com>
542 * mips-dis.c (mips_option_arg_t): New enumeration.
543 (mips_options): New variable.
544 (disassembler_options_mips): New function.
545 (print_mips_disassembler_options): Reimplement in terms of
546 `disassembler_options_mips'.
547 * arm-dis.c (disassembler_options_arm): Adapt to using the
548 `disasm_options_and_args_t' structure.
549 * ppc-dis.c (disassembler_options_powerpc): Likewise.
550 * s390-dis.c (disassembler_options_s390): Likewise.
552 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
554 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
556 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
557 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
558 * testsuite/ld-arm/tls-longplt.d: Likewise.
560 2018-06-29 Tamar Christina <tamar.christina@arm.com>
563 * aarch64-asm-2.c: Regenerate.
564 * aarch64-dis-2.c: Likewise.
565 * aarch64-opc-2.c: Likewise.
566 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
567 * aarch64-opc.c (operand_general_constraint_met_p,
568 aarch64_print_operand): Likewise.
569 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
570 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
572 (AARCH64_OPERANDS): Add Em2.
574 2018-06-26 Nick Clifton <nickc@redhat.com>
576 * po/uk.po: Updated Ukranian translation.
577 * po/de.po: Updated German translation.
578 * po/pt_BR.po: Updated Brazilian Portuguese translation.
580 2018-06-26 Nick Clifton <nickc@redhat.com>
582 * nfp-dis.c: Fix spelling mistake.
584 2018-06-24 Nick Clifton <nickc@redhat.com>
586 * configure: Regenerate.
587 * po/opcodes.pot: Regenerate.
589 2018-06-24 Nick Clifton <nickc@redhat.com>
593 2018-06-19 Tamar Christina <tamar.christina@arm.com>
595 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
596 * aarch64-asm-2.c: Regenerate.
597 * aarch64-dis-2.c: Likewise.
599 2018-06-21 Maciej W. Rozycki <macro@mips.com>
601 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
602 `-M ginv' option description.
604 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
607 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
610 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
612 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
613 * configure.ac: Remove AC_PREREQ.
614 * Makefile.in: Re-generate.
615 * aclocal.m4: Re-generate.
616 * configure: Re-generate.
618 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
620 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
621 mips64r6 descriptors.
622 (parse_mips_ase_option): Handle -Mginv option.
623 (print_mips_disassembler_options): Document -Mginv.
624 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
626 (mips_opcodes): Define ginvi and ginvt.
628 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
629 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
631 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
632 * mips-opc.c (CRC, CRC64): New macros.
633 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
634 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
637 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
640 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
641 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
643 2018-06-06 Alan Modra <amodra@gmail.com>
645 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
646 setjmp. Move init for some other vars later too.
648 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
650 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
651 (dis_private): Add new fields for property section tracking.
652 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
653 (xtensa_instruction_fits): New functions.
654 (fetch_data): Bump minimal fetch size to 4.
655 (print_insn_xtensa): Make struct dis_private static.
656 Load and prepare property table on section change.
657 Don't disassemble literals. Don't disassemble instructions that
658 cross property table boundaries.
660 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
662 * configure: Regenerated.
664 2018-06-01 Jan Beulich <jbeulich@suse.com>
666 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
667 * i386-tbl.h: Re-generate.
669 2018-06-01 Jan Beulich <jbeulich@suse.com>
671 * i386-opc.tbl (sldt, str): Add NoRex64.
672 * i386-tbl.h: Re-generate.
674 2018-06-01 Jan Beulich <jbeulich@suse.com>
676 * i386-opc.tbl (invpcid): Add Oword.
677 * i386-tbl.h: Re-generate.
679 2018-06-01 Alan Modra <amodra@gmail.com>
681 * sysdep.h (_bfd_error_handler): Don't declare.
682 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
683 * rl78-decode.opc: Likewise.
684 * msp430-decode.c: Regenerate.
685 * rl78-decode.c: Regenerate.
687 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
689 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
690 * i386-init.h : Regenerated.
692 2018-05-25 Alan Modra <amodra@gmail.com>
694 * Makefile.in: Regenerate.
695 * po/POTFILES.in: Regenerate.
697 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
699 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
700 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
701 (insert_bab, extract_bab, insert_btab, extract_btab,
702 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
703 (BAT, BBA VBA RBS XB6S): Delete macros.
704 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
705 (BB, BD, RBX, XC6): Update for new macros.
706 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
707 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
708 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
709 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
711 2018-05-18 John Darrington <john@darrington.wattle.id.au>
713 * Makefile.am: Add support for s12z architecture.
714 * configure.ac: Likewise.
715 * disassemble.c: Likewise.
716 * disassemble.h: Likewise.
717 * Makefile.in: Regenerate.
718 * configure: Regenerate.
719 * s12z-dis.c: New file.
722 2018-05-18 Alan Modra <amodra@gmail.com>
724 * nfp-dis.c: Don't #include libbfd.h.
725 (init_nfp3200_priv): Use bfd_get_section_contents.
726 (nit_nfp6000_mecsr_sec): Likewise.
728 2018-05-17 Nick Clifton <nickc@redhat.com>
730 * po/zh_CN.po: Updated simplified Chinese translation.
732 2018-05-16 Tamar Christina <tamar.christina@arm.com>
735 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
736 * aarch64-dis-2.c: Regenerate.
738 2018-05-15 Tamar Christina <tamar.christina@arm.com>
741 * aarch64-asm.c (opintl.h): Include.
742 (aarch64_ins_sysreg): Enforce read/write constraints.
743 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
744 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
745 (F_REG_READ, F_REG_WRITE): New.
746 * aarch64-opc.c (aarch64_print_operand): Generate notes for
748 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
749 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
750 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
751 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
752 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
753 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
754 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
755 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
756 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
757 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
758 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
759 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
760 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
761 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
762 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
763 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
764 msr (F_SYS_WRITE), mrs (F_SYS_READ).
766 2018-05-15 Tamar Christina <tamar.christina@arm.com>
769 * aarch64-dis.c (no_notes: New.
770 (parse_aarch64_dis_option): Support notes.
771 (aarch64_decode_insn, print_operands): Likewise.
772 (print_aarch64_disassembler_options): Document notes.
773 * aarch64-opc.c (aarch64_print_operand): Support notes.
775 2018-05-15 Tamar Christina <tamar.christina@arm.com>
778 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
779 and take error struct.
780 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
781 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
782 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
783 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
784 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
785 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
786 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
787 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
788 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
789 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
790 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
791 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
792 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
793 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
794 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
795 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
796 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
797 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
798 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
799 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
800 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
801 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
802 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
803 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
804 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
805 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
806 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
807 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
808 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
809 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
810 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
811 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
812 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
813 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
814 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
815 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
816 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
817 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
818 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
819 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
820 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
821 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
822 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
823 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
824 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
825 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
826 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
827 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
828 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
829 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
830 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
831 (determine_disassembling_preference, aarch64_decode_insn,
832 print_insn_aarch64_word, print_insn_data): Take errors struct.
833 (print_insn_aarch64): Use errors.
834 * aarch64-asm-2.c: Regenerate.
835 * aarch64-dis-2.c: Regenerate.
836 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
837 boolean in aarch64_insert_operan.
838 (print_operand_extractor): Likewise.
839 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
841 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
843 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
845 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
847 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
849 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
851 * cr16-opc.c (cr16_instruction): Comment typo fix.
852 * hppa-dis.c (print_insn_hppa): Likewise.
854 2018-05-08 Jim Wilson <jimw@sifive.com>
856 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
857 (match_c_slli64, match_srxi_as_c_srxi): New.
858 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
859 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
860 <c.slli, c.srli, c.srai>: Use match_s_slli.
861 <c.slli64, c.srli64, c.srai64>: New.
863 2018-05-08 Alan Modra <amodra@gmail.com>
865 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
866 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
867 partition opcode space for index lookup.
869 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
871 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
872 <insn_length>: ...with this. Update usage.
873 Remove duplicate call to *info->memory_error_func.
875 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
876 H.J. Lu <hongjiu.lu@intel.com>
878 * i386-dis.c (Gva): New.
879 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
880 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
881 (prefix_table): New instructions (see prefix above).
882 (mod_table): New instructions (see prefix above).
883 (OP_G): Handle va_mode.
884 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
886 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
887 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
888 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
889 * i386-opc.tbl: Add movidir{i,64b}.
890 * i386-init.h: Regenerated.
891 * i386-tbl.h: Likewise.
893 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
895 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
897 * i386-opc.h (AddrPrefixOp0): Renamed to ...
898 (AddrPrefixOpReg): This.
899 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
900 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
902 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
904 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
905 (vle_num_opcodes): Likewise.
906 (spe2_num_opcodes): Likewise.
907 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
909 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
910 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
913 2018-05-01 Tamar Christina <tamar.christina@arm.com>
915 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
917 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
919 Makefile.am: Added nfp-dis.c.
920 configure.ac: Added bfd_nfp_arch.
921 disassemble.h: Added print_insn_nfp prototype.
922 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
923 nfp-dis.c: New, for NFP support.
924 po/POTFILES.in: Added nfp-dis.c to the list.
925 Makefile.in: Regenerate.
926 configure: Regenerate.
928 2018-04-26 Jan Beulich <jbeulich@suse.com>
930 * i386-opc.tbl: Fold various non-memory operand AVX512VL
931 templates into their base ones.
932 * i386-tlb.h: Re-generate.
934 2018-04-26 Jan Beulich <jbeulich@suse.com>
936 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
937 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
938 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
939 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
940 * i386-init.h: Re-generate.
942 2018-04-26 Jan Beulich <jbeulich@suse.com>
944 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
945 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
946 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
947 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
949 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
951 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
953 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
954 cpuregzmm, and cpuregmask.
955 * i386-init.h: Re-generate.
956 * i386-tbl.h: Re-generate.
958 2018-04-26 Jan Beulich <jbeulich@suse.com>
960 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
961 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
962 * i386-init.h: Re-generate.
964 2018-04-26 Jan Beulich <jbeulich@suse.com>
966 * i386-gen.c (VexImmExt): Delete.
967 * i386-opc.h (VexImmExt, veximmext): Delete.
968 * i386-opc.tbl: Drop all VexImmExt uses.
969 * i386-tlb.h: Re-generate.
971 2018-04-25 Jan Beulich <jbeulich@suse.com>
973 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
975 * i386-tlb.h: Re-generate.
977 2018-04-25 Tamar Christina <tamar.christina@arm.com>
979 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
981 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
983 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
985 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
986 (cpu_flags): Add CpuCLDEMOTE.
987 * i386-init.h: Regenerate.
988 * i386-opc.h (enum): Add CpuCLDEMOTE,
989 (i386_cpu_flags): Add cpucldemote.
990 * i386-opc.tbl: Add cldemote.
991 * i386-tbl.h: Regenerate.
993 2018-04-16 Alan Modra <amodra@gmail.com>
995 * Makefile.am: Remove sh5 and sh64 support.
996 * configure.ac: Likewise.
997 * disassemble.c: Likewise.
998 * disassemble.h: Likewise.
999 * sh-dis.c: Likewise.
1000 * sh64-dis.c: Delete.
1001 * sh64-opc.c: Delete.
1002 * sh64-opc.h: Delete.
1003 * Makefile.in: Regenerate.
1004 * configure: Regenerate.
1005 * po/POTFILES.in: Regenerate.
1007 2018-04-16 Alan Modra <amodra@gmail.com>
1009 * Makefile.am: Remove w65 support.
1010 * configure.ac: Likewise.
1011 * disassemble.c: Likewise.
1012 * disassemble.h: Likewise.
1013 * w65-dis.c: Delete.
1014 * w65-opc.h: Delete.
1015 * Makefile.in: Regenerate.
1016 * configure: Regenerate.
1017 * po/POTFILES.in: Regenerate.
1019 2018-04-16 Alan Modra <amodra@gmail.com>
1021 * configure.ac: Remove we32k support.
1022 * configure: Regenerate.
1024 2018-04-16 Alan Modra <amodra@gmail.com>
1026 * Makefile.am: Remove m88k support.
1027 * configure.ac: Likewise.
1028 * disassemble.c: Likewise.
1029 * disassemble.h: Likewise.
1030 * m88k-dis.c: Delete.
1031 * Makefile.in: Regenerate.
1032 * configure: Regenerate.
1033 * po/POTFILES.in: Regenerate.
1035 2018-04-16 Alan Modra <amodra@gmail.com>
1037 * Makefile.am: Remove i370 support.
1038 * configure.ac: Likewise.
1039 * disassemble.c: Likewise.
1040 * disassemble.h: Likewise.
1041 * i370-dis.c: Delete.
1042 * i370-opc.c: Delete.
1043 * Makefile.in: Regenerate.
1044 * configure: Regenerate.
1045 * po/POTFILES.in: Regenerate.
1047 2018-04-16 Alan Modra <amodra@gmail.com>
1049 * Makefile.am: Remove h8500 support.
1050 * configure.ac: Likewise.
1051 * disassemble.c: Likewise.
1052 * disassemble.h: Likewise.
1053 * h8500-dis.c: Delete.
1054 * h8500-opc.h: Delete.
1055 * Makefile.in: Regenerate.
1056 * configure: Regenerate.
1057 * po/POTFILES.in: Regenerate.
1059 2018-04-16 Alan Modra <amodra@gmail.com>
1061 * configure.ac: Remove tahoe support.
1062 * configure: Regenerate.
1064 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1066 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1068 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1070 * i386-tbl.h: Regenerated.
1072 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1074 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1075 PREFIX_MOD_1_0FAE_REG_6.
1077 (OP_E_register): Use va_mode.
1078 * i386-dis-evex.h (prefix_table):
1079 New instructions (see prefixes above).
1080 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1081 (cpu_flags): Likewise.
1082 * i386-opc.h (enum): Likewise.
1083 (i386_cpu_flags): Likewise.
1084 * i386-opc.tbl: Add umonitor, umwait, tpause.
1085 * i386-init.h: Regenerate.
1086 * i386-tbl.h: Likewise.
1088 2018-04-11 Alan Modra <amodra@gmail.com>
1090 * opcodes/i860-dis.c: Delete.
1091 * opcodes/i960-dis.c: Delete.
1092 * Makefile.am: Remove i860 and i960 support.
1093 * configure.ac: Likewise.
1094 * disassemble.c: Likewise.
1095 * disassemble.h: Likewise.
1096 * Makefile.in: Regenerate.
1097 * configure: Regenerate.
1098 * po/POTFILES.in: Regenerate.
1100 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1103 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1105 (print_insn): Clear vex instead of vex.evex.
1107 2018-04-04 Nick Clifton <nickc@redhat.com>
1109 * po/es.po: Updated Spanish translation.
1111 2018-03-28 Jan Beulich <jbeulich@suse.com>
1113 * i386-gen.c (opcode_modifiers): Delete VecESize.
1114 * i386-opc.h (VecESize): Delete.
1115 (struct i386_opcode_modifier): Delete vecesize.
1116 * i386-opc.tbl: Drop VecESize.
1117 * i386-tlb.h: Re-generate.
1119 2018-03-28 Jan Beulich <jbeulich@suse.com>
1121 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1122 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1123 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1124 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1125 * i386-tlb.h: Re-generate.
1127 2018-03-28 Jan Beulich <jbeulich@suse.com>
1129 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1131 * i386-tlb.h: Re-generate.
1133 2018-03-28 Jan Beulich <jbeulich@suse.com>
1135 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1136 (vex_len_table): Drop Y for vcvt*2si.
1137 (putop): Replace plain 'Y' handling by abort().
1139 2018-03-28 Nick Clifton <nickc@redhat.com>
1142 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1143 instructions with only a base address register.
1144 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1145 handle AARHC64_OPND_SVE_ADDR_R.
1146 (aarch64_print_operand): Likewise.
1147 * aarch64-asm-2.c: Regenerate.
1148 * aarch64_dis-2.c: Regenerate.
1149 * aarch64-opc-2.c: Regenerate.
1151 2018-03-22 Jan Beulich <jbeulich@suse.com>
1153 * i386-opc.tbl: Drop VecESize from register only insn forms and
1154 memory forms not allowing broadcast.
1155 * i386-tlb.h: Re-generate.
1157 2018-03-22 Jan Beulich <jbeulich@suse.com>
1159 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1160 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1161 sha256*): Drop Disp<N>.
1163 2018-03-22 Jan Beulich <jbeulich@suse.com>
1165 * i386-dis.c (EbndS, bnd_swap_mode): New.
1166 (prefix_table): Use EbndS.
1167 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1168 * i386-opc.tbl (bndmov): Move misplaced Load.
1169 * i386-tlb.h: Re-generate.
1171 2018-03-22 Jan Beulich <jbeulich@suse.com>
1173 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1174 templates allowing memory operands and folded ones for register
1176 * i386-tlb.h: Re-generate.
1178 2018-03-22 Jan Beulich <jbeulich@suse.com>
1180 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1181 256-bit templates. Drop redundant leftover Disp<N>.
1182 * i386-tlb.h: Re-generate.
1184 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1186 * riscv-opc.c (riscv_insn_types): New.
1188 2018-03-13 Nick Clifton <nickc@redhat.com>
1190 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1192 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1194 * i386-opc.tbl: Add Optimize to clr.
1195 * i386-tbl.h: Regenerated.
1197 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1199 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1200 * i386-opc.h (OldGcc): Removed.
1201 (i386_opcode_modifier): Remove oldgcc.
1202 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1203 instructions for old (<= 2.8.1) versions of gcc.
1204 * i386-tbl.h: Regenerated.
1206 2018-03-08 Jan Beulich <jbeulich@suse.com>
1208 * i386-opc.h (EVEXDYN): New.
1209 * i386-opc.tbl: Fold various AVX512VL templates.
1210 * i386-tlb.h: Re-generate.
1212 2018-03-08 Jan Beulich <jbeulich@suse.com>
1214 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1215 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1216 vpexpandd, vpexpandq): Fold AFX512VF templates.
1217 * i386-tlb.h: Re-generate.
1219 2018-03-08 Jan Beulich <jbeulich@suse.com>
1221 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1222 Fold 128- and 256-bit VEX-encoded templates.
1223 * i386-tlb.h: Re-generate.
1225 2018-03-08 Jan Beulich <jbeulich@suse.com>
1227 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1228 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1229 vpexpandd, vpexpandq): Fold AVX512F templates.
1230 * i386-tlb.h: Re-generate.
1232 2018-03-08 Jan Beulich <jbeulich@suse.com>
1234 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1235 64-bit templates. Drop Disp<N>.
1236 * i386-tlb.h: Re-generate.
1238 2018-03-08 Jan Beulich <jbeulich@suse.com>
1240 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1241 and 256-bit templates.
1242 * i386-tlb.h: Re-generate.
1244 2018-03-08 Jan Beulich <jbeulich@suse.com>
1246 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1247 * i386-tlb.h: Re-generate.
1249 2018-03-08 Jan Beulich <jbeulich@suse.com>
1251 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1253 * i386-tlb.h: Re-generate.
1255 2018-03-08 Jan Beulich <jbeulich@suse.com>
1257 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1258 * i386-tlb.h: Re-generate.
1260 2018-03-08 Jan Beulich <jbeulich@suse.com>
1262 * i386-gen.c (opcode_modifiers): Delete FloatD.
1263 * i386-opc.h (FloatD): Delete.
1264 (struct i386_opcode_modifier): Delete floatd.
1265 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1267 * i386-tlb.h: Re-generate.
1269 2018-03-08 Jan Beulich <jbeulich@suse.com>
1271 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1273 2018-03-08 Jan Beulich <jbeulich@suse.com>
1275 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1276 * i386-tlb.h: Re-generate.
1278 2018-03-08 Jan Beulich <jbeulich@suse.com>
1280 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1282 * i386-tlb.h: Re-generate.
1284 2018-03-07 Alan Modra <amodra@gmail.com>
1286 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1288 * disassemble.h (print_insn_rs6000): Delete.
1289 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1290 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1291 (print_insn_rs6000): Delete.
1293 2018-03-03 Alan Modra <amodra@gmail.com>
1295 * sysdep.h (opcodes_error_handler): Define.
1296 (_bfd_error_handler): Declare.
1297 * Makefile.am: Remove stray #.
1298 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1300 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1301 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1302 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1303 opcodes_error_handler to print errors. Standardize error messages.
1304 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1305 and include opintl.h.
1306 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1307 * i386-gen.c: Standardize error messages.
1308 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1309 * Makefile.in: Regenerate.
1310 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1311 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1312 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1313 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1314 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1315 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1316 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1317 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1318 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1319 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1320 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1321 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1322 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1324 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1326 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1327 vpsub[bwdq] instructions.
1328 * i386-tbl.h: Regenerated.
1330 2018-03-01 Alan Modra <amodra@gmail.com>
1332 * configure.ac (ALL_LINGUAS): Sort.
1333 * configure: Regenerate.
1335 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1337 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1338 macro by assignements.
1340 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1343 * i386-gen.c (opcode_modifiers): Add Optimize.
1344 * i386-opc.h (Optimize): New enum.
1345 (i386_opcode_modifier): Add optimize.
1346 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1347 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1348 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1349 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1350 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1352 * i386-tbl.h: Regenerated.
1354 2018-02-26 Alan Modra <amodra@gmail.com>
1356 * crx-dis.c (getregliststring): Allocate a large enough buffer
1357 to silence false positive gcc8 warning.
1359 2018-02-22 Shea Levy <shea@shealevy.com>
1361 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1363 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1365 * i386-opc.tbl: Add {rex},
1366 * i386-tbl.h: Regenerated.
1368 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1370 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1371 (mips16_opcodes): Replace `M' with `m' for "restore".
1373 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1375 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1377 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1379 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1380 variable to `function_index'.
1382 2018-02-13 Nick Clifton <nickc@redhat.com>
1385 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1386 about truncation of printing.
1388 2018-02-12 Henry Wong <henry@stuffedcow.net>
1390 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1392 2018-02-05 Nick Clifton <nickc@redhat.com>
1394 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1396 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1398 * i386-dis.c (enum): Add pconfig.
1399 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1400 (cpu_flags): Add CpuPCONFIG.
1401 * i386-opc.h (enum): Add CpuPCONFIG.
1402 (i386_cpu_flags): Add cpupconfig.
1403 * i386-opc.tbl: Add PCONFIG instruction.
1404 * i386-init.h: Regenerate.
1405 * i386-tbl.h: Likewise.
1407 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1409 * i386-dis.c (enum): Add PREFIX_0F09.
1410 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1411 (cpu_flags): Add CpuWBNOINVD.
1412 * i386-opc.h (enum): Add CpuWBNOINVD.
1413 (i386_cpu_flags): Add cpuwbnoinvd.
1414 * i386-opc.tbl: Add WBNOINVD instruction.
1415 * i386-init.h: Regenerate.
1416 * i386-tbl.h: Likewise.
1418 2018-01-17 Jim Wilson <jimw@sifive.com>
1420 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1422 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1424 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1425 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1426 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1427 (cpu_flags): Add CpuIBT, CpuSHSTK.
1428 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1429 (i386_cpu_flags): Add cpuibt, cpushstk.
1430 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1431 * i386-init.h: Regenerate.
1432 * i386-tbl.h: Likewise.
1434 2018-01-16 Nick Clifton <nickc@redhat.com>
1436 * po/pt_BR.po: Updated Brazilian Portugese translation.
1437 * po/de.po: Updated German translation.
1439 2018-01-15 Jim Wilson <jimw@sifive.com>
1441 * riscv-opc.c (match_c_nop): New.
1442 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1444 2018-01-15 Nick Clifton <nickc@redhat.com>
1446 * po/uk.po: Updated Ukranian translation.
1448 2018-01-13 Nick Clifton <nickc@redhat.com>
1450 * po/opcodes.pot: Regenerated.
1452 2018-01-13 Nick Clifton <nickc@redhat.com>
1454 * configure: Regenerate.
1456 2018-01-13 Nick Clifton <nickc@redhat.com>
1458 2.30 branch created.
1460 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1462 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1463 * i386-tbl.h: Regenerate.
1465 2018-01-10 Jan Beulich <jbeulich@suse.com>
1467 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1468 * i386-tbl.h: Re-generate.
1470 2018-01-10 Jan Beulich <jbeulich@suse.com>
1472 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1473 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1474 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1475 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1476 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1477 Disp8MemShift of AVX512VL forms.
1478 * i386-tbl.h: Re-generate.
1480 2018-01-09 Jim Wilson <jimw@sifive.com>
1482 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1483 then the hi_addr value is zero.
1485 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1487 * arm-dis.c (arm_opcodes): Add csdb.
1488 (thumb32_opcodes): Add csdb.
1490 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1492 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1493 * aarch64-asm-2.c: Regenerate.
1494 * aarch64-dis-2.c: Regenerate.
1495 * aarch64-opc-2.c: Regenerate.
1497 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1500 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1501 Remove AVX512 vmovd with 64-bit operands.
1502 * i386-tbl.h: Regenerated.
1504 2018-01-05 Jim Wilson <jimw@sifive.com>
1506 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1509 2018-01-03 Alan Modra <amodra@gmail.com>
1511 Update year range in copyright notice of all files.
1513 2018-01-02 Jan Beulich <jbeulich@suse.com>
1515 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1516 and OPERAND_TYPE_REGZMM entries.
1518 For older changes see ChangeLog-2017
1520 Copyright (C) 2018 Free Software Foundation, Inc.
1522 Copying and distribution of this file, with or without modification,
1523 are permitted in any medium without royalty provided the copyright
1524 notice and this notice are preserved.
1530 version-control: never