1 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
3 * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
4 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
6 * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
7 (cpu_flags): Add CpuAVX512IFMA.
8 * i386-opc.h (enum): Add CpuAVX512IFMA.
9 (i386_cpu_flags): Add cpuavx512ifma.
10 * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
11 * i386-init.h: Regenerated.
12 * i386-tbl.h: Likewise.
14 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
16 * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
17 (prefix_table): Add pcommit.
18 * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
19 (cpu_flags): Add CpuPCOMMIT.
20 * i386-opc.h (enum): Add CpuPCOMMIT.
21 (i386_cpu_flags): Add cpupcommit.
22 * i386-opc.tbl: Add pcommit.
23 * i386-init.h: Regenerated.
24 * i386-tbl.h: Likewise.
26 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
28 * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
29 (prefix_table): Add clwb.
30 * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
31 (cpu_flags): Add CpuCLWB.
32 * i386-opc.h (enum): Add CpuCLWB.
33 (i386_cpu_flags): Add cpuclwb.
34 * i386-opc.tbl: Add clwb.
35 * i386-init.h: Regenerated.
36 * i386-tbl.h: Likewise.
38 2014-11-03 Nick Clifton <nickc@redhat.com>
40 * po/fi.po: Updated Finnish translation.
42 2014-10-29 Nick Clifton <nickc@redhat.com>
44 * po/de.po: Updated German translation.
46 2014-10-28 Alan Modra <amodra@gmail.com>
49 2014-10-21 Jan Beulich <jbeulich@suse.com>
50 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
52 2014-10-15 Tristan Gingold <gingold@adacore.com>
54 * configure: Regenerate.
56 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
58 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
59 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
60 Annotate table with HWCAP2 bits.
61 Add instructions xmontmul, xmontsqr, xmpmul.
62 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
63 r,i,%mwait' and `rd %mwait,r' instructions.
64 Add rd/wr instructions for accessing the %mcdper ancillary state
66 (sparc-opcodes): Add sparc5/vis4.0 instructions:
67 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
68 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
69 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
70 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
71 fpsubus16, and faligndatai.
72 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
73 ancillary state register to the table.
74 (print_insn_sparc): Handle the %mcdper ancillary state register.
75 (print_insn_sparc): Handle new operand type '}'.
77 2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
79 * i386-dis.c (MOD_0F20): Removed.
83 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
85 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
86 (OP_R): Check mod/rm byte and call OP_E_register.
88 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
90 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
91 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
92 keyword_aridxi): Add audio ISA extension.
93 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
94 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
95 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
96 for nds32-dis.c using.
97 (build_opcode_syntax): Remove dead code.
98 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
99 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
100 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
102 * nds32-asm.h: Declare.
103 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
106 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
107 Matthew Fortune <matthew.fortune@imgtec.com>
109 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
111 (parse_mips_dis_option): Allow MSA and virtualization support for
113 (mips_print_arg_state): Add fields dest_regno and seen_dest.
114 (mips_seen_register): New function.
115 (print_insn_arg): Refactored code to use mips_seen_register
116 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
117 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
118 the register rather than aborting.
119 (print_insn_args): Add length argument. Add code to correctly
120 calculate the instruction address for pc relative instructions.
121 (validate_insn_args): New static function.
122 (print_insn_mips): Prevent jalx disassembling for r6. Use
124 (print_insn_micromips): Use validate_insn_args.
125 all the arguments are valid.
126 * mips-formats.h (PREV_CHECK): New define.
127 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
128 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
133 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
134 MIPS R6 instructions from MIPS R2 instructions.
136 2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
138 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
139 (putop): Handle "%LP".
141 2014-09-03 Jiong Wang <jiong.wang@arm.com>
143 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
144 * aarch64-dis-2.c: Update auto-generated file.
146 2014-09-03 Jiong Wang <jiong.wang@arm.com>
148 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
149 (aarch64_feature_lse): New feature added.
151 (aarch64_opcode_table): New LSE instructions added. Improve
152 descriptions for ldarb/ldarh/ldar.
153 (aarch64_opcode_table): Describe PAIRREG.
154 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
155 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
156 (aarch64_print_operand): Recognize PAIRREG.
157 (operand_general_constraint_met_p): Check reg pair constraints for CASP
159 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
160 (do_special_decoding): Recognize F_LSE_SZ.
161 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
163 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
165 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
166 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
167 "sdbbp", "syscall" and "wait".
169 2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
170 Maciej W. Rozycki <macro@codesourcery.com>
172 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
173 returned if the U bit is set.
175 2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
177 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
178 48-bit "li" encoding.
180 2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
182 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
183 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
184 static functions, code was moved from...
185 (print_insn_s390): ...here.
186 (s390_extract_operand): Adjust comment. Change type of first
187 parameter from 'unsigned char *' to 'const bfd_byte *'.
188 (union operand_value): New.
189 (s390_extract_operand): Change return type to union operand_value.
190 Also avoid integer overflow in sign-extension.
191 (s390_print_insn_with_opcode): Adjust to changed return value from
192 s390_extract_operand(). Change "%i" printf format to "%u" for
194 (init_disasm): Simplify initialization of opc_index[]. This also
195 fixes an access after the last element of s390_opcodes[].
196 (print_insn_s390): Simplify the opcode search loop.
197 Check architecture mask against all searched opcodes, not just the
199 (s390_print_insn_with_opcode): Drop function pointer dereferences
201 (print_insn_s390): Likewise.
202 (s390_insn_length): Simplify formula for return value.
203 (s390_print_insn_with_opcode): Avoid special handling for the
204 separator before the first operand. Use new local variable
205 'flags' in place of 'operand->flags'.
207 2014-08-14 Mike Frysinger <vapier@gentoo.org>
209 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
210 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
211 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
212 Change assignment of 1 to priv->comment to TRUE.
213 (print_insn_bfin): Change legal to a bfd_boolean. Change
214 assignment of 0/1 with priv comment and parallel and legal
217 2014-08-14 Mike Frysinger <vapier@gentoo.org>
219 * bfin-dis.c (OUT): Define.
220 (decode_CC2stat_0): Declare new op_names array.
221 Replace multiple if statements with a single one.
223 2014-08-14 Mike Frysinger <vapier@gentoo.org>
225 * bfin-dis.c (struct private): Add iw0.
226 (_print_insn_bfin): Assign iw0 to priv.iw0.
227 (print_insn_bfin): Drop ifetch and use priv.iw0.
229 2014-08-13 Mike Frysinger <vapier@gentoo.org>
231 * bfin-dis.c (comment, parallel): Move from global scope ...
232 (struct private): ... to this new struct.
233 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
234 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
235 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
236 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
237 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
238 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
239 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
240 print_insn_bfin): Declare private struct. Use priv's comment and
243 2014-08-13 Mike Frysinger <vapier@gentoo.org>
245 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
246 (_print_insn_bfin): Add check for unaligned pc.
248 2014-08-13 Mike Frysinger <vapier@gentoo.org>
250 * bfin-dis.c (ifetch): New function.
251 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
254 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
256 * micromips-opc.c (COD): Rename throughout to...
257 (CM): New define, update to use INSN_COPROC_MOVE.
258 (LCD): Rename throughout to...
259 (LC): New define, update to use INSN_LOAD_COPROC.
260 * mips-opc.c: Likewise.
262 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
264 * micromips-opc.c (COD, LCD) New macros.
265 (cfc1, ctc1): Remove FP_S attribute.
266 (dmfc1, mfc1, mfhc1): Add LCD attribute.
267 (dmtc1, mtc1, mthc1): Add COD attribute.
268 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
270 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
271 Alexander Ivchenko <alexander.ivchenko@intel.com>
272 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
273 Sergey Lega <sergey.s.lega@intel.com>
274 Anna Tikhonova <anna.tikhonova@intel.com>
275 Ilya Tocar <ilya.tocar@intel.com>
276 Andrey Turetskiy <andrey.turetskiy@intel.com>
277 Ilya Verbin <ilya.verbin@intel.com>
278 Kirill Yukhin <kirill.yukhin@intel.com>
279 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
281 * i386-dis-evex.h: Updated.
282 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
283 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
284 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
285 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
287 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
288 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
289 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
290 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
291 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
292 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
293 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
294 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
295 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
296 (prefix_table): Add entries for new instructions.
297 (vex_len_table): Ditto.
298 (vex_w_table): Ditto.
299 (OP_E_memory): Update xmmq_mode handling.
300 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
301 (cpu_flags): Add CpuAVX512DQ.
302 * i386-init.h: Regenerared.
303 * i386-opc.h (CpuAVX512DQ): New.
304 (i386_cpu_flags): Add cpuavx512dq.
305 * i386-opc.tbl: Add AVX512DQ instructions.
306 * i386-tbl.h: Regenerate.
308 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
309 Alexander Ivchenko <alexander.ivchenko@intel.com>
310 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
311 Sergey Lega <sergey.s.lega@intel.com>
312 Anna Tikhonova <anna.tikhonova@intel.com>
313 Ilya Tocar <ilya.tocar@intel.com>
314 Andrey Turetskiy <andrey.turetskiy@intel.com>
315 Ilya Verbin <ilya.verbin@intel.com>
316 Kirill Yukhin <kirill.yukhin@intel.com>
317 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
319 * i386-dis-evex.h: Add new instructions (prefixes bellow).
320 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
321 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
322 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
323 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
324 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
325 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
326 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
327 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
328 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
329 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
330 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
331 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
332 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
333 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
334 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
335 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
336 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
337 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
338 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
339 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
340 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
341 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
342 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
343 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
344 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
345 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
346 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
347 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
348 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
349 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
350 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
351 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
352 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
353 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
354 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
355 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
356 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
357 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
358 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
359 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
360 (prefix_table): Add entries for new instructions.
362 (vex_len_table): Ditto.
363 (vex_w_table): Ditto.
364 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
365 mask_bd_mode handling.
366 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
368 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
370 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
371 (OP_EX): Add dqw_swap_mode handling.
372 (OP_VEX): Add mask_bd_mode handling.
373 (OP_Mask): Add mask_bd_mode handling.
374 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
375 (cpu_flags): Add CpuAVX512BW.
376 * i386-init.h: Regenerated.
377 * i386-opc.h (CpuAVX512BW): New.
378 (i386_cpu_flags): Add cpuavx512bw.
379 * i386-opc.tbl: Add AVX512BW instructions.
380 * i386-tbl.h: Regenerate.
382 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
383 Alexander Ivchenko <alexander.ivchenko@intel.com>
384 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
385 Sergey Lega <sergey.s.lega@intel.com>
386 Anna Tikhonova <anna.tikhonova@intel.com>
387 Ilya Tocar <ilya.tocar@intel.com>
388 Andrey Turetskiy <andrey.turetskiy@intel.com>
389 Ilya Verbin <ilya.verbin@intel.com>
390 Kirill Yukhin <kirill.yukhin@intel.com>
391 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
393 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
394 * i386-tbl.h: Regenerate.
396 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
397 Alexander Ivchenko <alexander.ivchenko@intel.com>
398 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
399 Sergey Lega <sergey.s.lega@intel.com>
400 Anna Tikhonova <anna.tikhonova@intel.com>
401 Ilya Tocar <ilya.tocar@intel.com>
402 Andrey Turetskiy <andrey.turetskiy@intel.com>
403 Ilya Verbin <ilya.verbin@intel.com>
404 Kirill Yukhin <kirill.yukhin@intel.com>
405 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
407 * i386-dis.c (intel_operand_size): Support 128/256 length in
408 vex_vsib_q_w_dq_mode.
409 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
410 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
411 (cpu_flags): Add CpuAVX512VL.
412 * i386-init.h: Regenerated.
413 * i386-opc.h (CpuAVX512VL): New.
414 (i386_cpu_flags): Add cpuavx512vl.
415 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
416 * i386-opc.tbl: Add AVX512VL instructions.
417 * i386-tbl.h: Regenerate.
419 2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
421 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
422 * or1k-opinst.c: Regenerate.
424 2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
426 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
427 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
429 2014-07-04 Alan Modra <amodra@gmail.com>
431 * configure.ac: Rename from configure.in.
432 * Makefile.in: Regenerate.
433 * config.in: Regenerate.
435 2014-07-04 Alan Modra <amodra@gmail.com>
437 * configure.in: Include bfd/version.m4.
438 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
439 (BFD_VERSION): Delete.
440 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
441 * configure: Regenerate.
442 * Makefile.in: Regenerate.
444 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
445 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
446 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
447 Soundararajan <Sounderarajan.D@atmel.com>
449 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
450 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
451 machine is not avrtiny.
453 2014-06-26 Philippe De Muyter <phdm@macqel.be>
455 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
458 2014-06-12 Alan Modra <amodra@gmail.com>
460 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
461 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
463 2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
465 * i386-dis.c (fwait_prefix): New.
466 (ckprefix): Set fwait_prefix.
467 (print_insn): Properly print prefixes before fwait.
469 2014-06-07 Alan Modra <amodra@gmail.com>
471 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
473 2014-06-05 Joel Brobecker <brobecker@adacore.com>
475 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
476 bfd's development.sh.
477 * Makefile.in, configure: Regenerate.
479 2014-06-03 Nick Clifton <nickc@redhat.com>
481 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
482 decide when extended addressing is being used.
484 2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
486 * sparc-opc.c (cas): Disable for LEON.
489 2014-05-20 Alan Modra <amodra@gmail.com>
491 * m68k-dis.c: Don't include setjmp.h.
493 2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
495 * i386-dis.c (ADDR16_PREFIX): Removed.
496 (ADDR32_PREFIX): Likewise.
497 (DATA16_PREFIX): Likewise.
498 (DATA32_PREFIX): Likewise.
499 (prefix_name): Updated.
500 (print_insn): Simplify data and address size prefixes processing.
502 2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
504 * or1k-desc.c: Regenerated.
505 * or1k-desc.h: Likewise.
506 * or1k-opc.c: Likewise.
507 * or1k-opc.h: Likewise.
508 * or1k-opinst.c: Likewise.
510 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
512 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
517 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
519 (parse_mips_dis_option): Update MSA and virtualization support to
520 allow mips64r3 and mips64r5.
522 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
524 * mips-opc.c (G3): Remove I4.
526 2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
529 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
530 (end_codep): Likewise.
531 (mandatory_prefix): Likewise.
532 (active_seg_prefix): Likewise.
533 (ckprefix): Set active_seg_prefix to the active segment register
535 (seg_prefix): Removed.
536 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
537 for prefix index. Ignore the index if it is invalid and the
538 mandatory prefix isn't required.
539 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
540 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
541 in used_prefixes here. Don't print unused prefixes. Check
542 active_seg_prefix for the active segment register prefix.
543 Restore the DFLAG bit in sizeflag if the data size prefix is
544 unused. Check the unused mandatory PREFIX_XXX prefixes
545 (append_seg): Only print the segment register which gets used.
546 (OP_E_memory): Check active_seg_prefix for the segment register
549 (OP_OFF64): Likewise.
550 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
552 2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
555 * config.in: Regenerated.
556 * configure: Likewise.
557 * configure.in: Check if sigsetjmp is available.
558 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
559 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
560 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
561 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
562 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
563 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
564 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
565 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
566 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
567 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
568 (OPCODES_SIGSETJMP): Likewise.
569 (OPCODES_SIGLONGJMP): Likewise.
570 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
571 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
572 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
573 * xtensa-dis.c (dis_private): Replace jmp_buf with
575 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
576 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
577 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
578 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
579 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
581 2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
584 * i386-dis.c (print_insn): Handle prefixes before fwait.
586 2014-04-26 Alan Modra <amodra@gmail.com>
588 * po/POTFILES.in: Regenerate.
590 2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
592 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
593 to allow the MIPS XPA ASE.
594 (parse_mips_dis_option): Process the -Mxpa option.
595 * mips-opc.c (XPA): New define.
596 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
597 locations of the ctc0 and cfc0 instructions.
599 2014-04-22 Christian Svensson <blue@cmd.nu>
601 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
602 * configure.in: Likewise.
603 * disassemble.c: Likewise.
604 * or1k-asm.c: New file.
605 * or1k-desc.c: New file.
606 * or1k-desc.h: New file.
607 * or1k-dis.c: New file.
608 * or1k-ibld.c: New file.
609 * or1k-opc.c: New file.
610 * or1k-opc.h: New file.
611 * or1k-opinst.c: New file.
612 * Makefile.in: Regenerate.
613 * configure: Regenerate.
614 * openrisc-asm.c: Delete.
615 * openrisc-desc.c: Delete.
616 * openrisc-desc.h: Delete.
617 * openrisc-dis.c: Delete.
618 * openrisc-ibld.c: Delete.
619 * openrisc-opc.c: Delete.
620 * openrisc-opc.h: Delete.
621 * or32-dis.c: Delete.
622 * or32-opc.c: Delete.
624 2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
626 * i386-dis.c (rm_table): Add encls, enclu.
627 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
628 (cpu_flags): Add CpuSE1.
629 * i386-opc.h (enum): Add CpuSE1.
630 (i386_cpu_flags): Add cpuse1.
631 * i386-opc.tbl: Add encls, enclu.
632 * i386-init.h: Regenerated.
633 * i386-tbl.h: Likewise.
635 2014-04-02 Anthony Green <green@moxielogic.com>
637 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
638 instructions, sex.b and sex.s.
640 2014-03-26 Jiong Wang <jiong.wang@arm.com>
642 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
645 2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
647 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
648 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
650 * i386-tbl.h: Regenerate.
652 2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
654 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
655 %hstick_enable added.
657 2014-03-19 Nick Clifton <nickc@redhat.com>
659 * rx-decode.opc (bwl): Allow for bogus instructions with a size
661 (sbwl, ubwl, SCALE): Likewise.
662 * rx-decode.c: Regenerate.
664 2014-03-12 Alan Modra <amodra@gmail.com>
666 * Makefile.in: Regenerate.
668 2014-03-05 Alan Modra <amodra@gmail.com>
670 Update copyright years.
672 2014-03-04 Heiher <r@hev.cc>
674 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
676 2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
678 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
679 so that they come after the Loongson extensions.
681 2014-03-03 Alan Modra <amodra@gmail.com>
683 * i386-gen.c (process_copyright): Emit copyright notice on one line.
685 2014-02-28 Alan Modra <amodra@gmail.com>
687 * msp430-decode.c: Regenerate.
689 2014-02-27 Jiong Wang <jiong.wang@arm.com>
691 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
692 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
694 2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
696 * aarch64-opc.c (print_register_offset_address): Call
697 get_int_reg_name to prepare the register name.
699 2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
701 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
702 * i386-tbl.h: Regenerate.
704 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
706 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
707 (cpu_flags): Add CpuPREFETCHWT1.
708 * i386-init.h: Regenerate.
709 * i386-opc.h (CpuPREFETCHWT1): New.
710 (i386_cpu_flags): Add cpuprefetchwt1.
711 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
712 * i386-tbl.h: Regenerate.
714 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
716 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
718 * i386-tbl.h: Regenerate.
720 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
722 * i386-gen.c (output_cpu_flags): Don't output trailing space.
723 (output_opcode_modifier): Likewise.
724 (output_operand_type): Likewise.
725 * i386-init.h: Regenerated.
726 * i386-tbl.h: Likewise.
728 2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
730 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
732 (PREFIX enum): Add PREFIX_0FAE_REG_7.
733 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
734 (prefix_table): Add clflusopt.
735 (mod_table): Add xrstors, xsavec, xsaves.
736 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
737 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
738 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
739 * i386-init.h: Regenerate.
740 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
741 xsaves64, xsavec, xsavec64.
742 * i386-tbl.h: Regenerate.
744 2014-02-10 Alan Modra <amodra@gmail.com>
746 * po/POTFILES.in: Regenerate.
747 * po/opcodes.pot: Regenerate.
749 2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
750 Jan Beulich <jbeulich@suse.com>
753 * i386-dis.c (OP_E_memory): Fix shift computation for
754 vex_vsib_q_w_dq_mode.
756 2014-01-09 Bradley Nelson <bradnelson@google.com>
757 Roland McGrath <mcgrathr@google.com>
759 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
760 last_rex_prefix is -1.
762 2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
764 * i386-gen.c (process_copyright): Update copyright year to 2014.
766 2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
768 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
770 For older changes see ChangeLog-2013
772 Copyright (C) 2014 Free Software Foundation, Inc.
774 Copying and distribution of this file, with or without modification,
775 are permitted in any medium without royalty provided the copyright
776 notice and this notice are preserved.
782 version-control: never