1 2011-10-26 Nick Clifton <nickc@redhat.com>
4 * i386-dis.c (print_insn): Fix testing of array subscript.
6 2011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
8 * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
9 * epiphany-asm.c, epiphany-opc.h: Regenerate.
11 2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
13 * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
14 (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
15 epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
16 (CLEANFILES): Add stamp-epiphany.
17 (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
18 (stamp-epiphany): New rule.
19 * configure.in: Handle bfd_epiphany_arch.
20 * disassemble.c (ARCH_epiphany): Define.
21 (disassembler): Handle bfd_arch_epiphany.
22 * epiphany-asm.c: New file.
23 * epiphany-desc.c: New file.
24 * epiphany-desc.h: New file.
25 * epiphany-dis.c: New file.
26 * epiphany-ibld.c: New file.
27 * epiphany-opc.c: New file.
28 * epiphany-opc.h: New file.
29 * Makefile.in: Regenerate.
30 * configure: Regenerate.
31 * po/POTFILES.in: Regenerate.
32 * po/opcodes.pot: Regenerate.
34 2011-10-24 Julian Brown <julian@codesourcery.com>
36 * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
38 2011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
40 * s390-opc.txt: Add CPUMF instructions.
42 2011-10-18 Jie Zhang <jie@codesourcery.com>
43 Julian Brown <julian@codesourcery.com>
45 * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
47 2011-10-10 Nick Clifton <nickc@redhat.com>
49 * po/es.po: Updated Spanish translation.
50 * po/fi.po: Updated Finnish translation.
52 2011-09-28 Jan Beulich <jbeulich@suse.com>
54 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
56 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
57 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
58 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
59 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
60 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
61 on DFP quad instructions.
63 2011-09-27 David S. Miller <davem@davemloft.net>
65 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
66 to a float instead of an integer register.
68 2011-09-26 David S. Miller <davem@davemloft.net>
70 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
73 2011-09-21 David S. Miller <davem@davemloft.net>
75 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
76 bits. Fix "fchksm16" mnemonic.
78 2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
80 The changes below bring 'mov' and 'ticc' instructions into line
81 with the V8 SPARC Architecture Manual.
82 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
83 * sparc-opc.c (sparc_opcodes): Add alias entries for
84 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
85 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
86 * sparc-opc.c (sparc_opcodes): Move/Change entries for
87 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
89 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
92 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
93 This has been reported as being accepted by the Sun assmebler.
95 2011-09-08 David S. Miller <davem@davemloft.net>
97 * sparc-opc.c (pdistn): Destination is integer not float register.
99 2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
102 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
104 2011-08-26 Nick Clifton <nickc@redhat.com>
106 * po/es.po: Updated Spanish translation.
108 2011-08-22 Nick Clifton <nickc@redhat.com>
110 * Makefile.am (CPUDIR): Redfine to point to top level cpu
112 (stamp-frv): Use CPUDIR.
113 (stamp-iq2000): Likewise.
114 (stamp-lm32): Likewise.
115 (stamp-m32c): Likewise.
116 (stamp-mt): Likewise.
117 (stamp-xc16x): Likewise.
118 * Makefile.in: Regenerate.
120 2011-08-09 Chao-ying Fu <fu@mips.com>
121 Maciej W. Rozycki <macro@codesourcery.com>
123 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
125 (print_insn_args, print_insn_micromips): Handle MCU.
126 * micromips-opc.c (MC): New macro.
127 (micromips_opcodes): Add "aclr", "aset" and "iret".
128 * mips-opc.c (MC): New macro.
129 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
131 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
133 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
134 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
135 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
136 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
137 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
138 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
139 (WR_s): Update macro.
140 (micromips_opcodes): Update register use flags of: "addiu",
141 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
142 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
143 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
144 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
145 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
146 "swm" and "xor" instructions.
148 2011-08-05 David S. Miller <davem@davemloft.net>
150 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
152 (print_insn_sparc): Handle '4', '5', and '(' format codes.
153 Accept %asr numbers below 28.
154 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
157 2011-08-02 Quentin Neill <quentin.neill@amd.com>
159 * i386-dis.c (xop_table): Remove spurious bextr insn.
161 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
164 * i386-dis.c (print_insn): Optimize info->mach check.
166 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
169 * i386-opc.tbl: Add Disp32S to 64bit call.
170 * i386-tbl.h: Regenerated.
172 2011-07-24 Chao-ying Fu <fu@mips.com>
173 Maciej W. Rozycki <macro@codesourcery.com>
175 * micromips-opc.c: New file.
176 * mips-dis.c (micromips_to_32_reg_b_map): New array.
177 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
178 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
179 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
180 (micromips_to_32_reg_q_map): Likewise.
181 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
182 (micromips_ase): New variable.
183 (is_micromips): New function.
184 (set_default_mips_dis_options): Handle microMIPS ASE.
185 (print_insn_micromips): New function.
186 (is_compressed_mode_p): Likewise.
187 (_print_insn_mips): Handle microMIPS instructions.
188 * Makefile.am (CFILES): Add micromips-opc.c.
189 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
190 * Makefile.in: Regenerate.
191 * configure: Regenerate.
193 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
194 (micromips_to_32_reg_i_map): Likewise.
195 (micromips_to_32_reg_m_map): Likewise.
196 (micromips_to_32_reg_n_map): New macro.
198 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
200 * mips-opc.c (NODS): New macro.
201 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
202 (DSP_VOLA): Likewise.
203 (mips_builtin_opcodes): Add NODS annotation to "deret" and
204 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
205 place of TRAP for "wait", "waiti" and "yield".
206 * mips16-opc.c (NODS): New macro.
207 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
208 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
209 "restore" and "save".
211 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
213 * configure.in: Handle bfd_k1om_arch.
214 * configure: Regenerated.
216 * disassemble.c (disassembler): Handle bfd_k1om_arch.
218 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
219 bfd_mach_k1om_intel_syntax.
221 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
222 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
223 (cpu_flags): Add CpuK1OM.
225 * i386-opc.h (CpuK1OM): New.
226 (i386_cpu_flags): Add cpuk1om.
228 * i386-init.h: Regenerated.
229 * i386-tbl.h: Likewise.
231 2011-07-12 Nick Clifton <nickc@redhat.com>
233 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
236 2011-07-01 Nick Clifton <nickc@redhat.com>
239 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
240 insns using post-increment addressing.
242 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
244 * i386-dis.c (vex_len_table): Update rorxS.
246 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
248 AVX Programming Reference (June, 2011)
249 * i386-dis.c (vex_len_table): Correct rorxS.
251 * i386-opc.tbl: Correct rorx.
252 * i386-tbl.h: Regenerated.
254 2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
256 * tilegx-opc.c (find_opcode): Replace "index" with "i".
257 * tilepro-opc.c (find_opcode): Likewise.
259 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
261 * mips16-opc.c (jalrc, jrc): Move earlier in file.
263 2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
265 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
268 2011-06-17 Andreas Schwab <schwab@redhat.com>
270 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
271 (MOSTLYCLEANFILES): ... here.
272 * Makefile.in: Regenerate.
274 2011-06-14 Alan Modra <amodra@gmail.com>
276 * Makefile.in: Regenerate.
278 2011-06-13 Walter Lee <walt@tilera.com>
280 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
281 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
282 * Makefile.in: Regenerate.
283 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
284 * configure: Regenerate.
285 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
286 * po/POTFILES.in: Regenerate.
287 * tilegx-dis.c: New file.
288 * tilegx-opc.c: New file.
289 * tilepro-dis.c: New file.
290 * tilepro-opc.c: New file.
292 2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
294 AVX Programming Reference (June, 2011)
295 * i386-dis.c (XMGatherQ): New.
296 * i386-dis.c (EXxmm_mb): New.
297 (EXxmm_mb): Likewise.
298 (EXxmm_mw): Likewise.
299 (EXxmm_md): Likewise.
300 (EXxmm_mq): Likewise.
303 (VexGatherQ): Likewise.
304 (MVexVSIBDWpX): Likewise.
305 (MVexVSIBQWpX): Likewise.
306 (xmm_mb_mode): Likewise.
307 (xmm_mw_mode): Likewise.
308 (xmm_md_mode): Likewise.
309 (xmm_mq_mode): Likewise.
310 (xmmdw_mode): Likewise.
311 (xmmqd_mode): Likewise.
312 (ymmxmm_mode): Likewise.
313 (vex_vsib_d_w_dq_mode): Likewise.
314 (vex_vsib_q_w_dq_mode): Likewise.
315 (MOD_VEX_0F385A_PREFIX_2): Likewise.
316 (MOD_VEX_0F388C_PREFIX_2): Likewise.
317 (MOD_VEX_0F388E_PREFIX_2): Likewise.
318 (PREFIX_0F3882): Likewise.
319 (PREFIX_VEX_0F3816): Likewise.
320 (PREFIX_VEX_0F3836): Likewise.
321 (PREFIX_VEX_0F3845): Likewise.
322 (PREFIX_VEX_0F3846): Likewise.
323 (PREFIX_VEX_0F3847): Likewise.
324 (PREFIX_VEX_0F3858): Likewise.
325 (PREFIX_VEX_0F3859): Likewise.
326 (PREFIX_VEX_0F385A): Likewise.
327 (PREFIX_VEX_0F3878): Likewise.
328 (PREFIX_VEX_0F3879): Likewise.
329 (PREFIX_VEX_0F388C): Likewise.
330 (PREFIX_VEX_0F388E): Likewise.
331 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
332 (PREFIX_VEX_0F38F5): Likewise.
333 (PREFIX_VEX_0F38F6): Likewise.
334 (PREFIX_VEX_0F3A00): Likewise.
335 (PREFIX_VEX_0F3A01): Likewise.
336 (PREFIX_VEX_0F3A02): Likewise.
337 (PREFIX_VEX_0F3A38): Likewise.
338 (PREFIX_VEX_0F3A39): Likewise.
339 (PREFIX_VEX_0F3A46): Likewise.
340 (PREFIX_VEX_0F3AF0): Likewise.
341 (VEX_LEN_0F3816_P_2): Likewise.
342 (VEX_LEN_0F3819_P_2): Likewise.
343 (VEX_LEN_0F3836_P_2): Likewise.
344 (VEX_LEN_0F385A_P_2_M_0): Likewise.
345 (VEX_LEN_0F38F5_P_0): Likewise.
346 (VEX_LEN_0F38F5_P_1): Likewise.
347 (VEX_LEN_0F38F5_P_3): Likewise.
348 (VEX_LEN_0F38F6_P_3): Likewise.
349 (VEX_LEN_0F38F7_P_1): Likewise.
350 (VEX_LEN_0F38F7_P_2): Likewise.
351 (VEX_LEN_0F38F7_P_3): Likewise.
352 (VEX_LEN_0F3A00_P_2): Likewise.
353 (VEX_LEN_0F3A01_P_2): Likewise.
354 (VEX_LEN_0F3A38_P_2): Likewise.
355 (VEX_LEN_0F3A39_P_2): Likewise.
356 (VEX_LEN_0F3A46_P_2): Likewise.
357 (VEX_LEN_0F3AF0_P_3): Likewise.
358 (VEX_W_0F3816_P_2): Likewise.
359 (VEX_W_0F3818_P_2): Likewise.
360 (VEX_W_0F3819_P_2): Likewise.
361 (VEX_W_0F3836_P_2): Likewise.
362 (VEX_W_0F3846_P_2): Likewise.
363 (VEX_W_0F3858_P_2): Likewise.
364 (VEX_W_0F3859_P_2): Likewise.
365 (VEX_W_0F385A_P_2_M_0): Likewise.
366 (VEX_W_0F3878_P_2): Likewise.
367 (VEX_W_0F3879_P_2): Likewise.
368 (VEX_W_0F3A00_P_2): Likewise.
369 (VEX_W_0F3A01_P_2): Likewise.
370 (VEX_W_0F3A02_P_2): Likewise.
371 (VEX_W_0F3A38_P_2): Likewise.
372 (VEX_W_0F3A39_P_2): Likewise.
373 (VEX_W_0F3A46_P_2): Likewise.
374 (MOD_VEX_0F3818_PREFIX_2): Removed.
375 (MOD_VEX_0F3819_PREFIX_2): Likewise.
376 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
377 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
378 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
379 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
380 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
381 (VEX_LEN_0F3A0E_P_2): Likewise.
382 (VEX_LEN_0F3A0F_P_2): Likewise.
383 (VEX_LEN_0F3A42_P_2): Likewise.
384 (VEX_LEN_0F3A4C_P_2): Likewise.
385 (VEX_W_0F3818_P_2_M_0): Likewise.
386 (VEX_W_0F3819_P_2_M_0): Likewise.
387 (prefix_table): Updated.
388 (three_byte_table): Likewise.
389 (vex_table): Likewise.
390 (vex_len_table): Likewise.
391 (vex_w_table): Likewise.
392 (mod_table): Likewise.
393 (putop): Handle "LW".
394 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
395 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
396 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
398 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
399 vex_vsib_q_w_dq_mode.
400 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
403 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
404 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
405 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
406 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
407 (opcode_modifiers): Add VecSIB.
409 * i386-opc.h (CpuAVX2): New.
411 (CpuLZCNT): Likewise.
412 (CpuINVPCID): Likewise.
413 (VecSIB128): Likewise.
414 (VecSIB256): Likewise.
416 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
417 (i386_opcode_modifier): Add vecsib.
419 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
420 * i386-init.h: Regenerated.
421 * i386-tbl.h: Likewise.
423 2011-06-03 Quentin Neill <quentin.neill@amd.com>
425 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
426 * i386-init.h: Regenerated.
428 2011-06-03 Nick Clifton <nickc@redhat.com>
431 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
432 computing address offsets.
433 (print_arm_address): Likewise.
434 (print_insn_arm): Likewise.
435 (print_insn_thumb16): Likewise.
436 (print_insn_thumb32): Likewise.
438 2011-06-02 Jie Zhang <jie@codesourcery.com>
439 Nathan Sidwell <nathan@codesourcery.com>
440 Maciej Rozycki <macro@codesourcery.com>
442 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
444 (print_arm_address): Likewise. Elide positive #0 appropriately.
445 (print_insn_arm): Likewise.
447 2011-06-02 Nick Clifton <nickc@redhat.com>
450 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
451 passed to print_address_func.
453 2011-06-02 Nick Clifton <nickc@redhat.com>
455 * arm-dis.c: Fix spelling mistakes.
456 * op/opcodes.pot: Regenerate.
458 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
460 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
461 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
462 * s390-opc.txt: Fix cxr instruction type.
464 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
466 * s390-opc.c: Add new instruction types marking register pair
468 * s390-opc.txt: Match instructions having register pair operands
469 to the new instruction types.
471 2011-05-19 Nick Clifton <nickc@redhat.com>
473 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
476 2011-05-10 Quentin Neill <quentin.neill@amd.com>
478 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
479 * i386-init.h: Regenerated.
481 2011-04-27 Nick Clifton <nickc@redhat.com>
483 * po/da.po: Updated Danish translation.
485 2011-04-26 Anton Blanchard <anton@samba.org>
487 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
489 2011-04-21 DJ Delorie <dj@redhat.com>
491 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
492 * rx-decode.c: Regenerate.
494 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
496 * i386-init.h: Regenerated.
498 2011-04-19 Quentin Neill <quentin.neill@amd.com>
500 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
503 2011-04-13 Nick Clifton <nickc@redhat.com>
505 * v850-dis.c (disassemble): Always print a closing square brace if
506 an opening square brace was printed.
508 2011-04-12 Nick Clifton <nickc@redhat.com>
511 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
513 (print_insn_thumb32): Handle %L.
515 2011-04-11 Julian Brown <julian@codesourcery.com>
517 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
518 (print_insn_thumb32): Add APSR bitmask support.
520 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
522 * arm-dis.c (print_insn): init vars moved into private_data structure.
524 2011-03-24 Mike Frysinger <vapier@gentoo.org>
526 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
528 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
530 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
531 post-increment to support LPM Z+ instruction. Add support for 'E'
532 constraint for DES instruction.
533 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
535 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
537 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
539 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
541 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
542 Use branch types instead.
543 (print_insn): Likewise.
545 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
547 * mips-opc.c (mips_builtin_opcodes): Correct register use
548 annotation of "alnv.ps".
550 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
552 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
554 2011-02-22 Mike Frysinger <vapier@gentoo.org>
556 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
558 2011-02-22 Mike Frysinger <vapier@gentoo.org>
560 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
562 2011-02-19 Mike Frysinger <vapier@gentoo.org>
564 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
565 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
566 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
567 exception, end_of_registers, msize, memory, bfd_mach.
568 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
569 LB0REG, LC1REG, LT1REG, LB1REG): Delete
570 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
571 (get_allreg): Change to new defines. Fallback to abort().
573 2011-02-14 Mike Frysinger <vapier@gentoo.org>
575 * bfin-dis.c: Add whitespace/parenthesis where needed.
577 2011-02-14 Mike Frysinger <vapier@gentoo.org>
579 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
582 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
584 * configure: Regenerate.
586 2011-02-13 Mike Frysinger <vapier@gentoo.org>
588 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
590 2011-02-13 Mike Frysinger <vapier@gentoo.org>
592 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
593 dregs only when P is set, and dregs_lo otherwise.
595 2011-02-13 Mike Frysinger <vapier@gentoo.org>
597 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
599 2011-02-12 Mike Frysinger <vapier@gentoo.org>
601 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
603 2011-02-12 Mike Frysinger <vapier@gentoo.org>
605 * bfin-dis.c (machine_registers): Delete REG_GP.
606 (reg_names): Delete "GP".
607 (decode_allregs): Change REG_GP to REG_LASTREG.
609 2011-02-12 Mike Frysinger <vapier@gentoo.org>
611 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
614 2011-02-11 Mike Frysinger <vapier@gentoo.org>
616 * bfin-dis.c (reg_names): Add const.
617 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
618 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
619 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
620 decode_counters, decode_allregs): Likewise.
622 2011-02-09 Michael Snyder <msnyder@vmware.com>
624 * i386-dis.c (OP_J): Parenthesize expression to prevent
626 (print_insn): Fix indentation off-by-one.
628 2011-02-01 Nick Clifton <nickc@redhat.com>
630 * po/da.po: Updated Danish translation.
632 2011-01-21 Dave Murphy <davem@devkitpro.org>
634 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
636 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
638 * i386-dis.c (sIbT): New.
639 (b_T_mode): Likewise.
640 (dis386): Replace sIb with sIbT on "pushT".
641 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
642 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
644 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
646 * i386-init.h: Regenerated.
647 * i386-tbl.h: Regenerated
649 2011-01-17 Quentin Neill <quentin.neill@amd.com>
651 * i386-dis.c (REG_XOP_TBM_01): New.
652 (REG_XOP_TBM_02): New.
653 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
654 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
655 entries, and add bextr instruction.
657 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
658 (cpu_flags): Add CpuTBM.
660 * i386-opc.h (CpuTBM) New.
661 (i386_cpu_flags): Add bit cputbm.
663 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
664 blcs, blsfill, blsic, t1mskc, and tzmsk.
666 2011-01-12 DJ Delorie <dj@redhat.com>
668 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
670 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
672 * mips-dis.c (print_insn_args): Adjust the value to print the real
673 offset for "+c" argument.
675 2011-01-10 Nick Clifton <nickc@redhat.com>
677 * po/da.po: Updated Danish translation.
679 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
681 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
683 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
685 * i386-dis.c (REG_VEX_38F3): New.
686 (PREFIX_0FBC): Likewise.
687 (PREFIX_VEX_38F2): Likewise.
688 (PREFIX_VEX_38F3_REG_1): Likewise.
689 (PREFIX_VEX_38F3_REG_2): Likewise.
690 (PREFIX_VEX_38F3_REG_3): Likewise.
691 (PREFIX_VEX_38F7): Likewise.
692 (VEX_LEN_38F2_P_0): Likewise.
693 (VEX_LEN_38F3_R_1_P_0): Likewise.
694 (VEX_LEN_38F3_R_2_P_0): Likewise.
695 (VEX_LEN_38F3_R_3_P_0): Likewise.
696 (VEX_LEN_38F7_P_0): Likewise.
697 (dis386_twobyte): Use PREFIX_0FBC.
698 (reg_table): Add REG_VEX_38F3.
699 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
700 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
701 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
702 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
704 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
705 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
708 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
709 (cpu_flags): Add CpuBMI.
711 * i386-opc.h (CpuBMI): New.
712 (i386_cpu_flags): Add cpubmi.
714 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
715 * i386-init.h: Regenerated.
716 * i386-tbl.h: Likewise.
718 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
720 * i386-dis.c (VexGdq): New.
721 (OP_VEX): Handle dq_mode.
723 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
725 * i386-gen.c (process_copyright): Update copyright to 2011.
727 For older changes see ChangeLog-2010
733 version-control: never