1 2016-10-06 Alan Modra <amodra@gmail.com>
3 * aarch64-opc.c: Spell fall through comments consistently.
4 * i386-dis.c: Likewise.
5 * aarch64-dis.c: Add missing fall through comments.
6 * aarch64-opc.c: Likewise.
9 * i386-dis.c: Likewise.
10 * m68k-dis.c: Likewise.
11 * mep-asm.c: Likewise.
12 * ns32k-dis.c: Likewise.
14 * tic4x-dis.c: Likewise.
15 * tic6x-dis.c: Likewise.
16 * vax-dis.c: Likewise.
18 2016-10-06 Alan Modra <amodra@gmail.com>
20 * arc-ext.c (create_map): Add missing break.
21 * msp430-decode.opc (encode_as): Likewise.
22 * msp430-decode.c: Regenerate.
24 2016-10-06 Alan Modra <amodra@gmail.com>
26 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
27 * crx-dis.c (print_insn_crx): Likewise.
29 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
32 * i386-dis.c (putop): Don't assign alt twice.
34 2016-09-29 Jiong Wang <jiong.wang@arm.com>
37 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
39 2016-09-29 Alan Modra <amodra@gmail.com>
41 * ppc-opc.c (L): Make compulsory.
42 (LOPT): New, optional form of L.
43 (HTM_R): Define as LOPT.
45 (L32OPT): New, optional for 32-bit L.
46 (L2OPT): New, 2-bit L for dcbf.
49 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
50 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
52 <tlbiel, tlbie>: Use LOPT.
53 <wclr, wclrall>: Use L2.
55 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
57 * Makefile.in: Regenerate.
58 * configure: Likewise.
60 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
62 * arc-ext-tbl.h (EXTINSN2OPF): Define.
63 (EXTINSN2OP): Use EXTINSN2OPF.
64 (bspeekm, bspop, modapp): New extension instructions.
65 * arc-opc.c (F_DNZ_ND): Define.
70 * arc-tbl.h (dbnz): New instruction.
71 (prealloc): Allow it for ARC EM.
74 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
76 * aarch64-opc.c (print_immediate_offset_address): Print spaces
77 after commas in addresses.
78 (aarch64_print_operand): Likewise.
80 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
82 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
83 rather than "should be" or "expected to be" in error messages.
85 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
87 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
88 (print_mnemonic_name): ...here.
89 (print_comment): New function.
90 (print_aarch64_insn): Call it.
91 * aarch64-opc.c (aarch64_conds): Add SVE names.
92 (aarch64_print_operand): Print alternative condition names in
95 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
97 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
98 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
99 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
100 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
101 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
102 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
103 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
104 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
105 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
106 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
107 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
108 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
109 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
110 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
111 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
112 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
113 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
114 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
115 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
116 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
117 (OP_SVE_XWU, OP_SVE_XXU): New macros.
118 (aarch64_feature_sve): New variable.
120 (_SVE_INSN): Likewise.
121 (aarch64_opcode_table): Add SVE instructions.
122 * aarch64-opc.h (extract_fields): Declare.
123 * aarch64-opc-2.c: Regenerate.
124 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
125 * aarch64-asm-2.c: Regenerate.
126 * aarch64-dis.c (extract_fields): Make global.
127 (do_misc_decoding): Handle the new SVE aarch64_ops.
128 * aarch64-dis-2.c: Regenerate.
130 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
132 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
133 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
135 * aarch64-opc.c (fields): Add corresponding entries.
136 * aarch64-asm.c (aarch64_get_variant): New function.
137 (aarch64_encode_variant_using_iclass): Likewise.
138 (aarch64_opcode_encode): Call it.
139 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
140 (aarch64_opcode_decode): Call it.
142 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
144 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
145 and FP register operands.
146 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
147 (FLD_SVE_Vn): New aarch64_field_kinds.
148 * aarch64-opc.c (fields): Add corresponding entries.
149 (aarch64_print_operand): Handle the new SVE core and FP register
151 * aarch64-opc-2.c: Regenerate.
152 * aarch64-asm-2.c: Likewise.
153 * aarch64-dis-2.c: Likewise.
155 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
157 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
159 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
160 * aarch64-opc.c (fields): Add corresponding entry.
161 (operand_general_constraint_met_p): Handle the new SVE FP immediate
163 (aarch64_print_operand): Likewise.
164 * aarch64-opc-2.c: Regenerate.
165 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
166 (ins_sve_float_zero_one): New inserters.
167 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
168 (aarch64_ins_sve_float_half_two): Likewise.
169 (aarch64_ins_sve_float_zero_one): Likewise.
170 * aarch64-asm-2.c: Regenerate.
171 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
172 (ext_sve_float_zero_one): New extractors.
173 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
174 (aarch64_ext_sve_float_half_two): Likewise.
175 (aarch64_ext_sve_float_zero_one): Likewise.
176 * aarch64-dis-2.c: Regenerate.
178 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
180 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
181 integer immediate operands.
182 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
183 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
184 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
185 * aarch64-opc.c (fields): Add corresponding entries.
186 (operand_general_constraint_met_p): Handle the new SVE integer
188 (aarch64_print_operand): Likewise.
189 (aarch64_sve_dupm_mov_immediate_p): New function.
190 * aarch64-opc-2.c: Regenerate.
191 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
192 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
193 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
194 (aarch64_ins_limm): ...here.
195 (aarch64_ins_inv_limm): New function.
196 (aarch64_ins_sve_aimm): Likewise.
197 (aarch64_ins_sve_asimm): Likewise.
198 (aarch64_ins_sve_limm_mov): Likewise.
199 (aarch64_ins_sve_shlimm): Likewise.
200 (aarch64_ins_sve_shrimm): Likewise.
201 * aarch64-asm-2.c: Regenerate.
202 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
203 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
204 * aarch64-dis.c (decode_limm): New function, split out from...
205 (aarch64_ext_limm): ...here.
206 (aarch64_ext_inv_limm): New function.
207 (decode_sve_aimm): Likewise.
208 (aarch64_ext_sve_aimm): Likewise.
209 (aarch64_ext_sve_asimm): Likewise.
210 (aarch64_ext_sve_limm_mov): Likewise.
211 (aarch64_top_bit): Likewise.
212 (aarch64_ext_sve_shlimm): Likewise.
213 (aarch64_ext_sve_shrimm): Likewise.
214 * aarch64-dis-2.c: Regenerate.
216 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
218 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
220 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
221 the AARCH64_MOD_MUL_VL entry.
222 (value_aligned_p): Cope with non-power-of-two alignments.
223 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
224 (print_immediate_offset_address): Likewise.
225 (aarch64_print_operand): Likewise.
226 * aarch64-opc-2.c: Regenerate.
227 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
228 (ins_sve_addr_ri_s9xvl): New inserters.
229 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
230 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
231 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
232 * aarch64-asm-2.c: Regenerate.
233 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
234 (ext_sve_addr_ri_s9xvl): New extractors.
235 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
236 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
237 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
238 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
239 * aarch64-dis-2.c: Regenerate.
241 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
243 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
245 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
246 (FLD_SVE_xs_22): New aarch64_field_kinds.
247 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
248 (get_operand_specific_data): New function.
249 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
250 FLD_SVE_xs_14 and FLD_SVE_xs_22.
251 (operand_general_constraint_met_p): Handle the new SVE address
253 (sve_reg): New array.
254 (get_addr_sve_reg_name): New function.
255 (aarch64_print_operand): Handle the new SVE address operands.
256 * aarch64-opc-2.c: Regenerate.
257 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
258 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
259 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
260 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
261 (aarch64_ins_sve_addr_rr_lsl): Likewise.
262 (aarch64_ins_sve_addr_rz_xtw): Likewise.
263 (aarch64_ins_sve_addr_zi_u5): Likewise.
264 (aarch64_ins_sve_addr_zz): Likewise.
265 (aarch64_ins_sve_addr_zz_lsl): Likewise.
266 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
267 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
268 * aarch64-asm-2.c: Regenerate.
269 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
270 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
271 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
272 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
273 (aarch64_ext_sve_addr_ri_u6): Likewise.
274 (aarch64_ext_sve_addr_rr_lsl): Likewise.
275 (aarch64_ext_sve_addr_rz_xtw): Likewise.
276 (aarch64_ext_sve_addr_zi_u5): Likewise.
277 (aarch64_ext_sve_addr_zz): Likewise.
278 (aarch64_ext_sve_addr_zz_lsl): Likewise.
279 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
280 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
281 * aarch64-dis-2.c: Regenerate.
283 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
285 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
286 AARCH64_OPND_SVE_PATTERN_SCALED.
287 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
288 * aarch64-opc.c (fields): Add a corresponding entry.
289 (set_multiplier_out_of_range_error): New function.
290 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
291 (operand_general_constraint_met_p): Handle
292 AARCH64_OPND_SVE_PATTERN_SCALED.
293 (print_register_offset_address): Use PRIi64 to print the
295 (aarch64_print_operand): Likewise. Handle
296 AARCH64_OPND_SVE_PATTERN_SCALED.
297 * aarch64-opc-2.c: Regenerate.
298 * aarch64-asm.h (ins_sve_scale): New inserter.
299 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
300 * aarch64-asm-2.c: Regenerate.
301 * aarch64-dis.h (ext_sve_scale): New inserter.
302 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
303 * aarch64-dis-2.c: Regenerate.
305 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
307 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
308 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
309 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
310 (FLD_SVE_prfop): Likewise.
311 * aarch64-opc.c: Include libiberty.h.
312 (aarch64_sve_pattern_array): New variable.
313 (aarch64_sve_prfop_array): Likewise.
314 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
315 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
316 AARCH64_OPND_SVE_PRFOP.
317 * aarch64-asm-2.c: Regenerate.
318 * aarch64-dis-2.c: Likewise.
319 * aarch64-opc-2.c: Likewise.
321 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
323 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
324 AARCH64_OPND_QLF_P_[ZM].
325 (aarch64_print_operand): Print /z and /m where appropriate.
327 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
329 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
330 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
331 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
332 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
333 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
334 * aarch64-opc.c (fields): Add corresponding entries here.
335 (operand_general_constraint_met_p): Check that SVE register lists
336 have the correct length. Check the ranges of SVE index registers.
337 Check for cases where p8-p15 are used in 3-bit predicate fields.
338 (aarch64_print_operand): Handle the new SVE operands.
339 * aarch64-opc-2.c: Regenerate.
340 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
341 * aarch64-asm.c (aarch64_ins_sve_index): New function.
342 (aarch64_ins_sve_reglist): Likewise.
343 * aarch64-asm-2.c: Regenerate.
344 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
345 * aarch64-dis.c (aarch64_ext_sve_index): New function.
346 (aarch64_ext_sve_reglist): Likewise.
347 * aarch64-dis-2.c: Regenerate.
349 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
351 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
352 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
353 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
354 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
357 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
359 * aarch64-opc.c (get_offset_int_reg_name): New function.
360 (print_immediate_offset_address): Likewise.
361 (print_register_offset_address): Take the base and offset
362 registers as parameters.
363 (aarch64_print_operand): Update caller accordingly. Use
364 print_immediate_offset_address.
366 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
368 * aarch64-opc.c (BANK): New macro.
369 (R32, R64): Take a register number as argument
372 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
374 * aarch64-opc.c (print_register_list): Add a prefix parameter.
375 (aarch64_print_operand): Update accordingly.
377 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
379 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
381 * aarch64-asm.h (ins_fpimm): New inserter.
382 * aarch64-asm.c (aarch64_ins_fpimm): New function.
383 * aarch64-asm-2.c: Regenerate.
384 * aarch64-dis.h (ext_fpimm): New extractor.
385 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
386 (aarch64_ext_fpimm): New function.
387 * aarch64-dis-2.c: Regenerate.
389 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
391 * aarch64-asm.c: Include libiberty.h.
392 (insert_fields): New function.
393 (aarch64_ins_imm): Use it.
394 * aarch64-dis.c (extract_fields): New function.
395 (aarch64_ext_imm): Use it.
397 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
399 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
400 with an esize parameter.
401 (operand_general_constraint_met_p): Update accordingly.
402 Fix misindented code.
403 * aarch64-asm.c (aarch64_ins_limm): Update call to
404 aarch64_logical_immediate_p.
406 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
408 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
410 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
412 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
414 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
416 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
418 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
420 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
421 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
422 xor3>: Delete mnemonics.
423 <cp_abort>: Rename mnemonic from ...
424 <cpabort>: ...to this.
425 <setb>: Change to a X form instruction.
426 <sync>: Change to 1 operand form.
427 <copy>: Delete mnemonic.
428 <copy_first>: Rename mnemonic from ...
430 <paste, paste.>: Delete mnemonics.
431 <paste_last>: Rename mnemonic from ...
432 <paste.>: ...to this.
434 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
436 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
438 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
440 * s390-mkopc.c (main): Support alternate arch strings.
442 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
444 * s390-opc.txt: Fix kmctr instruction type.
446 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
448 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
449 * i386-init.h: Regenerated.
451 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
453 * opcodes/arc-dis.c (print_insn_arc): Changed.
455 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
457 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
460 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
462 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
463 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
464 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
466 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
468 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
469 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
470 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
471 PREFIX_MOD_3_0FAE_REG_4.
472 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
473 PREFIX_MOD_3_0FAE_REG_4.
474 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
475 (cpu_flags): Add CpuPTWRITE.
476 * i386-opc.h (CpuPTWRITE): New.
477 (i386_cpu_flags): Add cpuptwrite.
478 * i386-opc.tbl: Add ptwrite instruction.
479 * i386-init.h: Regenerated.
480 * i386-tbl.h: Likewise.
482 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
484 * arc-dis.h: Wrap around in extern "C".
486 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
488 * aarch64-tbl.h (V8_2_INSN): New macro.
489 (aarch64_opcode_table): Use it.
491 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
493 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
494 CORE_INSN, __FP_INSN and SIMD_INSN.
496 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
498 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
499 (aarch64_opcode_table): Update uses accordingly.
501 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
502 Kwok Cheung Yeung <kcy@codesourcery.com>
505 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
506 'e_cmplwi' to 'e_cmpli' instead.
507 (OPVUPRT, OPVUPRT_MASK): Define.
508 (powerpc_opcodes): Add E200Z4 insns.
509 (vle_opcodes): Add context save/restore insns.
511 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
513 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
514 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
517 2016-07-27 Graham Markall <graham.markall@embecosm.com>
519 * arc-nps400-tbl.h: Change block comments to GNU format.
520 * arc-dis.c: Add new globals addrtypenames,
521 addrtypenames_max, and addtypeunknown.
522 (get_addrtype): New function.
523 (print_insn_arc): Print colons and address types when
525 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
526 define insert and extract functions for all address types.
527 (arc_operands): Add operands for colon and all address
529 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
530 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
531 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
532 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
533 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
534 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
536 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
538 * configure: Regenerated.
540 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
542 * arc-dis.c (skipclass): New structure.
543 (decodelist): New variable.
544 (is_compatible_p): New function.
545 (new_element): Likewise.
546 (skip_class_p): Likewise.
547 (find_format_from_table): Use skip_class_p function.
548 (find_format): Decode first the extension instructions.
549 (print_insn_arc): Select either ARCEM or ARCHS based on elf
551 (parse_option): New function.
552 (parse_disassembler_options): Likewise.
553 (print_arc_disassembler_options): Likewise.
554 (print_insn_arc): Use parse_disassembler_options function. Proper
555 select ARCv2 cpu variant.
556 * disassemble.c (disassembler_usage): Add ARC disassembler
559 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
561 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
562 annotation from the "nal" entry and reorder it beyond "bltzal".
564 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
566 * sparc-opc.c (ldtxa): New macro.
567 (sparc_opcodes): Use the macro defined above to add entries for
568 the LDTXA instructions.
569 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
572 2016-07-07 James Bowman <james.bowman@ftdichip.com>
574 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
577 2016-07-01 Jan Beulich <jbeulich@suse.com>
579 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
580 (movzb): Adjust to cover all permitted suffixes.
582 * i386-tbl.h: Re-generate.
584 2016-07-01 Jan Beulich <jbeulich@suse.com>
586 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
587 (lgdt): Remove Tbyte from non-64-bit variant.
588 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
589 xsaves64, xsavec64): Remove Disp16.
590 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
591 Remove Disp32S from non-64-bit variants. Remove Disp16 from
593 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
594 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
595 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
597 * i386-tbl.h: Re-generate.
599 2016-07-01 Jan Beulich <jbeulich@suse.com>
601 * i386-opc.tbl (xlat): Remove RepPrefixOk.
602 * i386-tbl.h: Re-generate.
604 2016-06-30 Yao Qi <yao.qi@linaro.org>
606 * arm-dis.c (print_insn): Fix typo in comment.
608 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
610 * aarch64-opc.c (operand_general_constraint_met_p): Check the
611 range of ldst_elemlist operands.
612 (print_register_list): Use PRIi64 to print the index.
613 (aarch64_print_operand): Likewise.
615 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
617 * mcore-opc.h: Remove sentinal.
618 * mcore-dis.c (print_insn_mcore): Adjust.
620 2016-06-23 Graham Markall <graham.markall@embecosm.com>
622 * arc-opc.c: Correct description of availability of NPS400
625 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
627 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
628 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
629 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
630 xor3>: New mnemonics.
631 <setb>: Change to a VX form instruction.
632 (insert_sh6): Add support for rldixor.
633 (extract_sh6): Likewise.
635 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
637 * arc-ext.h: Wrap in extern C.
639 2016-06-21 Graham Markall <graham.markall@embecosm.com>
641 * arc-dis.c (arc_insn_length): Add comment on instruction length.
642 Use same method for determining instruction length on ARC700 and
644 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
645 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
646 with the NPS400 subclass.
647 * arc-opc.c: Likewise.
649 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
651 * sparc-opc.c (rdasr): New macro.
657 (sparc_opcodes): Use the macros above to fix and expand the
658 definition of read/write instructions from/to
659 asr/privileged/hyperprivileged instructions.
660 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
661 %hva_mask_nz. Prefer softint_set and softint_clear over
662 set_softint and clear_softint.
663 (print_insn_sparc): Support %ver in Rd.
665 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
667 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
668 architecture according to the hardware capabilities they require.
670 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
672 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
673 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
674 bfd_mach_sparc_v9{c,d,e,v,m}.
675 * sparc-opc.c (MASK_V9C): Define.
676 (MASK_V9D): Likewise.
677 (MASK_V9E): Likewise.
678 (MASK_V9V): Likewise.
679 (MASK_V9M): Likewise.
680 (v6): Add MASK_V9{C,D,E,V,M}.
681 (v6notlet): Likewise.
685 (v9andleon): Likewise.
693 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
695 2016-06-15 Nick Clifton <nickc@redhat.com>
697 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
698 constants to match expected behaviour.
699 (nds32_parse_opcode): Likewise. Also for whitespace.
701 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
703 * arc-opc.c (extract_rhv1): Extract value from insn.
705 2016-06-14 Graham Markall <graham.markall@embecosm.com>
707 * arc-nps400-tbl.h: Add ldbit instruction.
708 * arc-opc.c: Add flag classes required for ldbit.
710 2016-06-14 Graham Markall <graham.markall@embecosm.com>
712 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
713 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
714 support the above instructions.
716 2016-06-14 Graham Markall <graham.markall@embecosm.com>
718 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
719 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
720 csma, cbba, zncv, and hofs.
721 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
722 support the above instructions.
724 2016-06-06 Graham Markall <graham.markall@embecosm.com>
726 * arc-nps400-tbl.h: Add andab and orab instructions.
728 2016-06-06 Graham Markall <graham.markall@embecosm.com>
730 * arc-nps400-tbl.h: Add addl-like instructions.
732 2016-06-06 Graham Markall <graham.markall@embecosm.com>
734 * arc-nps400-tbl.h: Add mxb and imxb instructions.
736 2016-06-06 Graham Markall <graham.markall@embecosm.com>
738 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
741 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
743 * s390-dis.c (option_use_insn_len_bits_p): New file scope
745 (init_disasm): Handle new command line option "insnlength".
746 (print_s390_disassembler_options): Mention new option in help
748 (print_insn_s390): Use the encoded insn length when dumping
749 unknown instructions.
751 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
753 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
754 to the address and set as symbol address for LDS/ STS immediate operands.
756 2016-06-07 Alan Modra <amodra@gmail.com>
758 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
759 cpu for "vle" to e500.
760 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
761 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
762 (PPCNONE): Delete, substitute throughout.
763 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
764 except for major opcode 4 and 31.
765 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
767 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
769 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
770 ARM_EXT_RAS in relevant entries.
772 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
775 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
778 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
781 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
783 Add comments for '&'.
784 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
786 (intel_operand_size): Handle indir_v_mode.
787 (OP_E_register): Likewise.
788 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
789 64-bit indirect call/jmp for AMD64.
790 * i386-tbl.h: Regenerated
792 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
794 * arc-dis.c (struct arc_operand_iterator): New structure.
795 (find_format_from_table): All the old content from find_format,
796 with some minor adjustments, and parameter renaming.
797 (find_format_long_instructions): New function.
798 (find_format): Rewritten.
799 (arc_insn_length): Add LSB parameter.
800 (extract_operand_value): New function.
801 (operand_iterator_next): New function.
802 (print_insn_arc): Use new functions to find opcode, and iterator
804 * arc-opc.c (insert_nps_3bit_dst_short): New function.
805 (extract_nps_3bit_dst_short): New function.
806 (insert_nps_3bit_src2_short): New function.
807 (extract_nps_3bit_src2_short): New function.
808 (insert_nps_bitop1_size): New function.
809 (extract_nps_bitop1_size): New function.
810 (insert_nps_bitop2_size): New function.
811 (extract_nps_bitop2_size): New function.
812 (insert_nps_bitop_mod4_msb): New function.
813 (extract_nps_bitop_mod4_msb): New function.
814 (insert_nps_bitop_mod4_lsb): New function.
815 (extract_nps_bitop_mod4_lsb): New function.
816 (insert_nps_bitop_dst_pos3_pos4): New function.
817 (extract_nps_bitop_dst_pos3_pos4): New function.
818 (insert_nps_bitop_ins_ext): New function.
819 (extract_nps_bitop_ins_ext): New function.
820 (arc_operands): Add new operands.
821 (arc_long_opcodes): New global array.
822 (arc_num_long_opcodes): New global.
823 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
825 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
827 * nds32-asm.h: Add extern "C".
828 * sh-opc.h: Likewise.
830 2016-06-01 Graham Markall <graham.markall@embecosm.com>
832 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
833 0,b,limm to the rflt instruction.
835 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
837 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
840 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
843 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
844 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
845 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
846 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
847 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
848 * i386-init.h: Regenerated.
850 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
853 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
854 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
855 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
856 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
857 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
858 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
859 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
860 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
861 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
862 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
863 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
864 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
865 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
866 CpuRegMask for AVX512.
867 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
869 (set_bitfield_from_cpu_flag_init): New function.
870 (set_bitfield): Remove const on f. Call
871 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
872 * i386-opc.h (CpuRegMMX): New.
873 (CpuRegXMM): Likewise.
874 (CpuRegYMM): Likewise.
875 (CpuRegZMM): Likewise.
876 (CpuRegMask): Likewise.
877 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
879 * i386-init.h: Regenerated.
880 * i386-tbl.h: Likewise.
882 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
885 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
886 (opcode_modifiers): Add AMD64 and Intel64.
887 (main): Properly verify CpuMax.
888 * i386-opc.h (CpuAMD64): Removed.
889 (CpuIntel64): Likewise.
890 (CpuMax): Set to CpuNo64.
891 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
894 (i386_opcode_modifier): Add amd64 and intel64.
895 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
897 * i386-init.h: Regenerated.
898 * i386-tbl.h: Likewise.
900 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
903 * i386-gen.c (main): Fail if CpuMax is incorrect.
904 * i386-opc.h (CpuMax): Set to CpuIntel64.
905 * i386-tbl.h: Regenerated.
907 2016-05-27 Nick Clifton <nickc@redhat.com>
910 * msp430-dis.c (msp430dis_read_two_bytes): New function.
911 (msp430dis_opcode_unsigned): New function.
912 (msp430dis_opcode_signed): New function.
913 (msp430_singleoperand): Use the new opcode reading functions.
914 Only disassenmble bytes if they were successfully read.
915 (msp430_doubleoperand): Likewise.
916 (msp430_branchinstr): Likewise.
917 (msp430x_callx_instr): Likewise.
918 (print_insn_msp430): Check that it is safe to read bytes before
919 attempting disassembly. Use the new opcode reading functions.
921 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
923 * ppc-opc.c (CY): New define. Document it.
924 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
926 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
928 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
929 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
930 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
931 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
933 * i386-init.h: Regenerated.
935 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
938 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
939 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
940 * i386-init.h: Regenerated.
942 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
944 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
945 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
946 * i386-init.h: Regenerated.
948 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
950 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
952 (print_insn_arc): Set insn_type information.
953 * arc-opc.c (C_CC): Add F_CLASS_COND.
954 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
955 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
956 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
957 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
958 (brne, brne_s, jeq_s, jne_s): Likewise.
960 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
962 * arc-tbl.h (neg): New instruction variant.
964 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
966 * arc-dis.c (find_format, find_format, get_auxreg)
967 (print_insn_arc): Changed.
968 * arc-ext.h (INSERT_XOP): Likewise.
970 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
972 * tic54x-dis.c (sprint_mmr): Adjust.
973 * tic54x-opc.c: Likewise.
975 2016-05-19 Alan Modra <amodra@gmail.com>
977 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
979 2016-05-19 Alan Modra <amodra@gmail.com>
981 * ppc-opc.c: Formatting.
982 (NSISIGNOPT): Define.
983 (powerpc_opcodes <subis>): Use NSISIGNOPT.
985 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
987 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
988 replacing references to `micromips_ase' throughout.
989 (_print_insn_mips): Don't use file-level microMIPS annotation to
990 determine the disassembly mode with the symbol table.
992 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
994 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
996 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
998 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1000 * mips-opc.c (D34): New macro.
1001 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1003 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1005 * i386-dis.c (prefix_table): Add RDPID instruction.
1006 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1007 (cpu_flags): Add RDPID bitfield.
1008 * i386-opc.h (enum): Add RDPID element.
1009 (i386_cpu_flags): Add RDPID field.
1010 * i386-opc.tbl: Add RDPID instruction.
1011 * i386-init.h: Regenerate.
1012 * i386-tbl.h: Regenerate.
1014 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1016 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1017 branch type of a symbol.
1018 (print_insn): Likewise.
1020 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1022 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1023 Mainline Security Extensions instructions.
1024 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1025 Extensions instructions.
1026 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1028 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1031 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1033 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1035 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1037 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1038 (arcExtMap_genOpcode): Likewise.
1039 * arc-opc.c (arg_32bit_rc): Define new variable.
1040 (arg_32bit_u6): Likewise.
1041 (arg_32bit_limm): Likewise.
1043 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1045 * aarch64-gen.c (VERIFIER): Define.
1046 * aarch64-opc.c (VERIFIER): Define.
1047 (verify_ldpsw): Use static linkage.
1048 * aarch64-opc.h (verify_ldpsw): Remove.
1049 * aarch64-tbl.h: Use VERIFIER for verifiers.
1051 2016-04-28 Nick Clifton <nickc@redhat.com>
1054 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1055 * aarch64-opc.c (verify_ldpsw): New function.
1056 * aarch64-opc.h (verify_ldpsw): New prototype.
1057 * aarch64-tbl.h: Add initialiser for verifier field.
1058 (LDPSW): Set verifier to verify_ldpsw.
1060 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1064 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1065 smaller than address size.
1067 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1069 * alpha-dis.c: Regenerate.
1070 * crx-dis.c: Likewise.
1071 * disassemble.c: Likewise.
1072 * epiphany-opc.c: Likewise.
1073 * fr30-opc.c: Likewise.
1074 * frv-opc.c: Likewise.
1075 * ip2k-opc.c: Likewise.
1076 * iq2000-opc.c: Likewise.
1077 * lm32-opc.c: Likewise.
1078 * lm32-opinst.c: Likewise.
1079 * m32c-opc.c: Likewise.
1080 * m32r-opc.c: Likewise.
1081 * m32r-opinst.c: Likewise.
1082 * mep-opc.c: Likewise.
1083 * mt-opc.c: Likewise.
1084 * or1k-opc.c: Likewise.
1085 * or1k-opinst.c: Likewise.
1086 * tic80-opc.c: Likewise.
1087 * xc16x-opc.c: Likewise.
1088 * xstormy16-opc.c: Likewise.
1090 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1092 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1093 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1094 calcsd, and calcxd instructions.
1095 * arc-opc.c (insert_nps_bitop_size): Delete.
1096 (extract_nps_bitop_size): Delete.
1097 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1098 (extract_nps_qcmp_m3): Define.
1099 (extract_nps_qcmp_m2): Define.
1100 (extract_nps_qcmp_m1): Define.
1101 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1102 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1103 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1104 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1105 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1108 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1110 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1112 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1114 * Makefile.in: Regenerated with automake 1.11.6.
1115 * aclocal.m4: Likewise.
1117 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1119 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1121 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1122 (extract_nps_cmem_uimm16): New function.
1123 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1125 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1127 * arc-dis.c (arc_insn_length): New function.
1128 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1129 (find_format): Change insnLen parameter to unsigned.
1131 2016-04-13 Nick Clifton <nickc@redhat.com>
1134 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1135 the LD.B and LD.BU instructions.
1137 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1139 * arc-dis.c (find_format): Check for extension flags.
1140 (print_flags): New function.
1141 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1143 * arc-ext.c (arcExtMap_coreRegName): Use
1144 LAST_EXTENSION_CORE_REGISTER.
1145 (arcExtMap_coreReadWrite): Likewise.
1146 (dump_ARC_extmap): Update printing.
1147 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1148 (arc_aux_regs): Add cpu field.
1149 * arc-regs.h: Add cpu field, lower case name aux registers.
1151 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1153 * arc-tbl.h: Add rtsc, sleep with no arguments.
1155 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1157 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1159 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1160 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1161 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1162 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1163 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1164 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1165 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1166 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1167 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1168 (arc_opcode arc_opcodes): Null terminate the array.
1169 (arc_num_opcodes): Remove.
1170 * arc-ext.h (INSERT_XOP): Define.
1171 (extInstruction_t): Likewise.
1172 (arcExtMap_instName): Delete.
1173 (arcExtMap_insn): New function.
1174 (arcExtMap_genOpcode): Likewise.
1175 * arc-ext.c (ExtInstruction): Remove.
1176 (create_map): Zero initialize instruction fields.
1177 (arcExtMap_instName): Remove.
1178 (arcExtMap_insn): New function.
1179 (dump_ARC_extmap): More info while debuging.
1180 (arcExtMap_genOpcode): New function.
1181 * arc-dis.c (find_format): New function.
1182 (print_insn_arc): Use find_format.
1183 (arc_get_disassembler): Enable dump_ARC_extmap only when
1186 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1188 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1189 instruction bits out.
1191 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1193 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1194 * arc-opc.c (arc_flag_operands): Add new flags.
1195 (arc_flag_classes): Add new classes.
1197 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1199 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1201 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1203 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1204 encode1, rflt, crc16, and crc32 instructions.
1205 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1206 (arc_flag_classes): Add C_NPS_R.
1207 (insert_nps_bitop_size_2b): New function.
1208 (extract_nps_bitop_size_2b): Likewise.
1209 (insert_nps_bitop_uimm8): Likewise.
1210 (extract_nps_bitop_uimm8): Likewise.
1211 (arc_operands): Add new operand entries.
1213 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1215 * arc-regs.h: Add a new subclass field. Add double assist
1216 accumulator register values.
1217 * arc-tbl.h: Use DPA subclass to mark the double assist
1218 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1219 * arc-opc.c (RSP): Define instead of SP.
1220 (arc_aux_regs): Add the subclass field.
1222 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1224 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1226 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1228 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1231 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1233 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1234 issues. No functional changes.
1236 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1238 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1239 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1240 (RTT): Remove duplicate.
1241 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1242 (PCT_CONFIG*): Remove.
1243 (D1L, D1H, D2H, D2L): Define.
1245 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1247 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1249 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1251 * arc-tbl.h (invld07): Remove.
1252 * arc-ext-tbl.h: New file.
1253 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1254 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1256 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1258 Fix -Wstack-usage warnings.
1259 * aarch64-dis.c (print_operands): Substitute size.
1260 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1262 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1264 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1265 to get a proper diagnostic when an invalid ASR register is used.
1267 2016-03-22 Nick Clifton <nickc@redhat.com>
1269 * configure: Regenerate.
1271 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1273 * arc-nps400-tbl.h: New file.
1274 * arc-opc.c: Add top level comment.
1275 (insert_nps_3bit_dst): New function.
1276 (extract_nps_3bit_dst): New function.
1277 (insert_nps_3bit_src2): New function.
1278 (extract_nps_3bit_src2): New function.
1279 (insert_nps_bitop_size): New function.
1280 (extract_nps_bitop_size): New function.
1281 (arc_flag_operands): Add nps400 entries.
1282 (arc_flag_classes): Add nps400 entries.
1283 (arc_operands): Add nps400 entries.
1284 (arc_opcodes): Add nps400 include.
1286 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1288 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1289 the new class enum values.
1291 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1293 * arc-dis.c (print_insn_arc): Handle nps400.
1295 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1297 * arc-opc.c (BASE): Delete.
1299 2016-03-18 Nick Clifton <nickc@redhat.com>
1302 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1303 of MOV insn that aliases an ORR insn.
1305 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1307 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1309 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1311 * mcore-opc.h: Add const qualifiers.
1312 * microblaze-opc.h (struct op_code_struct): Likewise.
1313 * sh-opc.h: Likewise.
1314 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1315 (tic4x_print_op): Likewise.
1317 2016-03-02 Alan Modra <amodra@gmail.com>
1319 * or1k-desc.h: Regenerate.
1320 * fr30-ibld.c: Regenerate.
1321 * rl78-decode.c: Regenerate.
1323 2016-03-01 Nick Clifton <nickc@redhat.com>
1326 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1328 2016-02-24 Renlin Li <renlin.li@arm.com>
1330 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1331 (print_insn_coprocessor): Support fp16 instructions.
1333 2016-02-24 Renlin Li <renlin.li@arm.com>
1335 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1336 vminnm, vrint(mpna).
1338 2016-02-24 Renlin Li <renlin.li@arm.com>
1340 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1341 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1343 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1345 * i386-dis.c (print_insn): Parenthesize expression to prevent
1346 truncated addresses.
1349 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1350 Janek van Oirschot <jvanoirs@synopsys.com>
1352 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1355 2016-02-04 Nick Clifton <nickc@redhat.com>
1358 * msp430-dis.c (print_insn_msp430): Add a special case for
1359 decoding an RRC instruction with the ZC bit set in the extension
1362 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1364 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1365 * epiphany-ibld.c: Regenerate.
1366 * fr30-ibld.c: Regenerate.
1367 * frv-ibld.c: Regenerate.
1368 * ip2k-ibld.c: Regenerate.
1369 * iq2000-ibld.c: Regenerate.
1370 * lm32-ibld.c: Regenerate.
1371 * m32c-ibld.c: Regenerate.
1372 * m32r-ibld.c: Regenerate.
1373 * mep-ibld.c: Regenerate.
1374 * mt-ibld.c: Regenerate.
1375 * or1k-ibld.c: Regenerate.
1376 * xc16x-ibld.c: Regenerate.
1377 * xstormy16-ibld.c: Regenerate.
1379 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1381 * epiphany-dis.c: Regenerated from latest cpu files.
1383 2016-02-01 Michael McConville <mmcco@mykolab.com>
1385 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1388 2016-01-25 Renlin Li <renlin.li@arm.com>
1390 * arm-dis.c (mapping_symbol_for_insn): New function.
1391 (find_ifthen_state): Call mapping_symbol_for_insn().
1393 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1395 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1396 of MSR UAO immediate operand.
1398 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1400 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1401 instruction support.
1403 2016-01-17 Alan Modra <amodra@gmail.com>
1405 * configure: Regenerate.
1407 2016-01-14 Nick Clifton <nickc@redhat.com>
1409 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1410 instructions that can support stack pointer operations.
1411 * rl78-decode.c: Regenerate.
1412 * rl78-dis.c: Fix display of stack pointer in MOVW based
1415 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1417 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1418 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1419 erxtatus_el1 and erxaddr_el1.
1421 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1423 * arm-dis.c (arm_opcodes): Add "esb".
1424 (thumb_opcodes): Likewise.
1426 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1428 * ppc-opc.c <xscmpnedp>: Delete.
1429 <xvcmpnedp>: Likewise.
1430 <xvcmpnedp.>: Likewise.
1431 <xvcmpnesp>: Likewise.
1432 <xvcmpnesp.>: Likewise.
1434 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1437 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1440 2016-01-01 Alan Modra <amodra@gmail.com>
1442 Update year range in copyright notice of all files.
1444 For older changes see ChangeLog-2015
1446 Copyright (C) 2016 Free Software Foundation, Inc.
1448 Copying and distribution of this file, with or without modification,
1449 are permitted in any medium without royalty provided the copyright
1450 notice and this notice are preserved.
1456 version-control: never