1 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
3 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
4 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
5 keyword_aridxi): Add audio ISA extension.
6 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
7 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
8 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
10 (build_opcode_syntax): Remove dead code.
11 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
12 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
13 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
15 * nds32-asm.h: Declare.
16 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
19 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
20 Matthew Fortune <matthew.fortune@imgtec.com>
22 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
24 (parse_mips_dis_option): Allow MSA and virtualization support for
26 (mips_print_arg_state): Add fields dest_regno and seen_dest.
27 (mips_seen_register): New function.
28 (print_insn_arg): Refactored code to use mips_seen_register
29 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
30 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
31 the register rather than aborting.
32 (print_insn_args): Add length argument. Add code to correctly
33 calculate the instruction address for pc relative instructions.
34 (validate_insn_args): New static function.
35 (print_insn_mips): Prevent jalx disassembling for r6. Use
37 (print_insn_micromips): Use validate_insn_args.
38 all the arguments are valid.
39 * mips-formats.h (PREV_CHECK): New define.
40 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
41 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
46 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
47 MIPS R6 instructions from MIPS R2 instructions.
49 2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
51 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
52 (putop): Handle "%LP".
54 2014-09-03 Jiong Wang <jiong.wang@arm.com>
56 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
57 * aarch64-dis-2.c: Update auto-generated file.
59 2014-09-03 Jiong Wang <jiong.wang@arm.com>
61 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
62 (aarch64_feature_lse): New feature added.
64 (aarch64_opcode_table): New LSE instructions added. Improve
65 descriptions for ldarb/ldarh/ldar.
66 (aarch64_opcode_table): Describe PAIRREG.
67 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
68 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
69 (aarch64_print_operand): Recognize PAIRREG.
70 (operand_general_constraint_met_p): Check reg pair constraints for CASP
72 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
73 (do_special_decoding): Recognize F_LSE_SZ.
74 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
76 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
78 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
79 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
80 "sdbbp", "syscall" and "wait".
82 2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
83 Maciej W. Rozycki <macro@codesourcery.com>
85 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
86 returned if the U bit is set.
88 2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
90 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
93 2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
95 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
96 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
97 static functions, code was moved from...
98 (print_insn_s390): ...here.
99 (s390_extract_operand): Adjust comment. Change type of first
100 parameter from 'unsigned char *' to 'const bfd_byte *'.
101 (union operand_value): New.
102 (s390_extract_operand): Change return type to union operand_value.
103 Also avoid integer overflow in sign-extension.
104 (s390_print_insn_with_opcode): Adjust to changed return value from
105 s390_extract_operand(). Change "%i" printf format to "%u" for
107 (init_disasm): Simplify initialization of opc_index[]. This also
108 fixes an access after the last element of s390_opcodes[].
109 (print_insn_s390): Simplify the opcode search loop.
110 Check architecture mask against all searched opcodes, not just the
112 (s390_print_insn_with_opcode): Drop function pointer dereferences
114 (print_insn_s390): Likewise.
115 (s390_insn_length): Simplify formula for return value.
116 (s390_print_insn_with_opcode): Avoid special handling for the
117 separator before the first operand. Use new local variable
118 'flags' in place of 'operand->flags'.
120 2014-08-14 Mike Frysinger <vapier@gentoo.org>
122 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
123 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
124 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
125 Change assignment of 1 to priv->comment to TRUE.
126 (print_insn_bfin): Change legal to a bfd_boolean. Change
127 assignment of 0/1 with priv comment and parallel and legal
130 2014-08-14 Mike Frysinger <vapier@gentoo.org>
132 * bfin-dis.c (OUT): Define.
133 (decode_CC2stat_0): Declare new op_names array.
134 Replace multiple if statements with a single one.
136 2014-08-14 Mike Frysinger <vapier@gentoo.org>
138 * bfin-dis.c (struct private): Add iw0.
139 (_print_insn_bfin): Assign iw0 to priv.iw0.
140 (print_insn_bfin): Drop ifetch and use priv.iw0.
142 2014-08-13 Mike Frysinger <vapier@gentoo.org>
144 * bfin-dis.c (comment, parallel): Move from global scope ...
145 (struct private): ... to this new struct.
146 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
147 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
148 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
149 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
150 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
151 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
152 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
153 print_insn_bfin): Declare private struct. Use priv's comment and
156 2014-08-13 Mike Frysinger <vapier@gentoo.org>
158 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
159 (_print_insn_bfin): Add check for unaligned pc.
161 2014-08-13 Mike Frysinger <vapier@gentoo.org>
163 * bfin-dis.c (ifetch): New function.
164 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
167 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
169 * micromips-opc.c (COD): Rename throughout to...
170 (CM): New define, update to use INSN_COPROC_MOVE.
171 (LCD): Rename throughout to...
172 (LC): New define, update to use INSN_LOAD_COPROC.
173 * mips-opc.c: Likewise.
175 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
177 * micromips-opc.c (COD, LCD) New macros.
178 (cfc1, ctc1): Remove FP_S attribute.
179 (dmfc1, mfc1, mfhc1): Add LCD attribute.
180 (dmtc1, mtc1, mthc1): Add COD attribute.
181 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
183 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
184 Alexander Ivchenko <alexander.ivchenko@intel.com>
185 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
186 Sergey Lega <sergey.s.lega@intel.com>
187 Anna Tikhonova <anna.tikhonova@intel.com>
188 Ilya Tocar <ilya.tocar@intel.com>
189 Andrey Turetskiy <andrey.turetskiy@intel.com>
190 Ilya Verbin <ilya.verbin@intel.com>
191 Kirill Yukhin <kirill.yukhin@intel.com>
192 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
194 * i386-dis-evex.h: Updated.
195 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
196 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
197 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
198 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
200 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
201 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
202 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
203 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
204 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
205 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
206 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
207 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
208 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
209 (prefix_table): Add entries for new instructions.
210 (vex_len_table): Ditto.
211 (vex_w_table): Ditto.
212 (OP_E_memory): Update xmmq_mode handling.
213 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
214 (cpu_flags): Add CpuAVX512DQ.
215 * i386-init.h: Regenerared.
216 * i386-opc.h (CpuAVX512DQ): New.
217 (i386_cpu_flags): Add cpuavx512dq.
218 * i386-opc.tbl: Add AVX512DQ instructions.
219 * i386-tbl.h: Regenerate.
221 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
222 Alexander Ivchenko <alexander.ivchenko@intel.com>
223 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
224 Sergey Lega <sergey.s.lega@intel.com>
225 Anna Tikhonova <anna.tikhonova@intel.com>
226 Ilya Tocar <ilya.tocar@intel.com>
227 Andrey Turetskiy <andrey.turetskiy@intel.com>
228 Ilya Verbin <ilya.verbin@intel.com>
229 Kirill Yukhin <kirill.yukhin@intel.com>
230 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
232 * i386-dis-evex.h: Add new instructions (prefixes bellow).
233 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
234 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
235 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
236 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
237 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
238 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
239 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
240 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
241 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
242 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
243 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
244 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
245 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
246 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
247 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
248 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
249 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
250 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
251 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
252 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
253 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
254 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
255 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
256 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
257 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
258 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
259 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
260 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
261 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
262 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
263 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
264 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
265 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
266 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
267 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
268 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
269 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
270 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
271 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
272 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
273 (prefix_table): Add entries for new instructions.
275 (vex_len_table): Ditto.
276 (vex_w_table): Ditto.
277 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
278 mask_bd_mode handling.
279 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
281 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
283 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
284 (OP_EX): Add dqw_swap_mode handling.
285 (OP_VEX): Add mask_bd_mode handling.
286 (OP_Mask): Add mask_bd_mode handling.
287 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
288 (cpu_flags): Add CpuAVX512BW.
289 * i386-init.h: Regenerated.
290 * i386-opc.h (CpuAVX512BW): New.
291 (i386_cpu_flags): Add cpuavx512bw.
292 * i386-opc.tbl: Add AVX512BW instructions.
293 * i386-tbl.h: Regenerate.
295 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
296 Alexander Ivchenko <alexander.ivchenko@intel.com>
297 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
298 Sergey Lega <sergey.s.lega@intel.com>
299 Anna Tikhonova <anna.tikhonova@intel.com>
300 Ilya Tocar <ilya.tocar@intel.com>
301 Andrey Turetskiy <andrey.turetskiy@intel.com>
302 Ilya Verbin <ilya.verbin@intel.com>
303 Kirill Yukhin <kirill.yukhin@intel.com>
304 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
306 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
307 * i386-tbl.h: Regenerate.
309 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
310 Alexander Ivchenko <alexander.ivchenko@intel.com>
311 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
312 Sergey Lega <sergey.s.lega@intel.com>
313 Anna Tikhonova <anna.tikhonova@intel.com>
314 Ilya Tocar <ilya.tocar@intel.com>
315 Andrey Turetskiy <andrey.turetskiy@intel.com>
316 Ilya Verbin <ilya.verbin@intel.com>
317 Kirill Yukhin <kirill.yukhin@intel.com>
318 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
320 * i386-dis.c (intel_operand_size): Support 128/256 length in
321 vex_vsib_q_w_dq_mode.
322 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
323 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
324 (cpu_flags): Add CpuAVX512VL.
325 * i386-init.h: Regenerated.
326 * i386-opc.h (CpuAVX512VL): New.
327 (i386_cpu_flags): Add cpuavx512vl.
328 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
329 * i386-opc.tbl: Add AVX512VL instructions.
330 * i386-tbl.h: Regenerate.
332 2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
334 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
335 * or1k-opinst.c: Regenerate.
337 2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
339 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
340 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
342 2014-07-04 Alan Modra <amodra@gmail.com>
344 * configure.ac: Rename from configure.in.
345 * Makefile.in: Regenerate.
346 * config.in: Regenerate.
348 2014-07-04 Alan Modra <amodra@gmail.com>
350 * configure.in: Include bfd/version.m4.
351 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
352 (BFD_VERSION): Delete.
353 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
354 * configure: Regenerate.
355 * Makefile.in: Regenerate.
357 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
358 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
359 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
360 Soundararajan <Sounderarajan.D@atmel.com>
362 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
363 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
364 machine is not avrtiny.
366 2014-06-26 Philippe De Muyter <phdm@macqel.be>
368 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
371 2014-06-12 Alan Modra <amodra@gmail.com>
373 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
374 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
376 2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
378 * i386-dis.c (fwait_prefix): New.
379 (ckprefix): Set fwait_prefix.
380 (print_insn): Properly print prefixes before fwait.
382 2014-06-07 Alan Modra <amodra@gmail.com>
384 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
386 2014-06-05 Joel Brobecker <brobecker@adacore.com>
388 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
389 bfd's development.sh.
390 * Makefile.in, configure: Regenerate.
392 2014-06-03 Nick Clifton <nickc@redhat.com>
394 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
395 decide when extended addressing is being used.
397 2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
399 * sparc-opc.c (cas): Disable for LEON.
402 2014-05-20 Alan Modra <amodra@gmail.com>
404 * m68k-dis.c: Don't include setjmp.h.
406 2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
408 * i386-dis.c (ADDR16_PREFIX): Removed.
409 (ADDR32_PREFIX): Likewise.
410 (DATA16_PREFIX): Likewise.
411 (DATA32_PREFIX): Likewise.
412 (prefix_name): Updated.
413 (print_insn): Simplify data and address size prefixes processing.
415 2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
417 * or1k-desc.c: Regenerated.
418 * or1k-desc.h: Likewise.
419 * or1k-opc.c: Likewise.
420 * or1k-opc.h: Likewise.
421 * or1k-opinst.c: Likewise.
423 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
425 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
430 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
432 (parse_mips_dis_option): Update MSA and virtualization support to
433 allow mips64r3 and mips64r5.
435 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
437 * mips-opc.c (G3): Remove I4.
439 2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
442 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
443 (end_codep): Likewise.
444 (mandatory_prefix): Likewise.
445 (active_seg_prefix): Likewise.
446 (ckprefix): Set active_seg_prefix to the active segment register
448 (seg_prefix): Removed.
449 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
450 for prefix index. Ignore the index if it is invalid and the
451 mandatory prefix isn't required.
452 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
453 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
454 in used_prefixes here. Don't print unused prefixes. Check
455 active_seg_prefix for the active segment register prefix.
456 Restore the DFLAG bit in sizeflag if the data size prefix is
457 unused. Check the unused mandatory PREFIX_XXX prefixes
458 (append_seg): Only print the segment register which gets used.
459 (OP_E_memory): Check active_seg_prefix for the segment register
462 (OP_OFF64): Likewise.
463 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
465 2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
468 * config.in: Regenerated.
469 * configure: Likewise.
470 * configure.in: Check if sigsetjmp is available.
471 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
472 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
473 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
474 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
475 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
476 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
477 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
478 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
479 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
480 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
481 (OPCODES_SIGSETJMP): Likewise.
482 (OPCODES_SIGLONGJMP): Likewise.
483 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
484 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
485 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
486 * xtensa-dis.c (dis_private): Replace jmp_buf with
488 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
489 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
490 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
491 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
492 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
494 2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
497 * i386-dis.c (print_insn): Handle prefixes before fwait.
499 2014-04-26 Alan Modra <amodra@gmail.com>
501 * po/POTFILES.in: Regenerate.
503 2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
505 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
506 to allow the MIPS XPA ASE.
507 (parse_mips_dis_option): Process the -Mxpa option.
508 * mips-opc.c (XPA): New define.
509 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
510 locations of the ctc0 and cfc0 instructions.
512 2014-04-22 Christian Svensson <blue@cmd.nu>
514 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
515 * configure.in: Likewise.
516 * disassemble.c: Likewise.
517 * or1k-asm.c: New file.
518 * or1k-desc.c: New file.
519 * or1k-desc.h: New file.
520 * or1k-dis.c: New file.
521 * or1k-ibld.c: New file.
522 * or1k-opc.c: New file.
523 * or1k-opc.h: New file.
524 * or1k-opinst.c: New file.
525 * Makefile.in: Regenerate.
526 * configure: Regenerate.
527 * openrisc-asm.c: Delete.
528 * openrisc-desc.c: Delete.
529 * openrisc-desc.h: Delete.
530 * openrisc-dis.c: Delete.
531 * openrisc-ibld.c: Delete.
532 * openrisc-opc.c: Delete.
533 * openrisc-opc.h: Delete.
534 * or32-dis.c: Delete.
535 * or32-opc.c: Delete.
537 2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
539 * i386-dis.c (rm_table): Add encls, enclu.
540 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
541 (cpu_flags): Add CpuSE1.
542 * i386-opc.h (enum): Add CpuSE1.
543 (i386_cpu_flags): Add cpuse1.
544 * i386-opc.tbl: Add encls, enclu.
545 * i386-init.h: Regenerated.
546 * i386-tbl.h: Likewise.
548 2014-04-02 Anthony Green <green@moxielogic.com>
550 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
551 instructions, sex.b and sex.s.
553 2014-03-26 Jiong Wang <jiong.wang@arm.com>
555 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
558 2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
560 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
561 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
563 * i386-tbl.h: Regenerate.
565 2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
567 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
568 %hstick_enable added.
570 2014-03-19 Nick Clifton <nickc@redhat.com>
572 * rx-decode.opc (bwl): Allow for bogus instructions with a size
574 (sbwl, ubwl, SCALE): Likewise.
575 * rx-decode.c: Regenerate.
577 2014-03-12 Alan Modra <amodra@gmail.com>
579 * Makefile.in: Regenerate.
581 2014-03-05 Alan Modra <amodra@gmail.com>
583 Update copyright years.
585 2014-03-04 Heiher <r@hev.cc>
587 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
589 2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
591 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
592 so that they come after the Loongson extensions.
594 2014-03-03 Alan Modra <amodra@gmail.com>
596 * i386-gen.c (process_copyright): Emit copyright notice on one line.
598 2014-02-28 Alan Modra <amodra@gmail.com>
600 * msp430-decode.c: Regenerate.
602 2014-02-27 Jiong Wang <jiong.wang@arm.com>
604 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
605 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
607 2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
609 * aarch64-opc.c (print_register_offset_address): Call
610 get_int_reg_name to prepare the register name.
612 2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
614 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
615 * i386-tbl.h: Regenerate.
617 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
619 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
620 (cpu_flags): Add CpuPREFETCHWT1.
621 * i386-init.h: Regenerate.
622 * i386-opc.h (CpuPREFETCHWT1): New.
623 (i386_cpu_flags): Add cpuprefetchwt1.
624 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
625 * i386-tbl.h: Regenerate.
627 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
629 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
631 * i386-tbl.h: Regenerate.
633 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
635 * i386-gen.c (output_cpu_flags): Don't output trailing space.
636 (output_opcode_modifier): Likewise.
637 (output_operand_type): Likewise.
638 * i386-init.h: Regenerated.
639 * i386-tbl.h: Likewise.
641 2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
643 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
645 (PREFIX enum): Add PREFIX_0FAE_REG_7.
646 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
647 (prefix_table): Add clflusopt.
648 (mod_table): Add xrstors, xsavec, xsaves.
649 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
650 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
651 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
652 * i386-init.h: Regenerate.
653 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
654 xsaves64, xsavec, xsavec64.
655 * i386-tbl.h: Regenerate.
657 2014-02-10 Alan Modra <amodra@gmail.com>
659 * po/POTFILES.in: Regenerate.
660 * po/opcodes.pot: Regenerate.
662 2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
663 Jan Beulich <jbeulich@suse.com>
666 * i386-dis.c (OP_E_memory): Fix shift computation for
667 vex_vsib_q_w_dq_mode.
669 2014-01-09 Bradley Nelson <bradnelson@google.com>
670 Roland McGrath <mcgrathr@google.com>
672 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
673 last_rex_prefix is -1.
675 2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
677 * i386-gen.c (process_copyright): Update copyright year to 2014.
679 2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
681 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
683 For older changes see ChangeLog-2013
685 Copyright (C) 2014 Free Software Foundation, Inc.
687 Copying and distribution of this file, with or without modification,
688 are permitted in any medium without royalty provided the copyright
689 notice and this notice are preserved.
695 version-control: never