1 2018-10-10 Jan Beulich <jbeulich@suse.com>
3 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
5 * i386-opc.h (Size16, Size32, Size64): Delete.
7 (SIZE16, SIZE32, SIZE64): Define.
8 (struct i386_opcode_modifier): Drop size16, size32, and size64.
10 * i386-opc.tbl (Size16, Size32, Size64): Define.
11 * i386-tbl.h: Re-generate.
13 2018-10-09 Sudakshina Das <sudi.das@arm.com>
15 * aarch64-opc.c (operand_general_constraint_met_p): Add
16 SSBS in the check for one-bit immediate.
17 (aarch64_sys_regs): New entry for SSBS.
18 (aarch64_sys_reg_supported_p): New check for above.
19 (aarch64_pstatefields): New entry for SSBS.
20 (aarch64_pstatefield_supported_p): New check for above.
22 2018-10-09 Sudakshina Das <sudi.das@arm.com>
24 * aarch64-opc.c (aarch64_sys_regs): New entries for
25 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
26 (aarch64_sys_reg_supported_p): New checks for above.
28 2018-10-09 Sudakshina Das <sudi.das@arm.com>
30 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
31 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
32 with the hint immediate.
33 * aarch64-opc.c (aarch64_hint_options): New entries for
34 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
35 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
36 while checking for HINT_OPD_F_NOPRINT flag.
37 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
39 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
40 (aarch64_opcode_table): Add entry for BTI.
41 (AARCH64_OPERANDS): Add new description for BTI targets.
42 * aarch64-asm-2.c: Regenerate.
43 * aarch64-dis-2.c: Regenerate.
44 * aarch64-opc-2.c: Regenerate.
46 2018-10-09 Sudakshina Das <sudi.das@arm.com>
48 * aarch64-opc.c (aarch64_sys_regs): New entries for
50 (aarch64_sys_reg_supported_p): New check for above.
52 2018-10-09 Sudakshina Das <sudi.das@arm.com>
54 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
55 (aarch64_sys_ins_reg_supported_p): New check for above.
57 2018-10-09 Sudakshina Das <sudi.das@arm.com>
59 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
60 AARCH64_OPND_SYSREG_SR.
61 * aarch64-opc.c (aarch64_print_operand): Likewise.
62 (aarch64_sys_regs_sr): Define table.
63 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
64 AARCH64_FEATURE_PREDRES.
65 * aarch64-tbl.h (aarch64_feature_predres): New.
66 (PREDRES, PREDRES_INSN): New.
67 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
68 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
69 * aarch64-asm-2.c: Regenerate.
70 * aarch64-dis-2.c: Regenerate.
71 * aarch64-opc-2.c: Regenerate.
73 2018-10-09 Sudakshina Das <sudi.das@arm.com>
75 * aarch64-tbl.h (aarch64_feature_sb): New.
77 (aarch64_opcode_table): Add entry for sb.
78 * aarch64-asm-2.c: Regenerate.
79 * aarch64-dis-2.c: Regenerate.
80 * aarch64-opc-2.c: Regenerate.
82 2018-10-09 Sudakshina Das <sudi.das@arm.com>
84 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
85 (aarch64_feature_frintts): New.
86 (FLAGMANIP, FRINTTS): New.
87 (aarch64_opcode_table): Add entries for xaflag, axflag
88 and frint[32,64][x,z] instructions.
89 * aarch64-asm-2.c: Regenerate.
90 * aarch64-dis-2.c: Regenerate.
91 * aarch64-opc-2.c: Regenerate.
93 2018-10-09 Sudakshina Das <sudi.das@arm.com>
95 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
96 (ARMV8_5, V8_5_INSN): New.
98 2018-10-08 Tamar Christina <tamar.christina@arm.com>
100 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
102 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
104 * i386-dis.c (rm_table): Add enclv.
105 * i386-opc.tbl: Add enclv.
106 * i386-tbl.h: Regenerated.
108 2018-10-05 Sudakshina Das <sudi.das@arm.com>
110 * arm-dis.c (arm_opcodes): Add sb.
111 (thumb32_opcodes): Likewise.
113 2018-10-05 Richard Henderson <rth@twiddle.net>
114 Stafford Horne <shorne@gmail.com>
116 * or1k-desc.c: Regenerate.
117 * or1k-desc.h: Regenerate.
118 * or1k-opc.c: Regenerate.
119 * or1k-opc.h: Regenerate.
120 * or1k-opinst.c: Regenerate.
122 2018-10-05 Richard Henderson <rth@twiddle.net>
124 * or1k-asm.c: Regenerated.
125 * or1k-desc.c: Regenerated.
126 * or1k-desc.h: Regenerated.
127 * or1k-dis.c: Regenerated.
128 * or1k-ibld.c: Regenerated.
129 * or1k-opc.c: Regenerated.
130 * or1k-opc.h: Regenerated.
131 * or1k-opinst.c: Regenerated.
133 2018-10-05 Richard Henderson <rth@twiddle.net>
135 * or1k-asm.c: Regenerate.
137 2018-10-03 Tamar Christina <tamar.christina@arm.com>
139 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
140 * aarch64-dis.c (print_operands): Refactor to take notes.
141 (print_verifier_notes): New.
142 (print_aarch64_insn): Apply constraint verifier.
143 (print_insn_aarch64_word): Update call to print_aarch64_insn.
144 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
146 2018-10-03 Tamar Christina <tamar.christina@arm.com>
148 * aarch64-opc.c (init_insn_block): New.
149 (verify_constraints, aarch64_is_destructive_by_operands): New.
150 * aarch64-opc.h (verify_constraints): New.
152 2018-10-03 Tamar Christina <tamar.christina@arm.com>
154 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
155 * aarch64-opc.c (verify_ldpsw): Update arguments.
157 2018-10-03 Tamar Christina <tamar.christina@arm.com>
159 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
160 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
162 2018-10-03 Tamar Christina <tamar.christina@arm.com>
164 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
165 * aarch64-dis.c (insn_sequence): New.
167 2018-10-03 Tamar Christina <tamar.christina@arm.com>
169 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
170 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
171 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
172 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
175 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
177 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
179 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
180 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
181 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
182 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
183 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
184 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
185 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
187 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
189 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
191 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
193 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
194 are used when extracting signed fields and converting them to
195 potentially 64-bit types.
197 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
199 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
200 * Makefile.in: Re-generate.
201 * aclocal.m4: Re-generate.
202 * configure: Re-generate.
203 * configure.ac: Remove check for -Wno-missing-field-initializers.
204 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
205 (csky_v2_opcodes): Likewise.
207 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
209 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
211 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
213 * nds32-asm.c (operand_fields): Remove the unused fields.
214 (nds32_opcodes): Remove the unused instructions.
215 * nds32-dis.c (nds32_ex9_info): Removed.
216 (nds32_parse_opcode): Updated.
217 (print_insn_nds32): Likewise.
218 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
219 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
220 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
221 build_opcode_hash_table): New functions.
222 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
223 nds32_opcode_table): New.
224 (hw_ktabs): Declare it to a pointer rather than an array.
225 (build_hash_table): Removed.
226 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
227 SYN_ROPT and upadte HW_GPR and HW_INT.
228 * nds32-dis.c (keywords): Remove const.
229 (match_field): New function.
230 (nds32_parse_opcode): Updated.
231 * disassemble.c (disassemble_init_for_target):
232 Add disassemble_init_nds32.
233 * nds32-dis.c (eum map_type): New.
234 (nds32_private_data): Likewise.
235 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
236 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
237 (print_insn_nds32): Updated.
238 * nds32-asm.c (parse_aext_reg): Add new parameter.
239 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
242 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
243 (operand_fields): Add new fields.
244 (nds32_opcodes): Add new instructions.
245 (keyword_aridxi_mx): New keyword.
246 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
248 (ALU2_1, ALU2_2, ALU2_3): New macros.
249 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
251 2018-09-17 Kito Cheng <kito@andestech.com>
253 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
255 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
258 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
259 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
260 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
261 (EVEX_LEN_0F7E_P_1): Likewise.
262 (EVEX_LEN_0F7E_P_2): Likewise.
263 (EVEX_LEN_0FD6_P_2): Likewise.
264 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
265 (EVEX_LEN_TABLE): Likewise.
266 (EVEX_LEN_0F6E_P_2): New enum.
267 (EVEX_LEN_0F7E_P_1): Likewise.
268 (EVEX_LEN_0F7E_P_2): Likewise.
269 (EVEX_LEN_0FD6_P_2): Likewise.
270 (evex_len_table): New.
271 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
272 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
273 * i386-tbl.h: Regenerated.
275 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
278 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
279 VEX_LEN_0F7E_P_2 entries.
280 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
281 * i386-tbl.h: Regenerated.
283 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
285 * i386-dis.c (VZERO_Fixup): Removed.
287 (VEX_LEN_0F10_P_1): Likewise.
288 (VEX_LEN_0F10_P_3): Likewise.
289 (VEX_LEN_0F11_P_1): Likewise.
290 (VEX_LEN_0F11_P_3): Likewise.
291 (VEX_LEN_0F2E_P_0): Likewise.
292 (VEX_LEN_0F2E_P_2): Likewise.
293 (VEX_LEN_0F2F_P_0): Likewise.
294 (VEX_LEN_0F2F_P_2): Likewise.
295 (VEX_LEN_0F51_P_1): Likewise.
296 (VEX_LEN_0F51_P_3): Likewise.
297 (VEX_LEN_0F52_P_1): Likewise.
298 (VEX_LEN_0F53_P_1): Likewise.
299 (VEX_LEN_0F58_P_1): Likewise.
300 (VEX_LEN_0F58_P_3): Likewise.
301 (VEX_LEN_0F59_P_1): Likewise.
302 (VEX_LEN_0F59_P_3): Likewise.
303 (VEX_LEN_0F5A_P_1): Likewise.
304 (VEX_LEN_0F5A_P_3): Likewise.
305 (VEX_LEN_0F5C_P_1): Likewise.
306 (VEX_LEN_0F5C_P_3): Likewise.
307 (VEX_LEN_0F5D_P_1): Likewise.
308 (VEX_LEN_0F5D_P_3): Likewise.
309 (VEX_LEN_0F5E_P_1): Likewise.
310 (VEX_LEN_0F5E_P_3): Likewise.
311 (VEX_LEN_0F5F_P_1): Likewise.
312 (VEX_LEN_0F5F_P_3): Likewise.
313 (VEX_LEN_0FC2_P_1): Likewise.
314 (VEX_LEN_0FC2_P_3): Likewise.
315 (VEX_LEN_0F3A0A_P_2): Likewise.
316 (VEX_LEN_0F3A0B_P_2): Likewise.
317 (VEX_W_0F10_P_0): Likewise.
318 (VEX_W_0F10_P_1): Likewise.
319 (VEX_W_0F10_P_2): Likewise.
320 (VEX_W_0F10_P_3): Likewise.
321 (VEX_W_0F11_P_0): Likewise.
322 (VEX_W_0F11_P_1): Likewise.
323 (VEX_W_0F11_P_2): Likewise.
324 (VEX_W_0F11_P_3): Likewise.
325 (VEX_W_0F12_P_0_M_0): Likewise.
326 (VEX_W_0F12_P_0_M_1): Likewise.
327 (VEX_W_0F12_P_1): Likewise.
328 (VEX_W_0F12_P_2): Likewise.
329 (VEX_W_0F12_P_3): Likewise.
330 (VEX_W_0F13_M_0): Likewise.
331 (VEX_W_0F14): Likewise.
332 (VEX_W_0F15): Likewise.
333 (VEX_W_0F16_P_0_M_0): Likewise.
334 (VEX_W_0F16_P_0_M_1): Likewise.
335 (VEX_W_0F16_P_1): Likewise.
336 (VEX_W_0F16_P_2): Likewise.
337 (VEX_W_0F17_M_0): Likewise.
338 (VEX_W_0F28): Likewise.
339 (VEX_W_0F29): Likewise.
340 (VEX_W_0F2B_M_0): Likewise.
341 (VEX_W_0F2E_P_0): Likewise.
342 (VEX_W_0F2E_P_2): Likewise.
343 (VEX_W_0F2F_P_0): Likewise.
344 (VEX_W_0F2F_P_2): Likewise.
345 (VEX_W_0F50_M_0): Likewise.
346 (VEX_W_0F51_P_0): Likewise.
347 (VEX_W_0F51_P_1): Likewise.
348 (VEX_W_0F51_P_2): Likewise.
349 (VEX_W_0F51_P_3): Likewise.
350 (VEX_W_0F52_P_0): Likewise.
351 (VEX_W_0F52_P_1): Likewise.
352 (VEX_W_0F53_P_0): Likewise.
353 (VEX_W_0F53_P_1): Likewise.
354 (VEX_W_0F58_P_0): Likewise.
355 (VEX_W_0F58_P_1): Likewise.
356 (VEX_W_0F58_P_2): Likewise.
357 (VEX_W_0F58_P_3): Likewise.
358 (VEX_W_0F59_P_0): Likewise.
359 (VEX_W_0F59_P_1): Likewise.
360 (VEX_W_0F59_P_2): Likewise.
361 (VEX_W_0F59_P_3): Likewise.
362 (VEX_W_0F5A_P_0): Likewise.
363 (VEX_W_0F5A_P_1): Likewise.
364 (VEX_W_0F5A_P_3): Likewise.
365 (VEX_W_0F5B_P_0): Likewise.
366 (VEX_W_0F5B_P_1): Likewise.
367 (VEX_W_0F5B_P_2): Likewise.
368 (VEX_W_0F5C_P_0): Likewise.
369 (VEX_W_0F5C_P_1): Likewise.
370 (VEX_W_0F5C_P_2): Likewise.
371 (VEX_W_0F5C_P_3): Likewise.
372 (VEX_W_0F5D_P_0): Likewise.
373 (VEX_W_0F5D_P_1): Likewise.
374 (VEX_W_0F5D_P_2): Likewise.
375 (VEX_W_0F5D_P_3): Likewise.
376 (VEX_W_0F5E_P_0): Likewise.
377 (VEX_W_0F5E_P_1): Likewise.
378 (VEX_W_0F5E_P_2): Likewise.
379 (VEX_W_0F5E_P_3): Likewise.
380 (VEX_W_0F5F_P_0): Likewise.
381 (VEX_W_0F5F_P_1): Likewise.
382 (VEX_W_0F5F_P_2): Likewise.
383 (VEX_W_0F5F_P_3): Likewise.
384 (VEX_W_0F60_P_2): Likewise.
385 (VEX_W_0F61_P_2): Likewise.
386 (VEX_W_0F62_P_2): Likewise.
387 (VEX_W_0F63_P_2): Likewise.
388 (VEX_W_0F64_P_2): Likewise.
389 (VEX_W_0F65_P_2): Likewise.
390 (VEX_W_0F66_P_2): Likewise.
391 (VEX_W_0F67_P_2): Likewise.
392 (VEX_W_0F68_P_2): Likewise.
393 (VEX_W_0F69_P_2): Likewise.
394 (VEX_W_0F6A_P_2): Likewise.
395 (VEX_W_0F6B_P_2): Likewise.
396 (VEX_W_0F6C_P_2): Likewise.
397 (VEX_W_0F6D_P_2): Likewise.
398 (VEX_W_0F6F_P_1): Likewise.
399 (VEX_W_0F6F_P_2): Likewise.
400 (VEX_W_0F70_P_1): Likewise.
401 (VEX_W_0F70_P_2): Likewise.
402 (VEX_W_0F70_P_3): Likewise.
403 (VEX_W_0F71_R_2_P_2): Likewise.
404 (VEX_W_0F71_R_4_P_2): Likewise.
405 (VEX_W_0F71_R_6_P_2): Likewise.
406 (VEX_W_0F72_R_2_P_2): Likewise.
407 (VEX_W_0F72_R_4_P_2): Likewise.
408 (VEX_W_0F72_R_6_P_2): Likewise.
409 (VEX_W_0F73_R_2_P_2): Likewise.
410 (VEX_W_0F73_R_3_P_2): Likewise.
411 (VEX_W_0F73_R_6_P_2): Likewise.
412 (VEX_W_0F73_R_7_P_2): Likewise.
413 (VEX_W_0F74_P_2): Likewise.
414 (VEX_W_0F75_P_2): Likewise.
415 (VEX_W_0F76_P_2): Likewise.
416 (VEX_W_0F77_P_0): Likewise.
417 (VEX_W_0F7C_P_2): Likewise.
418 (VEX_W_0F7C_P_3): Likewise.
419 (VEX_W_0F7D_P_2): Likewise.
420 (VEX_W_0F7D_P_3): Likewise.
421 (VEX_W_0F7E_P_1): Likewise.
422 (VEX_W_0F7F_P_1): Likewise.
423 (VEX_W_0F7F_P_2): Likewise.
424 (VEX_W_0FAE_R_2_M_0): Likewise.
425 (VEX_W_0FAE_R_3_M_0): Likewise.
426 (VEX_W_0FC2_P_0): Likewise.
427 (VEX_W_0FC2_P_1): Likewise.
428 (VEX_W_0FC2_P_2): Likewise.
429 (VEX_W_0FC2_P_3): Likewise.
430 (VEX_W_0FD0_P_2): Likewise.
431 (VEX_W_0FD0_P_3): Likewise.
432 (VEX_W_0FD1_P_2): Likewise.
433 (VEX_W_0FD2_P_2): Likewise.
434 (VEX_W_0FD3_P_2): Likewise.
435 (VEX_W_0FD4_P_2): Likewise.
436 (VEX_W_0FD5_P_2): Likewise.
437 (VEX_W_0FD6_P_2): Likewise.
438 (VEX_W_0FD7_P_2_M_1): Likewise.
439 (VEX_W_0FD8_P_2): Likewise.
440 (VEX_W_0FD9_P_2): Likewise.
441 (VEX_W_0FDA_P_2): Likewise.
442 (VEX_W_0FDB_P_2): Likewise.
443 (VEX_W_0FDC_P_2): Likewise.
444 (VEX_W_0FDD_P_2): Likewise.
445 (VEX_W_0FDE_P_2): Likewise.
446 (VEX_W_0FDF_P_2): Likewise.
447 (VEX_W_0FE0_P_2): Likewise.
448 (VEX_W_0FE1_P_2): Likewise.
449 (VEX_W_0FE2_P_2): Likewise.
450 (VEX_W_0FE3_P_2): Likewise.
451 (VEX_W_0FE4_P_2): Likewise.
452 (VEX_W_0FE5_P_2): Likewise.
453 (VEX_W_0FE6_P_1): Likewise.
454 (VEX_W_0FE6_P_2): Likewise.
455 (VEX_W_0FE6_P_3): Likewise.
456 (VEX_W_0FE7_P_2_M_0): Likewise.
457 (VEX_W_0FE8_P_2): Likewise.
458 (VEX_W_0FE9_P_2): Likewise.
459 (VEX_W_0FEA_P_2): Likewise.
460 (VEX_W_0FEB_P_2): Likewise.
461 (VEX_W_0FEC_P_2): Likewise.
462 (VEX_W_0FED_P_2): Likewise.
463 (VEX_W_0FEE_P_2): Likewise.
464 (VEX_W_0FEF_P_2): Likewise.
465 (VEX_W_0FF0_P_3_M_0): Likewise.
466 (VEX_W_0FF1_P_2): Likewise.
467 (VEX_W_0FF2_P_2): Likewise.
468 (VEX_W_0FF3_P_2): Likewise.
469 (VEX_W_0FF4_P_2): Likewise.
470 (VEX_W_0FF5_P_2): Likewise.
471 (VEX_W_0FF6_P_2): Likewise.
472 (VEX_W_0FF7_P_2): Likewise.
473 (VEX_W_0FF8_P_2): Likewise.
474 (VEX_W_0FF9_P_2): Likewise.
475 (VEX_W_0FFA_P_2): Likewise.
476 (VEX_W_0FFB_P_2): Likewise.
477 (VEX_W_0FFC_P_2): Likewise.
478 (VEX_W_0FFD_P_2): Likewise.
479 (VEX_W_0FFE_P_2): Likewise.
480 (VEX_W_0F3800_P_2): Likewise.
481 (VEX_W_0F3801_P_2): Likewise.
482 (VEX_W_0F3802_P_2): Likewise.
483 (VEX_W_0F3803_P_2): Likewise.
484 (VEX_W_0F3804_P_2): Likewise.
485 (VEX_W_0F3805_P_2): Likewise.
486 (VEX_W_0F3806_P_2): Likewise.
487 (VEX_W_0F3807_P_2): Likewise.
488 (VEX_W_0F3808_P_2): Likewise.
489 (VEX_W_0F3809_P_2): Likewise.
490 (VEX_W_0F380A_P_2): Likewise.
491 (VEX_W_0F380B_P_2): Likewise.
492 (VEX_W_0F3817_P_2): Likewise.
493 (VEX_W_0F381C_P_2): Likewise.
494 (VEX_W_0F381D_P_2): Likewise.
495 (VEX_W_0F381E_P_2): Likewise.
496 (VEX_W_0F3820_P_2): Likewise.
497 (VEX_W_0F3821_P_2): Likewise.
498 (VEX_W_0F3822_P_2): Likewise.
499 (VEX_W_0F3823_P_2): Likewise.
500 (VEX_W_0F3824_P_2): Likewise.
501 (VEX_W_0F3825_P_2): Likewise.
502 (VEX_W_0F3828_P_2): Likewise.
503 (VEX_W_0F3829_P_2): Likewise.
504 (VEX_W_0F382A_P_2_M_0): Likewise.
505 (VEX_W_0F382B_P_2): Likewise.
506 (VEX_W_0F3830_P_2): Likewise.
507 (VEX_W_0F3831_P_2): Likewise.
508 (VEX_W_0F3832_P_2): Likewise.
509 (VEX_W_0F3833_P_2): Likewise.
510 (VEX_W_0F3834_P_2): Likewise.
511 (VEX_W_0F3835_P_2): Likewise.
512 (VEX_W_0F3837_P_2): Likewise.
513 (VEX_W_0F3838_P_2): Likewise.
514 (VEX_W_0F3839_P_2): Likewise.
515 (VEX_W_0F383A_P_2): Likewise.
516 (VEX_W_0F383B_P_2): Likewise.
517 (VEX_W_0F383C_P_2): Likewise.
518 (VEX_W_0F383D_P_2): Likewise.
519 (VEX_W_0F383E_P_2): Likewise.
520 (VEX_W_0F383F_P_2): Likewise.
521 (VEX_W_0F3840_P_2): Likewise.
522 (VEX_W_0F3841_P_2): Likewise.
523 (VEX_W_0F38DB_P_2): Likewise.
524 (VEX_W_0F3A08_P_2): Likewise.
525 (VEX_W_0F3A09_P_2): Likewise.
526 (VEX_W_0F3A0A_P_2): Likewise.
527 (VEX_W_0F3A0B_P_2): Likewise.
528 (VEX_W_0F3A0C_P_2): Likewise.
529 (VEX_W_0F3A0D_P_2): Likewise.
530 (VEX_W_0F3A0E_P_2): Likewise.
531 (VEX_W_0F3A0F_P_2): Likewise.
532 (VEX_W_0F3A21_P_2): Likewise.
533 (VEX_W_0F3A40_P_2): Likewise.
534 (VEX_W_0F3A41_P_2): Likewise.
535 (VEX_W_0F3A42_P_2): Likewise.
536 (VEX_W_0F3A62_P_2): Likewise.
537 (VEX_W_0F3A63_P_2): Likewise.
538 (VEX_W_0F3ADF_P_2): Likewise.
539 (VEX_LEN_0F77_P_0): New.
540 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
541 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
542 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
543 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
544 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
545 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
546 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
547 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
548 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
549 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
550 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
551 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
552 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
553 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
554 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
555 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
556 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
557 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
558 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
559 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
560 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
561 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
562 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
563 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
564 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
565 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
566 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
567 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
568 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
569 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
570 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
571 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
572 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
573 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
574 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
575 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
576 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
577 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
578 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
579 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
580 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
581 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
582 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
583 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
584 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
585 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
586 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
587 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
588 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
589 (vex_table): Update VEX 0F28 and 0F29 entries.
590 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
591 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
592 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
593 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
594 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
595 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
596 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
597 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
598 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
599 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
600 VEX_LEN_0F3A0B_P_2 entries.
601 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
602 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
603 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
604 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
605 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
606 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
607 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
608 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
609 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
610 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
611 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
612 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
613 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
614 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
615 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
616 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
617 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
618 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
619 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
620 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
621 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
622 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
623 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
624 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
625 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
626 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
627 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
628 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
629 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
630 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
631 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
632 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
633 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
634 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
635 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
636 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
637 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
638 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
639 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
640 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
641 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
642 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
643 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
644 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
645 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
646 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
647 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
648 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
649 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
650 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
651 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
652 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
653 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
654 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
655 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
656 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
657 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
658 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
659 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
660 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
661 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
662 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
663 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
664 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
665 VEX_W_0F3ADF_P_2 entries.
666 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
667 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
668 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
670 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
672 * i386-opc.tbl (VexWIG): New.
673 Replace VexW=3 with VexWIG.
675 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
677 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
678 * i386-tbl.h: Regenerated.
680 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
683 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
684 VEX_LEN_0FD6_P_2 entries.
685 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
686 * i386-tbl.h: Regenerated.
688 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
691 * i386-opc.h (VEXWIG): New.
692 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
693 * i386-tbl.h: Regenerated.
695 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
698 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
699 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
700 * i386-dis.c (EXxEVexR64): New.
701 (evex_rounding_64_mode): Likewise.
702 (OP_Rounding): Handle evex_rounding_64_mode.
704 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
707 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
708 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
709 * i386-dis.c (Edqa): New.
710 (dqa_mode): Likewise.
711 (intel_operand_size): Handle dqa_mode as m_mode.
712 (OP_E_register): Handle dqa_mode as dq_mode.
713 (OP_E_memory): Set shift for dqa_mode based on address_mode.
715 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
717 * i386-dis.c (OP_E_memory): Reformat.
719 2018-09-14 Jan Beulich <jbeulich@suse.com>
721 * i386-opc.tbl (crc32): Fold byte and word forms.
722 * i386-tbl.h: Re-generate.
724 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
726 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
727 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
728 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
729 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
730 * i386-tbl.h: Regenerated.
732 2018-09-13 Jan Beulich <jbeulich@suse.com>
734 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
736 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
737 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
738 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
739 * i386-tbl.h: Re-generate.
741 2018-09-13 Jan Beulich <jbeulich@suse.com>
743 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
745 * i386-tbl.h: Re-generate.
747 2018-09-13 Jan Beulich <jbeulich@suse.com>
749 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
751 * i386-tbl.h: Re-generate.
753 2018-09-13 Jan Beulich <jbeulich@suse.com>
755 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
757 * i386-tbl.h: Re-generate.
759 2018-09-13 Jan Beulich <jbeulich@suse.com>
761 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
763 * i386-tbl.h: Re-generate.
765 2018-09-13 Jan Beulich <jbeulich@suse.com>
767 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
769 * i386-tbl.h: Re-generate.
771 2018-09-13 Jan Beulich <jbeulich@suse.com>
773 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
775 * i386-tbl.h: Re-generate.
777 2018-09-13 Jan Beulich <jbeulich@suse.com>
779 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
780 * i386-tbl.h: Re-generate.
782 2018-09-13 Jan Beulich <jbeulich@suse.com>
784 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
785 * i386-tbl.h: Re-generate.
787 2018-09-13 Jan Beulich <jbeulich@suse.com>
789 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
791 * i386-tbl.h: Re-generate.
793 2018-09-13 Jan Beulich <jbeulich@suse.com>
795 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
797 * i386-tbl.h: Re-generate.
799 2018-09-13 Jan Beulich <jbeulich@suse.com>
801 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
802 * i386-tbl.h: Re-generate.
804 2018-09-13 Jan Beulich <jbeulich@suse.com>
806 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
807 * i386-tbl.h: Re-generate.
809 2018-09-13 Jan Beulich <jbeulich@suse.com>
811 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
812 * i386-tbl.h: Re-generate.
814 2018-09-13 Jan Beulich <jbeulich@suse.com>
816 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
818 * i386-tbl.h: Re-generate.
820 2018-09-13 Jan Beulich <jbeulich@suse.com>
822 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
824 * i386-tbl.h: Re-generate.
826 2018-09-13 Jan Beulich <jbeulich@suse.com>
828 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
830 * i386-tbl.h: Re-generate.
832 2018-09-13 Jan Beulich <jbeulich@suse.com>
834 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
835 * i386-tbl.h: Re-generate.
837 2018-09-13 Jan Beulich <jbeulich@suse.com>
839 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
840 * i386-tbl.h: Re-generate.
842 2018-09-13 Jan Beulich <jbeulich@suse.com>
844 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
845 * i386-tbl.h: Re-generate.
847 2018-09-13 Jan Beulich <jbeulich@suse.com>
849 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
850 (vpbroadcastw, rdpid): Drop NoRex64.
851 * i386-tbl.h: Re-generate.
853 2018-09-13 Jan Beulich <jbeulich@suse.com>
855 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
856 store templates, adding D.
857 * i386-tbl.h: Re-generate.
859 2018-09-13 Jan Beulich <jbeulich@suse.com>
861 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
862 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
863 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
864 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
865 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
866 Fold load and store templates where possible, adding D. Drop
867 IgnoreSize where it was pointlessly present. Drop redundant
869 * i386-tbl.h: Re-generate.
871 2018-09-13 Jan Beulich <jbeulich@suse.com>
873 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
874 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
875 (intel_operand_size): Handle v_bndmk_mode.
876 (OP_E_memory): Likewise. Produce (bad) when also riprel.
878 2018-09-08 John Darrington <john@darrington.wattle.id.au>
880 * disassemble.c (ARCH_s12z): Define if ARCH_all.
882 2018-08-31 Kito Cheng <kito@andestech.com>
884 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
885 compressed floating point instructions.
887 2018-08-30 Kito Cheng <kito@andestech.com>
889 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
890 riscv_opcode.xlen_requirement.
891 * riscv-opc.c (riscv_opcodes): Update for struct change.
893 2018-08-29 Martin Aberg <maberg@gaisler.com>
895 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
896 psr (PWRPSR) instruction.
898 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
900 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
902 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
904 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
906 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
908 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
909 loongson3a as an alias of gs464 for compatibility.
910 * mips-opc.c (mips_opcodes): Change Comments.
912 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
914 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
916 (print_mips_disassembler_options): Document -M loongson-ext.
917 * mips-opc.c (LEXT2): New macro.
918 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
920 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
922 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
924 (parse_mips_ase_option): Handle -M loongson-ext option.
925 (print_mips_disassembler_options): Document -M loongson-ext.
926 * mips-opc.c (IL3A): Delete.
927 * mips-opc.c (LEXT): New macro.
928 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
931 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
933 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
935 (parse_mips_ase_option): Handle -M loongson-cam option.
936 (print_mips_disassembler_options): Document -M loongson-cam.
937 * mips-opc.c (LCAM): New macro.
938 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
941 2018-08-21 Alan Modra <amodra@gmail.com>
943 * ppc-dis.c (operand_value_powerpc): Init "invalid".
944 (skip_optional_operands): Count optional operands, and update
945 ppc_optional_operand_value call.
946 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
947 (extract_vlensi): Likewise.
948 (extract_fxm): Return default value for missing optional operand.
949 (extract_ls, extract_raq, extract_tbr): Likewise.
950 (insert_sxl, extract_sxl): New functions.
951 (insert_esync, extract_esync): Remove Power9 handling and simplify.
952 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
953 flag and extra entry.
954 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
957 2018-08-20 Alan Modra <amodra@gmail.com>
959 * sh-opc.h (MASK): Simplify.
961 2018-08-18 John Darrington <john@darrington.wattle.id.au>
963 * s12z-dis.c (bm_decode): Deal with cases where the mode is
964 BM_RESERVED0 or BM_RESERVED1
965 (bm_rel_decode, bm_n_bytes): Ditto.
967 2018-08-18 John Darrington <john@darrington.wattle.id.au>
971 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
973 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
974 address with the addr32 prefix and without base nor index
977 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
979 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
980 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
981 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
982 (cpu_flags): Add CpuCMOV and CpuFXSR.
983 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
984 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
985 * i386-init.h: Regenerated.
986 * i386-tbl.h: Likewise.
988 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
990 * arc-regs.h: Update auxiliary registers.
992 2018-08-06 Jan Beulich <jbeulich@suse.com>
994 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
995 (RegIP, RegIZ): Define.
996 * i386-reg.tbl: Adjust comments.
997 (rip): Use Qword instead of BaseIndex. Use RegIP.
998 (eip): Use Dword instead of BaseIndex. Use RegIP.
999 (riz): Add Qword. Use RegIZ.
1000 (eiz): Add Dword. Use RegIZ.
1001 * i386-tbl.h: Re-generate.
1003 2018-08-03 Jan Beulich <jbeulich@suse.com>
1005 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1006 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1007 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1008 * i386-tbl.h: Re-generate.
1010 2018-08-03 Jan Beulich <jbeulich@suse.com>
1012 * i386-gen.c (operand_types): Remove Mem field.
1013 * i386-opc.h (union i386_operand_type): Remove mem field.
1014 * i386-init.h, i386-tbl.h: Re-generate.
1016 2018-08-01 Alan Modra <amodra@gmail.com>
1018 * po/POTFILES.in: Regenerate.
1020 2018-07-31 Nick Clifton <nickc@redhat.com>
1022 * po/sv.po: Updated Swedish translation.
1024 2018-07-31 Jan Beulich <jbeulich@suse.com>
1026 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1027 * i386-init.h, i386-tbl.h: Re-generate.
1029 2018-07-31 Jan Beulich <jbeulich@suse.com>
1031 * i386-opc.h (ZEROING_MASKING) Rename to ...
1032 (DYNAMIC_MASKING): ... this. Adjust comment.
1033 * i386-opc.tbl (MaskingMorZ): Define.
1034 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1035 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1036 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1037 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1038 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1039 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1040 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1041 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1042 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1044 2018-07-31 Jan Beulich <jbeulich@suse.com>
1046 * i386-opc.tbl: Use element rather than vector size for AVX512*
1047 scatter/gather insns.
1048 * i386-tbl.h: Re-generate.
1050 2018-07-31 Jan Beulich <jbeulich@suse.com>
1052 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1053 (cpu_flags): Drop CpuVREX.
1054 * i386-opc.h (CpuVREX): Delete.
1055 (union i386_cpu_flags): Remove cpuvrex.
1056 * i386-init.h, i386-tbl.h: Re-generate.
1058 2018-07-30 Jim Wilson <jimw@sifive.com>
1060 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1062 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1064 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1066 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1067 * Makefile.in: Regenerated.
1068 * configure.ac: Add C-SKY.
1069 * configure: Regenerated.
1070 * csky-dis.c: New file.
1071 * csky-opc.h: New file.
1072 * disassemble.c (ARCH_csky): Define.
1073 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1074 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1076 2018-07-27 Alan Modra <amodra@gmail.com>
1078 * ppc-opc.c (insert_sprbat): Correct function parameter and
1080 (extract_sprbat): Likewise, variable too.
1082 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1083 Alan Modra <amodra@gmail.com>
1085 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1086 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1087 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1088 support disjointed BAT.
1089 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1090 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1091 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1093 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1094 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1096 * i386-gen.c (adjust_broadcast_modifier): New function.
1097 (process_i386_opcode_modifier): Add an argument for operands.
1098 Adjust the Broadcast value based on operands.
1099 (output_i386_opcode): Pass operand_types to
1100 process_i386_opcode_modifier.
1101 (process_i386_opcodes): Pass NULL as operands to
1102 process_i386_opcode_modifier.
1103 * i386-opc.h (BYTE_BROADCAST): New.
1104 (WORD_BROADCAST): Likewise.
1105 (DWORD_BROADCAST): Likewise.
1106 (QWORD_BROADCAST): Likewise.
1107 (i386_opcode_modifier): Expand broadcast to 3 bits.
1108 * i386-tbl.h: Regenerated.
1110 2018-07-24 Alan Modra <amodra@gmail.com>
1113 * or1k-desc.h: Regenerate.
1115 2018-07-24 Jan Beulich <jbeulich@suse.com>
1117 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1118 vcvtusi2ss, and vcvtusi2sd.
1119 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1120 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1121 * i386-tbl.h: Re-generate.
1123 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1125 * arc-opc.c (extract_w6): Fix extending the sign.
1127 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1129 * arc-tbl.h (vewt): Allow it for ARC EM family.
1131 2018-07-23 Alan Modra <amodra@gmail.com>
1134 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1135 opcode variants for mtspr/mfspr encodings.
1137 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1138 Maciej W. Rozycki <macro@mips.com>
1140 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1141 loongson3a descriptors.
1142 (parse_mips_ase_option): Handle -M loongson-mmi option.
1143 (print_mips_disassembler_options): Document -M loongson-mmi.
1144 * mips-opc.c (LMMI): New macro.
1145 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1148 2018-07-19 Jan Beulich <jbeulich@suse.com>
1150 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1151 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1152 IgnoreSize and [XYZ]MMword where applicable.
1153 * i386-tbl.h: Re-generate.
1155 2018-07-19 Jan Beulich <jbeulich@suse.com>
1157 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1158 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1159 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1160 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1161 * i386-tbl.h: Re-generate.
1163 2018-07-19 Jan Beulich <jbeulich@suse.com>
1165 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1166 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1167 VPCLMULQDQ templates into their respective AVX512VL counterparts
1168 where possible, using Disp8ShiftVL and CheckRegSize instead of
1169 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1170 * i386-tbl.h: Re-generate.
1172 2018-07-19 Jan Beulich <jbeulich@suse.com>
1174 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1175 AVX512VL counterparts where possible, using Disp8ShiftVL and
1176 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1177 IgnoreSize) as appropriate.
1178 * i386-tbl.h: Re-generate.
1180 2018-07-19 Jan Beulich <jbeulich@suse.com>
1182 * i386-opc.tbl: Fold AVX512BW templates into their respective
1183 AVX512VL counterparts where possible, using Disp8ShiftVL and
1184 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1185 IgnoreSize) as appropriate.
1186 * i386-tbl.h: Re-generate.
1188 2018-07-19 Jan Beulich <jbeulich@suse.com>
1190 * i386-opc.tbl: Fold AVX512CD templates into their respective
1191 AVX512VL counterparts where possible, using Disp8ShiftVL and
1192 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1193 IgnoreSize) as appropriate.
1194 * i386-tbl.h: Re-generate.
1196 2018-07-19 Jan Beulich <jbeulich@suse.com>
1198 * i386-opc.h (DISP8_SHIFT_VL): New.
1199 * i386-opc.tbl (Disp8ShiftVL): Define.
1200 (various): Fold AVX512VL templates into their respective
1201 AVX512F counterparts where possible, using Disp8ShiftVL and
1202 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1203 IgnoreSize) as appropriate.
1204 * i386-tbl.h: Re-generate.
1206 2018-07-19 Jan Beulich <jbeulich@suse.com>
1208 * Makefile.am: Change dependencies and rule for
1209 $(srcdir)/i386-init.h.
1210 * Makefile.in: Re-generate.
1211 * i386-gen.c (process_i386_opcodes): New local variable
1212 "marker". Drop opening of input file. Recognize marker and line
1214 * i386-opc.tbl (OPCODE_I386_H): Define.
1215 (i386-opc.h): Include it.
1218 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1221 * i386-opc.h (Byte): Update comments.
1227 (Xmmword): Likewise.
1228 (Ymmword): Likewise.
1229 (Zmmword): Likewise.
1230 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1232 * i386-tbl.h: Regenerated.
1234 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1236 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1237 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1238 * aarch64-asm-2.c: Regenerate.
1239 * aarch64-dis-2.c: Regenerate.
1240 * aarch64-opc-2.c: Regenerate.
1242 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1245 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1246 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1247 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1248 sqdmulh, sqrdmulh): Use Em16.
1250 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1252 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1253 csdb together with them.
1254 (thumb32_opcodes): Likewise.
1256 2018-07-11 Jan Beulich <jbeulich@suse.com>
1258 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1259 requiring 32-bit registers as operands 2 and 3. Improve
1261 (mwait, mwaitx): Fold templates. Improve comments.
1262 OPERAND_TYPE_INOUTPORTREG.
1263 * i386-tbl.h: Re-generate.
1265 2018-07-11 Jan Beulich <jbeulich@suse.com>
1267 * i386-gen.c (operand_type_init): Remove
1268 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1269 OPERAND_TYPE_INOUTPORTREG.
1270 * i386-init.h: Re-generate.
1272 2018-07-11 Jan Beulich <jbeulich@suse.com>
1274 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1275 (wrssq, wrussq): Add Qword.
1276 * i386-tbl.h: Re-generate.
1278 2018-07-11 Jan Beulich <jbeulich@suse.com>
1280 * i386-opc.h: Rename OTMax to OTNum.
1281 (OTNumOfUints): Adjust calculation.
1282 (OTUnused): Directly alias to OTNum.
1284 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1286 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1288 (lea_reg_xys): Likewise.
1289 (print_insn_loop_primitive): Rename `reg' local variable to
1292 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1295 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1297 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1300 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1301 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1303 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1306 * mips-dis.c (mips_option_arg_t): New enumeration.
1307 (mips_options): New variable.
1308 (disassembler_options_mips): New function.
1309 (print_mips_disassembler_options): Reimplement in terms of
1310 `disassembler_options_mips'.
1311 * arm-dis.c (disassembler_options_arm): Adapt to using the
1312 `disasm_options_and_args_t' structure.
1313 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1314 * s390-dis.c (disassembler_options_s390): Likewise.
1316 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1318 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1320 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1321 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1322 * testsuite/ld-arm/tls-longplt.d: Likewise.
1324 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1327 * aarch64-asm-2.c: Regenerate.
1328 * aarch64-dis-2.c: Likewise.
1329 * aarch64-opc-2.c: Likewise.
1330 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1331 * aarch64-opc.c (operand_general_constraint_met_p,
1332 aarch64_print_operand): Likewise.
1333 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1334 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1336 (AARCH64_OPERANDS): Add Em2.
1338 2018-06-26 Nick Clifton <nickc@redhat.com>
1340 * po/uk.po: Updated Ukranian translation.
1341 * po/de.po: Updated German translation.
1342 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1344 2018-06-26 Nick Clifton <nickc@redhat.com>
1346 * nfp-dis.c: Fix spelling mistake.
1348 2018-06-24 Nick Clifton <nickc@redhat.com>
1350 * configure: Regenerate.
1351 * po/opcodes.pot: Regenerate.
1353 2018-06-24 Nick Clifton <nickc@redhat.com>
1355 2.31 branch created.
1357 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1359 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1360 * aarch64-asm-2.c: Regenerate.
1361 * aarch64-dis-2.c: Likewise.
1363 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1365 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1366 `-M ginv' option description.
1368 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1371 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1374 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1376 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1377 * configure.ac: Remove AC_PREREQ.
1378 * Makefile.in: Re-generate.
1379 * aclocal.m4: Re-generate.
1380 * configure: Re-generate.
1382 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1384 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1385 mips64r6 descriptors.
1386 (parse_mips_ase_option): Handle -Mginv option.
1387 (print_mips_disassembler_options): Document -Mginv.
1388 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1390 (mips_opcodes): Define ginvi and ginvt.
1392 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1393 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1395 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1396 * mips-opc.c (CRC, CRC64): New macros.
1397 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1398 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1401 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1404 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1405 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1407 2018-06-06 Alan Modra <amodra@gmail.com>
1409 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1410 setjmp. Move init for some other vars later too.
1412 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1414 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1415 (dis_private): Add new fields for property section tracking.
1416 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1417 (xtensa_instruction_fits): New functions.
1418 (fetch_data): Bump minimal fetch size to 4.
1419 (print_insn_xtensa): Make struct dis_private static.
1420 Load and prepare property table on section change.
1421 Don't disassemble literals. Don't disassemble instructions that
1422 cross property table boundaries.
1424 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1426 * configure: Regenerated.
1428 2018-06-01 Jan Beulich <jbeulich@suse.com>
1430 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1431 * i386-tbl.h: Re-generate.
1433 2018-06-01 Jan Beulich <jbeulich@suse.com>
1435 * i386-opc.tbl (sldt, str): Add NoRex64.
1436 * i386-tbl.h: Re-generate.
1438 2018-06-01 Jan Beulich <jbeulich@suse.com>
1440 * i386-opc.tbl (invpcid): Add Oword.
1441 * i386-tbl.h: Re-generate.
1443 2018-06-01 Alan Modra <amodra@gmail.com>
1445 * sysdep.h (_bfd_error_handler): Don't declare.
1446 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1447 * rl78-decode.opc: Likewise.
1448 * msp430-decode.c: Regenerate.
1449 * rl78-decode.c: Regenerate.
1451 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1453 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1454 * i386-init.h : Regenerated.
1456 2018-05-25 Alan Modra <amodra@gmail.com>
1458 * Makefile.in: Regenerate.
1459 * po/POTFILES.in: Regenerate.
1461 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1463 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1464 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1465 (insert_bab, extract_bab, insert_btab, extract_btab,
1466 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1467 (BAT, BBA VBA RBS XB6S): Delete macros.
1468 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1469 (BB, BD, RBX, XC6): Update for new macros.
1470 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1471 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1472 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1473 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1475 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1477 * Makefile.am: Add support for s12z architecture.
1478 * configure.ac: Likewise.
1479 * disassemble.c: Likewise.
1480 * disassemble.h: Likewise.
1481 * Makefile.in: Regenerate.
1482 * configure: Regenerate.
1483 * s12z-dis.c: New file.
1486 2018-05-18 Alan Modra <amodra@gmail.com>
1488 * nfp-dis.c: Don't #include libbfd.h.
1489 (init_nfp3200_priv): Use bfd_get_section_contents.
1490 (nit_nfp6000_mecsr_sec): Likewise.
1492 2018-05-17 Nick Clifton <nickc@redhat.com>
1494 * po/zh_CN.po: Updated simplified Chinese translation.
1496 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1499 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1500 * aarch64-dis-2.c: Regenerate.
1502 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1505 * aarch64-asm.c (opintl.h): Include.
1506 (aarch64_ins_sysreg): Enforce read/write constraints.
1507 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1508 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1509 (F_REG_READ, F_REG_WRITE): New.
1510 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1511 AARCH64_OPND_SYSREG.
1512 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1513 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1514 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1515 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1516 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1517 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1518 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1519 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1520 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1521 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1522 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1523 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1524 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1525 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1526 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1527 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1528 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1530 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1533 * aarch64-dis.c (no_notes: New.
1534 (parse_aarch64_dis_option): Support notes.
1535 (aarch64_decode_insn, print_operands): Likewise.
1536 (print_aarch64_disassembler_options): Document notes.
1537 * aarch64-opc.c (aarch64_print_operand): Support notes.
1539 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1542 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1543 and take error struct.
1544 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1545 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1546 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1547 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1548 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1549 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1550 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1551 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1552 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1553 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1554 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1555 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1556 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1557 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1558 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1559 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1560 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1561 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1562 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1563 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1564 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1565 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1566 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1567 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1568 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1569 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1570 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1571 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1572 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1573 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1574 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1575 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1576 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1577 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1578 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1579 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1580 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1581 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1582 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1583 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1584 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1585 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1586 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1587 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1588 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1589 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1590 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1591 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1592 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1593 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1594 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1595 (determine_disassembling_preference, aarch64_decode_insn,
1596 print_insn_aarch64_word, print_insn_data): Take errors struct.
1597 (print_insn_aarch64): Use errors.
1598 * aarch64-asm-2.c: Regenerate.
1599 * aarch64-dis-2.c: Regenerate.
1600 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1601 boolean in aarch64_insert_operan.
1602 (print_operand_extractor): Likewise.
1603 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1605 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1607 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1609 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1611 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1613 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1615 * cr16-opc.c (cr16_instruction): Comment typo fix.
1616 * hppa-dis.c (print_insn_hppa): Likewise.
1618 2018-05-08 Jim Wilson <jimw@sifive.com>
1620 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1621 (match_c_slli64, match_srxi_as_c_srxi): New.
1622 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1623 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1624 <c.slli, c.srli, c.srai>: Use match_s_slli.
1625 <c.slli64, c.srli64, c.srai64>: New.
1627 2018-05-08 Alan Modra <amodra@gmail.com>
1629 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1630 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1631 partition opcode space for index lookup.
1633 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1635 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1636 <insn_length>: ...with this. Update usage.
1637 Remove duplicate call to *info->memory_error_func.
1639 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1640 H.J. Lu <hongjiu.lu@intel.com>
1642 * i386-dis.c (Gva): New.
1643 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1644 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1645 (prefix_table): New instructions (see prefix above).
1646 (mod_table): New instructions (see prefix above).
1647 (OP_G): Handle va_mode.
1648 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1649 CPU_MOVDIR64B_FLAGS.
1650 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1651 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1652 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1653 * i386-opc.tbl: Add movidir{i,64b}.
1654 * i386-init.h: Regenerated.
1655 * i386-tbl.h: Likewise.
1657 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1659 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1661 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1662 (AddrPrefixOpReg): This.
1663 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1664 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1666 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1668 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1669 (vle_num_opcodes): Likewise.
1670 (spe2_num_opcodes): Likewise.
1671 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1672 initialization loop.
1673 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1674 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1677 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1679 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1681 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1683 Makefile.am: Added nfp-dis.c.
1684 configure.ac: Added bfd_nfp_arch.
1685 disassemble.h: Added print_insn_nfp prototype.
1686 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1687 nfp-dis.c: New, for NFP support.
1688 po/POTFILES.in: Added nfp-dis.c to the list.
1689 Makefile.in: Regenerate.
1690 configure: Regenerate.
1692 2018-04-26 Jan Beulich <jbeulich@suse.com>
1694 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1695 templates into their base ones.
1696 * i386-tlb.h: Re-generate.
1698 2018-04-26 Jan Beulich <jbeulich@suse.com>
1700 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1701 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1702 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1703 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1704 * i386-init.h: Re-generate.
1706 2018-04-26 Jan Beulich <jbeulich@suse.com>
1708 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1709 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1710 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1711 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1713 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1715 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1717 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1718 cpuregzmm, and cpuregmask.
1719 * i386-init.h: Re-generate.
1720 * i386-tbl.h: Re-generate.
1722 2018-04-26 Jan Beulich <jbeulich@suse.com>
1724 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1725 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1726 * i386-init.h: Re-generate.
1728 2018-04-26 Jan Beulich <jbeulich@suse.com>
1730 * i386-gen.c (VexImmExt): Delete.
1731 * i386-opc.h (VexImmExt, veximmext): Delete.
1732 * i386-opc.tbl: Drop all VexImmExt uses.
1733 * i386-tlb.h: Re-generate.
1735 2018-04-25 Jan Beulich <jbeulich@suse.com>
1737 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1738 register-only forms.
1739 * i386-tlb.h: Re-generate.
1741 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1743 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1745 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1747 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1749 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1750 (cpu_flags): Add CpuCLDEMOTE.
1751 * i386-init.h: Regenerate.
1752 * i386-opc.h (enum): Add CpuCLDEMOTE,
1753 (i386_cpu_flags): Add cpucldemote.
1754 * i386-opc.tbl: Add cldemote.
1755 * i386-tbl.h: Regenerate.
1757 2018-04-16 Alan Modra <amodra@gmail.com>
1759 * Makefile.am: Remove sh5 and sh64 support.
1760 * configure.ac: Likewise.
1761 * disassemble.c: Likewise.
1762 * disassemble.h: Likewise.
1763 * sh-dis.c: Likewise.
1764 * sh64-dis.c: Delete.
1765 * sh64-opc.c: Delete.
1766 * sh64-opc.h: Delete.
1767 * Makefile.in: Regenerate.
1768 * configure: Regenerate.
1769 * po/POTFILES.in: Regenerate.
1771 2018-04-16 Alan Modra <amodra@gmail.com>
1773 * Makefile.am: Remove w65 support.
1774 * configure.ac: Likewise.
1775 * disassemble.c: Likewise.
1776 * disassemble.h: Likewise.
1777 * w65-dis.c: Delete.
1778 * w65-opc.h: Delete.
1779 * Makefile.in: Regenerate.
1780 * configure: Regenerate.
1781 * po/POTFILES.in: Regenerate.
1783 2018-04-16 Alan Modra <amodra@gmail.com>
1785 * configure.ac: Remove we32k support.
1786 * configure: Regenerate.
1788 2018-04-16 Alan Modra <amodra@gmail.com>
1790 * Makefile.am: Remove m88k support.
1791 * configure.ac: Likewise.
1792 * disassemble.c: Likewise.
1793 * disassemble.h: Likewise.
1794 * m88k-dis.c: Delete.
1795 * Makefile.in: Regenerate.
1796 * configure: Regenerate.
1797 * po/POTFILES.in: Regenerate.
1799 2018-04-16 Alan Modra <amodra@gmail.com>
1801 * Makefile.am: Remove i370 support.
1802 * configure.ac: Likewise.
1803 * disassemble.c: Likewise.
1804 * disassemble.h: Likewise.
1805 * i370-dis.c: Delete.
1806 * i370-opc.c: Delete.
1807 * Makefile.in: Regenerate.
1808 * configure: Regenerate.
1809 * po/POTFILES.in: Regenerate.
1811 2018-04-16 Alan Modra <amodra@gmail.com>
1813 * Makefile.am: Remove h8500 support.
1814 * configure.ac: Likewise.
1815 * disassemble.c: Likewise.
1816 * disassemble.h: Likewise.
1817 * h8500-dis.c: Delete.
1818 * h8500-opc.h: Delete.
1819 * Makefile.in: Regenerate.
1820 * configure: Regenerate.
1821 * po/POTFILES.in: Regenerate.
1823 2018-04-16 Alan Modra <amodra@gmail.com>
1825 * configure.ac: Remove tahoe support.
1826 * configure: Regenerate.
1828 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1830 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1832 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1834 * i386-tbl.h: Regenerated.
1836 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1838 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1839 PREFIX_MOD_1_0FAE_REG_6.
1841 (OP_E_register): Use va_mode.
1842 * i386-dis-evex.h (prefix_table):
1843 New instructions (see prefixes above).
1844 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1845 (cpu_flags): Likewise.
1846 * i386-opc.h (enum): Likewise.
1847 (i386_cpu_flags): Likewise.
1848 * i386-opc.tbl: Add umonitor, umwait, tpause.
1849 * i386-init.h: Regenerate.
1850 * i386-tbl.h: Likewise.
1852 2018-04-11 Alan Modra <amodra@gmail.com>
1854 * opcodes/i860-dis.c: Delete.
1855 * opcodes/i960-dis.c: Delete.
1856 * Makefile.am: Remove i860 and i960 support.
1857 * configure.ac: Likewise.
1858 * disassemble.c: Likewise.
1859 * disassemble.h: Likewise.
1860 * Makefile.in: Regenerate.
1861 * configure: Regenerate.
1862 * po/POTFILES.in: Regenerate.
1864 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1867 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1869 (print_insn): Clear vex instead of vex.evex.
1871 2018-04-04 Nick Clifton <nickc@redhat.com>
1873 * po/es.po: Updated Spanish translation.
1875 2018-03-28 Jan Beulich <jbeulich@suse.com>
1877 * i386-gen.c (opcode_modifiers): Delete VecESize.
1878 * i386-opc.h (VecESize): Delete.
1879 (struct i386_opcode_modifier): Delete vecesize.
1880 * i386-opc.tbl: Drop VecESize.
1881 * i386-tlb.h: Re-generate.
1883 2018-03-28 Jan Beulich <jbeulich@suse.com>
1885 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1886 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1887 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1888 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1889 * i386-tlb.h: Re-generate.
1891 2018-03-28 Jan Beulich <jbeulich@suse.com>
1893 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1895 * i386-tlb.h: Re-generate.
1897 2018-03-28 Jan Beulich <jbeulich@suse.com>
1899 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1900 (vex_len_table): Drop Y for vcvt*2si.
1901 (putop): Replace plain 'Y' handling by abort().
1903 2018-03-28 Nick Clifton <nickc@redhat.com>
1906 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1907 instructions with only a base address register.
1908 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1909 handle AARHC64_OPND_SVE_ADDR_R.
1910 (aarch64_print_operand): Likewise.
1911 * aarch64-asm-2.c: Regenerate.
1912 * aarch64_dis-2.c: Regenerate.
1913 * aarch64-opc-2.c: Regenerate.
1915 2018-03-22 Jan Beulich <jbeulich@suse.com>
1917 * i386-opc.tbl: Drop VecESize from register only insn forms and
1918 memory forms not allowing broadcast.
1919 * i386-tlb.h: Re-generate.
1921 2018-03-22 Jan Beulich <jbeulich@suse.com>
1923 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1924 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1925 sha256*): Drop Disp<N>.
1927 2018-03-22 Jan Beulich <jbeulich@suse.com>
1929 * i386-dis.c (EbndS, bnd_swap_mode): New.
1930 (prefix_table): Use EbndS.
1931 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1932 * i386-opc.tbl (bndmov): Move misplaced Load.
1933 * i386-tlb.h: Re-generate.
1935 2018-03-22 Jan Beulich <jbeulich@suse.com>
1937 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1938 templates allowing memory operands and folded ones for register
1940 * i386-tlb.h: Re-generate.
1942 2018-03-22 Jan Beulich <jbeulich@suse.com>
1944 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1945 256-bit templates. Drop redundant leftover Disp<N>.
1946 * i386-tlb.h: Re-generate.
1948 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1950 * riscv-opc.c (riscv_insn_types): New.
1952 2018-03-13 Nick Clifton <nickc@redhat.com>
1954 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1956 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1958 * i386-opc.tbl: Add Optimize to clr.
1959 * i386-tbl.h: Regenerated.
1961 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1963 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1964 * i386-opc.h (OldGcc): Removed.
1965 (i386_opcode_modifier): Remove oldgcc.
1966 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1967 instructions for old (<= 2.8.1) versions of gcc.
1968 * i386-tbl.h: Regenerated.
1970 2018-03-08 Jan Beulich <jbeulich@suse.com>
1972 * i386-opc.h (EVEXDYN): New.
1973 * i386-opc.tbl: Fold various AVX512VL templates.
1974 * i386-tlb.h: Re-generate.
1976 2018-03-08 Jan Beulich <jbeulich@suse.com>
1978 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1979 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1980 vpexpandd, vpexpandq): Fold AFX512VF templates.
1981 * i386-tlb.h: Re-generate.
1983 2018-03-08 Jan Beulich <jbeulich@suse.com>
1985 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1986 Fold 128- and 256-bit VEX-encoded templates.
1987 * i386-tlb.h: Re-generate.
1989 2018-03-08 Jan Beulich <jbeulich@suse.com>
1991 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1992 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1993 vpexpandd, vpexpandq): Fold AVX512F templates.
1994 * i386-tlb.h: Re-generate.
1996 2018-03-08 Jan Beulich <jbeulich@suse.com>
1998 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1999 64-bit templates. Drop Disp<N>.
2000 * i386-tlb.h: Re-generate.
2002 2018-03-08 Jan Beulich <jbeulich@suse.com>
2004 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2005 and 256-bit templates.
2006 * i386-tlb.h: Re-generate.
2008 2018-03-08 Jan Beulich <jbeulich@suse.com>
2010 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2011 * i386-tlb.h: Re-generate.
2013 2018-03-08 Jan Beulich <jbeulich@suse.com>
2015 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2017 * i386-tlb.h: Re-generate.
2019 2018-03-08 Jan Beulich <jbeulich@suse.com>
2021 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2022 * i386-tlb.h: Re-generate.
2024 2018-03-08 Jan Beulich <jbeulich@suse.com>
2026 * i386-gen.c (opcode_modifiers): Delete FloatD.
2027 * i386-opc.h (FloatD): Delete.
2028 (struct i386_opcode_modifier): Delete floatd.
2029 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2031 * i386-tlb.h: Re-generate.
2033 2018-03-08 Jan Beulich <jbeulich@suse.com>
2035 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2037 2018-03-08 Jan Beulich <jbeulich@suse.com>
2039 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2040 * i386-tlb.h: Re-generate.
2042 2018-03-08 Jan Beulich <jbeulich@suse.com>
2044 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2046 * i386-tlb.h: Re-generate.
2048 2018-03-07 Alan Modra <amodra@gmail.com>
2050 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2052 * disassemble.h (print_insn_rs6000): Delete.
2053 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2054 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2055 (print_insn_rs6000): Delete.
2057 2018-03-03 Alan Modra <amodra@gmail.com>
2059 * sysdep.h (opcodes_error_handler): Define.
2060 (_bfd_error_handler): Declare.
2061 * Makefile.am: Remove stray #.
2062 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2064 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2065 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2066 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2067 opcodes_error_handler to print errors. Standardize error messages.
2068 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2069 and include opintl.h.
2070 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2071 * i386-gen.c: Standardize error messages.
2072 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2073 * Makefile.in: Regenerate.
2074 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2075 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2076 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2077 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2078 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2079 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2080 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2081 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2082 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2083 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2084 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2085 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2086 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2088 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2090 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2091 vpsub[bwdq] instructions.
2092 * i386-tbl.h: Regenerated.
2094 2018-03-01 Alan Modra <amodra@gmail.com>
2096 * configure.ac (ALL_LINGUAS): Sort.
2097 * configure: Regenerate.
2099 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2101 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2102 macro by assignements.
2104 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2107 * i386-gen.c (opcode_modifiers): Add Optimize.
2108 * i386-opc.h (Optimize): New enum.
2109 (i386_opcode_modifier): Add optimize.
2110 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2111 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2112 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2113 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2114 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2116 * i386-tbl.h: Regenerated.
2118 2018-02-26 Alan Modra <amodra@gmail.com>
2120 * crx-dis.c (getregliststring): Allocate a large enough buffer
2121 to silence false positive gcc8 warning.
2123 2018-02-22 Shea Levy <shea@shealevy.com>
2125 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2127 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2129 * i386-opc.tbl: Add {rex},
2130 * i386-tbl.h: Regenerated.
2132 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2134 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2135 (mips16_opcodes): Replace `M' with `m' for "restore".
2137 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2139 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2141 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2143 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2144 variable to `function_index'.
2146 2018-02-13 Nick Clifton <nickc@redhat.com>
2149 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2150 about truncation of printing.
2152 2018-02-12 Henry Wong <henry@stuffedcow.net>
2154 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2156 2018-02-05 Nick Clifton <nickc@redhat.com>
2158 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2160 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2162 * i386-dis.c (enum): Add pconfig.
2163 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2164 (cpu_flags): Add CpuPCONFIG.
2165 * i386-opc.h (enum): Add CpuPCONFIG.
2166 (i386_cpu_flags): Add cpupconfig.
2167 * i386-opc.tbl: Add PCONFIG instruction.
2168 * i386-init.h: Regenerate.
2169 * i386-tbl.h: Likewise.
2171 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2173 * i386-dis.c (enum): Add PREFIX_0F09.
2174 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2175 (cpu_flags): Add CpuWBNOINVD.
2176 * i386-opc.h (enum): Add CpuWBNOINVD.
2177 (i386_cpu_flags): Add cpuwbnoinvd.
2178 * i386-opc.tbl: Add WBNOINVD instruction.
2179 * i386-init.h: Regenerate.
2180 * i386-tbl.h: Likewise.
2182 2018-01-17 Jim Wilson <jimw@sifive.com>
2184 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2186 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2188 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2189 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2190 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2191 (cpu_flags): Add CpuIBT, CpuSHSTK.
2192 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2193 (i386_cpu_flags): Add cpuibt, cpushstk.
2194 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2195 * i386-init.h: Regenerate.
2196 * i386-tbl.h: Likewise.
2198 2018-01-16 Nick Clifton <nickc@redhat.com>
2200 * po/pt_BR.po: Updated Brazilian Portugese translation.
2201 * po/de.po: Updated German translation.
2203 2018-01-15 Jim Wilson <jimw@sifive.com>
2205 * riscv-opc.c (match_c_nop): New.
2206 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2208 2018-01-15 Nick Clifton <nickc@redhat.com>
2210 * po/uk.po: Updated Ukranian translation.
2212 2018-01-13 Nick Clifton <nickc@redhat.com>
2214 * po/opcodes.pot: Regenerated.
2216 2018-01-13 Nick Clifton <nickc@redhat.com>
2218 * configure: Regenerate.
2220 2018-01-13 Nick Clifton <nickc@redhat.com>
2222 2.30 branch created.
2224 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2226 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2227 * i386-tbl.h: Regenerate.
2229 2018-01-10 Jan Beulich <jbeulich@suse.com>
2231 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2232 * i386-tbl.h: Re-generate.
2234 2018-01-10 Jan Beulich <jbeulich@suse.com>
2236 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2237 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2238 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2239 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2240 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2241 Disp8MemShift of AVX512VL forms.
2242 * i386-tbl.h: Re-generate.
2244 2018-01-09 Jim Wilson <jimw@sifive.com>
2246 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2247 then the hi_addr value is zero.
2249 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2251 * arm-dis.c (arm_opcodes): Add csdb.
2252 (thumb32_opcodes): Add csdb.
2254 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2256 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2257 * aarch64-asm-2.c: Regenerate.
2258 * aarch64-dis-2.c: Regenerate.
2259 * aarch64-opc-2.c: Regenerate.
2261 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2264 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2265 Remove AVX512 vmovd with 64-bit operands.
2266 * i386-tbl.h: Regenerated.
2268 2018-01-05 Jim Wilson <jimw@sifive.com>
2270 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2273 2018-01-03 Alan Modra <amodra@gmail.com>
2275 Update year range in copyright notice of all files.
2277 2018-01-02 Jan Beulich <jbeulich@suse.com>
2279 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2280 and OPERAND_TYPE_REGZMM entries.
2282 For older changes see ChangeLog-2017
2284 Copyright (C) 2018 Free Software Foundation, Inc.
2286 Copying and distribution of this file, with or without modification,
2287 are permitted in any medium without royalty provided the copyright
2288 notice and this notice are preserved.
2294 version-control: never