1 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
5 VEX_LEN_0FD6_P_2 entries.
6 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
7 * i386-tbl.h: Regenerated.
9 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
12 * i386-opc.h (VEXWIG): New.
13 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
14 * i386-tbl.h: Regenerated.
16 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
19 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
20 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
21 * i386-dis.c (EXxEVexR64): New.
22 (evex_rounding_64_mode): Likewise.
23 (OP_Rounding): Handle evex_rounding_64_mode.
25 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
28 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
29 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
30 * i386-dis.c (Edqa): New.
32 (intel_operand_size): Handle dqa_mode as m_mode.
33 (OP_E_register): Handle dqa_mode as dq_mode.
34 (OP_E_memory): Set shift for dqa_mode based on address_mode.
36 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
38 * i386-dis.c (OP_E_memory): Reformat.
40 2018-09-14 Jan Beulich <jbeulich@suse.com>
42 * i386-opc.tbl (crc32): Fold byte and word forms.
43 * i386-tbl.h: Re-generate.
45 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
47 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
48 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
49 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
50 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
51 * i386-tbl.h: Regenerated.
53 2018-09-13 Jan Beulich <jbeulich@suse.com>
55 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
57 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
58 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
59 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
60 * i386-tbl.h: Re-generate.
62 2018-09-13 Jan Beulich <jbeulich@suse.com>
64 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
66 * i386-tbl.h: Re-generate.
68 2018-09-13 Jan Beulich <jbeulich@suse.com>
70 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
72 * i386-tbl.h: Re-generate.
74 2018-09-13 Jan Beulich <jbeulich@suse.com>
76 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
78 * i386-tbl.h: Re-generate.
80 2018-09-13 Jan Beulich <jbeulich@suse.com>
82 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
84 * i386-tbl.h: Re-generate.
86 2018-09-13 Jan Beulich <jbeulich@suse.com>
88 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
90 * i386-tbl.h: Re-generate.
92 2018-09-13 Jan Beulich <jbeulich@suse.com>
94 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
96 * i386-tbl.h: Re-generate.
98 2018-09-13 Jan Beulich <jbeulich@suse.com>
100 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
101 * i386-tbl.h: Re-generate.
103 2018-09-13 Jan Beulich <jbeulich@suse.com>
105 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
106 * i386-tbl.h: Re-generate.
108 2018-09-13 Jan Beulich <jbeulich@suse.com>
110 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
112 * i386-tbl.h: Re-generate.
114 2018-09-13 Jan Beulich <jbeulich@suse.com>
116 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
118 * i386-tbl.h: Re-generate.
120 2018-09-13 Jan Beulich <jbeulich@suse.com>
122 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
123 * i386-tbl.h: Re-generate.
125 2018-09-13 Jan Beulich <jbeulich@suse.com>
127 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
128 * i386-tbl.h: Re-generate.
130 2018-09-13 Jan Beulich <jbeulich@suse.com>
132 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
133 * i386-tbl.h: Re-generate.
135 2018-09-13 Jan Beulich <jbeulich@suse.com>
137 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
139 * i386-tbl.h: Re-generate.
141 2018-09-13 Jan Beulich <jbeulich@suse.com>
143 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
145 * i386-tbl.h: Re-generate.
147 2018-09-13 Jan Beulich <jbeulich@suse.com>
149 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
151 * i386-tbl.h: Re-generate.
153 2018-09-13 Jan Beulich <jbeulich@suse.com>
155 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
156 * i386-tbl.h: Re-generate.
158 2018-09-13 Jan Beulich <jbeulich@suse.com>
160 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
161 * i386-tbl.h: Re-generate.
163 2018-09-13 Jan Beulich <jbeulich@suse.com>
165 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
166 * i386-tbl.h: Re-generate.
168 2018-09-13 Jan Beulich <jbeulich@suse.com>
170 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
171 (vpbroadcastw, rdpid): Drop NoRex64.
172 * i386-tbl.h: Re-generate.
174 2018-09-13 Jan Beulich <jbeulich@suse.com>
176 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
177 store templates, adding D.
178 * i386-tbl.h: Re-generate.
180 2018-09-13 Jan Beulich <jbeulich@suse.com>
182 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
183 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
184 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
185 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
186 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
187 Fold load and store templates where possible, adding D. Drop
188 IgnoreSize where it was pointlessly present. Drop redundant
190 * i386-tbl.h: Re-generate.
192 2018-09-13 Jan Beulich <jbeulich@suse.com>
194 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
195 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
196 (intel_operand_size): Handle v_bndmk_mode.
197 (OP_E_memory): Likewise. Produce (bad) when also riprel.
199 2018-09-08 John Darrington <john@darrington.wattle.id.au>
201 * disassemble.c (ARCH_s12z): Define if ARCH_all.
203 2018-08-31 Kito Cheng <kito@andestech.com>
205 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
206 compressed floating point instructions.
208 2018-08-30 Kito Cheng <kito@andestech.com>
210 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
211 riscv_opcode.xlen_requirement.
212 * riscv-opc.c (riscv_opcodes): Update for struct change.
214 2018-08-29 Martin Aberg <maberg@gaisler.com>
216 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
217 psr (PWRPSR) instruction.
219 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
221 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
223 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
225 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
227 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
229 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
230 loongson3a as an alias of gs464 for compatibility.
231 * mips-opc.c (mips_opcodes): Change Comments.
233 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
235 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
237 (print_mips_disassembler_options): Document -M loongson-ext.
238 * mips-opc.c (LEXT2): New macro.
239 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
241 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
243 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
245 (parse_mips_ase_option): Handle -M loongson-ext option.
246 (print_mips_disassembler_options): Document -M loongson-ext.
247 * mips-opc.c (IL3A): Delete.
248 * mips-opc.c (LEXT): New macro.
249 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
252 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
254 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
256 (parse_mips_ase_option): Handle -M loongson-cam option.
257 (print_mips_disassembler_options): Document -M loongson-cam.
258 * mips-opc.c (LCAM): New macro.
259 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
262 2018-08-21 Alan Modra <amodra@gmail.com>
264 * ppc-dis.c (operand_value_powerpc): Init "invalid".
265 (skip_optional_operands): Count optional operands, and update
266 ppc_optional_operand_value call.
267 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
268 (extract_vlensi): Likewise.
269 (extract_fxm): Return default value for missing optional operand.
270 (extract_ls, extract_raq, extract_tbr): Likewise.
271 (insert_sxl, extract_sxl): New functions.
272 (insert_esync, extract_esync): Remove Power9 handling and simplify.
273 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
274 flag and extra entry.
275 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
278 2018-08-20 Alan Modra <amodra@gmail.com>
280 * sh-opc.h (MASK): Simplify.
282 2018-08-18 John Darrington <john@darrington.wattle.id.au>
284 * s12z-dis.c (bm_decode): Deal with cases where the mode is
285 BM_RESERVED0 or BM_RESERVED1
286 (bm_rel_decode, bm_n_bytes): Ditto.
288 2018-08-18 John Darrington <john@darrington.wattle.id.au>
292 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
294 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
295 address with the addr32 prefix and without base nor index
298 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
300 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
301 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
302 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
303 (cpu_flags): Add CpuCMOV and CpuFXSR.
304 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
305 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
306 * i386-init.h: Regenerated.
307 * i386-tbl.h: Likewise.
309 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
311 * arc-regs.h: Update auxiliary registers.
313 2018-08-06 Jan Beulich <jbeulich@suse.com>
315 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
316 (RegIP, RegIZ): Define.
317 * i386-reg.tbl: Adjust comments.
318 (rip): Use Qword instead of BaseIndex. Use RegIP.
319 (eip): Use Dword instead of BaseIndex. Use RegIP.
320 (riz): Add Qword. Use RegIZ.
321 (eiz): Add Dword. Use RegIZ.
322 * i386-tbl.h: Re-generate.
324 2018-08-03 Jan Beulich <jbeulich@suse.com>
326 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
327 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
328 vpmovzxdq, vpmovzxwd): Remove NoRex64.
329 * i386-tbl.h: Re-generate.
331 2018-08-03 Jan Beulich <jbeulich@suse.com>
333 * i386-gen.c (operand_types): Remove Mem field.
334 * i386-opc.h (union i386_operand_type): Remove mem field.
335 * i386-init.h, i386-tbl.h: Re-generate.
337 2018-08-01 Alan Modra <amodra@gmail.com>
339 * po/POTFILES.in: Regenerate.
341 2018-07-31 Nick Clifton <nickc@redhat.com>
343 * po/sv.po: Updated Swedish translation.
345 2018-07-31 Jan Beulich <jbeulich@suse.com>
347 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
348 * i386-init.h, i386-tbl.h: Re-generate.
350 2018-07-31 Jan Beulich <jbeulich@suse.com>
352 * i386-opc.h (ZEROING_MASKING) Rename to ...
353 (DYNAMIC_MASKING): ... this. Adjust comment.
354 * i386-opc.tbl (MaskingMorZ): Define.
355 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
356 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
357 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
358 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
359 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
360 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
361 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
362 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
363 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
365 2018-07-31 Jan Beulich <jbeulich@suse.com>
367 * i386-opc.tbl: Use element rather than vector size for AVX512*
368 scatter/gather insns.
369 * i386-tbl.h: Re-generate.
371 2018-07-31 Jan Beulich <jbeulich@suse.com>
373 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
374 (cpu_flags): Drop CpuVREX.
375 * i386-opc.h (CpuVREX): Delete.
376 (union i386_cpu_flags): Remove cpuvrex.
377 * i386-init.h, i386-tbl.h: Re-generate.
379 2018-07-30 Jim Wilson <jimw@sifive.com>
381 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
383 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
385 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
387 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
388 * Makefile.in: Regenerated.
389 * configure.ac: Add C-SKY.
390 * configure: Regenerated.
391 * csky-dis.c: New file.
392 * csky-opc.h: New file.
393 * disassemble.c (ARCH_csky): Define.
394 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
395 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
397 2018-07-27 Alan Modra <amodra@gmail.com>
399 * ppc-opc.c (insert_sprbat): Correct function parameter and
401 (extract_sprbat): Likewise, variable too.
403 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
404 Alan Modra <amodra@gmail.com>
406 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
407 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
408 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
409 support disjointed BAT.
410 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
411 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
412 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
414 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
415 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
417 * i386-gen.c (adjust_broadcast_modifier): New function.
418 (process_i386_opcode_modifier): Add an argument for operands.
419 Adjust the Broadcast value based on operands.
420 (output_i386_opcode): Pass operand_types to
421 process_i386_opcode_modifier.
422 (process_i386_opcodes): Pass NULL as operands to
423 process_i386_opcode_modifier.
424 * i386-opc.h (BYTE_BROADCAST): New.
425 (WORD_BROADCAST): Likewise.
426 (DWORD_BROADCAST): Likewise.
427 (QWORD_BROADCAST): Likewise.
428 (i386_opcode_modifier): Expand broadcast to 3 bits.
429 * i386-tbl.h: Regenerated.
431 2018-07-24 Alan Modra <amodra@gmail.com>
434 * or1k-desc.h: Regenerate.
436 2018-07-24 Jan Beulich <jbeulich@suse.com>
438 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
439 vcvtusi2ss, and vcvtusi2sd.
440 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
441 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
442 * i386-tbl.h: Re-generate.
444 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
446 * arc-opc.c (extract_w6): Fix extending the sign.
448 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
450 * arc-tbl.h (vewt): Allow it for ARC EM family.
452 2018-07-23 Alan Modra <amodra@gmail.com>
455 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
456 opcode variants for mtspr/mfspr encodings.
458 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
459 Maciej W. Rozycki <macro@mips.com>
461 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
462 loongson3a descriptors.
463 (parse_mips_ase_option): Handle -M loongson-mmi option.
464 (print_mips_disassembler_options): Document -M loongson-mmi.
465 * mips-opc.c (LMMI): New macro.
466 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
469 2018-07-19 Jan Beulich <jbeulich@suse.com>
471 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
472 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
473 IgnoreSize and [XYZ]MMword where applicable.
474 * i386-tbl.h: Re-generate.
476 2018-07-19 Jan Beulich <jbeulich@suse.com>
478 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
479 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
480 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
481 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
482 * i386-tbl.h: Re-generate.
484 2018-07-19 Jan Beulich <jbeulich@suse.com>
486 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
487 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
488 VPCLMULQDQ templates into their respective AVX512VL counterparts
489 where possible, using Disp8ShiftVL and CheckRegSize instead of
490 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
491 * i386-tbl.h: Re-generate.
493 2018-07-19 Jan Beulich <jbeulich@suse.com>
495 * i386-opc.tbl: Fold AVX512DQ templates into their respective
496 AVX512VL counterparts where possible, using Disp8ShiftVL and
497 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
498 IgnoreSize) as appropriate.
499 * i386-tbl.h: Re-generate.
501 2018-07-19 Jan Beulich <jbeulich@suse.com>
503 * i386-opc.tbl: Fold AVX512BW templates into their respective
504 AVX512VL counterparts where possible, using Disp8ShiftVL and
505 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
506 IgnoreSize) as appropriate.
507 * i386-tbl.h: Re-generate.
509 2018-07-19 Jan Beulich <jbeulich@suse.com>
511 * i386-opc.tbl: Fold AVX512CD templates into their respective
512 AVX512VL counterparts where possible, using Disp8ShiftVL and
513 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
514 IgnoreSize) as appropriate.
515 * i386-tbl.h: Re-generate.
517 2018-07-19 Jan Beulich <jbeulich@suse.com>
519 * i386-opc.h (DISP8_SHIFT_VL): New.
520 * i386-opc.tbl (Disp8ShiftVL): Define.
521 (various): Fold AVX512VL templates into their respective
522 AVX512F counterparts where possible, using Disp8ShiftVL and
523 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
524 IgnoreSize) as appropriate.
525 * i386-tbl.h: Re-generate.
527 2018-07-19 Jan Beulich <jbeulich@suse.com>
529 * Makefile.am: Change dependencies and rule for
530 $(srcdir)/i386-init.h.
531 * Makefile.in: Re-generate.
532 * i386-gen.c (process_i386_opcodes): New local variable
533 "marker". Drop opening of input file. Recognize marker and line
535 * i386-opc.tbl (OPCODE_I386_H): Define.
536 (i386-opc.h): Include it.
539 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
542 * i386-opc.h (Byte): Update comments.
551 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
553 * i386-tbl.h: Regenerated.
555 2018-07-12 Sudakshina Das <sudi.das@arm.com>
557 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
558 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
559 * aarch64-asm-2.c: Regenerate.
560 * aarch64-dis-2.c: Regenerate.
561 * aarch64-opc-2.c: Regenerate.
563 2018-07-12 Tamar Christina <tamar.christina@arm.com>
566 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
567 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
568 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
569 sqdmulh, sqrdmulh): Use Em16.
571 2018-07-11 Sudakshina Das <sudi.das@arm.com>
573 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
574 csdb together with them.
575 (thumb32_opcodes): Likewise.
577 2018-07-11 Jan Beulich <jbeulich@suse.com>
579 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
580 requiring 32-bit registers as operands 2 and 3. Improve
582 (mwait, mwaitx): Fold templates. Improve comments.
583 OPERAND_TYPE_INOUTPORTREG.
584 * i386-tbl.h: Re-generate.
586 2018-07-11 Jan Beulich <jbeulich@suse.com>
588 * i386-gen.c (operand_type_init): Remove
589 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
590 OPERAND_TYPE_INOUTPORTREG.
591 * i386-init.h: Re-generate.
593 2018-07-11 Jan Beulich <jbeulich@suse.com>
595 * i386-opc.tbl (wrssd, wrussd): Add Dword.
596 (wrssq, wrussq): Add Qword.
597 * i386-tbl.h: Re-generate.
599 2018-07-11 Jan Beulich <jbeulich@suse.com>
601 * i386-opc.h: Rename OTMax to OTNum.
602 (OTNumOfUints): Adjust calculation.
603 (OTUnused): Directly alias to OTNum.
605 2018-07-09 Maciej W. Rozycki <macro@mips.com>
607 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
609 (lea_reg_xys): Likewise.
610 (print_insn_loop_primitive): Rename `reg' local variable to
613 2018-07-06 Tamar Christina <tamar.christina@arm.com>
616 * aarch64-tbl.h (ldarh): Fix disassembly mask.
618 2018-07-06 Tamar Christina <tamar.christina@arm.com>
621 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
622 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
624 2018-07-02 Maciej W. Rozycki <macro@mips.com>
627 * mips-dis.c (mips_option_arg_t): New enumeration.
628 (mips_options): New variable.
629 (disassembler_options_mips): New function.
630 (print_mips_disassembler_options): Reimplement in terms of
631 `disassembler_options_mips'.
632 * arm-dis.c (disassembler_options_arm): Adapt to using the
633 `disasm_options_and_args_t' structure.
634 * ppc-dis.c (disassembler_options_powerpc): Likewise.
635 * s390-dis.c (disassembler_options_s390): Likewise.
637 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
639 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
641 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
642 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
643 * testsuite/ld-arm/tls-longplt.d: Likewise.
645 2018-06-29 Tamar Christina <tamar.christina@arm.com>
648 * aarch64-asm-2.c: Regenerate.
649 * aarch64-dis-2.c: Likewise.
650 * aarch64-opc-2.c: Likewise.
651 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
652 * aarch64-opc.c (operand_general_constraint_met_p,
653 aarch64_print_operand): Likewise.
654 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
655 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
657 (AARCH64_OPERANDS): Add Em2.
659 2018-06-26 Nick Clifton <nickc@redhat.com>
661 * po/uk.po: Updated Ukranian translation.
662 * po/de.po: Updated German translation.
663 * po/pt_BR.po: Updated Brazilian Portuguese translation.
665 2018-06-26 Nick Clifton <nickc@redhat.com>
667 * nfp-dis.c: Fix spelling mistake.
669 2018-06-24 Nick Clifton <nickc@redhat.com>
671 * configure: Regenerate.
672 * po/opcodes.pot: Regenerate.
674 2018-06-24 Nick Clifton <nickc@redhat.com>
678 2018-06-19 Tamar Christina <tamar.christina@arm.com>
680 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
681 * aarch64-asm-2.c: Regenerate.
682 * aarch64-dis-2.c: Likewise.
684 2018-06-21 Maciej W. Rozycki <macro@mips.com>
686 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
687 `-M ginv' option description.
689 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
692 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
695 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
697 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
698 * configure.ac: Remove AC_PREREQ.
699 * Makefile.in: Re-generate.
700 * aclocal.m4: Re-generate.
701 * configure: Re-generate.
703 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
705 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
706 mips64r6 descriptors.
707 (parse_mips_ase_option): Handle -Mginv option.
708 (print_mips_disassembler_options): Document -Mginv.
709 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
711 (mips_opcodes): Define ginvi and ginvt.
713 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
714 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
716 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
717 * mips-opc.c (CRC, CRC64): New macros.
718 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
719 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
722 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
725 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
726 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
728 2018-06-06 Alan Modra <amodra@gmail.com>
730 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
731 setjmp. Move init for some other vars later too.
733 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
735 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
736 (dis_private): Add new fields for property section tracking.
737 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
738 (xtensa_instruction_fits): New functions.
739 (fetch_data): Bump minimal fetch size to 4.
740 (print_insn_xtensa): Make struct dis_private static.
741 Load and prepare property table on section change.
742 Don't disassemble literals. Don't disassemble instructions that
743 cross property table boundaries.
745 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
747 * configure: Regenerated.
749 2018-06-01 Jan Beulich <jbeulich@suse.com>
751 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
752 * i386-tbl.h: Re-generate.
754 2018-06-01 Jan Beulich <jbeulich@suse.com>
756 * i386-opc.tbl (sldt, str): Add NoRex64.
757 * i386-tbl.h: Re-generate.
759 2018-06-01 Jan Beulich <jbeulich@suse.com>
761 * i386-opc.tbl (invpcid): Add Oword.
762 * i386-tbl.h: Re-generate.
764 2018-06-01 Alan Modra <amodra@gmail.com>
766 * sysdep.h (_bfd_error_handler): Don't declare.
767 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
768 * rl78-decode.opc: Likewise.
769 * msp430-decode.c: Regenerate.
770 * rl78-decode.c: Regenerate.
772 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
774 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
775 * i386-init.h : Regenerated.
777 2018-05-25 Alan Modra <amodra@gmail.com>
779 * Makefile.in: Regenerate.
780 * po/POTFILES.in: Regenerate.
782 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
784 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
785 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
786 (insert_bab, extract_bab, insert_btab, extract_btab,
787 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
788 (BAT, BBA VBA RBS XB6S): Delete macros.
789 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
790 (BB, BD, RBX, XC6): Update for new macros.
791 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
792 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
793 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
794 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
796 2018-05-18 John Darrington <john@darrington.wattle.id.au>
798 * Makefile.am: Add support for s12z architecture.
799 * configure.ac: Likewise.
800 * disassemble.c: Likewise.
801 * disassemble.h: Likewise.
802 * Makefile.in: Regenerate.
803 * configure: Regenerate.
804 * s12z-dis.c: New file.
807 2018-05-18 Alan Modra <amodra@gmail.com>
809 * nfp-dis.c: Don't #include libbfd.h.
810 (init_nfp3200_priv): Use bfd_get_section_contents.
811 (nit_nfp6000_mecsr_sec): Likewise.
813 2018-05-17 Nick Clifton <nickc@redhat.com>
815 * po/zh_CN.po: Updated simplified Chinese translation.
817 2018-05-16 Tamar Christina <tamar.christina@arm.com>
820 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
821 * aarch64-dis-2.c: Regenerate.
823 2018-05-15 Tamar Christina <tamar.christina@arm.com>
826 * aarch64-asm.c (opintl.h): Include.
827 (aarch64_ins_sysreg): Enforce read/write constraints.
828 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
829 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
830 (F_REG_READ, F_REG_WRITE): New.
831 * aarch64-opc.c (aarch64_print_operand): Generate notes for
833 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
834 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
835 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
836 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
837 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
838 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
839 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
840 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
841 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
842 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
843 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
844 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
845 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
846 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
847 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
848 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
849 msr (F_SYS_WRITE), mrs (F_SYS_READ).
851 2018-05-15 Tamar Christina <tamar.christina@arm.com>
854 * aarch64-dis.c (no_notes: New.
855 (parse_aarch64_dis_option): Support notes.
856 (aarch64_decode_insn, print_operands): Likewise.
857 (print_aarch64_disassembler_options): Document notes.
858 * aarch64-opc.c (aarch64_print_operand): Support notes.
860 2018-05-15 Tamar Christina <tamar.christina@arm.com>
863 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
864 and take error struct.
865 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
866 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
867 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
868 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
869 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
870 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
871 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
872 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
873 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
874 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
875 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
876 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
877 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
878 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
879 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
880 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
881 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
882 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
883 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
884 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
885 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
886 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
887 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
888 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
889 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
890 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
891 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
892 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
893 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
894 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
895 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
896 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
897 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
898 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
899 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
900 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
901 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
902 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
903 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
904 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
905 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
906 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
907 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
908 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
909 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
910 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
911 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
912 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
913 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
914 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
915 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
916 (determine_disassembling_preference, aarch64_decode_insn,
917 print_insn_aarch64_word, print_insn_data): Take errors struct.
918 (print_insn_aarch64): Use errors.
919 * aarch64-asm-2.c: Regenerate.
920 * aarch64-dis-2.c: Regenerate.
921 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
922 boolean in aarch64_insert_operan.
923 (print_operand_extractor): Likewise.
924 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
926 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
928 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
930 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
932 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
934 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
936 * cr16-opc.c (cr16_instruction): Comment typo fix.
937 * hppa-dis.c (print_insn_hppa): Likewise.
939 2018-05-08 Jim Wilson <jimw@sifive.com>
941 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
942 (match_c_slli64, match_srxi_as_c_srxi): New.
943 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
944 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
945 <c.slli, c.srli, c.srai>: Use match_s_slli.
946 <c.slli64, c.srli64, c.srai64>: New.
948 2018-05-08 Alan Modra <amodra@gmail.com>
950 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
951 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
952 partition opcode space for index lookup.
954 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
956 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
957 <insn_length>: ...with this. Update usage.
958 Remove duplicate call to *info->memory_error_func.
960 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
961 H.J. Lu <hongjiu.lu@intel.com>
963 * i386-dis.c (Gva): New.
964 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
965 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
966 (prefix_table): New instructions (see prefix above).
967 (mod_table): New instructions (see prefix above).
968 (OP_G): Handle va_mode.
969 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
971 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
972 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
973 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
974 * i386-opc.tbl: Add movidir{i,64b}.
975 * i386-init.h: Regenerated.
976 * i386-tbl.h: Likewise.
978 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
980 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
982 * i386-opc.h (AddrPrefixOp0): Renamed to ...
983 (AddrPrefixOpReg): This.
984 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
985 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
987 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
989 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
990 (vle_num_opcodes): Likewise.
991 (spe2_num_opcodes): Likewise.
992 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
994 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
995 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
998 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1000 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1002 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1004 Makefile.am: Added nfp-dis.c.
1005 configure.ac: Added bfd_nfp_arch.
1006 disassemble.h: Added print_insn_nfp prototype.
1007 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1008 nfp-dis.c: New, for NFP support.
1009 po/POTFILES.in: Added nfp-dis.c to the list.
1010 Makefile.in: Regenerate.
1011 configure: Regenerate.
1013 2018-04-26 Jan Beulich <jbeulich@suse.com>
1015 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1016 templates into their base ones.
1017 * i386-tlb.h: Re-generate.
1019 2018-04-26 Jan Beulich <jbeulich@suse.com>
1021 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1022 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1023 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1024 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1025 * i386-init.h: Re-generate.
1027 2018-04-26 Jan Beulich <jbeulich@suse.com>
1029 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1030 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1031 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1032 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1034 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1036 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1038 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1039 cpuregzmm, and cpuregmask.
1040 * i386-init.h: Re-generate.
1041 * i386-tbl.h: Re-generate.
1043 2018-04-26 Jan Beulich <jbeulich@suse.com>
1045 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1046 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1047 * i386-init.h: Re-generate.
1049 2018-04-26 Jan Beulich <jbeulich@suse.com>
1051 * i386-gen.c (VexImmExt): Delete.
1052 * i386-opc.h (VexImmExt, veximmext): Delete.
1053 * i386-opc.tbl: Drop all VexImmExt uses.
1054 * i386-tlb.h: Re-generate.
1056 2018-04-25 Jan Beulich <jbeulich@suse.com>
1058 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1059 register-only forms.
1060 * i386-tlb.h: Re-generate.
1062 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1064 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1066 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1068 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1070 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1071 (cpu_flags): Add CpuCLDEMOTE.
1072 * i386-init.h: Regenerate.
1073 * i386-opc.h (enum): Add CpuCLDEMOTE,
1074 (i386_cpu_flags): Add cpucldemote.
1075 * i386-opc.tbl: Add cldemote.
1076 * i386-tbl.h: Regenerate.
1078 2018-04-16 Alan Modra <amodra@gmail.com>
1080 * Makefile.am: Remove sh5 and sh64 support.
1081 * configure.ac: Likewise.
1082 * disassemble.c: Likewise.
1083 * disassemble.h: Likewise.
1084 * sh-dis.c: Likewise.
1085 * sh64-dis.c: Delete.
1086 * sh64-opc.c: Delete.
1087 * sh64-opc.h: Delete.
1088 * Makefile.in: Regenerate.
1089 * configure: Regenerate.
1090 * po/POTFILES.in: Regenerate.
1092 2018-04-16 Alan Modra <amodra@gmail.com>
1094 * Makefile.am: Remove w65 support.
1095 * configure.ac: Likewise.
1096 * disassemble.c: Likewise.
1097 * disassemble.h: Likewise.
1098 * w65-dis.c: Delete.
1099 * w65-opc.h: Delete.
1100 * Makefile.in: Regenerate.
1101 * configure: Regenerate.
1102 * po/POTFILES.in: Regenerate.
1104 2018-04-16 Alan Modra <amodra@gmail.com>
1106 * configure.ac: Remove we32k support.
1107 * configure: Regenerate.
1109 2018-04-16 Alan Modra <amodra@gmail.com>
1111 * Makefile.am: Remove m88k support.
1112 * configure.ac: Likewise.
1113 * disassemble.c: Likewise.
1114 * disassemble.h: Likewise.
1115 * m88k-dis.c: Delete.
1116 * Makefile.in: Regenerate.
1117 * configure: Regenerate.
1118 * po/POTFILES.in: Regenerate.
1120 2018-04-16 Alan Modra <amodra@gmail.com>
1122 * Makefile.am: Remove i370 support.
1123 * configure.ac: Likewise.
1124 * disassemble.c: Likewise.
1125 * disassemble.h: Likewise.
1126 * i370-dis.c: Delete.
1127 * i370-opc.c: Delete.
1128 * Makefile.in: Regenerate.
1129 * configure: Regenerate.
1130 * po/POTFILES.in: Regenerate.
1132 2018-04-16 Alan Modra <amodra@gmail.com>
1134 * Makefile.am: Remove h8500 support.
1135 * configure.ac: Likewise.
1136 * disassemble.c: Likewise.
1137 * disassemble.h: Likewise.
1138 * h8500-dis.c: Delete.
1139 * h8500-opc.h: Delete.
1140 * Makefile.in: Regenerate.
1141 * configure: Regenerate.
1142 * po/POTFILES.in: Regenerate.
1144 2018-04-16 Alan Modra <amodra@gmail.com>
1146 * configure.ac: Remove tahoe support.
1147 * configure: Regenerate.
1149 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1151 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1153 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1155 * i386-tbl.h: Regenerated.
1157 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1159 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1160 PREFIX_MOD_1_0FAE_REG_6.
1162 (OP_E_register): Use va_mode.
1163 * i386-dis-evex.h (prefix_table):
1164 New instructions (see prefixes above).
1165 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1166 (cpu_flags): Likewise.
1167 * i386-opc.h (enum): Likewise.
1168 (i386_cpu_flags): Likewise.
1169 * i386-opc.tbl: Add umonitor, umwait, tpause.
1170 * i386-init.h: Regenerate.
1171 * i386-tbl.h: Likewise.
1173 2018-04-11 Alan Modra <amodra@gmail.com>
1175 * opcodes/i860-dis.c: Delete.
1176 * opcodes/i960-dis.c: Delete.
1177 * Makefile.am: Remove i860 and i960 support.
1178 * configure.ac: Likewise.
1179 * disassemble.c: Likewise.
1180 * disassemble.h: Likewise.
1181 * Makefile.in: Regenerate.
1182 * configure: Regenerate.
1183 * po/POTFILES.in: Regenerate.
1185 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1188 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1190 (print_insn): Clear vex instead of vex.evex.
1192 2018-04-04 Nick Clifton <nickc@redhat.com>
1194 * po/es.po: Updated Spanish translation.
1196 2018-03-28 Jan Beulich <jbeulich@suse.com>
1198 * i386-gen.c (opcode_modifiers): Delete VecESize.
1199 * i386-opc.h (VecESize): Delete.
1200 (struct i386_opcode_modifier): Delete vecesize.
1201 * i386-opc.tbl: Drop VecESize.
1202 * i386-tlb.h: Re-generate.
1204 2018-03-28 Jan Beulich <jbeulich@suse.com>
1206 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1207 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1208 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1209 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1210 * i386-tlb.h: Re-generate.
1212 2018-03-28 Jan Beulich <jbeulich@suse.com>
1214 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1216 * i386-tlb.h: Re-generate.
1218 2018-03-28 Jan Beulich <jbeulich@suse.com>
1220 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1221 (vex_len_table): Drop Y for vcvt*2si.
1222 (putop): Replace plain 'Y' handling by abort().
1224 2018-03-28 Nick Clifton <nickc@redhat.com>
1227 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1228 instructions with only a base address register.
1229 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1230 handle AARHC64_OPND_SVE_ADDR_R.
1231 (aarch64_print_operand): Likewise.
1232 * aarch64-asm-2.c: Regenerate.
1233 * aarch64_dis-2.c: Regenerate.
1234 * aarch64-opc-2.c: Regenerate.
1236 2018-03-22 Jan Beulich <jbeulich@suse.com>
1238 * i386-opc.tbl: Drop VecESize from register only insn forms and
1239 memory forms not allowing broadcast.
1240 * i386-tlb.h: Re-generate.
1242 2018-03-22 Jan Beulich <jbeulich@suse.com>
1244 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1245 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1246 sha256*): Drop Disp<N>.
1248 2018-03-22 Jan Beulich <jbeulich@suse.com>
1250 * i386-dis.c (EbndS, bnd_swap_mode): New.
1251 (prefix_table): Use EbndS.
1252 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1253 * i386-opc.tbl (bndmov): Move misplaced Load.
1254 * i386-tlb.h: Re-generate.
1256 2018-03-22 Jan Beulich <jbeulich@suse.com>
1258 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1259 templates allowing memory operands and folded ones for register
1261 * i386-tlb.h: Re-generate.
1263 2018-03-22 Jan Beulich <jbeulich@suse.com>
1265 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1266 256-bit templates. Drop redundant leftover Disp<N>.
1267 * i386-tlb.h: Re-generate.
1269 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1271 * riscv-opc.c (riscv_insn_types): New.
1273 2018-03-13 Nick Clifton <nickc@redhat.com>
1275 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1277 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1279 * i386-opc.tbl: Add Optimize to clr.
1280 * i386-tbl.h: Regenerated.
1282 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1284 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1285 * i386-opc.h (OldGcc): Removed.
1286 (i386_opcode_modifier): Remove oldgcc.
1287 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1288 instructions for old (<= 2.8.1) versions of gcc.
1289 * i386-tbl.h: Regenerated.
1291 2018-03-08 Jan Beulich <jbeulich@suse.com>
1293 * i386-opc.h (EVEXDYN): New.
1294 * i386-opc.tbl: Fold various AVX512VL templates.
1295 * i386-tlb.h: Re-generate.
1297 2018-03-08 Jan Beulich <jbeulich@suse.com>
1299 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1300 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1301 vpexpandd, vpexpandq): Fold AFX512VF templates.
1302 * i386-tlb.h: Re-generate.
1304 2018-03-08 Jan Beulich <jbeulich@suse.com>
1306 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1307 Fold 128- and 256-bit VEX-encoded templates.
1308 * i386-tlb.h: Re-generate.
1310 2018-03-08 Jan Beulich <jbeulich@suse.com>
1312 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1313 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1314 vpexpandd, vpexpandq): Fold AVX512F templates.
1315 * i386-tlb.h: Re-generate.
1317 2018-03-08 Jan Beulich <jbeulich@suse.com>
1319 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1320 64-bit templates. Drop Disp<N>.
1321 * i386-tlb.h: Re-generate.
1323 2018-03-08 Jan Beulich <jbeulich@suse.com>
1325 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1326 and 256-bit templates.
1327 * i386-tlb.h: Re-generate.
1329 2018-03-08 Jan Beulich <jbeulich@suse.com>
1331 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1332 * i386-tlb.h: Re-generate.
1334 2018-03-08 Jan Beulich <jbeulich@suse.com>
1336 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1338 * i386-tlb.h: Re-generate.
1340 2018-03-08 Jan Beulich <jbeulich@suse.com>
1342 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1343 * i386-tlb.h: Re-generate.
1345 2018-03-08 Jan Beulich <jbeulich@suse.com>
1347 * i386-gen.c (opcode_modifiers): Delete FloatD.
1348 * i386-opc.h (FloatD): Delete.
1349 (struct i386_opcode_modifier): Delete floatd.
1350 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1352 * i386-tlb.h: Re-generate.
1354 2018-03-08 Jan Beulich <jbeulich@suse.com>
1356 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1358 2018-03-08 Jan Beulich <jbeulich@suse.com>
1360 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1361 * i386-tlb.h: Re-generate.
1363 2018-03-08 Jan Beulich <jbeulich@suse.com>
1365 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1367 * i386-tlb.h: Re-generate.
1369 2018-03-07 Alan Modra <amodra@gmail.com>
1371 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1373 * disassemble.h (print_insn_rs6000): Delete.
1374 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1375 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1376 (print_insn_rs6000): Delete.
1378 2018-03-03 Alan Modra <amodra@gmail.com>
1380 * sysdep.h (opcodes_error_handler): Define.
1381 (_bfd_error_handler): Declare.
1382 * Makefile.am: Remove stray #.
1383 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1385 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1386 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1387 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1388 opcodes_error_handler to print errors. Standardize error messages.
1389 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1390 and include opintl.h.
1391 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1392 * i386-gen.c: Standardize error messages.
1393 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1394 * Makefile.in: Regenerate.
1395 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1396 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1397 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1398 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1399 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1400 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1401 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1402 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1403 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1404 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1405 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1406 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1407 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1409 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1411 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1412 vpsub[bwdq] instructions.
1413 * i386-tbl.h: Regenerated.
1415 2018-03-01 Alan Modra <amodra@gmail.com>
1417 * configure.ac (ALL_LINGUAS): Sort.
1418 * configure: Regenerate.
1420 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1422 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1423 macro by assignements.
1425 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1428 * i386-gen.c (opcode_modifiers): Add Optimize.
1429 * i386-opc.h (Optimize): New enum.
1430 (i386_opcode_modifier): Add optimize.
1431 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1432 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1433 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1434 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1435 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1437 * i386-tbl.h: Regenerated.
1439 2018-02-26 Alan Modra <amodra@gmail.com>
1441 * crx-dis.c (getregliststring): Allocate a large enough buffer
1442 to silence false positive gcc8 warning.
1444 2018-02-22 Shea Levy <shea@shealevy.com>
1446 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1448 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1450 * i386-opc.tbl: Add {rex},
1451 * i386-tbl.h: Regenerated.
1453 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1455 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1456 (mips16_opcodes): Replace `M' with `m' for "restore".
1458 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1460 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1462 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1464 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1465 variable to `function_index'.
1467 2018-02-13 Nick Clifton <nickc@redhat.com>
1470 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1471 about truncation of printing.
1473 2018-02-12 Henry Wong <henry@stuffedcow.net>
1475 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1477 2018-02-05 Nick Clifton <nickc@redhat.com>
1479 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1481 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1483 * i386-dis.c (enum): Add pconfig.
1484 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1485 (cpu_flags): Add CpuPCONFIG.
1486 * i386-opc.h (enum): Add CpuPCONFIG.
1487 (i386_cpu_flags): Add cpupconfig.
1488 * i386-opc.tbl: Add PCONFIG instruction.
1489 * i386-init.h: Regenerate.
1490 * i386-tbl.h: Likewise.
1492 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1494 * i386-dis.c (enum): Add PREFIX_0F09.
1495 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1496 (cpu_flags): Add CpuWBNOINVD.
1497 * i386-opc.h (enum): Add CpuWBNOINVD.
1498 (i386_cpu_flags): Add cpuwbnoinvd.
1499 * i386-opc.tbl: Add WBNOINVD instruction.
1500 * i386-init.h: Regenerate.
1501 * i386-tbl.h: Likewise.
1503 2018-01-17 Jim Wilson <jimw@sifive.com>
1505 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1507 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1509 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1510 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1511 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1512 (cpu_flags): Add CpuIBT, CpuSHSTK.
1513 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1514 (i386_cpu_flags): Add cpuibt, cpushstk.
1515 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1516 * i386-init.h: Regenerate.
1517 * i386-tbl.h: Likewise.
1519 2018-01-16 Nick Clifton <nickc@redhat.com>
1521 * po/pt_BR.po: Updated Brazilian Portugese translation.
1522 * po/de.po: Updated German translation.
1524 2018-01-15 Jim Wilson <jimw@sifive.com>
1526 * riscv-opc.c (match_c_nop): New.
1527 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1529 2018-01-15 Nick Clifton <nickc@redhat.com>
1531 * po/uk.po: Updated Ukranian translation.
1533 2018-01-13 Nick Clifton <nickc@redhat.com>
1535 * po/opcodes.pot: Regenerated.
1537 2018-01-13 Nick Clifton <nickc@redhat.com>
1539 * configure: Regenerate.
1541 2018-01-13 Nick Clifton <nickc@redhat.com>
1543 2.30 branch created.
1545 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1547 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1548 * i386-tbl.h: Regenerate.
1550 2018-01-10 Jan Beulich <jbeulich@suse.com>
1552 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1553 * i386-tbl.h: Re-generate.
1555 2018-01-10 Jan Beulich <jbeulich@suse.com>
1557 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1558 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1559 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1560 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1561 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1562 Disp8MemShift of AVX512VL forms.
1563 * i386-tbl.h: Re-generate.
1565 2018-01-09 Jim Wilson <jimw@sifive.com>
1567 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1568 then the hi_addr value is zero.
1570 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1572 * arm-dis.c (arm_opcodes): Add csdb.
1573 (thumb32_opcodes): Add csdb.
1575 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1577 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1578 * aarch64-asm-2.c: Regenerate.
1579 * aarch64-dis-2.c: Regenerate.
1580 * aarch64-opc-2.c: Regenerate.
1582 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1585 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1586 Remove AVX512 vmovd with 64-bit operands.
1587 * i386-tbl.h: Regenerated.
1589 2018-01-05 Jim Wilson <jimw@sifive.com>
1591 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1594 2018-01-03 Alan Modra <amodra@gmail.com>
1596 Update year range in copyright notice of all files.
1598 2018-01-02 Jan Beulich <jbeulich@suse.com>
1600 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1601 and OPERAND_TYPE_REGZMM entries.
1603 For older changes see ChangeLog-2017
1605 Copyright (C) 2018 Free Software Foundation, Inc.
1607 Copying and distribution of this file, with or without modification,
1608 are permitted in any medium without royalty provided the copyright
1609 notice and this notice are preserved.
1615 version-control: never