1 2006-10-18 Dave Brolley <brolley@redhat.com>
3 * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
4 * configure: Regenerated.
6 2006-09-29 Alan Modra <amodra@bigpond.net.au>
8 * po/POTFILES.in: Regenerate.
10 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
11 Joseph Myers <joseph@codesourcery.com>
12 Ian Lance Taylor <ian@wasabisystems.com>
13 Ben Elliston <bje@wasabisystems.com>
15 * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
16 only be used with the default multiply-add operation, so if N is
17 set, don't bother printing X. Add new iwmmxt instructions.
18 (IWMMXT_INSN_COUNT): Update.
19 (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
21 (print_insn_coprocessor): Check for iWMMXt2. Handle format
24 2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
27 * i386-dis.c (prefix_user_table): Fix the second operand of
28 maskmovdqu instruction to allow only %xmm register instead of
29 both %xmm register and memory.
31 2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
34 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
37 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
39 * score-dis.c: New file.
40 * score-opc.h: New file.
41 * Makefile.am: Add Score files.
42 * Makefile.in: Regenerate.
43 * configure.in: Add support for Score target.
44 * configure: Regenerate.
45 * disassemble.c: Add support for Score target.
47 2006-09-16 Nick Clifton <nickc@redhat.com>
48 Pedro Alves <pedro_alves@portugalmail.pt>
50 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
51 macros defined in bfd.h.
52 * cris-dis.c: Likewise.
53 * h8300-dis.c: Likewise.
54 * i386-dis.c: Likewise.
55 * ia64-gen.c: Likewise.
58 2006-09-04 Paul Brook <paul@codesourcery.com>
60 * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
62 2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
64 * i386-dis.c (three_byte_table): Expand to 256 elements.
66 2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
69 * i386-dis.c (MXC,EMC): Define.
70 (OP_MXC): New function to handle cvt* (convert instructions) between
71 %xmm and %mm register correctly.
73 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
74 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
77 2006-07-29 Richard Sandiford <richard@codesourcery.com>
79 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
82 2006-07-19 Paul Brook <paul@codesourcery.com>
84 * armd-dis.c (arm_opcodes): Fix rbit opcode.
86 2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
88 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
89 "sldt", "str" and "smsw".
91 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
94 * i386-dis.c (GRP11_C6): NEW.
102 (GRPPADLCK1): Likewise.
103 (GRPPADLCK2): Likewise.
104 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
106 (grps): Add entries for GRP11_C6 and GRP11_C7.
108 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
109 Michael Meissner <michael.meissner@amd.com>
111 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
112 support for amdfam10 SSE4a/ABM instructions. Modify all
113 initializer macros to have additional arguments. Disallow REP
114 prefix for non-string instructions.
117 2006-07-05 Julian Brown <julian@codesourcery.com>
119 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
121 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
123 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
124 (twobyte_has_modrm): Set 1 for 0x1f.
126 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
128 * i386-dis.c (NOP_Fixup): Removed.
130 (NOP_Fixup2): Likewise.
131 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
133 2006-06-12 Julian Brown <julian@codesourcery.com>
135 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
138 2006-06-10 H.J. Lu <hongjiu.lu@intel.com>
140 * i386.c (GRP10): Renamed to ...
142 (GRP11): Renamed to ...
144 (GRP12): Renamed to ...
146 (GRP13): Renamed to ...
148 (GRP14): Renamed to ...
150 (dis386_twobyte): Updated.
153 2006-06-09 Nick Clifton <nickc@redhat.com>
155 * po/fi.po: Updated Finnish translation.
157 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
159 * po/Make-in (pdf, ps): New dummy targets.
161 2006-06-06 Paul Brook <paul@codesourcery.com>
163 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
165 (neon_opcodes): Add conditional execution specifiers.
166 (thumb_opcodes): Ditto.
167 (thumb32_opcodes): Ditto.
168 (arm_conditional): Change 0xe to "al" and add "" to end.
169 (ifthen_state, ifthen_next_state, ifthen_address): New.
170 (IFTHEN_COND): Define.
171 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
172 (print_insn_arm): Change %c to use new values of arm_conditional.
173 (print_insn_thumb16): Print thumb conditions. Add %I.
174 (print_insn_thumb32): Print thumb conditions.
175 (find_ifthen_state): New function.
176 (print_insn): Track IT block state.
178 2006-06-06 Ben Elliston <bje@au.ibm.com>
179 Anton Blanchard <anton@samba.org>
180 Peter Bergner <bergner@vnet.ibm.com>
182 * ppc-dis.c (powerpc_dialect): Handle power6 option.
183 (print_ppc_disassembler_options): Mention power6.
185 2006-06-06 Thiemo Seufer <ths@mips.com>
186 Chao-ying Fu <fu@mips.com>
188 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
189 * mips-opc.c: Add DSP64 instructions.
191 2006-06-06 Alan Modra <amodra@bigpond.net.au>
193 * m68hc11-dis.c (print_insn): Warning fix.
195 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
197 * po/Make-in (top_builddir): Define.
199 2006-06-05 Alan Modra <amodra@bigpond.net.au>
201 * Makefile.am: Run "make dep-am".
202 * Makefile.in: Regenerate.
203 * config.in: Regenerate.
205 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
207 * Makefile.am (INCLUDES): Use @INCINTL@.
208 * acinclude.m4: Include new gettext macros.
209 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
210 Remove local code for po/Makefile.
211 * Makefile.in, aclocal.m4, configure: Regenerated.
213 2006-05-30 Nick Clifton <nickc@redhat.com>
215 * po/es.po: Updated Spanish translation.
217 2006-05-25 Richard Sandiford <richard@codesourcery.com>
219 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
220 and fmovem entries. Put register list entries before immediate
221 mask entries. Use "l" rather than "L" in the fmovem entries.
222 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
224 (m68k_scan_mask): New function, split out from...
225 (print_insn_m68k): ...here. If no architecture has been set,
226 first try printing an m680x0 instruction, then try a Coldfire one.
228 2006-05-24 Nick Clifton <nickc@redhat.com>
230 * po/ga.po: Updated Irish translation.
232 2006-05-22 Nick Clifton <nickc@redhat.com>
234 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
236 2006-05-22 Nick Clifton <nickc@redhat.com>
238 * po/nl.po: Updated translation.
240 2006-05-18 Alan Modra <amodra@bigpond.net.au>
242 * avr-dis.c: Formatting fix.
244 2006-05-14 Thiemo Seufer <ths@mips.com>
246 * mips16-opc.c (I1, I32, I64): New shortcut defines.
247 (mips16_opcodes): Change membership of instructions to their
250 2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
252 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
254 2006-05-05 Julian Brown <julian@codesourcery.com>
256 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
259 2006-05-05 Thiemo Seufer <ths@mips.com>
260 David Ung <davidu@mips.com>
262 * mips-opc.c: Add macro for cache instruction.
264 2006-05-04 Thiemo Seufer <ths@mips.com>
265 Nigel Stephens <nigel@mips.com>
266 David Ung <davidu@mips.com>
268 * mips-dis.c (mips_arch_choices): Add smartmips instruction
269 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
270 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
272 * mips-opc.c: fix random typos in comments.
273 (INSN_SMARTMIPS): New defines.
274 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
275 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
276 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
277 FP_S and FP_D flags to denote single and double register
278 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
279 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
280 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
281 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
283 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
285 2006-05-03 Thiemo Seufer <ths@mips.com>
287 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
289 2006-05-02 Thiemo Seufer <ths@mips.com>
290 Nigel Stephens <nigel@mips.com>
291 David Ung <davidu@mips.com>
293 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
294 (print_mips16_insn_arg): Force mips16 to odd addresses.
296 2006-04-30 Thiemo Seufer <ths@mips.com>
297 David Ung <davidu@mips.com>
299 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
301 * mips-dis.c (print_insn_args): Adds udi argument handling.
303 2006-04-28 James E Wilson <wilson@specifix.com>
305 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
308 2006-04-28 Thiemo Seufer <ths@mips.com>
309 David Ung <davidu@mips.com>
310 Nigel Stephens <nigel@mips.com>
312 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
315 2006-04-28 Thiemo Seufer <ths@mips.com>
316 Nigel Stephens <nigel@mips.com>
317 David Ung <davidu@mips.com>
319 * mips-dis.c (print_insn_args): Add mips_opcode argument.
320 (print_insn_mips): Adjust print_insn_args call.
322 2006-04-28 Thiemo Seufer <ths@mips.com>
323 Nigel Stephens <nigel@mips.com>
325 * mips-dis.c (print_insn_args): Print $fcc only for FP
326 instructions, use $cc elsewise.
328 2006-04-28 Thiemo Seufer <ths@mips.com>
329 Nigel Stephens <nigel@mips.com>
331 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
332 Map MIPS16 registers to O32 names.
333 (print_mips16_insn_arg): Use mips16_reg_names.
335 2006-04-26 Julian Brown <julian@codesourcery.com>
337 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
340 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
341 Julian Brown <julian@codesourcery.com>
343 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
344 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
345 Add unified load/store instruction names.
346 (neon_opcode_table): New.
347 (arm_opcodes): Expand meaning of %<bitfield>['`?].
348 (arm_decode_bitfield): New.
349 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
350 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
351 (print_insn_neon): New.
352 (print_insn_arm): Adjust print_insn_coprocessor call. Call
353 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
354 (print_insn_thumb32): Likewise.
356 2006-04-19 Alan Modra <amodra@bigpond.net.au>
358 * Makefile.am: Run "make dep-am".
359 * Makefile.in: Regenerate.
361 2006-04-19 Alan Modra <amodra@bigpond.net.au>
363 * avr-dis.c (avr_operand): Warning fix.
365 * configure: Regenerate.
367 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
369 * po/POTFILES.in: Regenerated.
371 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
374 * avr-dis.c (avr_operand): Arrange for a comment to appear before
375 the symolic form of an address, so that the output of objdump -d
378 2006-04-10 DJ Delorie <dj@redhat.com>
380 * m32c-asm.c: Regenerate.
382 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
384 * Makefile.am: Add install-html target.
385 * Makefile.in: Regenerate.
387 2006-04-06 Nick Clifton <nickc@redhat.com>
389 * po/vi/po: Updated Vietnamese translation.
391 2006-03-31 Paul Koning <ni1d@arrl.net>
393 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
395 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
397 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
398 logic to identify halfword shifts.
400 2006-03-16 Paul Brook <paul@codesourcery.com>
402 * arm-dis.c (arm_opcodes): Rename swi to svc.
403 (thumb_opcodes): Ditto.
405 2006-03-13 DJ Delorie <dj@redhat.com>
407 * m32c-asm.c: Regenerate.
408 * m32c-desc.c: Likewise.
409 * m32c-desc.h: Likewise.
410 * m32c-dis.c: Likewise.
411 * m32c-ibld.c: Likewise.
412 * m32c-opc.c: Likewise.
413 * m32c-opc.h: Likewise.
415 2006-03-10 DJ Delorie <dj@redhat.com>
417 * m32c-desc.c: Regenerate with mul.l, mulu.l.
418 * m32c-opc.c: Likewise.
419 * m32c-opc.h: Likewise.
422 2006-03-09 Nick Clifton <nickc@redhat.com>
424 * po/sv.po: Updated Swedish translation.
426 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
429 * i386-dis.c (REP_Fixup): New function.
430 (AL): Remove duplicate.
435 (indirDXr): Likewise.
438 (dis386): Updated entries of ins, outs, movs, lods and stos.
440 2006-03-05 Nick Clifton <nickc@redhat.com>
442 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
443 signed 32-bit value into an unsigned 32-bit field when the host is
445 * fr30-ibld.c: Regenerate.
446 * frv-ibld.c: Regenerate.
447 * ip2k-ibld.c: Regenerate.
448 * iq2000-asm.c: Regenerate.
449 * iq2000-ibld.c: Regenerate.
450 * m32c-ibld.c: Regenerate.
451 * m32r-ibld.c: Regenerate.
452 * openrisc-ibld.c: Regenerate.
453 * xc16x-ibld.c: Regenerate.
454 * xstormy16-ibld.c: Regenerate.
456 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
458 * xc16x-asm.c: Regenerate.
459 * xc16x-dis.c: Regenerate.
461 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
463 * po/Make-in: Add html target.
465 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
467 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
468 Intel Merom New Instructions.
469 (THREE_BYTE_0): Likewise.
470 (THREE_BYTE_1): Likewise.
471 (three_byte_table): Likewise.
472 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
473 THREE_BYTE_1 for entry 0x3a.
474 (twobyte_has_modrm): Updated.
475 (twobyte_uses_SSE_prefix): Likewise.
476 (print_insn): Handle 3-byte opcodes used by Intel Merom New
479 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
481 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
482 (v9_hpriv_reg_names): New table.
483 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
484 New cases '$' and '%' for read/write hyperprivileged register.
485 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
486 window handling and rdhpr/wrhpr instructions.
488 2006-02-24 DJ Delorie <dj@redhat.com>
490 * m32c-desc.c: Regenerate with linker relaxation attributes.
491 * m32c-desc.h: Likewise.
492 * m32c-dis.c: Likewise.
493 * m32c-opc.c: Likewise.
495 2006-02-24 Paul Brook <paul@codesourcery.com>
497 * arm-dis.c (arm_opcodes): Add V7 instructions.
498 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
499 (print_arm_address): New function.
500 (print_insn_arm): Use it. Add 'P' and 'U' cases.
501 (psr_name): New function.
502 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
504 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
506 * ia64-opc-i.c (bXc): New.
508 (OpX2TaTbYaXcC): Likewise.
511 (ia64_opcodes_i): Add instructions for tf.
513 * ia64-opc.h (IMMU5b): New.
515 * ia64-asmtab.c: Regenerated.
517 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
519 * ia64-gen.c: Update copyright years.
520 * ia64-opc-b.c: Likewise.
522 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
524 * ia64-gen.c (lookup_regindex): Handle ".vm".
525 (print_dependency_table): Handle '\"'.
527 * ia64-ic.tbl: Updated from SDM 2.2.
528 * ia64-raw.tbl: Likewise.
529 * ia64-waw.tbl: Likewise.
530 * ia64-asmtab.c: Regenerated.
532 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
534 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
535 Anil Paranjape <anilp1@kpitcummins.com>
536 Shilin Shakti <shilins@kpitcummins.com>
538 * xc16x-desc.h: New file
539 * xc16x-desc.c: New file
540 * xc16x-opc.h: New file
541 * xc16x-opc.c: New file
542 * xc16x-ibld.c: New file
543 * xc16x-asm.c: New file
544 * xc16x-dis.c: New file
545 * Makefile.am: Entries for xc16x
546 * Makefile.in: Regenerate
547 * cofigure.in: Add xc16x target information.
548 * configure: Regenerate.
549 * disassemble.c: Add xc16x target information.
551 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
553 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
556 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
558 * i386-dis.c ('Z'): Add a new macro.
559 (dis386_twobyte): Use "movZ" for control register moves.
561 2006-02-10 Nick Clifton <nickc@redhat.com>
563 * iq2000-asm.c: Regenerate.
565 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
567 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
569 2006-01-26 David Ung <davidu@mips.com>
571 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
572 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
573 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
574 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
575 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
577 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
579 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
580 ld_d_r, pref_xd_cb): Use signed char to hold data to be
582 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
583 buffer overflows when disassembling instructions like
585 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
586 operand, if the offset is negative.
588 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
590 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
591 unsigned char to hold data to be disassembled.
593 2006-01-17 Andreas Schwab <schwab@suse.de>
596 * disassemble.c (disassemble_init_for_target): Set
597 disassembler_needs_relocs for bfd_arch_arm.
599 2006-01-16 Paul Brook <paul@codesourcery.com>
601 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
602 f?add?, and f?sub? instructions.
604 2006-01-16 Nick Clifton <nickc@redhat.com>
606 * po/zh_CN.po: New Chinese (simplified) translation.
607 * configure.in (ALL_LINGUAS): Add "zh_CH".
608 * configure: Regenerate.
610 2006-01-05 Paul Brook <paul@codesourcery.com>
612 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
614 2006-01-06 DJ Delorie <dj@redhat.com>
616 * m32c-desc.c: Regenerate.
617 * m32c-opc.c: Regenerate.
618 * m32c-opc.h: Regenerate.
620 2006-01-03 DJ Delorie <dj@redhat.com>
622 * cgen-ibld.in (extract_normal): Avoid memory range errors.
623 * m32c-ibld.c: Regenerated.
625 For older changes see ChangeLog-2005
631 version-control: never