1 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
5 2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
7 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
9 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
10 Alexander Ivchenko <alexander.ivchenko@intel.com>
11 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
12 Sergey Lega <sergey.s.lega@intel.com>
13 Anna Tikhonova <anna.tikhonova@intel.com>
14 Ilya Tocar <ilya.tocar@intel.com>
15 Andrey Turetskiy <andrey.turetskiy@intel.com>
16 Ilya Verbin <ilya.verbin@intel.com>
17 Kirill Yukhin <kirill.yukhin@intel.com>
18 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
20 * i386-dis-evex.h: New.
21 * i386-dis.c (OP_Rounding): New.
28 (EXEvexHalfBcstXmmq): New.
40 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
41 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
42 evex_rounding_mode, evex_sae_mode, mask_mode.
43 (USE_EVEX_TABLE): New.
46 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
48 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
49 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
50 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
51 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
52 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
53 MOD_EVEX_0F38C7_REG_6.
54 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
55 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
56 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
57 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
58 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
59 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
60 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
61 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
62 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
63 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
64 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
65 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
66 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
67 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
68 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
69 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
70 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
71 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
72 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
73 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
74 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
75 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
76 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
77 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
78 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
79 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
80 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
81 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
82 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
83 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
84 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
85 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
86 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
87 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
88 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
89 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
90 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
91 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
92 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
93 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
94 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
95 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
96 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
97 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
98 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
99 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
100 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
101 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
102 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
103 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
104 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
105 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
106 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
107 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
108 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
109 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
110 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
111 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
112 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
113 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
114 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
115 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
116 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
117 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
118 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
119 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
120 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
121 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
122 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
123 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
124 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
125 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
126 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
127 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
128 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
129 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
131 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
132 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
133 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
134 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
135 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
136 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
137 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
138 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
139 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
140 VEX_W_0F3A32_P_2_LEN_0.
141 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
142 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
143 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
144 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
145 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
146 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
147 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
148 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
149 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
150 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
151 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
152 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
153 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
154 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
155 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
156 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
157 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
158 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
159 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
160 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
161 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
162 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
163 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
164 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
165 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
166 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
167 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
168 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
169 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
170 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
171 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
172 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
173 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
174 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
175 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
176 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
177 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
178 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
179 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
180 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
181 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
182 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
183 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
184 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
185 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
186 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
187 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
188 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
189 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
190 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
191 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
192 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
193 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
194 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
195 (struct vex): Add fields evex, r, v, mask_register_specifier,
197 (intel_names_xmm): Add upper 16 registers.
198 (att_names_xmm): Ditto.
199 (intel_names_ymm): Ditto.
200 (att_names_ymm): Ditto.
202 (intel_names_zmm): Ditto.
203 (att_names_zmm): Ditto.
205 (intel_names_mask): Ditto.
206 (att_names_mask): Ditto.
207 (names_rounding): Ditto.
208 (names_broadcast): Ditto.
209 (x86_64_table): Add escape to evex-table.
210 (reg_table): Include reg_table evex-entries from
211 i386-dis-evex.h. Fix prefetchwt1 instruction.
212 (prefix_table): Add entries for new instructions.
214 (vex_len_table): Ditto.
215 (vex_w_table): Ditto.
217 (get_valid_dis386): Properly handle new instructions.
218 (print_insn): Handle zmm and mask registers, print mask operand.
219 (intel_operand_size): Support EVEX, new modes and sizes.
220 (OP_E_register): Handle new modes.
221 (OP_E_memory): Ditto.
226 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
227 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
228 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
229 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
230 CpuAVX512PF and CpuVREX.
231 (operand_type_init): Add OPERAND_TYPE_REGZMM,
232 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
233 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
234 StaticRounding, SAE, Disp8MemShift, NoDefMask.
235 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
236 * i386-init.h: Regenerate.
237 * i386-opc.h (CpuAVX512F): New.
242 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
243 cpuavx512pf and cpuvrex fields.
244 (VecSIB): Add VecSIB512.
249 (StaticRounding): New.
251 (Disp8MemShift): New.
253 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
254 staticrounding, sae, disp8memshift and nodefmask.
258 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
261 * i386-opc.tbl: Add AVX512 instructions.
262 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
263 registers, mask registers.
264 * i386-tbl.h: Regenerate.
266 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
269 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
270 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
272 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
274 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
275 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
277 (prefix_table): Updated.
278 (three_byte_table): Likewise.
279 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
280 (cpu_flags): Add CpuSHA.
281 (i386_cpu_flags): Add cpusha.
282 * i386-init.h: Regenerate.
283 * i386-opc.h (CpuSHA): New.
284 (CpuUnused): Restored.
285 (i386_cpu_flags): Add cpusha.
286 * i386-opc.tbl: Add SHA instructions.
287 * i386-tbl.h: Regenerate.
289 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
290 Kirill Yukhin <kirill.yukhin@intel.com>
291 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
293 * i386-dis.c (BND_Fixup): New.
300 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
302 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
303 (dis tables): Replace XX with BND for near branch and call
305 (prefix_table): Add new entries.
306 (mod_table): Likewise.
308 (intel_names_bnd): New.
309 (att_names_bnd): New.
311 (prefix_name): Handle BND_PREFIX.
312 (print_insn): Initialize names_bnd.
313 (intel_operand_size): Handle new modes.
314 (OP_E_register): Likewise.
315 (OP_E_memory): Likewise.
317 * i386-gen.c (cpu_flag_init): Add CpuMPX.
318 (cpu_flags): Add CpuMPX.
319 (operand_type_init): Add RegBND.
320 (opcode_modifiers): Add BNDPrefixOk.
321 (operand_types): Add RegBND.
322 * i386-init.h: Regenerate.
323 * i386-opc.h (CpuMPX): New.
324 (CpuUnused): Comment out.
325 (i386_cpu_flags): Add cpumpx.
327 (i386_opcode_modifier): Add bndprefixok.
329 (i386_operand_type): Add regbnd.
330 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
331 Add MPX instructions and bnd prefix.
332 * i386-reg.tbl: Add bnd0-bnd3 registers.
333 * i386-tbl.h: Regenerate.
335 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
337 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
340 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
342 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
344 * Makefile.in: Regenerate.
345 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
346 all fields. Reformat.
348 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
350 * mips16-opc.c: Include mips-formats.h.
351 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
353 (decode_mips16_operand): New function.
354 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
355 (print_insn_arg): Handle OP_ENTRY_EXIT list.
356 Abort for OP_SAVE_RESTORE_LIST.
357 (print_mips16_insn_arg): Change interface. Use mips_operand
358 structures. Delete GET_OP_S. Move GET_OP definition to...
359 (print_insn_mips16): ...here. Call init_print_arg_state.
360 Update the call to print_mips16_insn_arg.
362 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
364 * mips-formats.h: New file.
365 * mips-opc.c: Include mips-formats.h.
366 (reg_0_map): New static array.
367 (decode_mips_operand): New function.
368 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
369 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
370 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
371 (int_c_map): New static arrays.
372 (decode_micromips_operand): New function.
373 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
374 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
375 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
376 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
377 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
378 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
379 (micromips_imm_b_map, micromips_imm_c_map): Delete.
380 (print_reg): New function.
381 (mips_print_arg_state): New structure.
382 (init_print_arg_state, print_insn_arg): New functions.
383 (print_insn_args): Change interface and use mips_operand structures.
384 Delete GET_OP_S. Move GET_OP definition to...
385 (print_insn_mips): ...here. Update the call to print_insn_args.
386 (print_insn_micromips): Use print_insn_args.
388 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
390 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
393 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
395 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
396 ADDA.S, MULA.S and SUBA.S.
398 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
401 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
402 * i386-tbl.h: Regenerated.
404 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
406 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
407 and SD A(B) macros up.
408 * micromips-opc.c (micromips_opcodes): Likewise.
410 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
412 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
415 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
417 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
418 MDMX-like instructions.
419 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
420 printing "Q" operands for INSN_5400 instructions.
422 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
424 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
426 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
429 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
431 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
433 * mips16-opc.c (mips16_opcodes): Likewise.
434 * micromips-opc.c (micromips_opcodes): Likewise.
435 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
436 (print_insn_mips16): Handle "+i".
437 (print_insn_micromips): Likewise. Conditionally preserve the
438 ISA bit for "a" but not for "+i".
440 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
442 * micromips-opc.c (WR_mhi): Rename to..
444 (micromips_opcodes): Update "movep" entry accordingly. Replace
446 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
447 (micromips_to_32_reg_h_map1): ...this.
448 (micromips_to_32_reg_i_map): Rename to...
449 (micromips_to_32_reg_h_map2): ...this.
450 (print_micromips_insn): Remove "mi" case. Print both registers
451 in the pair for "mh".
453 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
455 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
456 * micromips-opc.c (micromips_opcodes): Likewise.
457 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
458 and "+T" handling. Check for a "0" suffix when deciding whether to
459 use coprocessor 0 names. In that case, also check for ",H" selectors.
461 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
463 * s390-opc.c (J12_12, J24_24): New macros.
464 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
465 (MASK_MII_UPI): Rename to MASK_MII_UPP.
466 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
468 2013-07-04 Alan Modra <amodra@gmail.com>
470 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
472 2013-06-26 Nick Clifton <nickc@redhat.com>
474 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
475 field when checking for type 2 nop.
476 * rx-decode.c: Regenerate.
478 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
480 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
483 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
485 * mips-dis.c (is_mips16_plt_tail): New function.
486 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
488 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
490 2013-06-21 DJ Delorie <dj@redhat.com>
492 * msp430-decode.opc: New.
493 * msp430-decode.c: New/generated.
494 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
495 (MAINTAINER_CLEANFILES): Likewise.
496 Add rule to build msp430-decode.c frommsp430decode.opc
497 using the opc2c program.
498 * Makefile.in: Regenerate.
499 * configure.in: Add msp430-decode.lo to msp430 architecture files.
500 * configure: Regenerate.
502 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
504 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
505 (SYMTAB_AVAILABLE): Removed.
506 (#include "elf/aarch64.h): Ditto.
508 2013-06-17 Catherine Moore <clm@codesourcery.com>
509 Maciej W. Rozycki <macro@codesourcery.com>
510 Chao-Ying Fu <fu@mips.com>
512 * micromips-opc.c (EVA): Define.
514 (micromips_opcodes): Add EVA opcodes.
515 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
516 (print_insn_args): Handle EVA offsets.
517 (print_insn_micromips): Likewise.
518 * mips-opc.c (EVA): Define.
520 (mips_builtin_opcodes): Add EVA opcodes.
522 2013-06-17 Alan Modra <amodra@gmail.com>
524 * Makefile.am (mips-opc.lo): Add rules to create automatic
525 dependency files. Pass archdefs.
526 (micromips-opc.lo, mips16-opc.lo): Likewise.
527 * Makefile.in: Regenerate.
529 2013-06-14 DJ Delorie <dj@redhat.com>
531 * rx-decode.opc (rx_decode_opcode): Bit operations on
532 registers are 32-bit operations, not 8-bit operations.
533 * rx-decode.c: Regenerate.
535 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
537 * micromips-opc.c (IVIRT): New define.
538 (IVIRT64): New define.
539 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
540 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
542 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
543 dmtgc0 to print cp0 names.
545 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
547 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
550 2013-06-08 Catherine Moore <clm@codesourcery.com>
551 Richard Sandiford <rdsandiford@googlemail.com>
553 * micromips-opc.c (D32, D33, MC): Update definitions.
554 (micromips_opcodes): Initialize ase field.
555 * mips-dis.c (mips_arch_choice): Add ase field.
556 (mips_arch_choices): Initialize ase field.
557 (set_default_mips_dis_options): Declare and setup mips_ase.
558 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
559 MT32, MC): Update definitions.
560 (mips_builtin_opcodes): Initialize ase field.
562 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
564 * s390-opc.txt (flogr): Require a register pair destination.
566 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
568 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
571 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
573 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
575 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
577 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
578 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
579 XLS_MASK, PPCVSX2): New defines.
580 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
581 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
582 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
583 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
584 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
585 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
586 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
587 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
588 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
589 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
590 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
591 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
592 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
593 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
594 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
595 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
596 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
597 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
598 <lxvx, stxvx>: New extended mnemonics.
600 2013-05-17 Alan Modra <amodra@gmail.com>
602 * ia64-raw.tbl: Replace non-ASCII char.
603 * ia64-waw.tbl: Likewise.
604 * ia64-asmtab.c: Regenerate.
606 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
608 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
609 * i386-init.h: Regenerated.
611 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
613 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
614 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
615 check from [0, 255] to [-128, 255].
617 2013-05-09 Andrew Pinski <apinski@cavium.com>
619 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
620 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
621 (parse_mips_dis_option): Handle the virt option.
622 (print_insn_args): Handle "+J".
623 (print_mips_disassembler_options): Print out message about virt64.
624 * mips-opc.c (IVIRT): New define.
625 (IVIRT64): New define.
626 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
627 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
628 Move rfe to the bottom as it conflicts with tlbgp.
630 2013-05-09 Alan Modra <amodra@gmail.com>
632 * ppc-opc.c (extract_vlesi): Properly sign extend.
633 (extract_vlensi): Likewise. Comment reason for setting invalid.
635 2013-05-02 Nick Clifton <nickc@redhat.com>
637 * msp430-dis.c: Add support for MSP430X instructions.
639 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
641 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
644 2013-04-17 Wei-chen Wang <cole945@gmail.com>
647 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
649 (hash_insns_list): Likewise.
651 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
653 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
656 2013-04-08 Jan Beulich <jbeulich@suse.com>
658 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
659 * i386-tbl.h: Re-generate.
661 2013-04-06 David S. Miller <davem@davemloft.net>
663 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
664 of an opcode, prefer the one with F_PREFERRED set.
665 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
666 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
667 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
668 mark existing mnenomics as aliases. Add "cc" suffix to edge
669 instructions generating condition codes, mark existing mnenomics
670 as aliases. Add "fp" prefix to VIS compare instructions, mark
671 existing mnenomics as aliases.
673 2013-04-03 Nick Clifton <nickc@redhat.com>
675 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
676 destination address by subtracting the operand from the current
678 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
679 a positive value in the insn.
680 (extract_u16_loop): Do not negate the returned value.
681 (D16_LOOP): Add V850_INVERSE_PCREL flag.
683 (ceilf.sw): Remove duplicate entry.
684 (cvtf.hs): New entry.
690 (maddf.s): Restrict to E3V5 architectures.
692 (nmaddf.s): Likewise.
693 (nmsubf.s): Likewise.
695 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
697 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
699 (print_insn): Pass sizeflag to get_sib.
701 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
704 * tic6x-dis.c: Add support for displaying 16-bit insns.
706 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
709 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
710 individual msb and lsb halves in src1 & src2 fields. Discard the
711 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
712 follow what Ti SDK does in that case as any value in the src1
713 field yields the same output with SDK disassembler.
715 2013-03-12 Michael Eager <eager@eagercon.com>
717 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
719 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
721 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
723 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
725 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
727 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
729 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
731 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
733 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
734 (thumb32_opcodes): Likewise.
735 (print_insn_thumb32): Handle 'S' control char.
737 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
739 * lm32-desc.c: Regenerate.
741 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
743 * i386-reg.tbl (riz): Add RegRex64.
744 * i386-tbl.h: Regenerated.
746 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
748 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
749 (aarch64_feature_crc): New static.
751 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
752 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
753 * aarch64-asm-2.c: Re-generate.
754 * aarch64-dis-2.c: Ditto.
755 * aarch64-opc-2.c: Ditto.
757 2013-02-27 Alan Modra <amodra@gmail.com>
759 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
760 * rl78-decode.c: Regenerate.
762 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
764 * rl78-decode.opc: Fix encoding of DIVWU insn.
765 * rl78-decode.c: Regenerate.
767 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
770 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
772 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
773 (cpu_flags): Add CpuSMAP.
775 * i386-opc.h (CpuSMAP): New.
776 (i386_cpu_flags): Add cpusmap.
778 * i386-opc.tbl: Add clac and stac.
780 * i386-init.h: Regenerated.
781 * i386-tbl.h: Likewise.
783 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
785 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
786 which also makes the disassembler output be in little
787 endian like it should be.
789 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
791 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
793 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
795 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
797 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
798 section disassembled.
800 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
802 * arm-dis.c: Update strht pattern.
804 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
806 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
807 single-float. Disable ll, lld, sc and scd for EE. Disable the
808 trunc.w.s macro for EE.
810 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
811 Andrew Jenner <andrew@codesourcery.com>
813 Based on patches from Altera Corporation.
815 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
817 * Makefile.in: Regenerated.
818 * configure.in: Add case for bfd_nios2_arch.
819 * configure: Regenerated.
820 * disassemble.c (ARCH_nios2): Define.
821 (disassembler): Add case for bfd_arch_nios2.
822 * nios2-dis.c: New file.
823 * nios2-opc.c: New file.
825 2013-02-04 Alan Modra <amodra@gmail.com>
827 * po/POTFILES.in: Regenerate.
828 * rl78-decode.c: Regenerate.
829 * rx-decode.c: Regenerate.
831 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
833 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
834 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
835 * aarch64-asm.c (convert_xtl_to_shll): New function.
836 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
837 calling convert_xtl_to_shll.
838 * aarch64-dis.c (convert_shll_to_xtl): New function.
839 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
840 calling convert_shll_to_xtl.
841 * aarch64-gen.c: Update copyright year.
842 * aarch64-asm-2.c: Re-generate.
843 * aarch64-dis-2.c: Re-generate.
844 * aarch64-opc-2.c: Re-generate.
846 2013-01-24 Nick Clifton <nickc@redhat.com>
848 * v850-dis.c: Add support for e3v5 architecture.
849 * v850-opc.c: Likewise.
851 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
853 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
854 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
855 * aarch64-opc.c (operand_general_constraint_met_p): For
856 AARCH64_MOD_LSL, move the range check on the shift amount before the
857 alignment check; change to call set_sft_amount_out_of_range_error
858 instead of set_imm_out_of_range_error.
859 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
860 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
861 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
864 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
866 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
868 * i386-init.h: Regenerated.
869 * i386-tbl.h: Likewise.
871 2013-01-15 Nick Clifton <nickc@redhat.com>
873 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
875 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
877 2013-01-14 Will Newton <will.newton@imgtec.com>
879 * metag-dis.c (REG_WIDTH): Increase to 64.
881 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
883 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
884 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
885 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
887 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
888 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
889 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
890 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
892 2013-01-10 Will Newton <will.newton@imgtec.com>
894 * Makefile.am: Add Meta.
895 * configure.in: Add Meta.
896 * disassemble.c: Add Meta support.
897 * metag-dis.c: New file.
898 * Makefile.in: Regenerate.
899 * configure: Regenerate.
901 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
903 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
904 (match_opcode): Rename to cr16_match_opcode.
906 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
908 * mips-dis.c: Add names for CP0 registers of r5900.
909 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
910 instructions sq and lq.
911 Add support for MIPS r5900 CPU.
912 Add support for 128 bit MMI (Multimedia Instructions).
913 Add support for EE instructions (Emotion Engine).
914 Disable unsupported floating point instructions (64 bit and
915 undefined compare operations).
916 Enable instructions of MIPS ISA IV which are supported by r5900.
917 Disable 64 bit co processor instructions.
918 Disable 64 bit multiplication and division instructions.
919 Disable instructions for co-processor 2 and 3, because these are
920 not supported (preparation for later VU0 support (Vector Unit)).
921 Disable cvt.w.s because this behaves like trunc.w.s and the
922 correct execution can't be ensured on r5900.
923 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
924 will confuse less developers and compilers.
926 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
928 * aarch64-opc.c (aarch64_print_operand): Change to print
929 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
931 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
932 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
935 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
937 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
938 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
940 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
942 * i386-gen.c (process_copyright): Update copyright year to 2013.
944 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
946 * cr16-dis.c (match_opcode,make_instruction): Remove static
948 (dwordU,wordU): Moved typedefs to opcode/cr16.h
949 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
951 For older changes see ChangeLog-2012
953 Copyright (C) 2013 Free Software Foundation, Inc.
955 Copying and distribution of this file, with or without modification,
956 are permitted in any medium without royalty provided the copyright
957 notice and this notice are preserved.
963 version-control: never