1 2019-07-01 Jan Beulich <jbeulich@suse.com>
3 * opcodes/i386-gen.c (operand_type_init): Remove
4 OPERAND_TYPE_VEC_IMM4 entry.
5 (operand_types): Remove Vec_Imm4.
6 * opcodes/i386-opc.h (Vec_Imm4): Delete.
7 (union i386_operand_type): Remove vec_imm4.
8 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
9 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
11 2019-07-01 Jan Beulich <jbeulich@suse.com>
13 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
14 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
15 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
16 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
17 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
18 monitorx, mwaitx): Drop ImmExt from operand-less forms.
19 * i386-tbl.h: Re-generate.
21 2019-07-01 Jan Beulich <jbeulich@suse.com>
23 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
25 * i386-tbl.h: Re-generate.
27 2019-07-01 Jan Beulich <jbeulich@suse.com>
29 * i386-opc.tbl (C): New.
30 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
31 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
32 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
33 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
34 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
35 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
36 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
37 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
38 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
39 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
40 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
41 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
42 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
43 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
44 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
45 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
46 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
47 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
48 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
49 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
50 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
51 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
52 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
53 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
54 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
55 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
57 * i386-tbl.h: Re-generate.
59 2019-07-01 Jan Beulich <jbeulich@suse.com>
61 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
63 * i386-tbl.h: Re-generate.
65 2019-07-01 Jan Beulich <jbeulich@suse.com>
67 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
68 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
69 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
70 * i386-tbl.h: Re-generate.
72 2019-07-01 Jan Beulich <jbeulich@suse.com>
74 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
75 Disp8MemShift from register only templates.
76 * i386-tbl.h: Re-generate.
78 2019-07-01 Jan Beulich <jbeulich@suse.com>
80 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
81 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
82 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
83 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
84 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
85 EVEX_W_0F11_P_3_M_1): Delete.
86 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
87 EVEX_W_0F11_P_3): New.
88 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
89 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
90 MOD_EVEX_0F11_PREFIX_3 table entries.
91 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
92 PREFIX_EVEX_0F11 table entries.
93 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
94 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
95 EVEX_W_0F11_P_3_M_{0,1} table entries.
97 2019-07-01 Jan Beulich <jbeulich@suse.com>
99 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
102 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
105 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
106 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
107 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
108 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
109 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
110 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
111 EVEX_LEN_0F38C7_R_6_P_2_W_1.
112 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
113 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
114 PREFIX_EVEX_0F38C6_REG_6 entries.
115 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
116 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
117 EVEX_W_0F38C7_R_6_P_2 entries.
118 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
119 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
120 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
121 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
122 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
123 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
124 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
126 2019-06-27 Jan Beulich <jbeulich@suse.com>
128 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
129 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
130 VEX_LEN_0F2D_P_3): Delete.
131 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
132 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
133 (prefix_table): ... here.
135 2019-06-27 Jan Beulich <jbeulich@suse.com>
137 * i386-dis.c (Iq): Delete.
139 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
141 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
142 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
143 (OP_E_memory): Also honor needindex when deciding whether an
144 address size prefix needs printing.
145 (OP_I): Remove handling of q_mode. Add handling of d_mode.
147 2019-06-26 Jim Wilson <jimw@sifive.com>
150 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
151 Set info->display_endian to info->endian_code.
153 2019-06-25 Jan Beulich <jbeulich@suse.com>
155 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
156 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
157 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
158 OPERAND_TYPE_ACC64 entries.
159 * i386-init.h: Re-generate.
161 2019-06-25 Jan Beulich <jbeulich@suse.com>
163 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
165 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
167 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
169 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
170 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
172 2019-06-25 Jan Beulich <jbeulich@suse.com>
174 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
177 2019-06-25 Jan Beulich <jbeulich@suse.com>
179 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
180 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
182 * i386-opc.tbl (movnti): Add IgnoreSize.
183 * i386-tbl.h: Re-generate.
185 2019-06-25 Jan Beulich <jbeulich@suse.com>
187 * i386-opc.tbl (and): Mark Imm8S form for optimization.
188 * i386-tbl.h: Re-generate.
190 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
192 * i386-dis-evex.h: Break into ...
193 * i386-dis-evex-len.h: New file.
194 * i386-dis-evex-mod.h: Likewise.
195 * i386-dis-evex-prefix.h: Likewise.
196 * i386-dis-evex-reg.h: Likewise.
197 * i386-dis-evex-w.h: Likewise.
198 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
199 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
202 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
205 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
206 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
208 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
209 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
210 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
211 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
212 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
213 EVEX_LEN_0F385B_P_2_W_1.
214 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
215 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
216 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
217 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
218 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
219 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
220 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
221 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
222 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
223 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
225 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
228 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
229 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
230 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
231 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
232 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
233 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
234 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
235 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
236 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
237 EVEX_LEN_0F3A43_P_2_W_1.
238 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
239 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
240 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
241 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
242 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
243 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
244 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
245 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
246 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
247 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
248 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
249 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
251 2019-06-14 Nick Clifton <nickc@redhat.com>
253 * po/fr.po; Updated French translation.
255 2019-06-13 Stafford Horne <shorne@gmail.com>
257 * or1k-asm.c: Regenerated.
258 * or1k-desc.c: Regenerated.
259 * or1k-desc.h: Regenerated.
260 * or1k-dis.c: Regenerated.
261 * or1k-ibld.c: Regenerated.
262 * or1k-opc.c: Regenerated.
263 * or1k-opc.h: Regenerated.
264 * or1k-opinst.c: Regenerated.
266 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
268 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
270 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
273 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
274 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
275 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
276 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
277 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
278 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
279 EVEX_LEN_0F3A1B_P_2_W_1.
280 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
281 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
282 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
283 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
284 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
285 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
286 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
287 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
289 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
292 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
293 EVEX.vvvv when disassembling VEX and EVEX instructions.
294 (OP_VEX): Set vex.register_specifier to 0 after readding
295 vex.register_specifier.
296 (OP_Vex_2src_1): Likewise.
297 (OP_Vex_2src_2): Likewise.
298 (OP_LWP_E): Likewise.
299 (OP_EX_Vex): Don't check vex.register_specifier.
300 (OP_XMM_Vex): Likewise.
302 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
303 Lili Cui <lili.cui@intel.com>
305 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
306 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
308 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
309 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
310 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
311 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
312 (i386_cpu_flags): Add cpuavx512_vp2intersect.
313 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
314 * i386-init.h: Regenerated.
315 * i386-tbl.h: Likewise.
317 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
318 Lili Cui <lili.cui@intel.com>
320 * doc/c-i386.texi: Document enqcmd.
321 * testsuite/gas/i386/enqcmd-intel.d: New file.
322 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
323 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
324 * testsuite/gas/i386/enqcmd.d: Likewise.
325 * testsuite/gas/i386/enqcmd.s: Likewise.
326 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
327 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
328 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
329 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
330 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
331 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
332 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
335 2019-06-04 Alan Hayward <alan.hayward@arm.com>
337 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
339 2019-06-03 Alan Modra <amodra@gmail.com>
341 * ppc-dis.c (prefix_opcd_indices): Correct size.
343 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
346 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
348 * i386-tbl.h: Regenerated.
350 2019-05-24 Alan Modra <amodra@gmail.com>
352 * po/POTFILES.in: Regenerate.
354 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
355 Alan Modra <amodra@gmail.com>
357 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
358 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
359 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
360 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
361 XTOP>): Define and add entries.
362 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
363 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
364 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
365 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
367 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
368 Alan Modra <amodra@gmail.com>
370 * ppc-dis.c (ppc_opts): Add "future" entry.
371 (PREFIX_OPCD_SEGS): Define.
372 (prefix_opcd_indices): New array.
373 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
374 (lookup_prefix): New function.
375 (print_insn_powerpc): Handle 64-bit prefix instructions.
376 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
377 (PMRR, POWERXX): Define.
378 (prefix_opcodes): New instruction table.
379 (prefix_num_opcodes): New constant.
381 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
383 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
384 * configure: Regenerated.
385 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
387 (HFILES): Add bpf-desc.h and bpf-opc.h.
388 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
389 bpf-ibld.c and bpf-opc.c.
391 * Makefile.in: Regenerated.
392 * disassemble.c (ARCH_bpf): Define.
393 (disassembler): Add case for bfd_arch_bpf.
394 (disassemble_init_for_target): Likewise.
395 (enum epbf_isa_attr): Define.
396 * disassemble.h: extern print_insn_bpf.
397 * bpf-asm.c: Generated.
398 * bpf-opc.h: Likewise.
399 * bpf-opc.c: Likewise.
400 * bpf-ibld.c: Likewise.
401 * bpf-dis.c: Likewise.
402 * bpf-desc.h: Likewise.
403 * bpf-desc.c: Likewise.
405 2019-05-21 Sudakshina Das <sudi.das@arm.com>
407 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
408 and VMSR with the new operands.
410 2019-05-21 Sudakshina Das <sudi.das@arm.com>
412 * arm-dis.c (enum mve_instructions): New enum
413 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
415 (mve_opcodes): New instructions as above.
416 (is_mve_encoding_conflict): Add cases for csinc, csinv,
418 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
420 2019-05-21 Sudakshina Das <sudi.das@arm.com>
422 * arm-dis.c (emun mve_instructions): Updated for new instructions.
423 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
424 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
425 uqshl, urshrl and urshr.
426 (is_mve_okay_in_it): Add new instructions to TRUE list.
427 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
428 (print_insn_mve): Updated to accept new %j,
429 %<bitfield>m and %<bitfield>n patterns.
431 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
433 * mips-opc.c (mips_builtin_opcodes): Change source register
436 2019-05-20 Nick Clifton <nickc@redhat.com>
438 * po/fr.po: Updated French translation.
440 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
441 Michael Collison <michael.collison@arm.com>
443 * arm-dis.c (thumb32_opcodes): Add new instructions.
444 (enum mve_instructions): Likewise.
445 (enum mve_undefined): Add new reasons.
446 (is_mve_encoding_conflict): Handle new instructions.
447 (is_mve_undefined): Likewise.
448 (is_mve_unpredictable): Likewise.
449 (print_mve_undefined): Likewise.
450 (print_mve_size): Likewise.
452 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
453 Michael Collison <michael.collison@arm.com>
455 * arm-dis.c (thumb32_opcodes): Add new instructions.
456 (enum mve_instructions): Likewise.
457 (is_mve_encoding_conflict): Handle new instructions.
458 (is_mve_undefined): Likewise.
459 (is_mve_unpredictable): Likewise.
460 (print_mve_size): Likewise.
462 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
463 Michael Collison <michael.collison@arm.com>
465 * arm-dis.c (thumb32_opcodes): Add new instructions.
466 (enum mve_instructions): Likewise.
467 (is_mve_encoding_conflict): Likewise.
468 (is_mve_unpredictable): Likewise.
469 (print_mve_size): Likewise.
471 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
472 Michael Collison <michael.collison@arm.com>
474 * arm-dis.c (thumb32_opcodes): Add new instructions.
475 (enum mve_instructions): Likewise.
476 (is_mve_encoding_conflict): Handle new instructions.
477 (is_mve_undefined): Likewise.
478 (is_mve_unpredictable): Likewise.
479 (print_mve_size): Likewise.
481 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
482 Michael Collison <michael.collison@arm.com>
484 * arm-dis.c (thumb32_opcodes): Add new instructions.
485 (enum mve_instructions): Likewise.
486 (is_mve_encoding_conflict): Handle new instructions.
487 (is_mve_undefined): Likewise.
488 (is_mve_unpredictable): Likewise.
489 (print_mve_size): Likewise.
490 (print_insn_mve): Likewise.
492 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
493 Michael Collison <michael.collison@arm.com>
495 * arm-dis.c (thumb32_opcodes): Add new instructions.
496 (print_insn_thumb32): Handle new instructions.
498 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
499 Michael Collison <michael.collison@arm.com>
501 * arm-dis.c (enum mve_instructions): Add new instructions.
502 (enum mve_undefined): Add new reasons.
503 (is_mve_encoding_conflict): Handle new instructions.
504 (is_mve_undefined): Likewise.
505 (is_mve_unpredictable): Likewise.
506 (print_mve_undefined): Likewise.
507 (print_mve_size): Likewise.
508 (print_mve_shift_n): Likewise.
509 (print_insn_mve): Likewise.
511 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
512 Michael Collison <michael.collison@arm.com>
514 * arm-dis.c (enum mve_instructions): Add new instructions.
515 (is_mve_encoding_conflict): Handle new instructions.
516 (is_mve_unpredictable): Likewise.
517 (print_mve_rotate): Likewise.
518 (print_mve_size): Likewise.
519 (print_insn_mve): Likewise.
521 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
522 Michael Collison <michael.collison@arm.com>
524 * arm-dis.c (enum mve_instructions): Add new instructions.
525 (is_mve_encoding_conflict): Handle new instructions.
526 (is_mve_unpredictable): Likewise.
527 (print_mve_size): Likewise.
528 (print_insn_mve): Likewise.
530 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
531 Michael Collison <michael.collison@arm.com>
533 * arm-dis.c (enum mve_instructions): Add new instructions.
534 (enum mve_undefined): Add new reasons.
535 (is_mve_encoding_conflict): Handle new instructions.
536 (is_mve_undefined): Likewise.
537 (is_mve_unpredictable): Likewise.
538 (print_mve_undefined): Likewise.
539 (print_mve_size): Likewise.
540 (print_insn_mve): Likewise.
542 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
543 Michael Collison <michael.collison@arm.com>
545 * arm-dis.c (enum mve_instructions): Add new instructions.
546 (is_mve_encoding_conflict): Handle new instructions.
547 (is_mve_undefined): Likewise.
548 (is_mve_unpredictable): Likewise.
549 (print_mve_size): Likewise.
550 (print_insn_mve): Likewise.
552 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
553 Michael Collison <michael.collison@arm.com>
555 * arm-dis.c (enum mve_instructions): Add new instructions.
556 (enum mve_unpredictable): Add new reasons.
557 (enum mve_undefined): Likewise.
558 (is_mve_okay_in_it): Handle new isntructions.
559 (is_mve_encoding_conflict): Likewise.
560 (is_mve_undefined): Likewise.
561 (is_mve_unpredictable): Likewise.
562 (print_mve_vmov_index): Likewise.
563 (print_simd_imm8): Likewise.
564 (print_mve_undefined): Likewise.
565 (print_mve_unpredictable): Likewise.
566 (print_mve_size): Likewise.
567 (print_insn_mve): Likewise.
569 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
570 Michael Collison <michael.collison@arm.com>
572 * arm-dis.c (enum mve_instructions): Add new instructions.
573 (enum mve_unpredictable): Add new reasons.
574 (enum mve_undefined): Likewise.
575 (is_mve_encoding_conflict): Handle new instructions.
576 (is_mve_undefined): Likewise.
577 (is_mve_unpredictable): Likewise.
578 (print_mve_undefined): Likewise.
579 (print_mve_unpredictable): Likewise.
580 (print_mve_rounding_mode): Likewise.
581 (print_mve_vcvt_size): Likewise.
582 (print_mve_size): Likewise.
583 (print_insn_mve): Likewise.
585 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
586 Michael Collison <michael.collison@arm.com>
588 * arm-dis.c (enum mve_instructions): Add new instructions.
589 (enum mve_unpredictable): Add new reasons.
590 (enum mve_undefined): Likewise.
591 (is_mve_undefined): Handle new instructions.
592 (is_mve_unpredictable): Likewise.
593 (print_mve_undefined): Likewise.
594 (print_mve_unpredictable): Likewise.
595 (print_mve_size): Likewise.
596 (print_insn_mve): Likewise.
598 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
599 Michael Collison <michael.collison@arm.com>
601 * arm-dis.c (enum mve_instructions): Add new instructions.
602 (enum mve_undefined): Add new reasons.
603 (insns): Add new instructions.
604 (is_mve_encoding_conflict):
605 (print_mve_vld_str_addr): New print function.
606 (is_mve_undefined): Handle new instructions.
607 (is_mve_unpredictable): Likewise.
608 (print_mve_undefined): Likewise.
609 (print_mve_size): Likewise.
610 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
611 (print_insn_mve): Handle new operands.
613 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
614 Michael Collison <michael.collison@arm.com>
616 * arm-dis.c (enum mve_instructions): Add new instructions.
617 (enum mve_unpredictable): Add new reasons.
618 (is_mve_encoding_conflict): Handle new instructions.
619 (is_mve_unpredictable): Likewise.
620 (mve_opcodes): Add new instructions.
621 (print_mve_unpredictable): Handle new reasons.
622 (print_mve_register_blocks): New print function.
623 (print_mve_size): Handle new instructions.
624 (print_insn_mve): Likewise.
626 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
627 Michael Collison <michael.collison@arm.com>
629 * arm-dis.c (enum mve_instructions): Add new instructions.
630 (enum mve_unpredictable): Add new reasons.
631 (enum mve_undefined): Likewise.
632 (is_mve_encoding_conflict): Handle new instructions.
633 (is_mve_undefined): Likewise.
634 (is_mve_unpredictable): Likewise.
635 (coprocessor_opcodes): Move NEON VDUP from here...
636 (neon_opcodes): ... to here.
637 (mve_opcodes): Add new instructions.
638 (print_mve_undefined): Handle new reasons.
639 (print_mve_unpredictable): Likewise.
640 (print_mve_size): Handle new instructions.
641 (print_insn_neon): Handle vdup.
642 (print_insn_mve): Handle new operands.
644 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
645 Michael Collison <michael.collison@arm.com>
647 * arm-dis.c (enum mve_instructions): Add new instructions.
648 (enum mve_unpredictable): Add new values.
649 (mve_opcodes): Add new instructions.
650 (vec_condnames): New array with vector conditions.
651 (mve_predicatenames): New array with predicate suffixes.
652 (mve_vec_sizename): New array with vector sizes.
653 (enum vpt_pred_state): New enum with vector predication states.
654 (struct vpt_block): New struct type for vpt blocks.
655 (vpt_block_state): Global struct to keep track of state.
656 (mve_extract_pred_mask): New helper function.
657 (num_instructions_vpt_block): Likewise.
658 (mark_outside_vpt_block): Likewise.
659 (mark_inside_vpt_block): Likewise.
660 (invert_next_predicate_state): Likewise.
661 (update_next_predicate_state): Likewise.
662 (update_vpt_block_state): Likewise.
663 (is_vpt_instruction): Likewise.
664 (is_mve_encoding_conflict): Add entries for new instructions.
665 (is_mve_unpredictable): Likewise.
666 (print_mve_unpredictable): Handle new cases.
667 (print_instruction_predicate): Likewise.
668 (print_mve_size): New function.
669 (print_vec_condition): New function.
670 (print_insn_mve): Handle vpt blocks and new print operands.
672 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
674 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
675 8, 14 and 15 for Armv8.1-M Mainline.
677 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
678 Michael Collison <michael.collison@arm.com>
680 * arm-dis.c (enum mve_instructions): New enum.
681 (enum mve_unpredictable): Likewise.
682 (enum mve_undefined): Likewise.
683 (struct mopcode32): New struct.
684 (is_mve_okay_in_it): New function.
685 (is_mve_architecture): Likewise.
686 (arm_decode_field): Likewise.
687 (arm_decode_field_multiple): Likewise.
688 (is_mve_encoding_conflict): Likewise.
689 (is_mve_undefined): Likewise.
690 (is_mve_unpredictable): Likewise.
691 (print_mve_undefined): Likewise.
692 (print_mve_unpredictable): Likewise.
693 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
694 (print_insn_mve): New function.
695 (print_insn_thumb32): Handle MVE architecture.
696 (select_arm_features): Force thumb for Armv8.1-m Mainline.
698 2019-05-10 Nick Clifton <nickc@redhat.com>
701 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
702 end of the table prematurely.
704 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
706 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
709 2019-05-11 Alan Modra <amodra@gmail.com>
711 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
712 when -Mraw is in effect.
714 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
716 * aarch64-dis-2.c: Regenerate.
717 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
718 (OP_SVE_BBB): New variant set.
719 (OP_SVE_DDDD): New variant set.
720 (OP_SVE_HHH): New variant set.
721 (OP_SVE_HHHU): New variant set.
722 (OP_SVE_SSS): New variant set.
723 (OP_SVE_SSSU): New variant set.
724 (OP_SVE_SHH): New variant set.
725 (OP_SVE_SBBU): New variant set.
726 (OP_SVE_DSS): New variant set.
727 (OP_SVE_DHHU): New variant set.
728 (OP_SVE_VMV_HSD_BHS): New variant set.
729 (OP_SVE_VVU_HSD_BHS): New variant set.
730 (OP_SVE_VVVU_SD_BH): New variant set.
731 (OP_SVE_VVVU_BHSD): New variant set.
732 (OP_SVE_VVV_QHD_DBS): New variant set.
733 (OP_SVE_VVV_HSD_BHS): New variant set.
734 (OP_SVE_VVV_HSD_BHS2): New variant set.
735 (OP_SVE_VVV_BHS_HSD): New variant set.
736 (OP_SVE_VV_BHS_HSD): New variant set.
737 (OP_SVE_VVV_SD): New variant set.
738 (OP_SVE_VVU_BHS_HSD): New variant set.
739 (OP_SVE_VZVV_SD): New variant set.
740 (OP_SVE_VZVV_BH): New variant set.
741 (OP_SVE_VZV_SD): New variant set.
742 (aarch64_opcode_table): Add sve2 instructions.
744 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
746 * aarch64-asm-2.c: Regenerated.
747 * aarch64-dis-2.c: Regenerated.
748 * aarch64-opc-2.c: Regenerated.
749 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
750 for SVE_SHLIMM_UNPRED_22.
751 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
752 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
755 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
757 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
758 sve_size_tsz_bhs iclass encode.
759 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
760 sve_size_tsz_bhs iclass decode.
762 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
764 * aarch64-asm-2.c: Regenerated.
765 * aarch64-dis-2.c: Regenerated.
766 * aarch64-opc-2.c: Regenerated.
767 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
768 for SVE_Zm4_11_INDEX.
769 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
770 (fields): Handle SVE_i2h field.
771 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
772 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
774 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
776 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
777 sve_shift_tsz_bhsd iclass encode.
778 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
779 sve_shift_tsz_bhsd iclass decode.
781 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
783 * aarch64-asm-2.c: Regenerated.
784 * aarch64-dis-2.c: Regenerated.
785 * aarch64-opc-2.c: Regenerated.
786 * aarch64-asm.c (aarch64_ins_sve_shrimm):
787 (aarch64_encode_variant_using_iclass): Handle
788 sve_shift_tsz_hsd iclass encode.
789 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
790 sve_shift_tsz_hsd iclass decode.
791 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
792 for SVE_SHRIMM_UNPRED_22.
793 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
794 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
797 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
799 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
800 sve_size_013 iclass encode.
801 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
802 sve_size_013 iclass decode.
804 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
806 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
807 sve_size_bh iclass encode.
808 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
809 sve_size_bh iclass decode.
811 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
813 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
814 sve_size_sd2 iclass encode.
815 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
816 sve_size_sd2 iclass decode.
817 * aarch64-opc.c (fields): Handle SVE_sz2 field.
818 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
820 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
822 * aarch64-asm-2.c: Regenerated.
823 * aarch64-dis-2.c: Regenerated.
824 * aarch64-opc-2.c: Regenerated.
825 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
827 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
828 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
830 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
832 * aarch64-asm-2.c: Regenerated.
833 * aarch64-dis-2.c: Regenerated.
834 * aarch64-opc-2.c: Regenerated.
835 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
836 for SVE_Zm3_11_INDEX.
837 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
838 (fields): Handle SVE_i3l and SVE_i3h2 fields.
839 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
841 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
843 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
845 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
846 sve_size_hsd2 iclass encode.
847 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
848 sve_size_hsd2 iclass decode.
849 * aarch64-opc.c (fields): Handle SVE_size field.
850 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
852 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
854 * aarch64-asm-2.c: Regenerated.
855 * aarch64-dis-2.c: Regenerated.
856 * aarch64-opc-2.c: Regenerated.
857 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
859 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
860 (fields): Handle SVE_rot3 field.
861 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
862 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
864 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
866 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
869 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
872 (aarch64_feature_sve2, aarch64_feature_sve2aes,
873 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
874 aarch64_feature_sve2bitperm): New feature sets.
875 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
876 for feature set addresses.
877 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
878 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
880 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
881 Faraz Shahbazker <fshahbazker@wavecomp.com>
883 * mips-dis.c (mips_calculate_combination_ases): Add ISA
884 argument and set ASE_EVA_R6 appropriately.
885 (set_default_mips_dis_options): Pass ISA to above.
886 (parse_mips_dis_option): Likewise.
887 * mips-opc.c (EVAR6): New macro.
888 (mips_builtin_opcodes): Add llwpe, scwpe.
890 2019-05-01 Sudakshina Das <sudi.das@arm.com>
892 * aarch64-asm-2.c: Regenerated.
893 * aarch64-dis-2.c: Regenerated.
894 * aarch64-opc-2.c: Regenerated.
895 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
896 AARCH64_OPND_TME_UIMM16.
897 (aarch64_print_operand): Likewise.
898 * aarch64-tbl.h (QL_IMM_NIL): New.
901 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
903 2019-04-29 John Darrington <john@darrington.wattle.id.au>
905 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
907 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
908 Faraz Shahbazker <fshahbazker@wavecomp.com>
910 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
912 2019-04-24 John Darrington <john@darrington.wattle.id.au>
914 * s12z-opc.h: Add extern "C" bracketing to help
915 users who wish to use this interface in c++ code.
917 2019-04-24 John Darrington <john@darrington.wattle.id.au>
919 * s12z-opc.c (bm_decode): Handle bit map operations with the
922 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
924 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
925 specifier. Add entries for VLDR and VSTR of system registers.
926 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
927 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
928 of %J and %K format specifier.
930 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
932 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
933 Add new entries for VSCCLRM instruction.
934 (print_insn_coprocessor): Handle new %C format control code.
936 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
938 * arm-dis.c (enum isa): New enum.
939 (struct sopcode32): New structure.
940 (coprocessor_opcodes): change type of entries to struct sopcode32 and
941 set isa field of all current entries to ANY.
942 (print_insn_coprocessor): Change type of insn to struct sopcode32.
943 Only match an entry if its isa field allows the current mode.
945 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
947 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
949 (print_insn_thumb32): Add logic to print %n CLRM register list.
951 2019-04-15 Sudakshina Das <sudi.das@arm.com>
953 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
956 2019-04-15 Sudakshina Das <sudi.das@arm.com>
958 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
959 (print_insn_thumb32): Edit the switch case for %Z.
961 2019-04-15 Sudakshina Das <sudi.das@arm.com>
963 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
965 2019-04-15 Sudakshina Das <sudi.das@arm.com>
967 * arm-dis.c (thumb32_opcodes): New instruction bfl.
969 2019-04-15 Sudakshina Das <sudi.das@arm.com>
971 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
973 2019-04-15 Sudakshina Das <sudi.das@arm.com>
975 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
976 Arm register with r13 and r15 unpredictable.
977 (thumb32_opcodes): New instructions for bfx and bflx.
979 2019-04-15 Sudakshina Das <sudi.das@arm.com>
981 * arm-dis.c (thumb32_opcodes): New instructions for bf.
983 2019-04-15 Sudakshina Das <sudi.das@arm.com>
985 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
987 2019-04-15 Sudakshina Das <sudi.das@arm.com>
989 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
991 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
993 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
995 2019-04-12 John Darrington <john@darrington.wattle.id.au>
997 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
998 "optr". ("operator" is a reserved word in c++).
1000 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1002 * aarch64-opc.c (aarch64_print_operand): Add case for
1004 (verify_constraints): Likewise.
1005 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1006 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1007 to accept Rt|SP as first operand.
1008 (AARCH64_OPERANDS): Add new Rt_SP.
1009 * aarch64-asm-2.c: Regenerated.
1010 * aarch64-dis-2.c: Regenerated.
1011 * aarch64-opc-2.c: Regenerated.
1013 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1015 * aarch64-asm-2.c: Regenerated.
1016 * aarch64-dis-2.c: Likewise.
1017 * aarch64-opc-2.c: Likewise.
1018 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1020 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1022 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1024 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1026 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1027 * i386-init.h: Regenerated.
1029 2019-04-07 Alan Modra <amodra@gmail.com>
1031 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1032 op_separator to control printing of spaces, comma and parens
1033 rather than need_comma, need_paren and spaces vars.
1035 2019-04-07 Alan Modra <amodra@gmail.com>
1038 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1039 (print_insn_neon, print_insn_arm): Likewise.
1041 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1043 * i386-dis-evex.h (evex_table): Updated to support BF16
1045 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1046 and EVEX_W_0F3872_P_3.
1047 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1048 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1049 * i386-opc.h (enum): Add CpuAVX512_BF16.
1050 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1051 * i386-opc.tbl: Add AVX512 BF16 instructions.
1052 * i386-init.h: Regenerated.
1053 * i386-tbl.h: Likewise.
1055 2019-04-05 Alan Modra <amodra@gmail.com>
1057 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1058 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1059 to favour printing of "-" branch hint when using the "y" bit.
1060 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1062 2019-04-05 Alan Modra <amodra@gmail.com>
1064 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1065 opcode until first operand is output.
1067 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1070 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1071 (valid_bo_post_v2): Add support for 'at' branch hints.
1072 (insert_bo): Only error on branch on ctr.
1073 (get_bo_hint_mask): New function.
1074 (insert_boe): Add new 'branch_taken' formal argument. Add support
1075 for inserting 'at' branch hints.
1076 (extract_boe): Add new 'branch_taken' formal argument. Add support
1077 for extracting 'at' branch hints.
1078 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1079 (BOE): Delete operand.
1080 (BOM, BOP): New operands.
1082 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1083 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1084 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1085 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1086 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1087 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1088 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1089 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1090 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1091 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1092 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1093 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1094 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1095 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1096 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1097 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1098 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1099 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1100 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1101 bttarl+>: New extended mnemonics.
1103 2019-03-28 Alan Modra <amodra@gmail.com>
1106 * ppc-opc.c (BTF): Define.
1107 (powerpc_opcodes): Use for mtfsb*.
1108 * ppc-dis.c (print_insn_powerpc): Print fields with both
1109 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1111 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1113 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1114 (mapping_symbol_for_insn): Implement new algorithm.
1115 (print_insn): Remove duplicate code.
1117 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1119 * aarch64-dis.c (print_insn_aarch64):
1122 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1124 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1127 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1129 * aarch64-dis.c (last_stop_offset): New.
1130 (print_insn_aarch64): Use stop_offset.
1132 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1135 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1137 * i386-init.h: Regenerated.
1139 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1142 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1143 vmovdqu16, vmovdqu32 and vmovdqu64.
1144 * i386-tbl.h: Regenerated.
1146 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1148 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1149 from vstrszb, vstrszh, and vstrszf.
1151 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1153 * s390-opc.txt: Add instruction descriptions.
1155 2019-02-08 Jim Wilson <jimw@sifive.com>
1157 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1160 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1162 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1164 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1167 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1168 * aarch64-opc.c (verify_elem_sd): New.
1169 (fields): Add FLD_sz entr.
1170 * aarch64-tbl.h (_SIMD_INSN): New.
1171 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1172 fmulx scalar and vector by element isns.
1174 2019-02-07 Nick Clifton <nickc@redhat.com>
1176 * po/sv.po: Updated Swedish translation.
1178 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1180 * s390-mkopc.c (main): Accept arch13 as cpu string.
1181 * s390-opc.c: Add new instruction formats and instruction opcode
1183 * s390-opc.txt: Add new arch13 instructions.
1185 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1187 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1188 (aarch64_opcode): Change encoding for stg, stzg
1190 * aarch64-asm-2.c: Regenerated.
1191 * aarch64-dis-2.c: Regenerated.
1192 * aarch64-opc-2.c: Regenerated.
1194 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1196 * aarch64-asm-2.c: Regenerated.
1197 * aarch64-dis-2.c: Likewise.
1198 * aarch64-opc-2.c: Likewise.
1199 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1201 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1202 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1204 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1205 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1206 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1207 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1208 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1209 case for ldstgv_indexed.
1210 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1211 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1212 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1213 * aarch64-asm-2.c: Regenerated.
1214 * aarch64-dis-2.c: Regenerated.
1215 * aarch64-opc-2.c: Regenerated.
1217 2019-01-23 Nick Clifton <nickc@redhat.com>
1219 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1221 2019-01-21 Nick Clifton <nickc@redhat.com>
1223 * po/de.po: Updated German translation.
1224 * po/uk.po: Updated Ukranian translation.
1226 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1227 * mips-dis.c (mips_arch_choices): Fix typo in
1228 gs464, gs464e and gs264e descriptors.
1230 2019-01-19 Nick Clifton <nickc@redhat.com>
1232 * configure: Regenerate.
1233 * po/opcodes.pot: Regenerate.
1235 2018-06-24 Nick Clifton <nickc@redhat.com>
1237 2.32 branch created.
1239 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1241 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1243 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1246 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1248 * configure: Regenerate.
1250 2019-01-07 Alan Modra <amodra@gmail.com>
1252 * configure: Regenerate.
1253 * po/POTFILES.in: Regenerate.
1255 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1257 * s12z-opc.c: New file.
1258 * s12z-opc.h: New file.
1259 * s12z-dis.c: Removed all code not directly related to display
1260 of instructions. Used the interface provided by the new files
1262 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1263 * Makefile.in: Regenerate.
1264 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1265 * configure: Regenerate.
1267 2019-01-01 Alan Modra <amodra@gmail.com>
1269 Update year range in copyright notice of all files.
1271 For older changes see ChangeLog-2018
1273 Copyright (C) 2019 Free Software Foundation, Inc.
1275 Copying and distribution of this file, with or without modification,
1276 are permitted in any medium without royalty provided the copyright
1277 notice and this notice are preserved.
1283 version-control: never