1 2014-10-29 Nick Clifton <nickc@redhat.com>
3 * po/de.po: Updated German translation.
5 2014-10-28 Alan Modra <amodra@gmail.com>
8 2014-10-21 Jan Beulich <jbeulich@suse.com>
9 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
11 2014-10-15 Tristan Gingold <gingold@adacore.com>
13 * configure: Regenerate.
15 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
17 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
18 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
19 Annotate table with HWCAP2 bits.
20 Add instructions xmontmul, xmontsqr, xmpmul.
21 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
22 r,i,%mwait' and `rd %mwait,r' instructions.
23 Add rd/wr instructions for accessing the %mcdper ancillary state
25 (sparc-opcodes): Add sparc5/vis4.0 instructions:
26 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
27 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
28 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
29 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
30 fpsubus16, and faligndatai.
31 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
32 ancillary state register to the table.
33 (print_insn_sparc): Handle the %mcdper ancillary state register.
34 (print_insn_sparc): Handle new operand type '}'.
36 2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
38 * i386-dis.c (MOD_0F20): Removed.
42 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
44 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
45 (OP_R): Check mod/rm byte and call OP_E_register.
47 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
49 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
50 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
51 keyword_aridxi): Add audio ISA extension.
52 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
53 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
54 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
55 for nds32-dis.c using.
56 (build_opcode_syntax): Remove dead code.
57 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
58 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
59 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
61 * nds32-asm.h: Declare.
62 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
65 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
66 Matthew Fortune <matthew.fortune@imgtec.com>
68 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
70 (parse_mips_dis_option): Allow MSA and virtualization support for
72 (mips_print_arg_state): Add fields dest_regno and seen_dest.
73 (mips_seen_register): New function.
74 (print_insn_arg): Refactored code to use mips_seen_register
75 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
76 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
77 the register rather than aborting.
78 (print_insn_args): Add length argument. Add code to correctly
79 calculate the instruction address for pc relative instructions.
80 (validate_insn_args): New static function.
81 (print_insn_mips): Prevent jalx disassembling for r6. Use
83 (print_insn_micromips): Use validate_insn_args.
84 all the arguments are valid.
85 * mips-formats.h (PREV_CHECK): New define.
86 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
87 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
92 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
93 MIPS R6 instructions from MIPS R2 instructions.
95 2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
97 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
98 (putop): Handle "%LP".
100 2014-09-03 Jiong Wang <jiong.wang@arm.com>
102 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
103 * aarch64-dis-2.c: Update auto-generated file.
105 2014-09-03 Jiong Wang <jiong.wang@arm.com>
107 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
108 (aarch64_feature_lse): New feature added.
110 (aarch64_opcode_table): New LSE instructions added. Improve
111 descriptions for ldarb/ldarh/ldar.
112 (aarch64_opcode_table): Describe PAIRREG.
113 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
114 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
115 (aarch64_print_operand): Recognize PAIRREG.
116 (operand_general_constraint_met_p): Check reg pair constraints for CASP
118 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
119 (do_special_decoding): Recognize F_LSE_SZ.
120 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
122 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
124 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
125 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
126 "sdbbp", "syscall" and "wait".
128 2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
129 Maciej W. Rozycki <macro@codesourcery.com>
131 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
132 returned if the U bit is set.
134 2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
136 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
137 48-bit "li" encoding.
139 2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
141 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
142 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
143 static functions, code was moved from...
144 (print_insn_s390): ...here.
145 (s390_extract_operand): Adjust comment. Change type of first
146 parameter from 'unsigned char *' to 'const bfd_byte *'.
147 (union operand_value): New.
148 (s390_extract_operand): Change return type to union operand_value.
149 Also avoid integer overflow in sign-extension.
150 (s390_print_insn_with_opcode): Adjust to changed return value from
151 s390_extract_operand(). Change "%i" printf format to "%u" for
153 (init_disasm): Simplify initialization of opc_index[]. This also
154 fixes an access after the last element of s390_opcodes[].
155 (print_insn_s390): Simplify the opcode search loop.
156 Check architecture mask against all searched opcodes, not just the
158 (s390_print_insn_with_opcode): Drop function pointer dereferences
160 (print_insn_s390): Likewise.
161 (s390_insn_length): Simplify formula for return value.
162 (s390_print_insn_with_opcode): Avoid special handling for the
163 separator before the first operand. Use new local variable
164 'flags' in place of 'operand->flags'.
166 2014-08-14 Mike Frysinger <vapier@gentoo.org>
168 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
169 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
170 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
171 Change assignment of 1 to priv->comment to TRUE.
172 (print_insn_bfin): Change legal to a bfd_boolean. Change
173 assignment of 0/1 with priv comment and parallel and legal
176 2014-08-14 Mike Frysinger <vapier@gentoo.org>
178 * bfin-dis.c (OUT): Define.
179 (decode_CC2stat_0): Declare new op_names array.
180 Replace multiple if statements with a single one.
182 2014-08-14 Mike Frysinger <vapier@gentoo.org>
184 * bfin-dis.c (struct private): Add iw0.
185 (_print_insn_bfin): Assign iw0 to priv.iw0.
186 (print_insn_bfin): Drop ifetch and use priv.iw0.
188 2014-08-13 Mike Frysinger <vapier@gentoo.org>
190 * bfin-dis.c (comment, parallel): Move from global scope ...
191 (struct private): ... to this new struct.
192 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
193 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
194 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
195 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
196 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
197 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
198 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
199 print_insn_bfin): Declare private struct. Use priv's comment and
202 2014-08-13 Mike Frysinger <vapier@gentoo.org>
204 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
205 (_print_insn_bfin): Add check for unaligned pc.
207 2014-08-13 Mike Frysinger <vapier@gentoo.org>
209 * bfin-dis.c (ifetch): New function.
210 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
213 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
215 * micromips-opc.c (COD): Rename throughout to...
216 (CM): New define, update to use INSN_COPROC_MOVE.
217 (LCD): Rename throughout to...
218 (LC): New define, update to use INSN_LOAD_COPROC.
219 * mips-opc.c: Likewise.
221 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
223 * micromips-opc.c (COD, LCD) New macros.
224 (cfc1, ctc1): Remove FP_S attribute.
225 (dmfc1, mfc1, mfhc1): Add LCD attribute.
226 (dmtc1, mtc1, mthc1): Add COD attribute.
227 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
229 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
230 Alexander Ivchenko <alexander.ivchenko@intel.com>
231 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
232 Sergey Lega <sergey.s.lega@intel.com>
233 Anna Tikhonova <anna.tikhonova@intel.com>
234 Ilya Tocar <ilya.tocar@intel.com>
235 Andrey Turetskiy <andrey.turetskiy@intel.com>
236 Ilya Verbin <ilya.verbin@intel.com>
237 Kirill Yukhin <kirill.yukhin@intel.com>
238 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
240 * i386-dis-evex.h: Updated.
241 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
242 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
243 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
244 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
246 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
247 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
248 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
249 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
250 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
251 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
252 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
253 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
254 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
255 (prefix_table): Add entries for new instructions.
256 (vex_len_table): Ditto.
257 (vex_w_table): Ditto.
258 (OP_E_memory): Update xmmq_mode handling.
259 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
260 (cpu_flags): Add CpuAVX512DQ.
261 * i386-init.h: Regenerared.
262 * i386-opc.h (CpuAVX512DQ): New.
263 (i386_cpu_flags): Add cpuavx512dq.
264 * i386-opc.tbl: Add AVX512DQ instructions.
265 * i386-tbl.h: Regenerate.
267 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
268 Alexander Ivchenko <alexander.ivchenko@intel.com>
269 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
270 Sergey Lega <sergey.s.lega@intel.com>
271 Anna Tikhonova <anna.tikhonova@intel.com>
272 Ilya Tocar <ilya.tocar@intel.com>
273 Andrey Turetskiy <andrey.turetskiy@intel.com>
274 Ilya Verbin <ilya.verbin@intel.com>
275 Kirill Yukhin <kirill.yukhin@intel.com>
276 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
278 * i386-dis-evex.h: Add new instructions (prefixes bellow).
279 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
280 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
281 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
282 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
283 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
284 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
285 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
286 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
287 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
288 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
289 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
290 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
291 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
292 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
293 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
294 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
295 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
296 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
297 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
298 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
299 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
300 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
301 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
302 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
303 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
304 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
305 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
306 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
307 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
308 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
309 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
310 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
311 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
312 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
313 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
314 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
315 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
316 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
317 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
318 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
319 (prefix_table): Add entries for new instructions.
321 (vex_len_table): Ditto.
322 (vex_w_table): Ditto.
323 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
324 mask_bd_mode handling.
325 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
327 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
329 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
330 (OP_EX): Add dqw_swap_mode handling.
331 (OP_VEX): Add mask_bd_mode handling.
332 (OP_Mask): Add mask_bd_mode handling.
333 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
334 (cpu_flags): Add CpuAVX512BW.
335 * i386-init.h: Regenerated.
336 * i386-opc.h (CpuAVX512BW): New.
337 (i386_cpu_flags): Add cpuavx512bw.
338 * i386-opc.tbl: Add AVX512BW instructions.
339 * i386-tbl.h: Regenerate.
341 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
342 Alexander Ivchenko <alexander.ivchenko@intel.com>
343 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
344 Sergey Lega <sergey.s.lega@intel.com>
345 Anna Tikhonova <anna.tikhonova@intel.com>
346 Ilya Tocar <ilya.tocar@intel.com>
347 Andrey Turetskiy <andrey.turetskiy@intel.com>
348 Ilya Verbin <ilya.verbin@intel.com>
349 Kirill Yukhin <kirill.yukhin@intel.com>
350 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
352 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
353 * i386-tbl.h: Regenerate.
355 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
356 Alexander Ivchenko <alexander.ivchenko@intel.com>
357 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
358 Sergey Lega <sergey.s.lega@intel.com>
359 Anna Tikhonova <anna.tikhonova@intel.com>
360 Ilya Tocar <ilya.tocar@intel.com>
361 Andrey Turetskiy <andrey.turetskiy@intel.com>
362 Ilya Verbin <ilya.verbin@intel.com>
363 Kirill Yukhin <kirill.yukhin@intel.com>
364 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
366 * i386-dis.c (intel_operand_size): Support 128/256 length in
367 vex_vsib_q_w_dq_mode.
368 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
369 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
370 (cpu_flags): Add CpuAVX512VL.
371 * i386-init.h: Regenerated.
372 * i386-opc.h (CpuAVX512VL): New.
373 (i386_cpu_flags): Add cpuavx512vl.
374 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
375 * i386-opc.tbl: Add AVX512VL instructions.
376 * i386-tbl.h: Regenerate.
378 2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
380 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
381 * or1k-opinst.c: Regenerate.
383 2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
385 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
386 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
388 2014-07-04 Alan Modra <amodra@gmail.com>
390 * configure.ac: Rename from configure.in.
391 * Makefile.in: Regenerate.
392 * config.in: Regenerate.
394 2014-07-04 Alan Modra <amodra@gmail.com>
396 * configure.in: Include bfd/version.m4.
397 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
398 (BFD_VERSION): Delete.
399 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
400 * configure: Regenerate.
401 * Makefile.in: Regenerate.
403 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
404 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
405 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
406 Soundararajan <Sounderarajan.D@atmel.com>
408 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
409 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
410 machine is not avrtiny.
412 2014-06-26 Philippe De Muyter <phdm@macqel.be>
414 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
417 2014-06-12 Alan Modra <amodra@gmail.com>
419 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
420 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
422 2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
424 * i386-dis.c (fwait_prefix): New.
425 (ckprefix): Set fwait_prefix.
426 (print_insn): Properly print prefixes before fwait.
428 2014-06-07 Alan Modra <amodra@gmail.com>
430 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
432 2014-06-05 Joel Brobecker <brobecker@adacore.com>
434 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
435 bfd's development.sh.
436 * Makefile.in, configure: Regenerate.
438 2014-06-03 Nick Clifton <nickc@redhat.com>
440 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
441 decide when extended addressing is being used.
443 2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
445 * sparc-opc.c (cas): Disable for LEON.
448 2014-05-20 Alan Modra <amodra@gmail.com>
450 * m68k-dis.c: Don't include setjmp.h.
452 2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
454 * i386-dis.c (ADDR16_PREFIX): Removed.
455 (ADDR32_PREFIX): Likewise.
456 (DATA16_PREFIX): Likewise.
457 (DATA32_PREFIX): Likewise.
458 (prefix_name): Updated.
459 (print_insn): Simplify data and address size prefixes processing.
461 2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
463 * or1k-desc.c: Regenerated.
464 * or1k-desc.h: Likewise.
465 * or1k-opc.c: Likewise.
466 * or1k-opc.h: Likewise.
467 * or1k-opinst.c: Likewise.
469 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
471 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
476 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
478 (parse_mips_dis_option): Update MSA and virtualization support to
479 allow mips64r3 and mips64r5.
481 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
483 * mips-opc.c (G3): Remove I4.
485 2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
488 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
489 (end_codep): Likewise.
490 (mandatory_prefix): Likewise.
491 (active_seg_prefix): Likewise.
492 (ckprefix): Set active_seg_prefix to the active segment register
494 (seg_prefix): Removed.
495 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
496 for prefix index. Ignore the index if it is invalid and the
497 mandatory prefix isn't required.
498 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
499 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
500 in used_prefixes here. Don't print unused prefixes. Check
501 active_seg_prefix for the active segment register prefix.
502 Restore the DFLAG bit in sizeflag if the data size prefix is
503 unused. Check the unused mandatory PREFIX_XXX prefixes
504 (append_seg): Only print the segment register which gets used.
505 (OP_E_memory): Check active_seg_prefix for the segment register
508 (OP_OFF64): Likewise.
509 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
511 2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
514 * config.in: Regenerated.
515 * configure: Likewise.
516 * configure.in: Check if sigsetjmp is available.
517 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
518 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
519 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
520 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
521 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
522 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
523 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
524 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
525 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
526 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
527 (OPCODES_SIGSETJMP): Likewise.
528 (OPCODES_SIGLONGJMP): Likewise.
529 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
530 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
531 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
532 * xtensa-dis.c (dis_private): Replace jmp_buf with
534 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
535 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
536 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
537 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
538 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
540 2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
543 * i386-dis.c (print_insn): Handle prefixes before fwait.
545 2014-04-26 Alan Modra <amodra@gmail.com>
547 * po/POTFILES.in: Regenerate.
549 2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
551 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
552 to allow the MIPS XPA ASE.
553 (parse_mips_dis_option): Process the -Mxpa option.
554 * mips-opc.c (XPA): New define.
555 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
556 locations of the ctc0 and cfc0 instructions.
558 2014-04-22 Christian Svensson <blue@cmd.nu>
560 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
561 * configure.in: Likewise.
562 * disassemble.c: Likewise.
563 * or1k-asm.c: New file.
564 * or1k-desc.c: New file.
565 * or1k-desc.h: New file.
566 * or1k-dis.c: New file.
567 * or1k-ibld.c: New file.
568 * or1k-opc.c: New file.
569 * or1k-opc.h: New file.
570 * or1k-opinst.c: New file.
571 * Makefile.in: Regenerate.
572 * configure: Regenerate.
573 * openrisc-asm.c: Delete.
574 * openrisc-desc.c: Delete.
575 * openrisc-desc.h: Delete.
576 * openrisc-dis.c: Delete.
577 * openrisc-ibld.c: Delete.
578 * openrisc-opc.c: Delete.
579 * openrisc-opc.h: Delete.
580 * or32-dis.c: Delete.
581 * or32-opc.c: Delete.
583 2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
585 * i386-dis.c (rm_table): Add encls, enclu.
586 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
587 (cpu_flags): Add CpuSE1.
588 * i386-opc.h (enum): Add CpuSE1.
589 (i386_cpu_flags): Add cpuse1.
590 * i386-opc.tbl: Add encls, enclu.
591 * i386-init.h: Regenerated.
592 * i386-tbl.h: Likewise.
594 2014-04-02 Anthony Green <green@moxielogic.com>
596 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
597 instructions, sex.b and sex.s.
599 2014-03-26 Jiong Wang <jiong.wang@arm.com>
601 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
604 2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
606 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
607 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
609 * i386-tbl.h: Regenerate.
611 2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
613 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
614 %hstick_enable added.
616 2014-03-19 Nick Clifton <nickc@redhat.com>
618 * rx-decode.opc (bwl): Allow for bogus instructions with a size
620 (sbwl, ubwl, SCALE): Likewise.
621 * rx-decode.c: Regenerate.
623 2014-03-12 Alan Modra <amodra@gmail.com>
625 * Makefile.in: Regenerate.
627 2014-03-05 Alan Modra <amodra@gmail.com>
629 Update copyright years.
631 2014-03-04 Heiher <r@hev.cc>
633 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
635 2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
637 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
638 so that they come after the Loongson extensions.
640 2014-03-03 Alan Modra <amodra@gmail.com>
642 * i386-gen.c (process_copyright): Emit copyright notice on one line.
644 2014-02-28 Alan Modra <amodra@gmail.com>
646 * msp430-decode.c: Regenerate.
648 2014-02-27 Jiong Wang <jiong.wang@arm.com>
650 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
651 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
653 2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
655 * aarch64-opc.c (print_register_offset_address): Call
656 get_int_reg_name to prepare the register name.
658 2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
660 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
661 * i386-tbl.h: Regenerate.
663 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
665 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
666 (cpu_flags): Add CpuPREFETCHWT1.
667 * i386-init.h: Regenerate.
668 * i386-opc.h (CpuPREFETCHWT1): New.
669 (i386_cpu_flags): Add cpuprefetchwt1.
670 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
671 * i386-tbl.h: Regenerate.
673 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
675 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
677 * i386-tbl.h: Regenerate.
679 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
681 * i386-gen.c (output_cpu_flags): Don't output trailing space.
682 (output_opcode_modifier): Likewise.
683 (output_operand_type): Likewise.
684 * i386-init.h: Regenerated.
685 * i386-tbl.h: Likewise.
687 2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
689 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
691 (PREFIX enum): Add PREFIX_0FAE_REG_7.
692 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
693 (prefix_table): Add clflusopt.
694 (mod_table): Add xrstors, xsavec, xsaves.
695 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
696 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
697 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
698 * i386-init.h: Regenerate.
699 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
700 xsaves64, xsavec, xsavec64.
701 * i386-tbl.h: Regenerate.
703 2014-02-10 Alan Modra <amodra@gmail.com>
705 * po/POTFILES.in: Regenerate.
706 * po/opcodes.pot: Regenerate.
708 2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
709 Jan Beulich <jbeulich@suse.com>
712 * i386-dis.c (OP_E_memory): Fix shift computation for
713 vex_vsib_q_w_dq_mode.
715 2014-01-09 Bradley Nelson <bradnelson@google.com>
716 Roland McGrath <mcgrathr@google.com>
718 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
719 last_rex_prefix is -1.
721 2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
723 * i386-gen.c (process_copyright): Update copyright year to 2014.
725 2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
727 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
729 For older changes see ChangeLog-2013
731 Copyright (C) 2014 Free Software Foundation, Inc.
733 Copying and distribution of this file, with or without modification,
734 are permitted in any medium without royalty provided the copyright
735 notice and this notice are preserved.
741 version-control: never