1 2017-07-04 Tristan Gingold <gingold@adacore.com>
3 * configure: Regenerate.
5 2017-07-03 Tristan Gingold <gingold@adacore.com>
7 * po/opcodes.pot: Regenerate.
9 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
11 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
12 entries to the MSA ASE instruction block.
14 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
15 Maciej W. Rozycki <macro@imgtec.com>
17 * micromips-opc.c (XPA, XPAVZ): New macros.
18 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
21 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
22 Maciej W. Rozycki <macro@imgtec.com>
24 * micromips-opc.c (I36): New macro.
25 (micromips_opcodes): Add "eretnc".
27 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
28 Andrew Bennett <andrew.bennett@imgtec.com>
30 * mips-dis.c (mips_calculate_combination_ases): Handle the
32 (parse_mips_ase_option): New function.
33 (parse_mips_dis_option): Factor out ASE option handling to the
34 new function. Call `mips_calculate_combination_ases'.
35 * mips-opc.c (XPAVZ): New macro.
36 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
37 "mfhgc0", "mthc0" and "mthgc0".
39 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
41 * mips-dis.c (mips_calculate_combination_ases): New function.
42 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
43 calculation to the new function.
44 (set_default_mips_dis_options): Call the new function.
46 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
48 * arc-dis.c (parse_disassembler_options): Use
49 FOR_EACH_DISASSEMBLER_OPTION.
51 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
53 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
54 disassembler option strings.
55 (parse_cpu_option): Likewise.
57 2017-06-28 Tamar Christina <tamar.christina@arm.com>
59 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
60 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
61 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
62 (aarch64_feature_dotprod, DOT_INSN): New.
64 * aarch64-dis-2.c: Regenerated.
66 2017-06-28 Jiong Wang <jiong.wang@arm.com>
68 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
70 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
71 Matthew Fortune <matthew.fortune@imgtec.com>
72 Andrew Bennett <andrew.bennett@imgtec.com>
74 * mips-formats.h (INT_BIAS): New macro.
75 (INT_ADJ): Redefine in INT_BIAS terms.
76 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
77 (mips_print_save_restore): New function.
78 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
79 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
81 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
82 (print_mips16_insn_arg): Call `mips_print_save_restore' for
83 OP_SAVE_RESTORE_LIST handling, factored out from here.
84 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
85 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
86 (mips_builtin_opcodes): Add "restore" and "save" entries.
87 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
89 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
91 2017-06-23 Andrew Waterman <andrew@sifive.com>
93 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
94 alias; do not mark SLTI instruction as an alias.
96 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
98 * i386-dis.c (RM_0FAE_REG_5): Removed.
99 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
100 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
101 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
102 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
103 PREFIX_MOD_3_0F01_REG_5_RM_0.
104 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
105 PREFIX_MOD_3_0FAE_REG_5.
106 (mod_table): Update MOD_0FAE_REG_5.
107 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
108 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
109 * i386-tbl.h: Regenerated.
111 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
113 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
114 * i386-opc.tbl: Likewise.
115 * i386-tbl.h: Regenerated.
117 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
119 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
121 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
124 2017-06-19 Nick Clifton <nickc@redhat.com>
127 * score-dis.c (score_opcodes): Add sentinel.
129 2017-06-16 Alan Modra <amodra@gmail.com>
131 * rx-decode.c: Regenerate.
133 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
136 * i386-dis.c (OP_E_register): Check valid bnd register.
139 2017-06-15 Nick Clifton <nickc@redhat.com>
142 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
145 2017-06-15 Nick Clifton <nickc@redhat.com>
148 * rl78-decode.opc (OP_BUF_LEN): Define.
149 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
150 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
152 * rl78-decode.c: Regenerate.
154 2017-06-15 Nick Clifton <nickc@redhat.com>
157 * bfin-dis.c (gregs): Clip index to prevent overflow.
162 2017-06-14 Nick Clifton <nickc@redhat.com>
165 * score7-dis.c (score_opcodes): Add sentinel.
167 2017-06-14 Yao Qi <yao.qi@linaro.org>
169 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
170 * arm-dis.c: Likewise.
171 * ia64-dis.c: Likewise.
172 * mips-dis.c: Likewise.
173 * spu-dis.c: Likewise.
174 * disassemble.h (print_insn_aarch64): New declaration, moved from
176 (print_insn_big_arm, print_insn_big_mips): Likewise.
177 (print_insn_i386, print_insn_ia64): Likewise.
178 (print_insn_little_arm, print_insn_little_mips): Likewise.
180 2017-06-14 Nick Clifton <nickc@redhat.com>
183 * rx-decode.opc: Include libiberty.h
184 (GET_SCALE): New macro - validates access to SCALE array.
185 (GET_PSCALE): New macro - validates access to PSCALE array.
186 (DIs, SIs, S2Is, rx_disp): Use new macros.
187 * rx-decode.c: Regenerate.
189 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
191 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
193 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
195 * arc-dis.c (enforced_isa_mask): Declare.
196 (cpu_types): Likewise.
197 (parse_cpu_option): New function.
198 (parse_disassembler_options): Use it.
199 (print_insn_arc): Use enforced_isa_mask.
200 (print_arc_disassembler_options): Document new options.
202 2017-05-24 Yao Qi <yao.qi@linaro.org>
204 * alpha-dis.c: Include disassemble.h, don't include
206 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
207 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
208 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
209 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
210 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
211 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
212 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
213 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
214 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
215 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
216 * moxie-dis.c, msp430-dis.c, mt-dis.c:
217 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
218 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
219 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
220 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
221 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
222 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
223 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
224 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
225 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
226 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
227 * z80-dis.c, z8k-dis.c: Likewise.
228 * disassemble.h: New file.
230 2017-05-24 Yao Qi <yao.qi@linaro.org>
232 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
233 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
235 2017-05-24 Yao Qi <yao.qi@linaro.org>
237 * disassemble.c (disassembler): Add arguments a, big and mach.
240 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
242 * i386-dis.c (NOTRACK_Fixup): New.
244 (NOTRACK_PREFIX): Likewise.
245 (last_active_prefix): Likewise.
246 (reg_table): Use NOTRACK on indirect call and jmp.
247 (ckprefix): Set last_active_prefix.
248 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
249 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
250 * i386-opc.h (NoTrackPrefixOk): New.
251 (i386_opcode_modifier): Add notrackprefixok.
252 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
254 * i386-tbl.h: Regenerated.
256 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
258 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
260 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
262 (print_insn_sparc): Handle new operand types.
263 * sparc-opc.c (MASK_M8): Define.
265 (v6notlet): Likewise.
276 (v9andleon): Likewise.
279 (HWS2_VM8): Likewise.
280 (sparc_opcode_archs): Add entry for "m8".
281 (sparc_opcodes): Add OSA2017 and M8 instructions
282 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
284 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
285 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
286 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
287 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
288 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
289 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
290 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
291 ASI_CORE_SELECT_COMMIT_NHT.
293 2017-05-18 Alan Modra <amodra@gmail.com>
295 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
296 * aarch64-dis.c: Likewise.
297 * aarch64-gen.c: Likewise.
298 * aarch64-opc.c: Likewise.
300 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
301 Matthew Fortune <matthew.fortune@imgtec.com>
303 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
304 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
305 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
306 (print_insn_arg) <OP_REG28>: Add handler.
307 (validate_insn_args) <OP_REG28>: Handle.
308 (print_mips16_insn_arg): Handle MIPS16 instructions that require
309 32-bit encoding and 9-bit immediates.
310 (print_insn_mips16): Handle MIPS16 instructions that require
311 32-bit encoding and MFC0/MTC0 operand decoding.
312 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
313 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
314 (RD_C0, WR_C0, E2, E2MT): New macros.
315 (mips16_opcodes): Add entries for MIPS16e2 instructions:
316 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
317 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
318 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
319 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
320 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
321 instructions, "swl", "swr", "sync" and its "sync_acquire",
322 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
323 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
324 regular/extended entries for original MIPS16 ISA revision
325 instructions whose extended forms are subdecoded in the MIPS16e2
326 ISA revision: "li", "sll" and "srl".
328 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
330 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
331 reference in CP0 move operand decoding.
333 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
335 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
337 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
339 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
341 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
342 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
343 "sync_rmb" and "sync_wmb" as aliases.
344 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
345 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
347 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
349 * arc-dis.c (parse_option): Update quarkse_em option..
350 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
352 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
354 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
356 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
358 2017-05-01 Michael Clark <michaeljclark@mac.com>
360 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
363 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
365 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
366 and branches and not synthetic data instructions.
368 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
370 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
372 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
374 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
375 * arc-opc.c (insert_r13el): New function.
377 * arc-tbl.h: Add new enter/leave variants.
379 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
381 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
383 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
385 * mips-dis.c (print_mips_disassembler_options): Add
388 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
390 * mips16-opc.c (AL): New macro.
391 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
392 of "ld" and "lw" as aliases.
394 2017-04-24 Tamar Christina <tamar.christina@arm.com>
396 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
399 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
400 Alan Modra <amodra@gmail.com>
402 * ppc-opc.c (ELEV): Define.
403 (vle_opcodes): Add se_rfgi and e_sc.
404 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
407 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
409 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
411 2017-04-21 Nick Clifton <nickc@redhat.com>
414 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
417 2017-04-13 Alan Modra <amodra@gmail.com>
419 * epiphany-desc.c: Regenerate.
420 * fr30-desc.c: Regenerate.
421 * frv-desc.c: Regenerate.
422 * ip2k-desc.c: Regenerate.
423 * iq2000-desc.c: Regenerate.
424 * lm32-desc.c: Regenerate.
425 * m32c-desc.c: Regenerate.
426 * m32r-desc.c: Regenerate.
427 * mep-desc.c: Regenerate.
428 * mt-desc.c: Regenerate.
429 * or1k-desc.c: Regenerate.
430 * xc16x-desc.c: Regenerate.
431 * xstormy16-desc.c: Regenerate.
433 2017-04-11 Alan Modra <amodra@gmail.com>
435 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
436 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
437 PPC_OPCODE_TMR for e6500.
438 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
439 (PPCVEC3): Define as PPC_OPCODE_POWER9.
440 (PPCVSX2): Define as PPC_OPCODE_POWER8.
441 (PPCVSX3): Define as PPC_OPCODE_POWER9.
442 (PPCHTM): Define as PPC_OPCODE_POWER8.
443 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
445 2017-04-10 Alan Modra <amodra@gmail.com>
447 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
448 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
449 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
450 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
452 2017-04-09 Pip Cet <pipcet@gmail.com>
454 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
455 appropriate floating-point precision directly.
457 2017-04-07 Alan Modra <amodra@gmail.com>
459 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
460 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
461 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
462 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
463 vector instructions with E6500 not PPCVEC2.
465 2017-04-06 Pip Cet <pipcet@gmail.com>
467 * Makefile.am: Add wasm32-dis.c.
468 * configure.ac: Add wasm32-dis.c to wasm32 target.
469 * disassemble.c: Add wasm32 disassembler code.
470 * wasm32-dis.c: New file.
471 * Makefile.in: Regenerate.
472 * configure: Regenerate.
473 * po/POTFILES.in: Regenerate.
474 * po/opcodes.pot: Regenerate.
476 2017-04-05 Pedro Alves <palves@redhat.com>
478 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
479 * arm-dis.c (parse_arm_disassembler_options): Constify.
480 * ppc-dis.c (powerpc_init_dialect): Constify local.
481 * vax-dis.c (parse_disassembler_options): Constify.
483 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
485 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
488 2017-03-30 Pip Cet <pipcet@gmail.com>
490 * configure.ac: Add (empty) bfd_wasm32_arch target.
491 * configure: Regenerate
492 * po/opcodes.pot: Regenerate.
494 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
496 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
498 * opcodes/sparc-opc.c (asi_table): New ASIs.
500 2017-03-29 Alan Modra <amodra@gmail.com>
502 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
504 (lookup_powerpc): Don't special case -1 dialect. Handle
506 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
507 lookup_powerpc call, pass it on second.
509 2017-03-27 Alan Modra <amodra@gmail.com>
512 * ppc-dis.c (struct ppc_mopt): Comment.
513 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
515 2017-03-27 Rinat Zelig <rinat@mellanox.com>
517 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
518 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
519 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
520 (insert_nps_misc_imm_offset): New function.
521 (extract_nps_misc imm_offset): New function.
522 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
523 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
525 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
527 * s390-mkopc.c (main): Remove vx2 check.
528 * s390-opc.txt: Remove vx2 instruction flags.
530 2017-03-21 Rinat Zelig <rinat@mellanox.com>
532 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
533 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
534 (insert_nps_imm_offset): New function.
535 (extract_nps_imm_offset): New function.
536 (insert_nps_imm_entry): New function.
537 (extract_nps_imm_entry): New function.
539 2017-03-17 Alan Modra <amodra@gmail.com>
542 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
543 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
544 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
546 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
548 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
552 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
554 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
556 2017-03-13 Andrew Waterman <andrew@sifive.com>
558 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
563 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
565 * i386-gen.c (opcode_modifiers): Replace S with Load.
566 * i386-opc.h (S): Removed.
568 (i386_opcode_modifier): Replace s with load.
569 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
570 and {evex}. Replace S with Load.
571 * i386-tbl.h: Regenerated.
573 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
575 * i386-opc.tbl: Use CpuCET on rdsspq.
576 * i386-tbl.h: Regenerated.
578 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
580 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
581 <vsx>: Do not use PPC_OPCODE_VSX3;
583 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
585 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
587 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
589 * i386-dis.c (REG_0F1E_MOD_3): New enum.
590 (MOD_0F1E_PREFIX_1): Likewise.
591 (MOD_0F38F5_PREFIX_2): Likewise.
592 (MOD_0F38F6_PREFIX_0): Likewise.
593 (RM_0F1E_MOD_3_REG_7): Likewise.
594 (PREFIX_MOD_0_0F01_REG_5): Likewise.
595 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
596 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
597 (PREFIX_0F1E): Likewise.
598 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
599 (PREFIX_0F38F5): Likewise.
600 (dis386_twobyte): Use PREFIX_0F1E.
601 (reg_table): Add REG_0F1E_MOD_3.
602 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
603 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
604 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
605 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
606 (three_byte_table): Use PREFIX_0F38F5.
607 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
608 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
609 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
610 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
611 PREFIX_MOD_3_0F01_REG_5_RM_2.
612 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
613 (cpu_flags): Add CpuCET.
614 * i386-opc.h (CpuCET): New enum.
615 (CpuUnused): Commented out.
616 (i386_cpu_flags): Add cpucet.
617 * i386-opc.tbl: Add Intel CET instructions.
618 * i386-init.h: Regenerated.
619 * i386-tbl.h: Likewise.
621 2017-03-06 Alan Modra <amodra@gmail.com>
624 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
625 (extract_raq, extract_ras, extract_rbx): New functions.
626 (powerpc_operands): Use opposite corresponding insert function.
628 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
629 register restriction.
631 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
633 * disassemble.c Include "safe-ctype.h".
634 (disassemble_init_for_target): Handle s390 init.
635 (remove_whitespace_and_extra_commas): New function.
636 (disassembler_options_cmp): Likewise.
637 * arm-dis.c: Include "libiberty.h".
639 (regnames): Use long disassembler style names.
640 Add force-thumb and no-force-thumb options.
641 (NUM_ARM_REGNAMES): Rename from this...
642 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
643 (get_arm_regname_num_options): Delete.
644 (set_arm_regname_option): Likewise.
645 (get_arm_regnames): Likewise.
646 (parse_disassembler_options): Likewise.
647 (parse_arm_disassembler_option): Rename from this...
648 (parse_arm_disassembler_options): ...to this. Make static.
649 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
650 (print_insn): Use parse_arm_disassembler_options.
651 (disassembler_options_arm): New function.
652 (print_arm_disassembler_options): Handle updated regnames.
653 * ppc-dis.c: Include "libiberty.h".
654 (ppc_opts): Add "32" and "64" entries.
655 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
656 (powerpc_init_dialect): Add break to switch statement.
657 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
658 (disassembler_options_powerpc): New function.
659 (print_ppc_disassembler_options): Use ARRAY_SIZE.
660 Remove printing of "32" and "64".
661 * s390-dis.c: Include "libiberty.h".
662 (init_flag): Remove unneeded variable.
663 (struct s390_options_t): New structure type.
664 (options): New structure.
665 (init_disasm): Rename from this...
666 (disassemble_init_s390): ...to this. Add initializations for
667 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
668 (print_insn_s390): Delete call to init_disasm.
669 (disassembler_options_s390): New function.
670 (print_s390_disassembler_options): Print using information from
672 * po/opcodes.pot: Regenerate.
674 2017-02-28 Jan Beulich <jbeulich@suse.com>
676 * i386-dis.c (PCMPESTR_Fixup): New.
677 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
678 (prefix_table): Use PCMPESTR_Fixup.
679 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
681 (vex_w_table): Delete VPCMPESTR{I,M} entries.
682 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
683 Split 64-bit and non-64-bit variants.
684 * opcodes/i386-tbl.h: Re-generate.
686 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
688 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
689 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
690 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
691 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
692 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
693 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
694 (OP_SVE_V_HSD): New macros.
695 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
696 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
697 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
698 (aarch64_opcode_table): Add new SVE instructions.
699 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
700 for rotation operands. Add new SVE operands.
701 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
702 (ins_sve_quad_index): Likewise.
703 (ins_imm_rotate): Split into...
704 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
705 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
706 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
708 (aarch64_ins_sve_addr_ri_s4): New function.
709 (aarch64_ins_sve_quad_index): Likewise.
710 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
711 * aarch64-asm-2.c: Regenerate.
712 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
713 (ext_sve_quad_index): Likewise.
714 (ext_imm_rotate): Split into...
715 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
716 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
717 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
719 (aarch64_ext_sve_addr_ri_s4): New function.
720 (aarch64_ext_sve_quad_index): Likewise.
721 (aarch64_ext_sve_index): Allow quad indices.
722 (do_misc_decoding): Likewise.
723 * aarch64-dis-2.c: Regenerate.
724 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
726 (OPD_F_OD_MASK): Widen by one bit.
727 (OPD_F_NO_ZR): Bump accordingly.
728 (get_operand_field_width): New function.
729 * aarch64-opc.c (fields): Add new SVE fields.
730 (operand_general_constraint_met_p): Handle new SVE operands.
731 (aarch64_print_operand): Likewise.
732 * aarch64-opc-2.c: Regenerate.
734 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
736 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
737 (aarch64_feature_compnum): ...this.
738 (SIMD_V8_3): Replace with...
740 (CNUM_INSN): New macro.
741 (aarch64_opcode_table): Use it for the complex number instructions.
743 2017-02-24 Jan Beulich <jbeulich@suse.com>
745 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
747 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
749 Add support for associating SPARC ASIs with an architecture level.
750 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
751 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
752 decoding of SPARC ASIs.
754 2017-02-23 Jan Beulich <jbeulich@suse.com>
756 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
757 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
759 2017-02-21 Jan Beulich <jbeulich@suse.com>
761 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
762 1 (instead of to itself). Correct typo.
764 2017-02-14 Andrew Waterman <andrew@sifive.com>
766 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
769 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
771 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
772 (aarch64_sys_reg_supported_p): Handle them.
774 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
776 * arc-opc.c (UIMM6_20R): Define.
777 (SIMM12_20): Use above.
778 (SIMM12_20R): Define.
779 (SIMM3_5_S): Use above.
780 (UIMM7_A32_11R_S): Define.
781 (UIMM7_9_S): Use above.
782 (UIMM3_13R_S): Define.
783 (SIMM11_A32_7_S): Use above.
785 (UIMM10_A32_8_S): Use above.
786 (UIMM8_8R_S): Define.
788 (arc_relax_opcodes): Use all above defines.
790 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
792 * arc-regs.h: Distinguish some of the registers different on
793 ARC700 and HS38 cpus.
795 2017-02-14 Alan Modra <amodra@gmail.com>
798 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
799 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
801 2017-02-11 Stafford Horne <shorne@gmail.com>
802 Alan Modra <amodra@gmail.com>
804 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
805 Use insn_bytes_value and insn_int_value directly instead. Don't
806 free allocated memory until function exit.
808 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
810 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
812 2017-02-03 Nick Clifton <nickc@redhat.com>
815 * aarch64-opc.c (print_register_list): Ensure that the register
816 list index will fir into the tb buffer.
817 (print_register_offset_address): Likewise.
818 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
820 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
823 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
824 instructions when the previous fetch packet ends with a 32-bit
827 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
829 * pru-opc.c: Remove vague reference to a future GDB port.
831 2017-01-20 Nick Clifton <nickc@redhat.com>
833 * po/ga.po: Updated Irish translation.
835 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
837 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
839 2017-01-13 Yao Qi <yao.qi@linaro.org>
841 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
842 if FETCH_DATA returns 0.
843 (m68k_scan_mask): Likewise.
844 (print_insn_m68k): Update code to handle -1 return value.
846 2017-01-13 Yao Qi <yao.qi@linaro.org>
848 * m68k-dis.c (enum print_insn_arg_error): New.
849 (NEXTBYTE): Replace -3 with
850 PRINT_INSN_ARG_MEMORY_ERROR.
851 (NEXTULONG): Likewise.
852 (NEXTSINGLE): Likewise.
853 (NEXTDOUBLE): Likewise.
854 (NEXTDOUBLE): Likewise.
855 (NEXTPACKED): Likewise.
856 (FETCH_ARG): Likewise.
857 (FETCH_DATA): Update comments.
858 (print_insn_arg): Update comments. Replace magic numbers with
860 (match_insn_m68k): Likewise.
862 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
864 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
865 * i386-dis-evex.h (evex_table): Updated.
866 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
867 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
868 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
869 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
870 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
871 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
872 * i386-init.h: Regenerate.
875 2017-01-12 Yao Qi <yao.qi@linaro.org>
877 * msp430-dis.c (msp430_singleoperand): Return -1 if
878 msp430dis_opcode_signed returns false.
879 (msp430_doubleoperand): Likewise.
880 (msp430_branchinstr): Return -1 if
881 msp430dis_opcode_unsigned returns false.
882 (msp430x_calla_instr): Likewise.
883 (print_insn_msp430): Likewise.
885 2017-01-05 Nick Clifton <nickc@redhat.com>
888 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
889 could not be matched.
890 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
893 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
895 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
896 (aarch64_opcode_table): Use RCPC_INSN.
898 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
900 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
902 * riscv-opcodes/all-opcodes: Likewise.
904 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
906 * riscv-dis.c (print_insn_args): Add fall through comment.
908 2017-01-03 Nick Clifton <nickc@redhat.com>
910 * po/sr.po: New Serbian translation.
911 * configure.ac (ALL_LINGUAS): Add sr.
912 * configure: Regenerate.
914 2017-01-02 Alan Modra <amodra@gmail.com>
916 * epiphany-desc.h: Regenerate.
917 * epiphany-opc.h: Regenerate.
918 * fr30-desc.h: Regenerate.
919 * fr30-opc.h: Regenerate.
920 * frv-desc.h: Regenerate.
921 * frv-opc.h: Regenerate.
922 * ip2k-desc.h: Regenerate.
923 * ip2k-opc.h: Regenerate.
924 * iq2000-desc.h: Regenerate.
925 * iq2000-opc.h: Regenerate.
926 * lm32-desc.h: Regenerate.
927 * lm32-opc.h: Regenerate.
928 * m32c-desc.h: Regenerate.
929 * m32c-opc.h: Regenerate.
930 * m32r-desc.h: Regenerate.
931 * m32r-opc.h: Regenerate.
932 * mep-desc.h: Regenerate.
933 * mep-opc.h: Regenerate.
934 * mt-desc.h: Regenerate.
935 * mt-opc.h: Regenerate.
936 * or1k-desc.h: Regenerate.
937 * or1k-opc.h: Regenerate.
938 * xc16x-desc.h: Regenerate.
939 * xc16x-opc.h: Regenerate.
940 * xstormy16-desc.h: Regenerate.
941 * xstormy16-opc.h: Regenerate.
943 2017-01-02 Alan Modra <amodra@gmail.com>
945 Update year range in copyright notice of all files.
947 For older changes see ChangeLog-2016
949 Copyright (C) 2017 Free Software Foundation, Inc.
951 Copying and distribution of this file, with or without modification,
952 are permitted in any medium without royalty provided the copyright
953 notice and this notice are preserved.
959 version-control: never