1 2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
5 2005-01-10 Andreas Schwab <schwab@suse.de>
7 * disassemble.c (disassemble_init_for_target) <case
8 bfd_arch_ia64>: Set skip_zeroes to 16.
9 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
11 2004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
13 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
15 2004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
17 * avr-dis.c: Prettyprint. Added printing of symbol names in all
18 memory references. Convert avr_operand() to C90 formatting.
20 2004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
22 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
24 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
26 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
27 (no_op_insn): Initialize array with instructions that have no
29 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
31 2004-11-29 Richard Earnshaw <rearnsha@arm.com>
33 * arm-dis.c: Correct top-level comment.
35 2004-11-27 Richard Earnshaw <rearnsha@arm.com>
37 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
38 architecuture defining the insn.
39 (arm_opcodes, thumb_opcodes): Delete. Move to ...
40 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
42 Also include opcode/arm.h.
43 * Makefile.am (arm-dis.lo): Update dependency list.
44 * Makefile.in: Regenerate.
46 2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
48 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
49 reflect the change to the short immediate syntax.
51 2004-11-19 Alan Modra <amodra@bigpond.net.au>
53 * or32-opc.c (debug): Warning fix.
54 * po/POTFILES.in: Regenerate.
56 * maxq-dis.c: Formatting.
57 (print_insn): Warning fix.
59 2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
61 * arm-dis.c (WORD_ADDRESS): Define.
62 (print_insn): Use it. Correct big-endian end-of-section handling.
64 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
65 Vineet Sharma <vineets@noida.hcltech.com>
67 * maxq-dis.c: New file.
68 * disassemble.c (ARCH_maxq): Define.
69 (disassembler): Add 'print_insn_maxq_little' for handling maxq
71 * configure.in: Add case for bfd_maxq_arch.
72 * configure: Regenerate.
73 * Makefile.am: Add support for maxq-dis.c
74 * Makefile.in: Regenerate.
75 * aclocal.m4: Regenerate.
77 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
79 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
81 * crx-dis.c: Likewise.
83 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
85 Generally, handle CRISv32.
86 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
87 (struct cris_disasm_data): New type.
88 (format_reg, format_hex, cris_constraint, print_flags)
89 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
91 (format_sup_reg, print_insn_crisv32_with_register_prefix)
92 (print_insn_crisv32_without_register_prefix)
93 (print_insn_crisv10_v32_with_register_prefix)
94 (print_insn_crisv10_v32_without_register_prefix)
95 (cris_parse_disassembler_options): New functions.
96 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
97 parameter. All callers changed.
98 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
100 (cris_constraint) <case 'Y', 'U'>: New cases.
101 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
103 (print_with_operands) <case 'Y'>: New case.
104 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
105 <case 'N', 'Y', 'Q'>: New cases.
106 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
107 (print_insn_cris_with_register_prefix)
108 (print_insn_cris_without_register_prefix): Call
109 cris_parse_disassembler_options.
110 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
111 for CRISv32 and the size of immediate operands. New v32-only
112 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
113 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
114 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
115 Change brp to be v3..v10.
116 (cris_support_regs): New vector.
117 (cris_opcodes): Update head comment. New format characters '[',
118 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
119 Add new opcodes for v32 and adjust existing opcodes to accommodate
120 differences to earlier variants.
121 (cris_cond15s): New vector.
123 2004-11-04 Jan Beulich <jbeulich@novell.com>
125 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
127 (Mp): Use f_mode rather than none at all.
128 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
129 replaces what previously was x_mode; x_mode now means 128-bit SSE
131 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
132 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
133 pinsrw's second operand is Edqw.
134 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
135 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
136 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
137 mode when an operand size override is present or always suffixing.
138 More instructions will need to be added to this group.
139 (putop): Handle new macro chars 'C' (short/long suffix selector),
140 'I' (Intel mode override for following macro char), and 'J' (for
141 adding the 'l' prefix to far branches in AT&T mode). When an
142 alternative was specified in the template, honor macro character when
143 specified for Intel mode.
144 (OP_E): Handle new *_mode values. Correct pointer specifications for
145 memory operands. Consolidate output of index register.
146 (OP_G): Handle new *_mode values.
147 (OP_I): Handle const_1_mode.
148 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
149 respective opcode prefix bits have been consumed.
150 (OP_EM, OP_EX): Provide some default handling for generating pointer
153 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
155 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
158 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
160 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
161 (getregliststring): Support HI/LO and user registers.
162 * crx-opc.c (crx_instruction): Update data structure according to the
163 rearrangement done in CRX opcode header file.
164 (crx_regtab): Likewise.
165 (crx_optab): Likewise.
166 (crx_instruction): Reorder load/stor instructions, remove unsupported
168 support new Co-Processor instruction 'cpi'.
170 2004-10-27 Nick Clifton <nickc@redhat.com>
172 * opcodes/iq2000-asm.c: Regenerate.
173 * opcodes/iq2000-desc.c: Regenerate.
174 * opcodes/iq2000-desc.h: Regenerate.
175 * opcodes/iq2000-dis.c: Regenerate.
176 * opcodes/iq2000-ibld.c: Regenerate.
177 * opcodes/iq2000-opc.c: Regenerate.
178 * opcodes/iq2000-opc.h: Regenerate.
180 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
182 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
183 us4, us5 (respectively).
184 Remove unsupported 'popa' instruction.
185 Reverse operands order in store co-processor instructions.
187 2004-10-15 Alan Modra <amodra@bigpond.net.au>
189 * Makefile.am: Run "make dep-am"
190 * Makefile.in: Regenerate.
192 2004-10-12 Bob Wilson <bob.wilson@acm.org>
194 * xtensa-dis.c: Use ISO C90 formatting.
196 2004-10-09 Alan Modra <amodra@bigpond.net.au>
198 * ppc-opc.c: Revert 2004-09-09 change.
200 2004-10-07 Bob Wilson <bob.wilson@acm.org>
202 * xtensa-dis.c (state_names): Delete.
203 (fetch_data): Use xtensa_isa_maxlength.
204 (print_xtensa_operand): Replace operand parameter with opcode/operand
205 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
206 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
207 instruction bundles. Use xmalloc instead of malloc.
209 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
211 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
214 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
216 * crx-opc.c (crx_instruction): Support Co-processor insns.
217 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
218 (getregliststring): Change function to use the above enum.
219 (print_arg): Handle CO-Processor insns.
220 (crx_cinvs): Add 'b' option to invalidate the branch-target
223 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
225 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
226 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
227 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
228 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
229 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
231 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
233 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
236 2004-09-30 Paul Brook <paul@codesourcery.com>
238 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
239 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
241 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
243 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
244 (CONFIG_STATUS_DEPENDENCIES): New.
246 (config.status): Likewise.
247 * Makefile.in: Regenerated.
249 2004-09-17 Alan Modra <amodra@bigpond.net.au>
251 * Makefile.am: Run "make dep-am".
252 * Makefile.in: Regenerate.
253 * aclocal.m4: Regenerate.
254 * configure: Regenerate.
255 * po/POTFILES.in: Regenerate.
256 * po/opcodes.pot: Regenerate.
258 2004-09-11 Andreas Schwab <schwab@suse.de>
260 * configure: Rebuild.
262 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
264 * ppc-opc.c (L): Make this field not optional.
266 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
268 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
269 Fix parameter to 'm[t|f]csr' insns.
271 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
273 * configure.in: Autoupdate to autoconf 2.59.
274 * aclocal.m4: Rebuild with aclocal 1.4p6.
275 * configure: Rebuild with autoconf 2.59.
276 * Makefile.in: Rebuild with automake 1.4p6 (picking up
277 bfd changes for autoconf 2.59 on the way).
278 * config.in: Rebuild with autoheader 2.59.
280 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
282 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
284 2004-07-30 Michal Ludvig <mludvig@suse.cz>
286 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
287 (GRPPADLCK2): New define.
288 (twobyte_has_modrm): True for 0xA6.
289 (grps): GRPPADLCK2 for opcode 0xA6.
291 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
293 Introduce SH2a support.
294 * sh-opc.h (arch_sh2a_base): Renumber.
295 (arch_sh2a_nofpu_base): Remove.
296 (arch_sh_base_mask): Adjust.
297 (arch_opann_mask): New.
298 (arch_sh2a, arch_sh2a_nofpu): Adjust.
299 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
300 (sh_table): Adjust whitespace.
301 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
302 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
303 instruction list throughout.
304 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
305 of arch_sh2a in instruction list throughout.
306 (arch_sh2e_up): Accomodate above changes.
307 (arch_sh2_up): Ditto.
308 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
309 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
310 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
311 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
312 * sh-opc.h (arch_sh2a_nofpu): New.
313 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
314 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
316 2004-01-20 DJ Delorie <dj@redhat.com>
317 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
318 2003-12-29 DJ Delorie <dj@redhat.com>
319 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
320 sh_opcode_info, sh_table): Add sh2a support.
321 (arch_op32): New, to tag 32-bit opcodes.
322 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
323 2003-12-02 Michael Snyder <msnyder@redhat.com>
324 * sh-opc.h (arch_sh2a): Add.
325 * sh-dis.c (arch_sh2a): Handle.
326 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
328 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
330 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
332 2004-07-22 Nick Clifton <nickc@redhat.com>
335 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
336 insns - this is done by objdump itself.
337 * h8500-dis.c (print_insn_h8500): Likewise.
339 2004-07-21 Jan Beulich <jbeulich@novell.com>
341 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
342 regardless of address size prefix in effect.
343 (ptr_reg): Size or address registers does not depend on rex64, but
344 on the presence of an address size override.
345 (OP_MMX): Use rex.x only for xmm registers.
346 (OP_EM): Use rex.z only for xmm registers.
348 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
350 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
351 move/branch operations to the bottom so that VR5400 multimedia
352 instructions take precedence in disassembly.
354 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
356 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
357 ISA-specific "break" encoding.
359 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
361 * arm-opc.h: Fix typo in comment.
363 2004-07-11 Andreas Schwab <schwab@suse.de>
365 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
367 2004-07-09 Andreas Schwab <schwab@suse.de>
369 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
371 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
373 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
374 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
375 (crx-dis.lo): New target.
376 (crx-opc.lo): Likewise.
377 * Makefile.in: Regenerate.
378 * configure.in: Handle bfd_crx_arch.
379 * configure: Regenerate.
380 * crx-dis.c: New file.
381 * crx-opc.c: New file.
382 * disassemble.c (ARCH_crx): Define.
383 (disassembler): Handle ARCH_crx.
385 2004-06-29 James E Wilson <wilson@specifixinc.com>
387 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
388 * ia64-asmtab.c: Regnerate.
390 2004-06-28 Alan Modra <amodra@bigpond.net.au>
392 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
393 (extract_fxm): Don't test dialect.
394 (XFXFXM_MASK): Include the power4 bit.
395 (XFXM): Add p4 param.
396 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
398 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
400 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
401 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
403 2004-06-26 Alan Modra <amodra@bigpond.net.au>
405 * ppc-opc.c (BH, XLBH_MASK): Define.
406 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
408 2004-06-24 Alan Modra <amodra@bigpond.net.au>
410 * i386-dis.c (x_mode): Comment.
411 (two_source_ops): File scope.
412 (float_mem): Correct fisttpll and fistpll.
413 (float_mem_mode): New table.
415 (OP_E): Correct intel mode PTR output.
416 (ptr_reg): Use open_char and close_char.
417 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
418 operands. Set two_source_ops.
420 2004-06-15 Alan Modra <amodra@bigpond.net.au>
422 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
423 instead of _raw_size.
425 2004-06-08 Jakub Jelinek <jakub@redhat.com>
427 * ia64-gen.c (in_iclass): Handle more postinc st
429 * ia64-asmtab.c: Rebuilt.
431 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
433 * s390-opc.txt: Correct architecture mask for some opcodes.
434 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
435 in the esa mode as well.
437 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
439 * sh-dis.c (target_arch): Make unsigned.
440 (print_insn_sh): Replace (most of) switch with a call to
441 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
442 * sh-opc.h: Redefine architecture flags values.
443 Add sh3-nommu architecture.
444 Reorganise <arch>_up macros so they make more visual sense.
445 (SH_MERGE_ARCH_SET): Define new macro.
446 (SH_VALID_BASE_ARCH_SET): Likewise.
447 (SH_VALID_MMU_ARCH_SET): Likewise.
448 (SH_VALID_CO_ARCH_SET): Likewise.
449 (SH_VALID_ARCH_SET): Likewise.
450 (SH_MERGE_ARCH_SET_VALID): Likewise.
451 (SH_ARCH_SET_HAS_FPU): Likewise.
452 (SH_ARCH_SET_HAS_DSP): Likewise.
453 (SH_ARCH_UNKNOWN_ARCH): Likewise.
454 (sh_get_arch_from_bfd_mach): Add prototype.
455 (sh_get_arch_up_from_bfd_mach): Likewise.
456 (sh_get_bfd_mach_from_arch_set): Likewise.
457 (sh_merge_bfd_arc): Likewise.
459 2004-05-24 Peter Barada <peter@the-baradas.com>
461 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
462 into new match_insn_m68k function. Loop over canidate
463 matches and select first that completely matches.
464 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
465 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
466 to verify addressing for MAC/EMAC.
467 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
468 reigster halves since 'fpu' and 'spl' look misleading.
469 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
470 * m68k-opc.c: Rearragne mac/emac cases to use longest for
471 first, tighten up match masks.
472 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
473 'size' from special case code in print_insn_m68k to
474 determine decode size of insns.
476 2004-05-19 Alan Modra <amodra@bigpond.net.au>
478 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
479 well as when -mpower4.
481 2004-05-13 Nick Clifton <nickc@redhat.com>
483 * po/fr.po: Updated French translation.
485 2004-05-05 Peter Barada <peter@the-baradas.com>
487 * m68k-dis.c(print_insn_m68k): Add new chips, use core
488 variants in arch_mask. Only set m68881/68851 for 68k chips.
489 * m68k-op.c: Switch from ColdFire chips to core variants.
491 2004-05-05 Alan Modra <amodra@bigpond.net.au>
494 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
496 2004-04-29 Ben Elliston <bje@au.ibm.com>
498 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
499 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
501 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
503 * sh-dis.c (print_insn_sh): Print the value in constant pool
504 as a symbol if it looks like a symbol.
506 2004-04-22 Peter Barada <peter@the-baradas.com>
508 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
509 appropriate ColdFire architectures.
510 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
512 Add EMAC instructions, fix MAC instructions. Remove
513 macmw/macml/msacmw/msacml instructions since mask addressing now
516 2004-04-20 Jakub Jelinek <jakub@redhat.com>
518 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
519 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
520 suffix. Use fmov*x macros, create all 3 fpsize variants in one
521 macro. Adjust all users.
523 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
525 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
528 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
530 * m32r-asm.c: Regenerate.
532 2004-03-29 Stan Shebs <shebs@apple.com>
534 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
537 2004-03-19 Alan Modra <amodra@bigpond.net.au>
539 * aclocal.m4: Regenerate.
540 * config.in: Regenerate.
541 * configure: Regenerate.
542 * po/POTFILES.in: Regenerate.
543 * po/opcodes.pot: Regenerate.
545 2004-03-16 Alan Modra <amodra@bigpond.net.au>
547 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
549 * ppc-opc.c (RA0): Define.
550 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
551 (RAOPT): Rename from RAO. Update all uses.
552 (powerpc_opcodes): Use RA0 as appropriate.
554 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
556 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
558 2004-03-15 Alan Modra <amodra@bigpond.net.au>
560 * sparc-dis.c (print_insn_sparc): Update getword prototype.
562 2004-03-12 Michal Ludvig <mludvig@suse.cz>
564 * i386-dis.c (GRPPLOCK): Delete.
565 (grps): Delete GRPPLOCK entry.
567 2004-03-12 Alan Modra <amodra@bigpond.net.au>
569 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
571 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
573 (dis386): Use NOP_Fixup on "nop".
574 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
575 (twobyte_has_modrm): Set for 0xa7.
576 (padlock_table): Delete. Move to..
577 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
579 (print_insn): Revert PADLOCK_SPECIAL code.
580 (OP_E): Delete sfence, lfence, mfence checks.
582 2004-03-12 Jakub Jelinek <jakub@redhat.com>
584 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
585 (INVLPG_Fixup): New function.
586 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
588 2004-03-12 Michal Ludvig <mludvig@suse.cz>
590 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
591 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
592 (padlock_table): New struct with PadLock instructions.
593 (print_insn): Handle PADLOCK_SPECIAL.
595 2004-03-12 Alan Modra <amodra@bigpond.net.au>
597 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
598 (OP_E): Twiddle clflush to sfence here.
600 2004-03-08 Nick Clifton <nickc@redhat.com>
602 * po/de.po: Updated German translation.
604 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
606 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
607 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
608 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
611 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
613 * frv-asm.c: Regenerate.
614 * frv-desc.c: Regenerate.
615 * frv-desc.h: Regenerate.
616 * frv-dis.c: Regenerate.
617 * frv-ibld.c: Regenerate.
618 * frv-opc.c: Regenerate.
619 * frv-opc.h: Regenerate.
621 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
623 * frv-desc.c, frv-opc.c: Regenerate.
625 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
627 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
629 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
631 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
632 Also correct mistake in the comment.
634 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
636 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
637 ensure that double registers have even numbers.
638 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
639 that reserved instruction 0xfffd does not decode the same
641 * sh-opc.h: Add REG_N_D nibble type and use it whereever
642 REG_N refers to a double register.
643 Add REG_N_B01 nibble type and use it instead of REG_NM
645 Adjust the bit patterns in a few comments.
647 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
649 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
651 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
653 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
655 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
657 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
659 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
661 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
662 mtivor32, mtivor33, mtivor34.
664 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
666 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
668 2004-02-10 Petko Manolov <petkan@nucleusys.com>
670 * arm-opc.h Maverick accumulator register opcode fixes.
672 2004-02-13 Ben Elliston <bje@wasabisystems.com>
674 * m32r-dis.c: Regenerate.
676 2004-01-27 Michael Snyder <msnyder@redhat.com>
678 * sh-opc.h (sh_table): "fsrra", not "fssra".
680 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
682 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
685 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
687 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
689 2004-01-19 Alan Modra <amodra@bigpond.net.au>
691 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
692 1. Don't print scale factor on AT&T mode when index missing.
694 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
696 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
697 when loaded into XR registers.
699 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
701 * frv-desc.h: Regenerate.
702 * frv-desc.c: Regenerate.
703 * frv-opc.c: Regenerate.
705 2004-01-13 Michael Snyder <msnyder@redhat.com>
707 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
709 2004-01-09 Paul Brook <paul@codesourcery.com>
711 * arm-opc.h (arm_opcodes): Move generic mcrr after known
714 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
716 * Makefile.am (libopcodes_la_DEPENDENCIES)
717 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
718 comment about the problem.
719 * Makefile.in: Regenerate.
721 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
723 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
724 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
725 cut&paste errors in shifting/truncating numerical operands.
726 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
727 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
728 (parse_uslo16): Likewise.
729 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
730 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
731 (parse_s12): Likewise.
732 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
733 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
734 (parse_uslo16): Likewise.
735 (parse_uhi16): Parse gothi and gotfuncdeschi.
736 (parse_d12): Parse got12 and gotfuncdesc12.
737 (parse_s12): Likewise.
739 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
741 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
742 instruction which looks similar to an 'rla' instruction.
744 For older changes see ChangeLog-0203
750 version-control: never