1 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-gen.c (opcode_modifiers): Add Optimize.
5 * i386-opc.h (Optimize): New enum.
6 (i386_opcode_modifier): Add optimize.
7 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
8 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
9 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
10 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
11 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
13 * i386-tbl.h: Regenerated.
15 2018-02-26 Alan Modra <amodra@gmail.com>
17 * crx-dis.c (getregliststring): Allocate a large enough buffer
18 to silence false positive gcc8 warning.
20 2018-02-22 Shea Levy <shea@shealevy.com>
22 * disassemble.c (ARCH_riscv): Define if ARCH_all.
24 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
26 * i386-opc.tbl: Add {rex},
27 * i386-tbl.h: Regenerated.
29 2018-02-20 Maciej W. Rozycki <macro@mips.com>
31 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
32 (mips16_opcodes): Replace `M' with `m' for "restore".
34 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
36 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
38 2018-02-13 Maciej W. Rozycki <macro@mips.com>
40 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
41 variable to `function_index'.
43 2018-02-13 Nick Clifton <nickc@redhat.com>
46 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
47 about truncation of printing.
49 2018-02-12 Henry Wong <henry@stuffedcow.net>
51 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
53 2018-02-05 Nick Clifton <nickc@redhat.com>
55 * po/pt_BR.po: Updated Brazilian Portuguese translation.
57 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
59 * i386-dis.c (enum): Add pconfig.
60 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
61 (cpu_flags): Add CpuPCONFIG.
62 * i386-opc.h (enum): Add CpuPCONFIG.
63 (i386_cpu_flags): Add cpupconfig.
64 * i386-opc.tbl: Add PCONFIG instruction.
65 * i386-init.h: Regenerate.
66 * i386-tbl.h: Likewise.
68 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
70 * i386-dis.c (enum): Add PREFIX_0F09.
71 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
72 (cpu_flags): Add CpuWBNOINVD.
73 * i386-opc.h (enum): Add CpuWBNOINVD.
74 (i386_cpu_flags): Add cpuwbnoinvd.
75 * i386-opc.tbl: Add WBNOINVD instruction.
76 * i386-init.h: Regenerate.
77 * i386-tbl.h: Likewise.
79 2018-01-17 Jim Wilson <jimw@sifive.com>
81 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
83 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
85 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
86 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
87 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
88 (cpu_flags): Add CpuIBT, CpuSHSTK.
89 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
90 (i386_cpu_flags): Add cpuibt, cpushstk.
91 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
92 * i386-init.h: Regenerate.
93 * i386-tbl.h: Likewise.
95 2018-01-16 Nick Clifton <nickc@redhat.com>
97 * po/pt_BR.po: Updated Brazilian Portugese translation.
98 * po/de.po: Updated German translation.
100 2018-01-15 Jim Wilson <jimw@sifive.com>
102 * riscv-opc.c (match_c_nop): New.
103 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
105 2018-01-15 Nick Clifton <nickc@redhat.com>
107 * po/uk.po: Updated Ukranian translation.
109 2018-01-13 Nick Clifton <nickc@redhat.com>
111 * po/opcodes.pot: Regenerated.
113 2018-01-13 Nick Clifton <nickc@redhat.com>
115 * configure: Regenerate.
117 2018-01-13 Nick Clifton <nickc@redhat.com>
121 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
123 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
124 * i386-tbl.h: Regenerate.
126 2018-01-10 Jan Beulich <jbeulich@suse.com>
128 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
129 * i386-tbl.h: Re-generate.
131 2018-01-10 Jan Beulich <jbeulich@suse.com>
133 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
134 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
135 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
136 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
137 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
138 Disp8MemShift of AVX512VL forms.
139 * i386-tbl.h: Re-generate.
141 2018-01-09 Jim Wilson <jimw@sifive.com>
143 * riscv-dis.c (maybe_print_address): If base_reg is zero,
144 then the hi_addr value is zero.
146 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
148 * arm-dis.c (arm_opcodes): Add csdb.
149 (thumb32_opcodes): Add csdb.
151 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
153 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
154 * aarch64-asm-2.c: Regenerate.
155 * aarch64-dis-2.c: Regenerate.
156 * aarch64-opc-2.c: Regenerate.
158 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
161 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
162 Remove AVX512 vmovd with 64-bit operands.
163 * i386-tbl.h: Regenerated.
165 2018-01-05 Jim Wilson <jimw@sifive.com>
167 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
170 2018-01-03 Alan Modra <amodra@gmail.com>
172 Update year range in copyright notice of all files.
174 2018-01-02 Jan Beulich <jbeulich@suse.com>
176 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
177 and OPERAND_TYPE_REGZMM entries.
179 For older changes see ChangeLog-2017
181 Copyright (C) 2018 Free Software Foundation, Inc.
183 Copying and distribution of this file, with or without modification,
184 are permitted in any medium without royalty provided the copyright
185 notice and this notice are preserved.
191 version-control: never