1 2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
3 * disassemble.c (disassemble_init_for_target): Don't put PRU
4 between powerpc and rs6000 cases.
6 2017-12-15 Jan Beulich <jbeulich@suse.com>
8 * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
9 movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
10 sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
11 stos, sub, test, xor): Drop CheckRegSize from variants not
12 allowing for two (or more) register operands.
13 * i386-tbl.h: Re-generate.
15 2017-12-13 Jim Wilson <jimw@sifive.com>
18 * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
20 2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
22 * disassemble.c: Enable disassembler_needs_relocs for PRU.
24 2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
25 Renlin Li <renlin.li@arm.com>
27 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
28 (get_sym_code_type): Here.
30 2017-12-03 Alan Modra <amodra@gmail.com>
32 * ppc-opc.c (extract_li20): Rewrite.
34 2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
36 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
37 (operand_value_powerpc): Update return and argument type.
38 <value, top>: Update type.
39 (skip_optional_operands): Update argument type.
40 (lookup_powerpc): Likewise.
41 (lookup_vle): Likewise.
42 <table_opcd, table_mask, insn2>: Update type.
43 (lookup_spe2): Update argument type.
44 <table_opcd, table_mask, insn2>: Update type.
45 (print_insn_powerpc) <insn, value>: Update type.
46 Use PPC_INT_FMT for printing instructions and operands.
47 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
48 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
49 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
50 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
51 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
52 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
53 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
54 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
55 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
56 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
57 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
58 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
59 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
60 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
61 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
62 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
63 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
64 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
65 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
66 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
67 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
68 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
69 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
70 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
71 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
72 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
73 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
74 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
75 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
76 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
77 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
78 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
79 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
80 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
81 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
82 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
83 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
85 2017-11-29 Jan Beulich <jbeulich@suse.com>
87 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
89 (output_cpu_flags): Update active_cpu_flags.
90 (process_i386_opcode_modifier): Update active_isstring.
91 (output_operand_type): Rename "macro" parameter to "stage",
93 (process_i386_operand_type): Likewise. Track presence of
94 BaseIndex and emit DispN accordingly.
95 (output_i386_opcode, process_i386_registers,
96 process_i386_initializers): Adjust calls to
97 process_i386_operand_type() for its changed parameter type.
98 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
99 all insns operands having BaseIndex set.
100 * i386-tbl.h: Re-generate.
102 2017-11-29 Jan Beulich <jbeulich@suse.com>
104 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
106 (operand_types): Remove Vec_Disp8 entry.
107 * i386-opc.h (Vec_Disp8): Delete.
108 (union i386_operand_type): Remove vec_disp8.
109 (i386-opc.tbl): Remove Vec_Disp8.
110 * i386-init.h, i386-tbl.h: Re-generate.
112 2017-11-29 Stefan Stroe <stroestefan@gmail.com>
114 * po/Make-in (datadir): Define as @datadir@.
115 (localedir): Define as @localedir@.
116 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
118 2017-11-27 Nick Clifton <nickc@redhat.com>
120 * po/zh_CN.po: Updated simplified Chinese translation.
122 2017-11-24 Jan Beulich <jbeulich@suse.com>
124 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
127 2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
129 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
130 * i386-tbl.h: Regenerate.
132 2017-11-23 Jan Beulich <jbeulich@suse.com>
134 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
135 the 16-bit addressing case.
137 2017-11-23 Jan Beulich <jbeulich@suse.com>
139 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
140 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
141 * i386-opc.tbl (ud1, ud2b): Add operands.
143 * i386-tbl.h: Re-generate.
145 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
147 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
148 * i386-tbl.h: Regenerate.
150 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
152 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
153 * i386-tbl.h: Regenerate.
155 2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
157 *arc-opc (insert_rhv2): Check h-regs range.
159 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
161 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
162 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
164 2017-11-16 Tamar Christina <tamar.christina@arm.com>
166 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
167 and AARCH64_FEATURE_F16.
169 2017-11-16 Tamar Christina <tamar.christina@arm.com>
171 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
172 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
173 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
174 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
175 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
176 (ldapur, ldapursw, stlur): New.
177 * aarch64-dis-2.c: Regenerate.
179 2017-11-16 Jan Beulich <jbeulich@suse.com>
181 (get_valid_dis386): Never flag bad opcode when
182 vex.register_specifier is beyond 7. Always store all four
183 bits of it. Move 16-/32-bit override in EVEX handling after
184 all to be overridden bits have been set.
185 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
186 Use rex to determine GPR register set.
187 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
188 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
190 2017-11-15 Jan Beulich <jbeulich@suse.com>
192 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
193 determine GPR register set.
195 2017-11-15 Jan Beulich <jbeulich@suse.com>
197 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
198 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
199 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
201 (OP_REG_VexI4): Drop low 4 bits check.
203 2017-11-15 Jan Beulich <jbeulich@suse.com>
205 * i386-reg.tbl (axl): Remove Acc and Byte.
206 * i386-tbl.h: Re-generate.
208 2017-11-14 Jan Beulich <jbeulich@suse.com>
210 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
211 (vex_len_table): Use VPCOM.
213 2017-11-14 Jan Beulich <jbeulich@suse.com>
215 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
216 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
217 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
219 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
220 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
221 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
222 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
224 * i386-tbl.h: Re-generate.
226 2017-11-14 Jan Beulich <jbeulich@suse.com>
228 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
229 smov, ssca, stos, ssto, xlat): Drop Disp*.
230 * i386-tbl.h: Re-generate.
232 2017-11-13 Jan Beulich <jbeulich@suse.com>
234 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
235 xsaveopt64): Add No_qSuf.
236 * i386-tbl.h: Re-generate.
238 2017-11-09 Tamar Christina <tamar.christina@arm.com>
240 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
241 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
242 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
243 sder32_el2, vncr_el2.
244 (aarch64_sys_reg_supported_p): Likewise.
245 (aarch64_pstatefields): Add dit register.
246 (aarch64_pstatefield_supported_p): Likewise.
247 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
248 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
249 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
250 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
251 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
252 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
253 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
255 2017-11-09 Tamar Christina <tamar.christina@arm.com>
257 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
258 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
259 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
260 (QL_STLW, QL_STLX): New.
262 2017-11-09 Tamar Christina <tamar.christina@arm.com>
264 * aarch64-asm.h (ins_addr_offset): New.
265 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
266 (aarch64_ins_addr_offset): New.
267 * aarch64-asm-2.c: Regenerate.
268 * aarch64-dis.h (ext_addr_offset): New.
269 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
270 (aarch64_ext_addr_offset): New.
271 * aarch64-dis-2.c: Regenerate.
272 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
273 FLD_imm4_2 and FLD_SM3_imm2.
274 * aarch64-opc.c (fields): Add FLD_imm6_2,
275 FLD_imm4_2 and FLD_SM3_imm2.
276 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
277 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
278 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
279 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
281 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
283 2017-11-09 Tamar Christina <tamar.christina@arm.com>
286 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
287 (aarch64_feature_sm4, aarch64_feature_sha3): New.
288 (aarch64_feature_fp_16_v8_2): New.
289 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
290 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
291 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
293 2017-11-08 Tamar Christina <tamar.christina@arm.com>
295 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
296 (aarch64_feature_sha2, aarch64_feature_aes): New.
298 (AES_INSN, SHA2_INSN): New.
299 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
300 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
301 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
304 2017-11-08 Jiong Wang <jiong.wang@arm.com>
305 Tamar Christina <tamar.christina@arm.com>
307 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
308 FP16 instructions, including vfmal.f16 and vfmsl.f16.
310 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
312 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
314 2017-11-07 Alan Modra <amodra@gmail.com>
316 * opintl.h: Formatting, comment fixes.
317 (gettext, ngettext): Redefine when ENABLE_NLS.
318 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
319 (_): Define using gettext.
320 (textdomain, bindtextdomain): Use safer "do nothing".
322 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
324 * arc-dis.c (print_hex): New variable.
325 (parse_option): Check for hex option.
326 (print_insn_arc): Use hexadecimal representation for short
327 immediate values when requested.
328 (print_arc_disassembler_options): Add hex option to the list.
330 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
332 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
333 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
334 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
335 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
336 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
337 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
338 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
339 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
340 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
341 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
342 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
343 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
344 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
345 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
346 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
347 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
348 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
349 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
350 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
352 (prealloc, prefetch*): Place them before ld instruction.
353 * arc-opc.c (skip_this_opcode): Add ARITH class.
355 2017-10-25 Alan Modra <amodra@gmail.com>
358 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
359 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
360 (imm4flag, size_changed): Likewise.
361 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
362 (words, allWords, processing_argument_number): Likewise.
363 (cst4flag, size_changed): Likewise.
364 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
365 (crx_cst4_maps): Rename from cst4_maps.
366 (crx_no_op_insn): Rename from no_op_insn.
368 2017-10-24 Andrew Waterman <andrew@sifive.com>
370 * riscv-opc.c (match_c_addi16sp) : New function.
371 (match_c_addi4spn): New function.
372 (match_c_lui): Don't allow 0-immediate encodings.
373 (riscv_opcodes) <addi>: Use the above functions.
375 <c.addi4spn>: Likewise.
376 <c.addi16sp>: Likewise.
378 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
380 * i386-init.h: Regenerate
381 * i386-tbl.h: Likewise
383 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
385 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
386 (enum): Add EVEX_W_0F3854_P_2.
387 * i386-dis-evex.h (evex_table): Updated.
388 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
389 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
390 (cpu_flags): Add CpuAVX512_BITALG.
391 * i386-opc.h (enum): Add CpuAVX512_BITALG.
392 (i386_cpu_flags): Add cpuavx512_bitalg..
393 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
394 * i386-init.h: Regenerate.
395 * i386-tbl.h: Likewise.
397 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
399 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
400 * i386-dis-evex.h (evex_table): Updated.
401 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
402 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
403 (cpu_flags): Add CpuAVX512_VNNI.
404 * i386-opc.h (enum): Add CpuAVX512_VNNI.
405 (i386_cpu_flags): Add cpuavx512_vnni.
406 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
407 * i386-init.h: Regenerate.
408 * i386-tbl.h: Likewise.
410 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
412 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
413 (enum): Remove VEX_LEN_0F3A44_P_2.
414 (vex_len_table): Ditto.
415 (enum): Remove VEX_W_0F3A44_P_2.
416 (vew_w_table): Ditto.
417 (prefix_table): Adjust instructions (see prefixes above).
418 * i386-dis-evex.h (evex_table):
419 Add new instructions (see prefixes above).
420 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
421 (bitfield_cpu_flags): Ditto.
422 * i386-opc.h (enum): Ditto.
423 (i386_cpu_flags): Ditto.
424 (CpuUnused): Comment out to avoid zero-width field problem.
425 * i386-opc.tbl (vpclmulqdq): New instruction.
426 * i386-init.h: Regenerate.
429 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
431 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
432 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
433 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
434 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
435 (vex_len_table): Ditto.
436 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
437 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
438 (vew_w_table): Ditto.
439 (prefix_table): Adjust instructions (see prefixes above).
440 * i386-dis-evex.h (evex_table):
441 Add new instructions (see prefixes above).
442 * i386-gen.c (cpu_flag_init): Add VAES.
443 (bitfield_cpu_flags): Ditto.
444 * i386-opc.h (enum): Ditto.
445 (i386_cpu_flags): Ditto.
446 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
447 * i386-init.h: Regenerate.
450 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
452 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
453 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
454 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
455 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
456 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
457 (prefix_table): Updated (see prefixes above).
458 (three_byte_table): Likewise.
459 (vex_w_table): Likewise.
460 * i386-dis-evex.h: Likewise.
461 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
462 (cpu_flags): Add CpuGFNI.
463 * i386-opc.h (enum): Add CpuGFNI.
464 (i386_cpu_flags): Add cpugfni.
465 * i386-opc.tbl: Add Intel GFNI instructions.
466 * i386-init.h: Regenerate.
467 * i386-tbl.h: Likewise.
469 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
471 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
472 Define EXbScalar and EXwScalar for OP_EX.
473 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
474 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
475 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
476 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
477 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
478 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
479 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
480 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
481 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
482 (OP_E_memory): Likewise.
483 * i386-dis-evex.h: Updated.
484 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
485 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
486 (cpu_flags): Add CpuAVX512_VBMI2.
487 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
488 (i386_cpu_flags): Add cpuavx512_vbmi2.
489 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
490 * i386-init.h: Regenerate.
491 * i386-tbl.h: Likewise.
493 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
495 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
497 2017-10-12 James Bowman <james.bowman@ftdichip.com>
499 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
500 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
501 K15. Add jmpix pattern.
503 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
505 * s390-opc.txt (prno, tpei, irbm): New instructions added.
507 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
509 * s390-opc.c (INSTR_SI_RD): New macro.
510 (INSTR_S_RD): Adjust example instruction.
511 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
514 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
516 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
517 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
518 VLE multimple load/store instructions. Old e_ldm* variants are
520 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
522 2017-09-27 Nick Clifton <nickc@redhat.com>
525 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
526 names for the fmv.x.s and fmv.s.x instructions respectively.
528 2017-09-26 do <do@nerilex.org>
531 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
532 be used on CPUs that have emacs support.
534 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
536 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
538 2017-09-09 Kamil Rytarowski <n54@gmx.com>
540 * nds32-asm.c: Rename __BIT() to N32_BIT().
541 * nds32-asm.h: Likewise.
542 * nds32-dis.c: Likewise.
544 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
546 * i386-dis.c (last_active_prefix): Removed.
547 (ckprefix): Don't set last_active_prefix.
548 (NOTRACK_Fixup): Don't check last_active_prefix.
550 2017-08-31 Nick Clifton <nickc@redhat.com>
552 * po/fr.po: Updated French translation.
554 2017-08-31 James Bowman <james.bowman@ftdichip.com>
556 * ft32-dis.c (print_insn_ft32): Correct display of non-address
559 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
560 Edmar Wienskoski <edmar.wienskoski@nxp.com>
562 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
563 PPC_OPCODE_EFS2 flag to "e200z4" entry.
564 New entries efs2 and spe2.
565 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
566 (SPE2_OPCD_SEGS): New macro.
567 (spe2_opcd_indices): New.
568 (disassemble_init_powerpc): Handle SPE2 opcodes.
569 (lookup_spe2): New function.
570 (print_insn_powerpc): call lookup_spe2.
571 * ppc-opc.c (insert_evuimm1_ex0): New function.
572 (extract_evuimm1_ex0): Likewise.
573 (insert_evuimm_lt8): Likewise.
574 (extract_evuimm_lt8): Likewise.
575 (insert_off_spe2): Likewise.
576 (extract_off_spe2): Likewise.
577 (insert_Ddd): Likewise.
578 (extract_Ddd): Likewise.
580 (EVUIMM_LT8): Likewise.
581 (EVUIMM_LT16): Adjust.
583 (EVUIMM_1): Likewise.
584 (EVUIMM_1_EX0): Likewise.
587 (VX_OFF_SPE2): Likewise.
590 (VX_MASK_DDD): New mask.
592 (VX_RA_CONST): New macro.
593 (VX_RA_CONST_MASK): Likewise.
594 (VX_RB_CONST): Likewise.
595 (VX_RB_CONST_MASK): Likewise.
596 (VX_OFF_SPE2_MASK): Likewise.
597 (VX_SPE_CRFD): Likewise.
598 (VX_SPE_CRFD_MASK VX): Likewise.
599 (VX_SPE2_CLR): Likewise.
600 (VX_SPE2_CLR_MASK): Likewise.
601 (VX_SPE2_SPLATB): Likewise.
602 (VX_SPE2_SPLATB_MASK): Likewise.
603 (VX_SPE2_OCTET): Likewise.
604 (VX_SPE2_OCTET_MASK): Likewise.
605 (VX_SPE2_DDHH): Likewise.
606 (VX_SPE2_DDHH_MASK): Likewise.
607 (VX_SPE2_HH): Likewise.
608 (VX_SPE2_HH_MASK): Likewise.
609 (VX_SPE2_EVMAR): Likewise.
610 (VX_SPE2_EVMAR_MASK): Likewise.
613 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
614 (powerpc_macros): Map old SPE instructions have new names
615 with the same opcodes. Add SPE2 instructions which just are
617 (spe2_opcodes): Add SPE2 opcodes.
619 2017-08-23 Alan Modra <amodra@gmail.com>
621 * ppc-opc.c: Formatting and comment fixes. Move insert and
622 extract functions earlier, deleting forward declarations.
623 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
626 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
628 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
630 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
631 Edmar Wienskoski <edmar.wienskoski@nxp.com>
633 * ppc-opc.c (insert_evuimm2_ex0): New function.
634 (extract_evuimm2_ex0): Likewise.
635 (insert_evuimm4_ex0): Likewise.
636 (extract_evuimm4_ex0): Likewise.
637 (insert_evuimm8_ex0): Likewise.
638 (extract_evuimm8_ex0): Likewise.
639 (insert_evuimm_lt16): Likewise.
640 (extract_evuimm_lt16): Likewise.
641 (insert_rD_rS_even): Likewise.
642 (extract_rD_rS_even): Likewise.
643 (insert_off_lsp): Likewise.
644 (extract_off_lsp): Likewise.
645 (RD_EVEN): New operand.
648 (EVUIMM_LT16): New operand.
650 (EVUIMM_2_EX0): New operand.
652 (EVUIMM_4_EX0): New operand.
654 (EVUIMM_8_EX0): New operand.
656 (VX_OFF): New operand.
658 (VX_LSP_MASK): Likewise.
659 (VX_LSP_OFF_MASK): Likewise.
660 (PPC_OPCODE_LSP): Likewise.
661 (vle_opcodes): Add LSP opcodes.
662 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
664 2017-08-09 Jiong Wang <jiong.wang@arm.com>
666 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
667 register operands in CRC instructions.
668 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
671 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
673 * disassemble.c (disassembler): Mark big and mach with
676 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
678 * disassemble.c (disassembler): Remove arch/mach/endian
681 2017-07-25 Nick Clifton <nickc@redhat.com>
684 * arc-opc.c (insert_rhv2): Use lower case first letter in error
686 (insert_r0): Likewise.
687 (insert_r1): Likewise.
688 (insert_r2): Likewise.
689 (insert_r3): Likewise.
690 (insert_sp): Likewise.
691 (insert_gp): Likewise.
692 (insert_pcl): Likewise.
693 (insert_blink): Likewise.
694 (insert_ilink1): Likewise.
695 (insert_ilink2): Likewise.
696 (insert_ras): Likewise.
697 (insert_rbs): Likewise.
698 (insert_rcs): Likewise.
699 (insert_simm3s): Likewise.
700 (insert_rrange): Likewise.
701 (insert_r13el): Likewise.
702 (insert_fpel): Likewise.
703 (insert_blinkel): Likewise.
704 (insert_pclel): Likewise.
705 (insert_nps_bitop_size_2b): Likewise.
706 (insert_nps_imm_offset): Likewise.
707 (insert_nps_imm_entry): Likewise.
708 (insert_nps_size_16bit): Likewise.
709 (insert_nps_##NAME##_pos): Likewise.
710 (insert_nps_##NAME): Likewise.
711 (insert_nps_bitop_ins_ext): Likewise.
712 (insert_nps_##NAME): Likewise.
713 (insert_nps_min_hofs): Likewise.
714 (insert_nps_##NAME): Likewise.
715 (insert_nps_rbdouble_64): Likewise.
716 (insert_nps_misc_imm_offset): Likewise.
717 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
720 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
721 Jiong Wang <jiong.wang@arm.com>
723 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
725 * aarch64-dis-2.c: Regenerated.
727 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
729 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
732 2017-07-20 Nick Clifton <nickc@redhat.com>
734 * po/de.po: Updated German translation.
736 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
738 * arc-regs.h (sec_stat): New aux register.
739 (aux_kernel_sp): Likewise.
740 (aux_sec_u_sp): Likewise.
741 (aux_sec_k_sp): Likewise.
742 (sec_vecbase_build): Likewise.
743 (nsc_table_top): Likewise.
744 (nsc_table_base): Likewise.
745 (ersec_stat): Likewise.
746 (aux_sec_except): Likewise.
748 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
750 * arc-opc.c (extract_uimm12_20): New function.
751 (UIMM12_20): New operand.
753 * arc-tbl.h (sjli): Add new instruction.
755 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
756 John Eric Martin <John.Martin@emmicro-us.com>
758 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
759 (UIMM3_23): Adjust accordingly.
760 * arc-regs.h: Add/correct jli_base register.
761 * arc-tbl.h (jli_s): Likewise.
763 2017-07-18 Nick Clifton <nickc@redhat.com>
766 * aarch64-opc.c: Fix spelling typos.
767 * i386-dis.c: Likewise.
769 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
771 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
772 max_addr_offset and octets variables to size_t.
774 2017-07-12 Alan Modra <amodra@gmail.com>
776 * po/da.po: Update from translationproject.org/latest/opcodes/.
777 * po/de.po: Likewise.
778 * po/es.po: Likewise.
779 * po/fi.po: Likewise.
780 * po/fr.po: Likewise.
781 * po/id.po: Likewise.
782 * po/it.po: Likewise.
783 * po/nl.po: Likewise.
784 * po/pt_BR.po: Likewise.
785 * po/ro.po: Likewise.
786 * po/sv.po: Likewise.
787 * po/tr.po: Likewise.
788 * po/uk.po: Likewise.
789 * po/vi.po: Likewise.
790 * po/zh_CN.po: Likewise.
792 2017-07-11 Yao Qi <yao.qi@linaro.org>
793 Alan Modra <amodra@gmail.com>
795 * cgen.sh: Mark generated files read-only.
796 * epiphany-asm.c: Regenerate.
797 * epiphany-desc.c: Regenerate.
798 * epiphany-desc.h: Regenerate.
799 * epiphany-dis.c: Regenerate.
800 * epiphany-ibld.c: Regenerate.
801 * epiphany-opc.c: Regenerate.
802 * epiphany-opc.h: Regenerate.
803 * fr30-asm.c: Regenerate.
804 * fr30-desc.c: Regenerate.
805 * fr30-desc.h: Regenerate.
806 * fr30-dis.c: Regenerate.
807 * fr30-ibld.c: Regenerate.
808 * fr30-opc.c: Regenerate.
809 * fr30-opc.h: Regenerate.
810 * frv-asm.c: Regenerate.
811 * frv-desc.c: Regenerate.
812 * frv-desc.h: Regenerate.
813 * frv-dis.c: Regenerate.
814 * frv-ibld.c: Regenerate.
815 * frv-opc.c: Regenerate.
816 * frv-opc.h: Regenerate.
817 * ip2k-asm.c: Regenerate.
818 * ip2k-desc.c: Regenerate.
819 * ip2k-desc.h: Regenerate.
820 * ip2k-dis.c: Regenerate.
821 * ip2k-ibld.c: Regenerate.
822 * ip2k-opc.c: Regenerate.
823 * ip2k-opc.h: Regenerate.
824 * iq2000-asm.c: Regenerate.
825 * iq2000-desc.c: Regenerate.
826 * iq2000-desc.h: Regenerate.
827 * iq2000-dis.c: Regenerate.
828 * iq2000-ibld.c: Regenerate.
829 * iq2000-opc.c: Regenerate.
830 * iq2000-opc.h: Regenerate.
831 * lm32-asm.c: Regenerate.
832 * lm32-desc.c: Regenerate.
833 * lm32-desc.h: Regenerate.
834 * lm32-dis.c: Regenerate.
835 * lm32-ibld.c: Regenerate.
836 * lm32-opc.c: Regenerate.
837 * lm32-opc.h: Regenerate.
838 * lm32-opinst.c: Regenerate.
839 * m32c-asm.c: Regenerate.
840 * m32c-desc.c: Regenerate.
841 * m32c-desc.h: Regenerate.
842 * m32c-dis.c: Regenerate.
843 * m32c-ibld.c: Regenerate.
844 * m32c-opc.c: Regenerate.
845 * m32c-opc.h: Regenerate.
846 * m32r-asm.c: Regenerate.
847 * m32r-desc.c: Regenerate.
848 * m32r-desc.h: Regenerate.
849 * m32r-dis.c: Regenerate.
850 * m32r-ibld.c: Regenerate.
851 * m32r-opc.c: Regenerate.
852 * m32r-opc.h: Regenerate.
853 * m32r-opinst.c: Regenerate.
854 * mep-asm.c: Regenerate.
855 * mep-desc.c: Regenerate.
856 * mep-desc.h: Regenerate.
857 * mep-dis.c: Regenerate.
858 * mep-ibld.c: Regenerate.
859 * mep-opc.c: Regenerate.
860 * mep-opc.h: Regenerate.
861 * mt-asm.c: Regenerate.
862 * mt-desc.c: Regenerate.
863 * mt-desc.h: Regenerate.
864 * mt-dis.c: Regenerate.
865 * mt-ibld.c: Regenerate.
866 * mt-opc.c: Regenerate.
867 * mt-opc.h: Regenerate.
868 * or1k-asm.c: Regenerate.
869 * or1k-desc.c: Regenerate.
870 * or1k-desc.h: Regenerate.
871 * or1k-dis.c: Regenerate.
872 * or1k-ibld.c: Regenerate.
873 * or1k-opc.c: Regenerate.
874 * or1k-opc.h: Regenerate.
875 * or1k-opinst.c: Regenerate.
876 * xc16x-asm.c: Regenerate.
877 * xc16x-desc.c: Regenerate.
878 * xc16x-desc.h: Regenerate.
879 * xc16x-dis.c: Regenerate.
880 * xc16x-ibld.c: Regenerate.
881 * xc16x-opc.c: Regenerate.
882 * xc16x-opc.h: Regenerate.
883 * xstormy16-asm.c: Regenerate.
884 * xstormy16-desc.c: Regenerate.
885 * xstormy16-desc.h: Regenerate.
886 * xstormy16-dis.c: Regenerate.
887 * xstormy16-ibld.c: Regenerate.
888 * xstormy16-opc.c: Regenerate.
889 * xstormy16-opc.h: Regenerate.
891 2017-07-07 Alan Modra <amodra@gmail.com>
893 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
894 * m32c-dis.c: Regenerate.
895 * mep-dis.c: Regenerate.
897 2017-07-05 Borislav Petkov <bp@suse.de>
899 * i386-dis.c: Enable ModRM.reg /6 aliases.
901 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
903 * opcodes/arm-dis.c: Support MVFR2 in disassembly
906 2017-07-04 Tristan Gingold <gingold@adacore.com>
908 * configure: Regenerate.
910 2017-07-03 Tristan Gingold <gingold@adacore.com>
912 * po/opcodes.pot: Regenerate.
914 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
916 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
917 entries to the MSA ASE instruction block.
919 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
920 Maciej W. Rozycki <macro@imgtec.com>
922 * micromips-opc.c (XPA, XPAVZ): New macros.
923 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
926 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
927 Maciej W. Rozycki <macro@imgtec.com>
929 * micromips-opc.c (I36): New macro.
930 (micromips_opcodes): Add "eretnc".
932 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
933 Andrew Bennett <andrew.bennett@imgtec.com>
935 * mips-dis.c (mips_calculate_combination_ases): Handle the
937 (parse_mips_ase_option): New function.
938 (parse_mips_dis_option): Factor out ASE option handling to the
939 new function. Call `mips_calculate_combination_ases'.
940 * mips-opc.c (XPAVZ): New macro.
941 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
942 "mfhgc0", "mthc0" and "mthgc0".
944 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
946 * mips-dis.c (mips_calculate_combination_ases): New function.
947 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
948 calculation to the new function.
949 (set_default_mips_dis_options): Call the new function.
951 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
953 * arc-dis.c (parse_disassembler_options): Use
954 FOR_EACH_DISASSEMBLER_OPTION.
956 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
958 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
959 disassembler option strings.
960 (parse_cpu_option): Likewise.
962 2017-06-28 Tamar Christina <tamar.christina@arm.com>
964 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
965 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
966 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
967 (aarch64_feature_dotprod, DOT_INSN): New.
969 * aarch64-dis-2.c: Regenerated.
971 2017-06-28 Jiong Wang <jiong.wang@arm.com>
973 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
975 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
976 Matthew Fortune <matthew.fortune@imgtec.com>
977 Andrew Bennett <andrew.bennett@imgtec.com>
979 * mips-formats.h (INT_BIAS): New macro.
980 (INT_ADJ): Redefine in INT_BIAS terms.
981 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
982 (mips_print_save_restore): New function.
983 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
984 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
986 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
987 (print_mips16_insn_arg): Call `mips_print_save_restore' for
988 OP_SAVE_RESTORE_LIST handling, factored out from here.
989 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
990 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
991 (mips_builtin_opcodes): Add "restore" and "save" entries.
992 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
994 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
996 2017-06-23 Andrew Waterman <andrew@sifive.com>
998 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
999 alias; do not mark SLTI instruction as an alias.
1001 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1003 * i386-dis.c (RM_0FAE_REG_5): Removed.
1004 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1005 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
1006 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
1007 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
1008 PREFIX_MOD_3_0F01_REG_5_RM_0.
1009 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
1010 PREFIX_MOD_3_0FAE_REG_5.
1011 (mod_table): Update MOD_0FAE_REG_5.
1012 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
1013 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
1014 * i386-tbl.h: Regenerated.
1016 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1018 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1019 * i386-opc.tbl: Likewise.
1020 * i386-tbl.h: Regenerated.
1022 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1024 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1026 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1029 2017-06-19 Nick Clifton <nickc@redhat.com>
1032 * score-dis.c (score_opcodes): Add sentinel.
1034 2017-06-16 Alan Modra <amodra@gmail.com>
1036 * rx-decode.c: Regenerate.
1038 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1041 * i386-dis.c (OP_E_register): Check valid bnd register.
1044 2017-06-15 Nick Clifton <nickc@redhat.com>
1047 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1050 2017-06-15 Nick Clifton <nickc@redhat.com>
1053 * rl78-decode.opc (OP_BUF_LEN): Define.
1054 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1055 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1057 * rl78-decode.c: Regenerate.
1059 2017-06-15 Nick Clifton <nickc@redhat.com>
1062 * bfin-dis.c (gregs): Clip index to prevent overflow.
1064 (regs_lo): Likewise.
1065 (regs_hi): Likewise.
1067 2017-06-14 Nick Clifton <nickc@redhat.com>
1070 * score7-dis.c (score_opcodes): Add sentinel.
1072 2017-06-14 Yao Qi <yao.qi@linaro.org>
1074 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1075 * arm-dis.c: Likewise.
1076 * ia64-dis.c: Likewise.
1077 * mips-dis.c: Likewise.
1078 * spu-dis.c: Likewise.
1079 * disassemble.h (print_insn_aarch64): New declaration, moved from
1081 (print_insn_big_arm, print_insn_big_mips): Likewise.
1082 (print_insn_i386, print_insn_ia64): Likewise.
1083 (print_insn_little_arm, print_insn_little_mips): Likewise.
1085 2017-06-14 Nick Clifton <nickc@redhat.com>
1088 * rx-decode.opc: Include libiberty.h
1089 (GET_SCALE): New macro - validates access to SCALE array.
1090 (GET_PSCALE): New macro - validates access to PSCALE array.
1091 (DIs, SIs, S2Is, rx_disp): Use new macros.
1092 * rx-decode.c: Regenerate.
1094 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1096 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1098 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1100 * arc-dis.c (enforced_isa_mask): Declare.
1101 (cpu_types): Likewise.
1102 (parse_cpu_option): New function.
1103 (parse_disassembler_options): Use it.
1104 (print_insn_arc): Use enforced_isa_mask.
1105 (print_arc_disassembler_options): Document new options.
1107 2017-05-24 Yao Qi <yao.qi@linaro.org>
1109 * alpha-dis.c: Include disassemble.h, don't include
1111 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1112 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1113 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1114 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1115 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1116 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1117 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1118 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1119 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1120 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1121 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1122 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1123 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1124 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1125 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1126 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1127 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1128 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1129 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1130 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1131 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1132 * z80-dis.c, z8k-dis.c: Likewise.
1133 * disassemble.h: New file.
1135 2017-05-24 Yao Qi <yao.qi@linaro.org>
1137 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1138 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1140 2017-05-24 Yao Qi <yao.qi@linaro.org>
1142 * disassemble.c (disassembler): Add arguments a, big and mach.
1145 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1147 * i386-dis.c (NOTRACK_Fixup): New.
1148 (NOTRACK): Likewise.
1149 (NOTRACK_PREFIX): Likewise.
1150 (last_active_prefix): Likewise.
1151 (reg_table): Use NOTRACK on indirect call and jmp.
1152 (ckprefix): Set last_active_prefix.
1153 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1154 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1155 * i386-opc.h (NoTrackPrefixOk): New.
1156 (i386_opcode_modifier): Add notrackprefixok.
1157 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1159 * i386-tbl.h: Regenerated.
1161 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1163 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1165 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1166 bfd_mach_sparc_v9m8.
1167 (print_insn_sparc): Handle new operand types.
1168 * sparc-opc.c (MASK_M8): Define.
1170 (v6notlet): Likewise.
1181 (v9andleon): Likewise.
1184 (HWS2_VM8): Likewise.
1185 (sparc_opcode_archs): Add entry for "m8".
1186 (sparc_opcodes): Add OSA2017 and M8 instructions
1187 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1189 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1190 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1191 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1192 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1193 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1194 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1195 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1196 ASI_CORE_SELECT_COMMIT_NHT.
1198 2017-05-18 Alan Modra <amodra@gmail.com>
1200 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1201 * aarch64-dis.c: Likewise.
1202 * aarch64-gen.c: Likewise.
1203 * aarch64-opc.c: Likewise.
1205 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1206 Matthew Fortune <matthew.fortune@imgtec.com>
1208 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1209 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1210 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1211 (print_insn_arg) <OP_REG28>: Add handler.
1212 (validate_insn_args) <OP_REG28>: Handle.
1213 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1214 32-bit encoding and 9-bit immediates.
1215 (print_insn_mips16): Handle MIPS16 instructions that require
1216 32-bit encoding and MFC0/MTC0 operand decoding.
1217 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1218 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1219 (RD_C0, WR_C0, E2, E2MT): New macros.
1220 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1221 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1222 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1223 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1224 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1225 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1226 instructions, "swl", "swr", "sync" and its "sync_acquire",
1227 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1228 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1229 regular/extended entries for original MIPS16 ISA revision
1230 instructions whose extended forms are subdecoded in the MIPS16e2
1231 ISA revision: "li", "sll" and "srl".
1233 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1235 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1236 reference in CP0 move operand decoding.
1238 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1240 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1241 type to hexadecimal.
1242 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1244 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1246 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1247 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1248 "sync_rmb" and "sync_wmb" as aliases.
1249 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1250 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1252 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1254 * arc-dis.c (parse_option): Update quarkse_em option..
1255 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1257 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1259 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1261 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1263 2017-05-01 Michael Clark <michaeljclark@mac.com>
1265 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1268 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1270 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1271 and branches and not synthetic data instructions.
1273 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1275 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1277 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1279 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1280 * arc-opc.c (insert_r13el): New function.
1282 * arc-tbl.h: Add new enter/leave variants.
1284 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1286 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1288 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1290 * mips-dis.c (print_mips_disassembler_options): Add
1293 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1295 * mips16-opc.c (AL): New macro.
1296 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1297 of "ld" and "lw" as aliases.
1299 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1301 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1304 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1305 Alan Modra <amodra@gmail.com>
1307 * ppc-opc.c (ELEV): Define.
1308 (vle_opcodes): Add se_rfgi and e_sc.
1309 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1312 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1314 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1316 2017-04-21 Nick Clifton <nickc@redhat.com>
1319 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1322 2017-04-13 Alan Modra <amodra@gmail.com>
1324 * epiphany-desc.c: Regenerate.
1325 * fr30-desc.c: Regenerate.
1326 * frv-desc.c: Regenerate.
1327 * ip2k-desc.c: Regenerate.
1328 * iq2000-desc.c: Regenerate.
1329 * lm32-desc.c: Regenerate.
1330 * m32c-desc.c: Regenerate.
1331 * m32r-desc.c: Regenerate.
1332 * mep-desc.c: Regenerate.
1333 * mt-desc.c: Regenerate.
1334 * or1k-desc.c: Regenerate.
1335 * xc16x-desc.c: Regenerate.
1336 * xstormy16-desc.c: Regenerate.
1338 2017-04-11 Alan Modra <amodra@gmail.com>
1340 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1341 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1342 PPC_OPCODE_TMR for e6500.
1343 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1344 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1345 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1346 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1347 (PPCHTM): Define as PPC_OPCODE_POWER8.
1348 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1350 2017-04-10 Alan Modra <amodra@gmail.com>
1352 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1353 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1354 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1355 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1357 2017-04-09 Pip Cet <pipcet@gmail.com>
1359 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1360 appropriate floating-point precision directly.
1362 2017-04-07 Alan Modra <amodra@gmail.com>
1364 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1365 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1366 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1367 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1368 vector instructions with E6500 not PPCVEC2.
1370 2017-04-06 Pip Cet <pipcet@gmail.com>
1372 * Makefile.am: Add wasm32-dis.c.
1373 * configure.ac: Add wasm32-dis.c to wasm32 target.
1374 * disassemble.c: Add wasm32 disassembler code.
1375 * wasm32-dis.c: New file.
1376 * Makefile.in: Regenerate.
1377 * configure: Regenerate.
1378 * po/POTFILES.in: Regenerate.
1379 * po/opcodes.pot: Regenerate.
1381 2017-04-05 Pedro Alves <palves@redhat.com>
1383 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1384 * arm-dis.c (parse_arm_disassembler_options): Constify.
1385 * ppc-dis.c (powerpc_init_dialect): Constify local.
1386 * vax-dis.c (parse_disassembler_options): Constify.
1388 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1390 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1393 2017-03-30 Pip Cet <pipcet@gmail.com>
1395 * configure.ac: Add (empty) bfd_wasm32_arch target.
1396 * configure: Regenerate
1397 * po/opcodes.pot: Regenerate.
1399 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1401 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1403 * opcodes/sparc-opc.c (asi_table): New ASIs.
1405 2017-03-29 Alan Modra <amodra@gmail.com>
1407 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1409 (lookup_powerpc): Don't special case -1 dialect. Handle
1411 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1412 lookup_powerpc call, pass it on second.
1414 2017-03-27 Alan Modra <amodra@gmail.com>
1417 * ppc-dis.c (struct ppc_mopt): Comment.
1418 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1420 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1422 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1423 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1424 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1425 (insert_nps_misc_imm_offset): New function.
1426 (extract_nps_misc imm_offset): New function.
1427 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1428 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1430 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1432 * s390-mkopc.c (main): Remove vx2 check.
1433 * s390-opc.txt: Remove vx2 instruction flags.
1435 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1437 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1438 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1439 (insert_nps_imm_offset): New function.
1440 (extract_nps_imm_offset): New function.
1441 (insert_nps_imm_entry): New function.
1442 (extract_nps_imm_entry): New function.
1444 2017-03-17 Alan Modra <amodra@gmail.com>
1447 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1448 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1449 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1451 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1453 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1457 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1459 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1461 2017-03-13 Andrew Waterman <andrew@sifive.com>
1463 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1468 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1470 * i386-gen.c (opcode_modifiers): Replace S with Load.
1471 * i386-opc.h (S): Removed.
1473 (i386_opcode_modifier): Replace s with load.
1474 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1475 and {evex}. Replace S with Load.
1476 * i386-tbl.h: Regenerated.
1478 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1480 * i386-opc.tbl: Use CpuCET on rdsspq.
1481 * i386-tbl.h: Regenerated.
1483 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1485 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1486 <vsx>: Do not use PPC_OPCODE_VSX3;
1488 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1490 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1492 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1494 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1495 (MOD_0F1E_PREFIX_1): Likewise.
1496 (MOD_0F38F5_PREFIX_2): Likewise.
1497 (MOD_0F38F6_PREFIX_0): Likewise.
1498 (RM_0F1E_MOD_3_REG_7): Likewise.
1499 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1500 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1501 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1502 (PREFIX_0F1E): Likewise.
1503 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1504 (PREFIX_0F38F5): Likewise.
1505 (dis386_twobyte): Use PREFIX_0F1E.
1506 (reg_table): Add REG_0F1E_MOD_3.
1507 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1508 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1509 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1510 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1511 (three_byte_table): Use PREFIX_0F38F5.
1512 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1513 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1514 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1515 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1516 PREFIX_MOD_3_0F01_REG_5_RM_2.
1517 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1518 (cpu_flags): Add CpuCET.
1519 * i386-opc.h (CpuCET): New enum.
1520 (CpuUnused): Commented out.
1521 (i386_cpu_flags): Add cpucet.
1522 * i386-opc.tbl: Add Intel CET instructions.
1523 * i386-init.h: Regenerated.
1524 * i386-tbl.h: Likewise.
1526 2017-03-06 Alan Modra <amodra@gmail.com>
1529 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1530 (extract_raq, extract_ras, extract_rbx): New functions.
1531 (powerpc_operands): Use opposite corresponding insert function.
1533 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1534 register restriction.
1536 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1538 * disassemble.c Include "safe-ctype.h".
1539 (disassemble_init_for_target): Handle s390 init.
1540 (remove_whitespace_and_extra_commas): New function.
1541 (disassembler_options_cmp): Likewise.
1542 * arm-dis.c: Include "libiberty.h".
1544 (regnames): Use long disassembler style names.
1545 Add force-thumb and no-force-thumb options.
1546 (NUM_ARM_REGNAMES): Rename from this...
1547 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1548 (get_arm_regname_num_options): Delete.
1549 (set_arm_regname_option): Likewise.
1550 (get_arm_regnames): Likewise.
1551 (parse_disassembler_options): Likewise.
1552 (parse_arm_disassembler_option): Rename from this...
1553 (parse_arm_disassembler_options): ...to this. Make static.
1554 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1555 (print_insn): Use parse_arm_disassembler_options.
1556 (disassembler_options_arm): New function.
1557 (print_arm_disassembler_options): Handle updated regnames.
1558 * ppc-dis.c: Include "libiberty.h".
1559 (ppc_opts): Add "32" and "64" entries.
1560 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1561 (powerpc_init_dialect): Add break to switch statement.
1562 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1563 (disassembler_options_powerpc): New function.
1564 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1565 Remove printing of "32" and "64".
1566 * s390-dis.c: Include "libiberty.h".
1567 (init_flag): Remove unneeded variable.
1568 (struct s390_options_t): New structure type.
1569 (options): New structure.
1570 (init_disasm): Rename from this...
1571 (disassemble_init_s390): ...to this. Add initializations for
1572 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1573 (print_insn_s390): Delete call to init_disasm.
1574 (disassembler_options_s390): New function.
1575 (print_s390_disassembler_options): Print using information from
1577 * po/opcodes.pot: Regenerate.
1579 2017-02-28 Jan Beulich <jbeulich@suse.com>
1581 * i386-dis.c (PCMPESTR_Fixup): New.
1582 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1583 (prefix_table): Use PCMPESTR_Fixup.
1584 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1586 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1587 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1588 Split 64-bit and non-64-bit variants.
1589 * opcodes/i386-tbl.h: Re-generate.
1591 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1593 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1594 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1595 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1596 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1597 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1598 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1599 (OP_SVE_V_HSD): New macros.
1600 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1601 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1602 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1603 (aarch64_opcode_table): Add new SVE instructions.
1604 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1605 for rotation operands. Add new SVE operands.
1606 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1607 (ins_sve_quad_index): Likewise.
1608 (ins_imm_rotate): Split into...
1609 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1610 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1611 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1613 (aarch64_ins_sve_addr_ri_s4): New function.
1614 (aarch64_ins_sve_quad_index): Likewise.
1615 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1616 * aarch64-asm-2.c: Regenerate.
1617 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1618 (ext_sve_quad_index): Likewise.
1619 (ext_imm_rotate): Split into...
1620 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1621 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1622 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1624 (aarch64_ext_sve_addr_ri_s4): New function.
1625 (aarch64_ext_sve_quad_index): Likewise.
1626 (aarch64_ext_sve_index): Allow quad indices.
1627 (do_misc_decoding): Likewise.
1628 * aarch64-dis-2.c: Regenerate.
1629 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1630 aarch64_field_kinds.
1631 (OPD_F_OD_MASK): Widen by one bit.
1632 (OPD_F_NO_ZR): Bump accordingly.
1633 (get_operand_field_width): New function.
1634 * aarch64-opc.c (fields): Add new SVE fields.
1635 (operand_general_constraint_met_p): Handle new SVE operands.
1636 (aarch64_print_operand): Likewise.
1637 * aarch64-opc-2.c: Regenerate.
1639 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1641 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1642 (aarch64_feature_compnum): ...this.
1643 (SIMD_V8_3): Replace with...
1645 (CNUM_INSN): New macro.
1646 (aarch64_opcode_table): Use it for the complex number instructions.
1648 2017-02-24 Jan Beulich <jbeulich@suse.com>
1650 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1652 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1654 Add support for associating SPARC ASIs with an architecture level.
1655 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1656 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1657 decoding of SPARC ASIs.
1659 2017-02-23 Jan Beulich <jbeulich@suse.com>
1661 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1662 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1664 2017-02-21 Jan Beulich <jbeulich@suse.com>
1666 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1667 1 (instead of to itself). Correct typo.
1669 2017-02-14 Andrew Waterman <andrew@sifive.com>
1671 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1674 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1676 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1677 (aarch64_sys_reg_supported_p): Handle them.
1679 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1681 * arc-opc.c (UIMM6_20R): Define.
1682 (SIMM12_20): Use above.
1683 (SIMM12_20R): Define.
1684 (SIMM3_5_S): Use above.
1685 (UIMM7_A32_11R_S): Define.
1686 (UIMM7_9_S): Use above.
1687 (UIMM3_13R_S): Define.
1688 (SIMM11_A32_7_S): Use above.
1690 (UIMM10_A32_8_S): Use above.
1691 (UIMM8_8R_S): Define.
1693 (arc_relax_opcodes): Use all above defines.
1695 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1697 * arc-regs.h: Distinguish some of the registers different on
1698 ARC700 and HS38 cpus.
1700 2017-02-14 Alan Modra <amodra@gmail.com>
1703 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1704 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1706 2017-02-11 Stafford Horne <shorne@gmail.com>
1707 Alan Modra <amodra@gmail.com>
1709 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1710 Use insn_bytes_value and insn_int_value directly instead. Don't
1711 free allocated memory until function exit.
1713 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1715 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1717 2017-02-03 Nick Clifton <nickc@redhat.com>
1720 * aarch64-opc.c (print_register_list): Ensure that the register
1721 list index will fir into the tb buffer.
1722 (print_register_offset_address): Likewise.
1723 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1725 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1728 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1729 instructions when the previous fetch packet ends with a 32-bit
1732 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1734 * pru-opc.c: Remove vague reference to a future GDB port.
1736 2017-01-20 Nick Clifton <nickc@redhat.com>
1738 * po/ga.po: Updated Irish translation.
1740 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1742 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1744 2017-01-13 Yao Qi <yao.qi@linaro.org>
1746 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1747 if FETCH_DATA returns 0.
1748 (m68k_scan_mask): Likewise.
1749 (print_insn_m68k): Update code to handle -1 return value.
1751 2017-01-13 Yao Qi <yao.qi@linaro.org>
1753 * m68k-dis.c (enum print_insn_arg_error): New.
1754 (NEXTBYTE): Replace -3 with
1755 PRINT_INSN_ARG_MEMORY_ERROR.
1756 (NEXTULONG): Likewise.
1757 (NEXTSINGLE): Likewise.
1758 (NEXTDOUBLE): Likewise.
1759 (NEXTDOUBLE): Likewise.
1760 (NEXTPACKED): Likewise.
1761 (FETCH_ARG): Likewise.
1762 (FETCH_DATA): Update comments.
1763 (print_insn_arg): Update comments. Replace magic numbers with
1765 (match_insn_m68k): Likewise.
1767 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1769 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1770 * i386-dis-evex.h (evex_table): Updated.
1771 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1772 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1773 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1774 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1775 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1776 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1777 * i386-init.h: Regenerate.
1778 * i386-tbl.h: Ditto.
1780 2017-01-12 Yao Qi <yao.qi@linaro.org>
1782 * msp430-dis.c (msp430_singleoperand): Return -1 if
1783 msp430dis_opcode_signed returns false.
1784 (msp430_doubleoperand): Likewise.
1785 (msp430_branchinstr): Return -1 if
1786 msp430dis_opcode_unsigned returns false.
1787 (msp430x_calla_instr): Likewise.
1788 (print_insn_msp430): Likewise.
1790 2017-01-05 Nick Clifton <nickc@redhat.com>
1793 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1794 could not be matched.
1795 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1798 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1800 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1801 (aarch64_opcode_table): Use RCPC_INSN.
1803 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1805 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1807 * riscv-opcodes/all-opcodes: Likewise.
1809 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1811 * riscv-dis.c (print_insn_args): Add fall through comment.
1813 2017-01-03 Nick Clifton <nickc@redhat.com>
1815 * po/sr.po: New Serbian translation.
1816 * configure.ac (ALL_LINGUAS): Add sr.
1817 * configure: Regenerate.
1819 2017-01-02 Alan Modra <amodra@gmail.com>
1821 * epiphany-desc.h: Regenerate.
1822 * epiphany-opc.h: Regenerate.
1823 * fr30-desc.h: Regenerate.
1824 * fr30-opc.h: Regenerate.
1825 * frv-desc.h: Regenerate.
1826 * frv-opc.h: Regenerate.
1827 * ip2k-desc.h: Regenerate.
1828 * ip2k-opc.h: Regenerate.
1829 * iq2000-desc.h: Regenerate.
1830 * iq2000-opc.h: Regenerate.
1831 * lm32-desc.h: Regenerate.
1832 * lm32-opc.h: Regenerate.
1833 * m32c-desc.h: Regenerate.
1834 * m32c-opc.h: Regenerate.
1835 * m32r-desc.h: Regenerate.
1836 * m32r-opc.h: Regenerate.
1837 * mep-desc.h: Regenerate.
1838 * mep-opc.h: Regenerate.
1839 * mt-desc.h: Regenerate.
1840 * mt-opc.h: Regenerate.
1841 * or1k-desc.h: Regenerate.
1842 * or1k-opc.h: Regenerate.
1843 * xc16x-desc.h: Regenerate.
1844 * xc16x-opc.h: Regenerate.
1845 * xstormy16-desc.h: Regenerate.
1846 * xstormy16-opc.h: Regenerate.
1848 2017-01-02 Alan Modra <amodra@gmail.com>
1850 Update year range in copyright notice of all files.
1852 For older changes see ChangeLog-2016
1854 Copyright (C) 2017 Free Software Foundation, Inc.
1856 Copying and distribution of this file, with or without modification,
1857 are permitted in any medium without royalty provided the copyright
1858 notice and this notice are preserved.
1864 version-control: never