2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
37 abi16_chan_nv04(struct nouveau_object *obj)
39 struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
40 struct nv04_fifo *nv04 = obj->data;
41 struct drm_nouveau_channel_alloc req = {nv04->vram, nv04->gart};
44 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
49 nv04->base.channel = req.channel;
50 nv04->base.pushbuf = req.pushbuf_domains;
51 nv04->notify = req.notifier_handle;
52 nv04->base.object->handle = req.channel;
53 nv04->base.object->length = sizeof(*nv04);
58 abi16_chan_nvc0(struct nouveau_object *obj)
60 struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
61 struct drm_nouveau_channel_alloc req = {};
62 struct nvc0_fifo *nvc0 = obj->data;
65 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
70 nvc0->base.channel = req.channel;
71 nvc0->base.pushbuf = req.pushbuf_domains;
72 nvc0->notify = req.notifier_handle;
73 nvc0->base.object->handle = req.channel;
74 nvc0->base.object->length = sizeof(*nvc0);
79 abi16_chan_nve0(struct nouveau_object *obj)
81 struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
82 struct drm_nouveau_channel_alloc req = {};
83 struct nve0_fifo *nve0 = obj->data;
86 if (obj->length > offsetof(struct nve0_fifo, engine)) {
87 req.fb_ctxdma_handle = 0xffffffff;
88 req.tt_ctxdma_handle = nve0->engine;
91 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
96 nve0->base.channel = req.channel;
97 nve0->base.pushbuf = req.pushbuf_domains;
98 nve0->notify = req.notifier_handle;
99 nve0->base.object->handle = req.channel;
100 nve0->base.object->length = sizeof(*nve0);
105 abi16_engobj(struct nouveau_object *obj)
107 struct drm_nouveau_grobj_alloc req = {
108 obj->parent->handle, obj->handle, obj->oclass
110 struct nouveau_device *dev;
113 dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS);
114 ret = drmCommandWrite(dev->fd, DRM_NOUVEAU_GROBJ_ALLOC,
119 obj->length = sizeof(struct nouveau_object *);
124 abi16_ntfy(struct nouveau_object *obj)
126 struct nv04_notify *ntfy = obj->data;
127 struct drm_nouveau_notifierobj_alloc req = {
128 obj->parent->handle, ntfy->object->handle, ntfy->length
130 struct nouveau_device *dev;
133 dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS);
134 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC,
139 ntfy->offset = req.offset;
140 ntfy->object->length = sizeof(*ntfy);
145 abi16_bo_info(struct nouveau_bo *bo, struct drm_nouveau_gem_info *info)
147 struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
149 nvbo->map_handle = info->map_handle;
150 bo->handle = info->handle;
151 bo->size = info->size;
152 bo->offset = info->offset;
155 if (info->domain & NOUVEAU_GEM_DOMAIN_VRAM)
156 bo->flags |= NOUVEAU_BO_VRAM;
157 if (info->domain & NOUVEAU_GEM_DOMAIN_GART)
158 bo->flags |= NOUVEAU_BO_GART;
159 if (!(info->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG))
160 bo->flags |= NOUVEAU_BO_CONTIG;
161 if (nvbo->map_handle)
162 bo->flags |= NOUVEAU_BO_MAP;
164 if (bo->device->chipset >= 0xc0) {
165 bo->config.nvc0.memtype = (info->tile_flags & 0xff00) >> 8;
166 bo->config.nvc0.tile_mode = info->tile_mode;
168 if (bo->device->chipset >= 0x80 || bo->device->chipset == 0x50) {
169 bo->config.nv50.memtype = (info->tile_flags & 0x07f00) >> 8 |
170 (info->tile_flags & 0x30000) >> 9;
171 bo->config.nv50.tile_mode = info->tile_mode << 4;
173 bo->config.nv04.surf_flags = info->tile_flags & 7;
174 bo->config.nv04.surf_pitch = info->tile_mode;
179 abi16_bo_init(struct nouveau_bo *bo, uint32_t alignment,
180 union nouveau_bo_config *config)
182 struct nouveau_device *dev = bo->device;
183 struct drm_nouveau_gem_new req = {};
184 struct drm_nouveau_gem_info *info = &req.info;
187 if (bo->flags & NOUVEAU_BO_VRAM)
188 info->domain |= NOUVEAU_GEM_DOMAIN_VRAM;
189 if (bo->flags & NOUVEAU_BO_GART)
190 info->domain |= NOUVEAU_GEM_DOMAIN_GART;
192 info->domain |= NOUVEAU_GEM_DOMAIN_VRAM |
193 NOUVEAU_GEM_DOMAIN_GART;
195 if (bo->flags & NOUVEAU_BO_MAP)
196 info->domain |= NOUVEAU_GEM_DOMAIN_MAPPABLE;
198 if (!(bo->flags & NOUVEAU_BO_CONTIG))
199 info->tile_flags = NOUVEAU_GEM_TILE_NONCONTIG;
201 info->size = bo->size;
202 req.align = alignment;
205 if (dev->chipset >= 0xc0) {
206 info->tile_flags = (config->nvc0.memtype & 0xff) << 8;
207 info->tile_mode = config->nvc0.tile_mode;
209 if (dev->chipset >= 0x80 || dev->chipset == 0x50) {
210 info->tile_flags = (config->nv50.memtype & 0x07f) << 8 |
211 (config->nv50.memtype & 0x180) << 9;
212 info->tile_mode = config->nv50.tile_mode >> 4;
214 info->tile_flags = config->nv04.surf_flags & 7;
215 info->tile_mode = config->nv04.surf_pitch;
219 if (!nouveau_device(dev)->have_bo_usage)
220 info->tile_flags &= 0x0000ff00;
222 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_GEM_NEW,
225 abi16_bo_info(bo, &req.info);