2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
31 abi16_chan_nv04(struct nouveau_object *obj)
33 struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
34 struct drm_nouveau_channel_alloc req;
35 struct nv04_fifo *nv04 = obj->data;
38 req.fb_ctxdma_handle = nv04->vram;
39 req.tt_ctxdma_handle = nv04->gart;
41 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
46 nv04->base.channel = req.channel;
47 nv04->base.pushbuf = req.pushbuf_domains;
48 nv04->notify = req.notifier_handle;
49 nv04->base.object->handle = req.channel;
50 nv04->base.object->length = sizeof(*nv04);
55 abi16_chan_nvc0(struct nouveau_object *obj)
57 struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
58 struct drm_nouveau_channel_alloc req;
59 struct nvc0_fifo *nvc0 = obj->data;
62 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
67 nvc0->base.channel = req.channel;
68 nvc0->base.pushbuf = req.pushbuf_domains;
69 nvc0->base.object->handle = req.channel;
70 nvc0->base.object->length = sizeof(*nvc0);
75 abi16_engobj(struct nouveau_object *obj)
77 struct drm_nouveau_grobj_alloc req = {
78 obj->parent->handle, obj->handle, obj->oclass
80 struct nouveau_device *dev;
83 dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS);
84 ret = drmCommandWrite(dev->fd, DRM_NOUVEAU_GROBJ_ALLOC,
89 obj->length = sizeof(struct nouveau_object *);
94 abi16_ntfy(struct nouveau_object *obj)
96 struct nv04_notify *ntfy = obj->data;
97 struct drm_nouveau_notifierobj_alloc req = {
98 obj->parent->handle, ntfy->object->handle, ntfy->length
100 struct nouveau_device *dev;
103 dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS);
104 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC,
109 ntfy->offset = req.offset;
110 ntfy->object->length = sizeof(*ntfy);
115 abi16_bo_info(struct nouveau_bo *bo, struct drm_nouveau_gem_info *info)
117 struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
119 nvbo->map_handle = info->map_handle;
120 bo->handle = info->handle;
121 bo->size = info->size;
122 bo->offset = info->offset;
125 if (info->domain & NOUVEAU_GEM_DOMAIN_VRAM)
126 bo->flags |= NOUVEAU_BO_VRAM;
127 if (info->domain & NOUVEAU_GEM_DOMAIN_GART)
128 bo->flags |= NOUVEAU_BO_GART;
129 if (!(info->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG))
130 bo->flags |= NOUVEAU_BO_CONTIG;
131 if (nvbo->map_handle)
132 bo->flags |= NOUVEAU_BO_MAP;
134 if (bo->device->chipset >= 0xc0) {
135 bo->config.nvc0.memtype = (info->tile_flags & 0xff00) >> 8;
136 bo->config.nvc0.tile_mode = info->tile_mode;
138 if (bo->device->chipset >= 0x80 || bo->device->chipset == 0x50) {
139 bo->config.nv50.memtype = (info->tile_flags & 0x07f00) >> 8 |
140 (info->tile_flags & 0x30000) >> 9;
141 bo->config.nv50.tile_mode = info->tile_mode << 4;
143 bo->config.nv04.surf_flags = info->tile_flags & 7;
144 bo->config.nv04.surf_pitch = info->tile_mode;
149 abi16_bo_init(struct nouveau_bo *bo, uint32_t alignment,
150 union nouveau_bo_config *config)
152 struct nouveau_device *dev = bo->device;
153 struct drm_nouveau_gem_new req = {};
154 struct drm_nouveau_gem_info *info = &req.info;
157 if (bo->flags & NOUVEAU_BO_VRAM)
158 info->domain |= NOUVEAU_GEM_DOMAIN_VRAM;
159 if (bo->flags & NOUVEAU_BO_GART)
160 info->domain |= NOUVEAU_GEM_DOMAIN_GART;
162 info->domain |= NOUVEAU_GEM_DOMAIN_VRAM |
163 NOUVEAU_GEM_DOMAIN_GART;
165 if (bo->flags & NOUVEAU_BO_MAP)
166 info->domain |= NOUVEAU_GEM_DOMAIN_MAPPABLE;
168 if (!(bo->flags & NOUVEAU_BO_CONTIG))
169 info->tile_flags = NOUVEAU_GEM_TILE_NONCONTIG;
171 info->size = bo->size;
172 req.align = alignment;
175 if (dev->chipset >= 0xc0) {
176 info->tile_flags = (config->nvc0.memtype & 0xff) << 8;
177 info->tile_mode = config->nvc0.tile_mode;
179 if (dev->chipset >= 0x80 || dev->chipset == 0x50) {
180 info->tile_flags = (config->nv50.memtype & 0x07f) << 8 |
181 (config->nv50.memtype & 0x180) << 9;
182 info->tile_mode = config->nv50.tile_mode >> 4;
184 info->tile_flags = config->nv04.surf_flags & 7;
185 info->tile_mode = config->nv04.surf_pitch;
189 if (!nouveau_device(dev)->have_bo_usage)
190 info->tile_flags &= 0x0000ff00;
192 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_GEM_NEW,
195 abi16_bo_info(bo, &req.info);