1 // SPDX-License-Identifier: GPL-2.0+
3 * rtl8169.c : U-Boot driver for the RealTek RTL8169
5 * Masami Komiya (mkomiya@sonare.it)
7 * Most part is taken from r8169.c of etherboot
11 /**************************************************************************
12 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
13 * Written 2003 by Timothy Legge <tlegge@rogers.com>
15 * Portions of this code based on:
16 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
17 * for Linux kernel 2.4.x.
19 * Written 2002 ShuChen <shuchen@realtek.com.tw>
20 * See Linux Driver for full information
22 * Linux Driver Version 1.27a, 10.02.2002
25 * Jean Chen of RealTek Semiconductor Corp. for
26 * providing the evaluation NIC used to develop
27 * this driver. RealTek's support for Etherboot
33 * v1.0 11-26-2003 timlegge Initial port of Linux driver
34 * v1.5 01-17-2004 timlegge Initial driver output cleanup
36 * Indent Options: indent -kr -i8
37 ***************************************************************************/
39 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
40 * Modified to use le32_to_cpu and cpu_to_le32 properly
50 #include <asm/cache.h>
53 #include <linux/delay.h>
56 #undef DEBUG_RTL8169_TX
57 #undef DEBUG_RTL8169_RX
59 #define drv_version "v1.5"
60 #define drv_date "01-17-2004"
62 static unsigned long ioaddr;
64 /* Condensed operations for readability. */
65 #define currticks() get_timer(0)
69 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
71 /* MAC address length*/
72 #define MAC_ADDR_LEN 6
74 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
75 #define MAX_ETH_FRAME_SIZE 1536
77 #define TX_FIFO_THRESH 256 /* In bytes */
79 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
83 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
84 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
86 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
87 #ifdef CONFIG_SYS_RX_ETH_BUFFER
88 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
90 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
92 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
93 #define RX_BUF_LEN 8192
95 #define RTL_MIN_IO_SIZE 0x80
96 #define TX_TIMEOUT (6*HZ)
98 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
99 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
100 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
101 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
102 #define RTL_R8(reg) readb(ioaddr + (reg))
103 #define RTL_R16(reg) readw(ioaddr + (reg))
104 #define RTL_R32(reg) readl(ioaddr + (reg))
106 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
107 (pci_addr_t)(unsigned long)a)
108 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
111 enum RTL8169_registers {
112 MAC0 = 0, /* Ethernet hardware address. */
113 MAR0 = 8, /* Multicast filter. */
114 TxDescStartAddrLow = 0x20,
115 TxDescStartAddrHigh = 0x24,
116 TxHDescStartAddrLow = 0x28,
117 TxHDescStartAddrHigh = 0x2c,
142 RxDescStartAddrLow = 0xE4,
143 RxDescStartAddrHigh = 0xE8,
146 FuncEventMask = 0xF4,
147 FuncPresetState = 0xF8,
148 FuncForceEvent = 0xFC,
151 enum RTL8169_register_content {
152 /*InterruptStatusBits */
156 TxDescUnavail = 0x80,
179 Cfg9346_Unlock = 0xC0,
184 AcceptBroadcast = 0x08,
185 AcceptMulticast = 0x04,
187 AcceptAllPhys = 0x01,
194 TxInterFrameGapShift = 24,
195 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
197 /*rtl8169_PHYstatus */
207 /*GIGABIT_PHY_registers */
210 PHY_AUTO_NEGO_REG = 4,
211 PHY_1000_CTRL_REG = 9,
213 /*GIGABIT_PHY_REG_BIT */
214 PHY_Restart_Auto_Nego = 0x0200,
215 PHY_Enable_Auto_Nego = 0x1000,
217 /* PHY_STAT_REG = 1; */
218 PHY_Auto_Nego_Comp = 0x0020,
220 /* PHY_AUTO_NEGO_REG = 4; */
221 PHY_Cap_10_Half = 0x0020,
222 PHY_Cap_10_Full = 0x0040,
223 PHY_Cap_100_Half = 0x0080,
224 PHY_Cap_100_Full = 0x0100,
226 /* PHY_1000_CTRL_REG = 9; */
227 PHY_Cap_1000_Full = 0x0200,
239 TBILinkOK = 0x02000000,
242 RxDv_Gated_En = 0x80000,
247 u8 version; /* depend on RTL8169 docs */
248 u32 RxConfigMask; /* should clear the bits supported by this chip */
249 } rtl_chip_info[] = {
250 {"RTL-8169", 0x00, 0xff7e1880,},
251 {"RTL-8169", 0x04, 0xff7e1880,},
252 {"RTL-8169", 0x00, 0xff7e1880,},
253 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
254 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
255 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
256 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
257 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
258 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
259 {"RTL-8168c/8111c", 0x3c, 0xff7e1880,},
260 {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
261 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
262 {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
263 {"RTL-8101e", 0x34, 0xff7e1880,},
264 {"RTL-8100e", 0x32, 0xff7e1880,},
265 {"RTL-8168h/8111h", 0x54, 0xff7e1880,},
268 enum _DescStatusBit {
289 static unsigned char rxdata[RX_BUF_LEN];
291 #define RTL8169_DESC_SIZE 16
293 #if ARCH_DMA_MINALIGN > 256
294 # define RTL8169_ALIGN ARCH_DMA_MINALIGN
296 # define RTL8169_ALIGN 256
300 * Warn if the cache-line size is larger than the descriptor size. In such
301 * cases the driver will likely fail because the CPU needs to flush the cache
302 * when requeuing RX buffers, therefore descriptors written by the hardware
305 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
306 * the driver to allocate descriptors from a pool of non-cached memory.
308 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
309 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
310 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
311 #warning cache-line size is larger than descriptor size
316 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
317 * descriptors point to a part of this buffer.
319 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
322 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
323 * descriptors point to a part of this buffer.
325 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
327 struct rtl8169_private {
329 void *mmio_addr; /* memory map physical address */
331 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
332 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
333 unsigned long dirty_tx;
334 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
335 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
336 unsigned char *RxBufferRings; /* Index of Rx Buffer */
337 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
338 unsigned char *Tx_skbuff[NUM_TX_DESC];
341 static struct rtl8169_private *tpc;
343 static const unsigned int rtl8169_rx_config =
344 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
346 static struct pci_device_id supported[] = {
347 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
348 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
349 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
353 void mdio_write(int RegAddr, int value)
357 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
360 for (i = 2000; i > 0; i--) {
361 /* Check if the RTL8169 has completed writing to the specified MII register */
362 if (!(RTL_R32(PHYAR) & 0x80000000)) {
370 int mdio_read(int RegAddr)
374 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
377 for (i = 2000; i > 0; i--) {
378 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
379 if (RTL_R32(PHYAR) & 0x80000000) {
380 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
389 static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
395 printf ("%s\n", __FUNCTION__);
399 /* Soft reset the chip. */
400 RTL_W8(ChipCmd, CmdReset);
402 /* Check that the chip has finished the reset. */
403 for (i = 1000; i > 0; i--)
404 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
409 /* identify chip attached to board */
410 tmp = RTL_R32(TxConfig);
411 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
413 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
414 if (tmp == rtl_chip_info[i].version) {
420 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
421 printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
423 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
431 * TX and RX descriptors are 16 bytes. This causes problems with the cache
432 * maintenance on CPUs where the cache-line size exceeds the size of these
433 * descriptors. What will happen is that when the driver receives a packet
434 * it will be immediately requeued for the hardware to reuse. The CPU will
435 * therefore need to flush the cache-line containing the descriptor, which
436 * will cause all other descriptors in the same cache-line to be flushed
437 * along with it. If one of those descriptors had been written to by the
438 * device those changes (and the associated packet) will be lost.
440 * To work around this, we make use of non-cached memory if available. If
441 * descriptors are mapped uncached there's no need to manually flush them
442 * or invalidate them.
444 * Note that this only applies to descriptors. The packet data buffers do
445 * not have the same constraints since they are 1536 bytes large, so they
446 * are unlikely to share cache-lines.
448 static void *rtl_alloc_descs(unsigned int num)
450 size_t size = num * RTL8169_DESC_SIZE;
452 #ifdef CONFIG_SYS_NONCACHED_MEMORY
453 return (void *)noncached_alloc(size, RTL8169_ALIGN);
455 return memalign(RTL8169_ALIGN, size);
460 * Cache maintenance functions. These are simple wrappers around the more
461 * general purpose flush_cache() and invalidate_dcache_range() functions.
464 static void rtl_inval_rx_desc(struct RxDesc *desc)
466 #ifndef CONFIG_SYS_NONCACHED_MEMORY
467 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
468 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
470 invalidate_dcache_range(start, end);
474 static void rtl_flush_rx_desc(struct RxDesc *desc)
476 #ifndef CONFIG_SYS_NONCACHED_MEMORY
477 flush_cache((unsigned long)desc, sizeof(*desc));
481 static void rtl_inval_tx_desc(struct TxDesc *desc)
483 #ifndef CONFIG_SYS_NONCACHED_MEMORY
484 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
485 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
487 invalidate_dcache_range(start, end);
491 static void rtl_flush_tx_desc(struct TxDesc *desc)
493 #ifndef CONFIG_SYS_NONCACHED_MEMORY
494 flush_cache((unsigned long)desc, sizeof(*desc));
498 static void rtl_inval_buffer(void *buf, size_t size)
500 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
501 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
503 invalidate_dcache_range(start, end);
506 static void rtl_flush_buffer(void *buf, size_t size)
508 flush_cache((unsigned long)buf, size);
511 /**************************************************************************
512 RECV - Receive a frame
513 ***************************************************************************/
514 static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
517 /* return true if there's an ethernet packet ready to read */
518 /* nic->packet should contain data on return */
519 /* nic->packetlen should contain length of data */
523 #ifdef DEBUG_RTL8169_RX
524 printf ("%s\n", __FUNCTION__);
528 cur_rx = tpc->cur_rx;
530 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
532 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
533 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
534 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
535 status) & 0x00001FFF) - 4;
537 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
538 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
540 if (cur_rx == NUM_RX_DESC - 1)
541 tpc->RxDescArray[cur_rx].status =
542 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
544 tpc->RxDescArray[cur_rx].status =
545 cpu_to_le32(OWNbit + RX_BUF_SIZE);
546 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
547 dm_pci_mem_to_phys(dev,
548 (pci_addr_t)(unsigned long)
549 tpc->RxBufferRing[cur_rx]));
550 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
556 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
557 tpc->cur_rx = cur_rx;
561 ushort sts = RTL_R8(IntrStatus);
562 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
563 udelay(100); /* wait */
565 tpc->cur_rx = cur_rx;
566 return (0); /* initially as this is called to flush the input */
569 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
571 struct rtl8169_private *priv = dev_get_priv(dev);
573 return rtl_recv_common(dev, priv->iobase, packetp);
577 /**************************************************************************
578 SEND - Transmit a frame
579 ***************************************************************************/
580 static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
581 void *packet, int length)
583 /* send the packet to destination */
587 int entry = tpc->cur_tx % NUM_TX_DESC;
591 #ifdef DEBUG_RTL8169_TX
592 int stime = currticks();
593 printf ("%s\n", __FUNCTION__);
594 printf("sending %d bytes\n", len);
599 /* point to the current txb incase multiple tx_rings are used */
600 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
601 memcpy(ptxb, (char *)packet, (int)length);
603 while (len < ETH_ZLEN)
606 rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
608 tpc->TxDescArray[entry].buf_Haddr = 0;
609 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
610 dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
611 if (entry != (NUM_TX_DESC - 1)) {
612 tpc->TxDescArray[entry].status =
613 cpu_to_le32((OWNbit | FSbit | LSbit) |
614 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
616 tpc->TxDescArray[entry].status =
617 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
618 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
620 rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
621 RTL_W8(TxPoll, 0x40); /* set polling bit */
624 to = currticks() + TX_TIMEOUT;
626 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
627 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
628 && (currticks() < to)); /* wait */
630 if (currticks() >= to) {
631 #ifdef DEBUG_RTL8169_TX
632 puts("tx timeout/error\n");
633 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
637 #ifdef DEBUG_RTL8169_TX
642 /* Delay to make net console (nc) work properly */
647 int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
649 struct rtl8169_private *priv = dev_get_priv(dev);
651 return rtl_send_common(dev, priv->iobase, packet, length);
654 static void rtl8169_set_rx_mode(void)
656 u32 mc_filter[2]; /* Multicast hash filter */
661 printf ("%s\n", __FUNCTION__);
665 /* Too many to filter perfectly -- accept all multicasts. */
666 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
667 mc_filter[1] = mc_filter[0] = 0xffffffff;
669 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
670 rtl_chip_info[tpc->chipset].RxConfigMask);
672 RTL_W32(RxConfig, tmp);
673 RTL_W32(MAR0 + 0, mc_filter[0]);
674 RTL_W32(MAR0 + 4, mc_filter[1]);
677 static void rtl8169_hw_start(struct udevice *dev)
682 int stime = currticks();
683 printf ("%s\n", __FUNCTION__);
687 /* Soft reset the chip. */
688 RTL_W8(ChipCmd, CmdReset);
690 /* Check that the chip has finished the reset. */
691 for (i = 1000; i > 0; i--) {
692 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
699 RTL_W8(Cfg9346, Cfg9346_Unlock);
701 /* RTL-8169sb/8110sb or previous version */
702 if (tpc->chipset <= 5)
703 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
705 RTL_W8(EarlyTxThres, EarlyTxThld);
707 /* For gigabit rtl8169 */
708 RTL_W16(RxMaxSize, RxPacketMaxSize);
710 /* Set Rx Config register */
711 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
712 rtl_chip_info[tpc->chipset].RxConfigMask);
713 RTL_W32(RxConfig, i);
715 /* Set DMA burst size and Interframe Gap Time */
716 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
717 (InterFrameGap << TxInterFrameGapShift));
722 RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
723 (pci_addr_t)(unsigned long)tpc->TxDescArray));
724 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
725 RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
726 dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
727 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
729 /* RTL-8169sc/8110sc or later version */
730 if (tpc->chipset > 5)
731 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
733 RTL_W8(Cfg9346, Cfg9346_Lock);
736 RTL_W32(RxMissed, 0);
738 rtl8169_set_rx_mode();
740 /* no early-rx interrupts */
741 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
744 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
748 static void rtl8169_init_ring(struct udevice *dev)
753 int stime = currticks();
754 printf ("%s\n", __FUNCTION__);
760 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
761 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
763 for (i = 0; i < NUM_TX_DESC; i++) {
764 tpc->Tx_skbuff[i] = &txb[i];
767 for (i = 0; i < NUM_RX_DESC; i++) {
768 if (i == (NUM_RX_DESC - 1))
769 tpc->RxDescArray[i].status =
770 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
772 tpc->RxDescArray[i].status =
773 cpu_to_le32(OWNbit + RX_BUF_SIZE);
775 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
776 tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
777 dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
778 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
782 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
786 static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
787 unsigned long dev_iobase)
792 int stime = currticks();
793 printf ("%s\n", __FUNCTION__);
798 rtl8169_init_ring(dev);
799 rtl8169_hw_start(dev);
800 /* Construct a perfect filter frame with the mac address as first match
801 * and broadcast for all others */
802 for (i = 0; i < 192; i++)
805 txb[0] = enetaddr[0];
806 txb[1] = enetaddr[1];
807 txb[2] = enetaddr[2];
808 txb[3] = enetaddr[3];
809 txb[4] = enetaddr[4];
810 txb[5] = enetaddr[5];
813 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
817 static int rtl8169_eth_start(struct udevice *dev)
819 struct eth_pdata *plat = dev_get_plat(dev);
820 struct rtl8169_private *priv = dev_get_priv(dev);
822 rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
827 static void rtl_halt_common(unsigned long dev_iobase)
832 printf ("%s\n", __FUNCTION__);
837 /* Stop the chip's Tx and Rx DMA processes. */
838 RTL_W8(ChipCmd, 0x00);
840 /* Disable interrupts by clearing the interrupt mask. */
841 RTL_W16(IntrMask, 0x0000);
843 RTL_W32(RxMissed, 0);
845 for (i = 0; i < NUM_RX_DESC; i++) {
846 tpc->RxBufferRing[i] = NULL;
850 void rtl8169_eth_stop(struct udevice *dev)
852 struct rtl8169_private *priv = dev_get_priv(dev);
854 rtl_halt_common(priv->iobase);
857 static int rtl8169_write_hwaddr(struct udevice *dev)
859 struct eth_pdata *plat = dev_get_plat(dev);
862 RTL_W8(Cfg9346, Cfg9346_Unlock);
864 for (i = 0; i < MAC_ADDR_LEN; i++)
865 RTL_W8(MAC0 + i, plat->enetaddr[i]);
867 RTL_W8(Cfg9346, Cfg9346_Lock);
872 /**************************************************************************
873 INIT - Look for an adapter, this routine's visible to the outside
874 ***************************************************************************/
876 #define board_found 1
878 static int rtl_init(unsigned long dev_ioaddr, const char *name,
879 unsigned char *enetaddr)
881 static int board_idx = -1;
883 int option = -1, Cap10_100 = 0, Cap1000 = 0;
886 printf ("%s\n", __FUNCTION__);
892 /* point to private storage */
895 rc = rtl8169_init_board(ioaddr, name);
899 /* Get MAC address. FIXME: read EEPROM */
900 for (i = 0; i < MAC_ADDR_LEN; i++)
901 enetaddr[i] = RTL_R8(MAC0 + i);
904 printf("chipset = %d\n", tpc->chipset);
905 printf("MAC Address");
906 for (i = 0; i < MAC_ADDR_LEN; i++)
907 printf(":%02x", enetaddr[i]);
912 /* Print out some hardware info */
913 printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
916 /* if TBI is not endbled */
917 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
918 int val = mdio_read(PHY_AUTO_NEGO_REG);
920 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
921 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
924 printf("%s: Force-mode Enabled.\n", name);
926 Cap10_100 = 0, Cap1000 = 0;
929 Cap10_100 = PHY_Cap_10_Half;
930 Cap1000 = PHY_Cap_Null;
933 Cap10_100 = PHY_Cap_10_Full;
934 Cap1000 = PHY_Cap_Null;
937 Cap10_100 = PHY_Cap_100_Half;
938 Cap1000 = PHY_Cap_Null;
941 Cap10_100 = PHY_Cap_100_Full;
942 Cap1000 = PHY_Cap_Null;
945 Cap10_100 = PHY_Cap_Null;
946 Cap1000 = PHY_Cap_1000_Full;
951 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
952 mdio_write(PHY_1000_CTRL_REG, Cap1000);
955 printf("%s: Auto-negotiation Enabled.\n",
958 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
959 mdio_write(PHY_AUTO_NEGO_REG,
960 PHY_Cap_10_Half | PHY_Cap_10_Full |
961 PHY_Cap_100_Half | PHY_Cap_100_Full |
964 /* enable 1000 Full Mode */
965 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
969 /* Enable auto-negotiation and restart auto-nigotiation */
970 mdio_write(PHY_CTRL_REG,
971 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
974 /* wait for auto-negotiation process */
975 for (i = 10000; i > 0; i--) {
976 /* check if auto-negotiation complete */
977 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
979 option = RTL_R8(PHYstatus);
980 if (option & _1000bpsF) {
982 printf("%s: 1000Mbps Full-duplex operation.\n",
987 printf("%s: %sMbps %s-duplex operation.\n",
989 (option & _100bps) ? "100" :
991 (option & FullDup) ? "Full" :
999 } /* end for-loop to wait for auto-negotiation process */
1003 #ifdef DEBUG_RTL8169
1005 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1007 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1012 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
1013 if (!tpc->RxDescArray)
1016 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
1017 if (!tpc->TxDescArray)
1023 static int rtl8169_eth_probe(struct udevice *dev)
1025 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
1026 struct rtl8169_private *priv = dev_get_priv(dev);
1027 struct eth_pdata *plat = dev_get_plat(dev);
1032 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1033 switch (pplat->device) {
1041 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
1043 priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
1045 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
1047 printf(pr_fmt("failed to initialize card: %d\n"), ret);
1052 * WAR for DHCP failure after rebooting from kernel.
1053 * Clear RxDv_Gated_En bit which was set by kernel driver.
1054 * Without this, U-Boot can't get an IP via DHCP.
1055 * Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from
1056 * the r8169.c kernel driver.
1059 u32 val = RTL_R32(FuncEvent);
1060 debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val);
1061 val &= ~RxDv_Gated_En;
1062 RTL_W32(FuncEvent, val);
1067 static const struct eth_ops rtl8169_eth_ops = {
1068 .start = rtl8169_eth_start,
1069 .send = rtl8169_eth_send,
1070 .recv = rtl8169_eth_recv,
1071 .stop = rtl8169_eth_stop,
1072 .write_hwaddr = rtl8169_write_hwaddr,
1075 static const struct udevice_id rtl8169_eth_ids[] = {
1076 { .compatible = "realtek,rtl8169" },
1080 U_BOOT_DRIVER(eth_rtl8169) = {
1081 .name = "eth_rtl8169",
1083 .of_match = rtl8169_eth_ids,
1084 .probe = rtl8169_eth_probe,
1085 .ops = &rtl8169_eth_ops,
1086 .priv_auto = sizeof(struct rtl8169_private),
1087 .plat_auto = sizeof(struct eth_pdata),
1090 U_BOOT_PCI_DEVICE(eth_rtl8169, supported);