1 // SPDX-License-Identifier: GPL-2.0
3 * Opencore 10/100 ethernet mac driver
5 * Copyright (C) 2007-2008 Avionic Design Development GmbH
6 * Copyright (C) 2008-2009 Avionic Design GmbH
7 * Thierry Reding <thierry.reding@avionic-design.de>
8 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
9 * Copyright (C) 2016 Cadence Design Systems Inc.
16 #include <dm/platform_data/net_ethoc.h>
21 #include <asm/cache.h>
24 /* register offsets */
26 #define INT_SOURCE 0x04
31 #define PACKETLEN 0x18
33 #define TX_BD_NUM 0x20
34 #define CTRLMODER 0x24
36 #define MIICOMMAND 0x2c
37 #define MIIADDRESS 0x30
38 #define MIITX_DATA 0x34
39 #define MIIRX_DATA 0x38
40 #define MIISTATUS 0x3c
41 #define MAC_ADDR0 0x40
42 #define MAC_ADDR1 0x44
43 #define ETH_HASH0 0x48
44 #define ETH_HASH1 0x4c
45 #define ETH_TXCTRL 0x50
48 #define MODER_RXEN (1 << 0) /* receive enable */
49 #define MODER_TXEN (1 << 1) /* transmit enable */
50 #define MODER_NOPRE (1 << 2) /* no preamble */
51 #define MODER_BRO (1 << 3) /* broadcast address */
52 #define MODER_IAM (1 << 4) /* individual address mode */
53 #define MODER_PRO (1 << 5) /* promiscuous mode */
54 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
55 #define MODER_LOOP (1 << 7) /* loopback */
56 #define MODER_NBO (1 << 8) /* no back-off */
57 #define MODER_EDE (1 << 9) /* excess defer enable */
58 #define MODER_FULLD (1 << 10) /* full duplex */
59 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
60 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
61 #define MODER_CRC (1 << 13) /* CRC enable */
62 #define MODER_HUGE (1 << 14) /* huge packets enable */
63 #define MODER_PAD (1 << 15) /* padding enabled */
64 #define MODER_RSM (1 << 16) /* receive small packets */
66 /* interrupt source and mask registers */
67 #define INT_MASK_TXF (1 << 0) /* transmit frame */
68 #define INT_MASK_TXE (1 << 1) /* transmit error */
69 #define INT_MASK_RXF (1 << 2) /* receive frame */
70 #define INT_MASK_RXE (1 << 3) /* receive error */
71 #define INT_MASK_BUSY (1 << 4)
72 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
73 #define INT_MASK_RXC (1 << 6) /* receive control frame */
75 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
76 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
78 #define INT_MASK_ALL ( \
79 INT_MASK_TXF | INT_MASK_TXE | \
80 INT_MASK_RXF | INT_MASK_RXE | \
81 INT_MASK_TXC | INT_MASK_RXC | \
85 /* packet length register */
86 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
87 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
88 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
91 /* transmit buffer number register */
92 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
94 /* control module mode register */
95 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
96 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
97 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
99 /* MII mode register */
100 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
101 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
103 /* MII command register */
104 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
105 #define MIICOMMAND_READ (1 << 1) /* read status */
106 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
108 /* MII address register */
109 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
110 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
111 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
112 MIIADDRESS_RGAD(reg))
114 /* MII transmit data register */
115 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
117 /* MII receive data register */
118 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
120 /* MII status register */
121 #define MIISTATUS_LINKFAIL (1 << 0)
122 #define MIISTATUS_BUSY (1 << 1)
123 #define MIISTATUS_INVALID (1 << 2)
125 /* TX buffer descriptor */
126 #define TX_BD_CS (1 << 0) /* carrier sense lost */
127 #define TX_BD_DF (1 << 1) /* defer indication */
128 #define TX_BD_LC (1 << 2) /* late collision */
129 #define TX_BD_RL (1 << 3) /* retransmission limit */
130 #define TX_BD_RETRY_MASK (0x00f0)
131 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
132 #define TX_BD_UR (1 << 8) /* transmitter underrun */
133 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
134 #define TX_BD_PAD (1 << 12) /* pad enable */
135 #define TX_BD_WRAP (1 << 13)
136 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
137 #define TX_BD_READY (1 << 15) /* TX buffer ready */
138 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
139 #define TX_BD_LEN_MASK (0xffff << 16)
141 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
142 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
144 /* RX buffer descriptor */
145 #define RX_BD_LC (1 << 0) /* late collision */
146 #define RX_BD_CRC (1 << 1) /* RX CRC error */
147 #define RX_BD_SF (1 << 2) /* short frame */
148 #define RX_BD_TL (1 << 3) /* too long */
149 #define RX_BD_DN (1 << 4) /* dribble nibble */
150 #define RX_BD_IS (1 << 5) /* invalid symbol */
151 #define RX_BD_OR (1 << 6) /* receiver overrun */
152 #define RX_BD_MISS (1 << 7)
153 #define RX_BD_CF (1 << 8) /* control frame */
154 #define RX_BD_WRAP (1 << 13)
155 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
156 #define RX_BD_EMPTY (1 << 15)
157 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
159 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
160 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
162 #define ETHOC_BUFSIZ 1536
163 #define ETHOC_ZLEN 64
164 #define ETHOC_BD_BASE 0x400
165 #define ETHOC_TIMEOUT (HZ / 2)
166 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
167 #define ETHOC_IOSIZE 0x54
170 * struct ethoc - driver-private device structure
171 * @num_tx: number of send buffers
172 * @cur_tx: last send buffer written
173 * @dty_tx: last buffer actually sent
174 * @num_rx: number of receive buffers
175 * @cur_rx: current receive buffer
183 void __iomem *iobase;
184 void __iomem *packet;
185 phys_addr_t packet_phys;
189 struct phy_device *phydev;
194 * struct ethoc_bd - buffer descriptor
195 * @stat: buffer statistics
196 * @addr: physical memory address
203 static inline u32 *ethoc_reg(struct ethoc *priv, size_t offset)
205 return priv->iobase + offset;
208 static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
210 return readl(ethoc_reg(priv, offset));
213 static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
215 writel(data, ethoc_reg(priv, offset));
218 static inline void ethoc_read_bd(struct ethoc *priv, int index,
221 size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
222 bd->stat = ethoc_read(priv, offset + 0);
223 bd->addr = ethoc_read(priv, offset + 4);
226 static inline void ethoc_write_bd(struct ethoc *priv, int index,
227 const struct ethoc_bd *bd)
229 size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
230 ethoc_write(priv, offset + 0, bd->stat);
231 ethoc_write(priv, offset + 4, bd->addr);
234 static int ethoc_write_hwaddr_common(struct ethoc *priv, u8 *mac)
236 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
237 (mac[4] << 8) | (mac[5] << 0));
238 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
242 static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask)
244 ethoc_write(priv, INT_SOURCE, mask);
247 static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
249 u32 mode = ethoc_read(priv, MODER);
250 mode |= MODER_RXEN | MODER_TXEN;
251 ethoc_write(priv, MODER, mode);
254 static inline void ethoc_disable_rx_and_tx(struct ethoc *priv)
256 u32 mode = ethoc_read(priv, MODER);
257 mode &= ~(MODER_RXEN | MODER_TXEN);
258 ethoc_write(priv, MODER, mode);
261 static int ethoc_init_ring(struct ethoc *priv)
264 phys_addr_t addr = priv->packet_phys;
271 /* setup transmission buffers */
272 bd.stat = TX_BD_IRQ | TX_BD_CRC;
275 for (i = 0; i < priv->num_tx; i++) {
278 addr += PKTSIZE_ALIGN;
280 if (i == priv->num_tx - 1)
281 bd.stat |= TX_BD_WRAP;
283 ethoc_write_bd(priv, i, &bd);
286 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
288 for (i = 0; i < priv->num_rx; i++) {
291 addr += PKTSIZE_ALIGN;
293 bd.addr = virt_to_phys(net_rx_packets[i]);
295 if (i == priv->num_rx - 1)
296 bd.stat |= RX_BD_WRAP;
298 flush_dcache_range((ulong)net_rx_packets[i],
299 (ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
300 ethoc_write_bd(priv, priv->num_tx + i, &bd);
306 static int ethoc_reset(struct ethoc *priv)
310 /* TODO: reset controller? */
312 ethoc_disable_rx_and_tx(priv);
314 /* TODO: setup registers */
316 /* enable FCS generation and automatic padding */
317 mode = ethoc_read(priv, MODER);
318 mode |= MODER_CRC | MODER_PAD;
319 ethoc_write(priv, MODER, mode);
321 /* set full-duplex mode */
322 mode = ethoc_read(priv, MODER);
324 ethoc_write(priv, MODER, mode);
325 ethoc_write(priv, IPGT, 0x15);
327 ethoc_ack_irq(priv, INT_MASK_ALL);
328 ethoc_enable_rx_and_tx(priv);
332 static int ethoc_init_common(struct ethoc *priv)
337 priv->num_rx = PKTBUFSRX;
338 ethoc_write(priv, TX_BD_NUM, priv->num_tx);
339 ethoc_init_ring(priv);
343 ret = phy_startup(priv->phydev);
345 printf("Could not initialize PHY %s\n",
346 priv->phydev->dev->name);
353 static void ethoc_stop_common(struct ethoc *priv)
355 ethoc_disable_rx_and_tx(priv);
357 phy_shutdown(priv->phydev);
361 static int ethoc_update_rx_stats(struct ethoc_bd *bd)
365 if (bd->stat & RX_BD_TL) {
366 debug("ETHOC: " "RX: frame too long\n");
370 if (bd->stat & RX_BD_SF) {
371 debug("ETHOC: " "RX: frame too short\n");
375 if (bd->stat & RX_BD_DN)
376 debug("ETHOC: " "RX: dribble nibble\n");
378 if (bd->stat & RX_BD_CRC) {
379 debug("ETHOC: " "RX: wrong CRC\n");
383 if (bd->stat & RX_BD_OR) {
384 debug("ETHOC: " "RX: overrun\n");
388 if (bd->stat & RX_BD_LC) {
389 debug("ETHOC: " "RX: late collision\n");
396 static int ethoc_rx_common(struct ethoc *priv, uchar **packetp)
399 u32 i = priv->cur_rx % priv->num_rx;
400 u32 entry = priv->num_tx + i;
402 ethoc_read_bd(priv, entry, &bd);
403 if (bd.stat & RX_BD_EMPTY)
406 debug("%s(): RX buffer %d, %x received\n",
407 __func__, priv->cur_rx, bd.stat);
408 if (ethoc_update_rx_stats(&bd) == 0) {
409 int size = bd.stat >> 16;
411 size -= 4; /* strip the CRC */
413 *packetp = priv->packet + entry * PKTSIZE_ALIGN;
415 *packetp = net_rx_packets[i];
422 static int ethoc_is_new_packet_received(struct ethoc *priv)
426 pending = ethoc_read(priv, INT_SOURCE);
427 ethoc_ack_irq(priv, pending);
428 if (pending & INT_MASK_BUSY)
429 debug("%s(): packet dropped\n", __func__);
430 if (pending & INT_MASK_RX) {
431 debug("%s(): rx irq\n", __func__);
438 static int ethoc_update_tx_stats(struct ethoc_bd *bd)
440 if (bd->stat & TX_BD_LC)
441 debug("ETHOC: " "TX: late collision\n");
443 if (bd->stat & TX_BD_RL)
444 debug("ETHOC: " "TX: retransmit limit\n");
446 if (bd->stat & TX_BD_UR)
447 debug("ETHOC: " "TX: underrun\n");
449 if (bd->stat & TX_BD_CS)
450 debug("ETHOC: " "TX: carrier sense lost\n");
455 static void ethoc_tx(struct ethoc *priv)
457 u32 entry = priv->dty_tx % priv->num_tx;
460 ethoc_read_bd(priv, entry, &bd);
461 if ((bd.stat & TX_BD_READY) == 0)
462 (void)ethoc_update_tx_stats(&bd);
465 static int ethoc_send_common(struct ethoc *priv, void *packet, int length)
472 entry = priv->cur_tx % priv->num_tx;
473 ethoc_read_bd(priv, entry, &bd);
474 if (unlikely(length < ETHOC_ZLEN))
475 bd.stat |= TX_BD_PAD;
477 bd.stat &= ~TX_BD_PAD;
480 void *p = priv->packet + entry * PKTSIZE_ALIGN;
482 memcpy(p, packet, length);
485 bd.addr = virt_to_phys(packet);
487 flush_dcache_range((ulong)packet, (ulong)packet + length);
488 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
489 bd.stat |= TX_BD_LEN(length);
490 ethoc_write_bd(priv, entry, &bd);
493 bd.stat |= TX_BD_READY;
494 ethoc_write_bd(priv, entry, &bd);
496 /* wait for transfer to succeed */
497 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
499 pending = ethoc_read(priv, INT_SOURCE);
500 ethoc_ack_irq(priv, pending & ~INT_MASK_RX);
501 if (pending & INT_MASK_BUSY)
502 debug("%s(): packet dropped\n", __func__);
504 if (pending & INT_MASK_TX) {
508 if (get_timer(0) >= tmo) {
509 debug("%s(): timed out\n", __func__);
514 debug("%s(): packet sent\n", __func__);
518 static int ethoc_free_pkt_common(struct ethoc *priv)
521 u32 i = priv->cur_rx % priv->num_rx;
522 u32 entry = priv->num_tx + i;
525 ethoc_read_bd(priv, entry, &bd);
528 src = priv->packet + entry * PKTSIZE_ALIGN;
530 src = net_rx_packets[i];
531 /* clear the buffer descriptor so it can be reused */
532 flush_dcache_range((ulong)src,
533 (ulong)src + PKTSIZE_ALIGN);
534 bd.stat &= ~RX_BD_STATS;
535 bd.stat |= RX_BD_EMPTY;
536 ethoc_write_bd(priv, entry, &bd);
544 static int ethoc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
546 struct ethoc *priv = bus->priv;
549 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
550 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
552 rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
553 MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
556 u32 data = ethoc_read(priv, MIIRX_DATA);
558 /* reset MII command register */
559 ethoc_write(priv, MIICOMMAND, 0);
565 static int ethoc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
568 struct ethoc *priv = bus->priv;
571 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
572 ethoc_write(priv, MIITX_DATA, val);
573 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
575 rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
576 MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
579 /* reset MII command register */
580 ethoc_write(priv, MIICOMMAND, 0);
585 static int ethoc_mdio_init(const char *name, struct ethoc *priv)
587 struct mii_dev *bus = mdio_alloc();
591 printf("Failed to allocate MDIO bus\n");
595 bus->read = ethoc_mdio_read;
596 bus->write = ethoc_mdio_write;
597 snprintf(bus->name, sizeof(bus->name), "%s", name);
600 ret = mdio_register(bus);
604 priv->bus = miiphy_get_dev_by_name(name);
608 static int ethoc_phy_init(struct ethoc *priv, void *dev)
610 struct phy_device *phydev;
611 int mask = 0xffffffff;
613 #ifdef CONFIG_PHY_ADDR
614 mask = 1 << CONFIG_PHY_ADDR;
617 phydev = phy_find_by_mask(priv->bus, mask);
621 phy_connect_dev(phydev, dev, PHY_INTERFACE_MODE_MII);
623 phydev->supported &= PHY_BASIC_FEATURES;
624 phydev->advertising = phydev->supported;
626 priv->phydev = phydev;
634 static inline int ethoc_mdio_init(const char *name, struct ethoc *priv)
639 static inline int ethoc_phy_init(struct ethoc *priv, void *dev)
646 static int ethoc_write_hwaddr(struct udevice *dev)
648 struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
649 struct ethoc *priv = dev_get_priv(dev);
650 u8 *mac = pdata->eth_pdata.enetaddr;
652 return ethoc_write_hwaddr_common(priv, mac);
655 static int ethoc_send(struct udevice *dev, void *packet, int length)
657 return ethoc_send_common(dev_get_priv(dev), packet, length);
660 static int ethoc_free_pkt(struct udevice *dev, uchar *packet, int length)
662 return ethoc_free_pkt_common(dev_get_priv(dev));
665 static int ethoc_recv(struct udevice *dev, int flags, uchar **packetp)
667 struct ethoc *priv = dev_get_priv(dev);
669 if (flags & ETH_RECV_CHECK_DEVICE)
670 if (!ethoc_is_new_packet_received(priv))
673 return ethoc_rx_common(priv, packetp);
676 static int ethoc_start(struct udevice *dev)
678 return ethoc_init_common(dev_get_priv(dev));
681 static void ethoc_stop(struct udevice *dev)
683 ethoc_stop_common(dev_get_priv(dev));
686 static int ethoc_of_to_plat(struct udevice *dev)
688 struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
691 pdata->eth_pdata.iobase = dev_read_addr(dev);
692 addr = devfdt_get_addr_index(dev, 1);
693 if (addr != FDT_ADDR_T_NONE)
694 pdata->packet_base = addr;
698 static int ethoc_probe(struct udevice *dev)
700 struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
701 struct ethoc *priv = dev_get_priv(dev);
703 priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE);
704 if (pdata->packet_base) {
705 priv->packet_phys = pdata->packet_base;
706 priv->packet = ioremap(pdata->packet_base,
707 (1 + PKTBUFSRX) * PKTSIZE_ALIGN);
710 ethoc_mdio_init(dev->name, priv);
711 ethoc_phy_init(priv, dev);
716 static int ethoc_remove(struct udevice *dev)
718 struct ethoc *priv = dev_get_priv(dev);
722 mdio_unregister(priv->bus);
723 mdio_free(priv->bus);
725 iounmap(priv->iobase);
729 static const struct eth_ops ethoc_ops = {
730 .start = ethoc_start,
734 .free_pkt = ethoc_free_pkt,
735 .write_hwaddr = ethoc_write_hwaddr,
738 static const struct udevice_id ethoc_ids[] = {
739 { .compatible = "opencores,ethoc" },
743 U_BOOT_DRIVER(ethoc) = {
746 .of_match = ethoc_ids,
747 .of_to_plat = ethoc_of_to_plat,
748 .probe = ethoc_probe,
749 .remove = ethoc_remove,
751 .priv_auto = sizeof(struct ethoc),
752 .plat_auto = sizeof(struct ethoc_eth_pdata),