3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/ppc4xx.h>
10 #include <asm/processor.h>
13 static void wait_init_complete(void)
18 mfsdram(SDRAM0_MCSTS, val);
19 } while (!(val & 0x80000000));
23 * phys_size_t initdram(int board_type)
25 * As the name already indicates, this function is called very early
26 * from start.S and configures the SDRAM with fixed values. This is needed,
27 * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
28 * not enough free space to implement the complete I2C SPD DDR autodetection
29 * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
30 * when booting from NAND flash.
33 * As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
34 * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
35 * modules are still plugged in. So it is recommended to remove the DIMM
36 * modules while using the NAND booting code with the fixed SDRAM setup!
38 phys_size_t initdram(int board_type)
41 * Soft-reset SDRAM controller.
43 mtsdr(SDR0_SRST, SDR0_SRST_DMC);
44 mtsdr(SDR0_SRST, 0x00000000);
47 * Disable memory controller.
49 mtsdram(SDRAM0_CFG0, 0x00000000);
54 mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
55 mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
56 mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
57 mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
58 mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
61 * Following for CAS Latency = 2.5 @ 133 MHz PLB
63 mtsdram(SDRAM0_B0CR, 0x00082001);
64 mtsdram(SDRAM0_TR0, 0x41094012);
65 mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
66 mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
67 mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
70 * Enable the controller, then wait for DCEN to complete
72 mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
75 return CONFIG_SYS_MBYTES_SDRAM << 20;