1 dnl Intel Pentium mpn_and_n,...,mpn_xnor_n -- bitwise logical operations.
3 dnl Copyright 2001, 2002 Free Software Foundation, Inc.
5 dnl This file is part of the GNU MP Library.
7 dnl The GNU MP Library is free software; you can redistribute it and/or
8 dnl modify it under the terms of the GNU Lesser General Public License as
9 dnl published by the Free Software Foundation; either version 3 of the
10 dnl License, or (at your option) any later version.
12 dnl The GNU MP Library is distributed in the hope that it will be useful,
13 dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
14 dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 dnl Lesser General Public License for more details.
17 dnl You should have received a copy of the GNU Lesser General Public License
18 dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/.
20 include(`../config.m4')
23 C P5: 3.0 c/l and, ior, xor
24 C 3.5 c/l andn, iorn, nand, nior, xnor
28 `ifdef(`OPERATION_$1',`
29 define(`M4_function', `mpn_$1')
30 define(`M4_want_pre', `$4')
32 define(`M4_want_post',`$2')
34 define(M4pre, `ifelse(M4_want_pre, yes,`$1')')
35 define(M4post,`ifelse(M4_want_post,yes,`$1')')
37 M4_choose_op( and_n, , andl, )
38 M4_choose_op( andn_n, , andl, yes)
39 M4_choose_op( nand_n, yes, andl, )
40 M4_choose_op( ior_n, , orl, )
41 M4_choose_op( iorn_n, , orl, yes)
42 M4_choose_op( nior_n, yes, orl, )
43 M4_choose_op( xor_n, , xorl, )
44 M4_choose_op( xnor_n, yes, xorl, )
47 `m4_error(`Unrecognised or undefined OPERATION symbol
50 MULFUNC_PROLOGUE(mpn_and_n mpn_andn_n mpn_nand_n mpn_ior_n mpn_iorn_n mpn_nior_n mpn_xor_n mpn_xnor_n)
55 C void M4_function (mp_ptr wp, mp_srcptr xp, mp_srcptr yp, mp_size_t size);
57 C Nothing complicated here, just some care to avoid data cache bank clashes
60 C We're one register short of being able to do a simple 4 loads, 2 ops, 2
61 C stores. Instead %ebp is juggled a bit and nops are introduced to keep the
62 C pairings as intended. An in-place operation would free up a register, for
63 C an 0.5 c/l speedup, if that's worth bothering with.
65 C This code seems best for P55 too. Data alignment is a big problem for MMX
66 C and the pairing restrictions on movq and integer instructions make life
69 defframe(PARAM_SIZE,16)
70 defframe(PARAM_YP, 12)
80 pushl %ebx FRAME_pushl()
81 pushl %esi FRAME_pushl()
83 pushl %edi FRAME_pushl()
84 pushl %ebp FRAME_pushl()
95 movl (%ebx,%ecx,8), %eax C risk of data cache bank clash here
96 movl (%esi,%ecx,8), %edx
98 M4pre(` notl_or_xorl_GMP_NUMB_MASK(%edx)')
102 M4post(`xorl $GMP_NUMB_MASK, %eax')
105 movl %eax, (%edi,%ecx,8)
114 C ecx counter, limb pairs, decrementing
123 M4post(`xorl $GMP_NUMB_MASK, %eax')
124 M4post(`xorl $GMP_NUMB_MASK, %edx')
126 movl %eax, 4(%edi,%ecx,8)
127 movl %edx, (%edi,%ecx,8)
130 movl -4(%ebx,%ecx,8), %ebp
133 movl -4(%esi,%ecx,8), %eax
134 movl -8(%esi,%ecx,8), %edx
136 M4pre(` xorl $GMP_NUMB_MASK, %eax')
137 M4pre(` xorl $GMP_NUMB_MASK, %edx')
140 movl -8(%ebx,%ecx,8), %ebp
149 M4post(`xorl $GMP_NUMB_MASK, %eax')
150 M4post(`xorl $GMP_NUMB_MASK, %edx')
152 movl %eax, 4(%edi,%ecx,8)
153 movl %edx, (%edi,%ecx,8)