1 Copyright 2000, 2001 Free Software Foundation, Inc.
3 This file is part of the GNU MP Library.
5 The GNU MP Library is free software; you can redistribute it and/or modify
6 it under the terms of the GNU Lesser General Public License as published by
7 the Free Software Foundation; either version 3 of the License, or (at your
8 option) any later version.
10 The GNU MP Library is distributed in the hope that it will be useful, but
11 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
13 License for more details.
15 You should have received a copy of the GNU Lesser General Public License
16 along with the GNU MP Library. If not, see http://www.gnu.org/licenses/.
21 AMD K7 MPN SUBROUTINES
24 This directory contains code optimized for the AMD Athlon CPU.
26 The mmx subdirectory has routines using MMX instructions. All Athlons have
27 MMX, the separate directory is just so that configure can omit it if the
28 assembler doesn't support MMX.
34 Times for the loops, with all code and data in L1 cache.
39 mpn_copyi 0.75 or 1.0 \ varying with data alignment
40 mpn_copyd 0.75 or 1.0 /
42 mpn_divrem_1 17.0 integer part, 15.0 fractional part
49 mpn_addmul/submul_1 3.9
51 mpn_mul_basecase 4.42 cycles/crossproduct (approx)
52 mpn_sqr_basecase 2.3 cycles/crossproduct (approx)
53 or 4.55 cycles/triangleproduct (approx)
55 Prefetching of sources hasn't yet been tried.
61 cmov, MMX, 3DNow and some extensions to MMX and 3DNow are available.
63 Write-allocate L1 data cache means prefetching of destinations is unnecessary.
65 Floating point multiplications can be done in parallel with integer
66 multiplications, but there doesn't seem to be any way to make use of this.
68 Unsigned "mul"s can be issued every 3 cycles. This suggests 3 is a limit on
69 the speed of the multiplication routines. The documentation shows mul
70 executing in IEU0 (or maybe in IEU0 and IEU1 together), so it might be that,
71 to get near 3 cycles code has to be arranged so that nothing else is issued
72 to IEU0. A busy IEU0 could explain why some code takes 4 cycles and other
73 apparently equivalent code takes 5.
79 Unrolled loops are used to reduce looping overhead. The unrolling is
80 configurable up to 32 limbs/loop for most routines and up to 64 for some.
81 The K7 has 64k L1 code cache so quite big unrolling is allowable.
83 Computed jumps into the unrolling are used to handle sizes not a multiple of
84 the unrolling. An attractive feature of this is that times increase
85 smoothly with operand size, but it may be that some routines should just
86 have simple loops to finish up, especially when PIC adds between 2 and 16
89 Position independent code is implemented using a call to get %eip for the
90 computed jumps and a ret is always done, rather than an addl $4,%esp or a
91 popl, so the CPU return address branch prediction stack stays synchronised
92 with the actual stack in memory.
94 Branch prediction, in absence of any history, will guess forward jumps are
95 not taken and backward jumps are taken. Where possible it's arranged that
96 the less likely or less important case is under a taken forward jump.
102 Instructions in general code have been shown grouped if they can execute
103 together, which means up to three direct-path instructions which have no
104 successive dependencies. K7 always decodes three and has out-of-order
105 execution, but the groupings show what slots might be available and what
106 dependency chains exist.
108 When there's vector-path instructions an effort is made to get triplets of
109 direct-path instructions in between them, even if there's dependencies,
110 since this maximizes decoding throughput and might save a cycle or two if
111 decoding is the limiting factor.
118 divl 39 cycles back-to-back
120 loop 1 cycle vector (decl/jnz opens up one decode slot)
123 mull issue every 3 cycles, latency 4 cycles low word, 6 cycles high word
124 popl vector (use movl for more than one pop)
125 pushl direct, will pair with a load
126 shrdl %cl vector, 3 cycles, seems to be 3 decode too
127 xorl r,r false read dependency recognised
133 "AMD Athlon Processor X86 Code Optimization Guide", AMD publication number
134 22007, revision K, February 2002. Available on-line,
136 http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22007.pdf
138 "3DNow Technology Manual", AMD publication number 21928G/0-March 2000.
139 This describes the femms and prefetch instructions. Available on-line,
141 http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21928.pdf
143 "AMD Extensions to the 3DNow and MMX Instruction Sets Manual", AMD
144 publication number 22466, revision D, March 2000. This describes
145 instructions added in the Athlon processor, such as pswapd and the extra
146 prefetch forms. Available on-line,
148 http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf
150 "3DNow Instruction Porting Guide", AMD publication number 22621, revision B,
151 August 1999. This has some notes on general Athlon optimizations as well as
152 3DNow. Available on-line,
154 http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22621.pdf