1 dnl Alpha ev6 nails mpn_add_n and mpn_sub_n.
3 dnl Copyright 2002, 2006 Free Software Foundation, Inc.
5 dnl This file is part of the GNU MP Library.
7 dnl The GNU MP Library is free software; you can redistribute it and/or
8 dnl modify it under the terms of the GNU Lesser General Public License as
9 dnl published by the Free Software Foundation; either version 3 of the
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14 dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 dnl Lesser General Public License for more details.
17 dnl You should have received a copy of the GNU Lesser General Public License
18 dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/.
21 dnl Runs at 2.5 cycles/limb. It would be possible to reach 2.0 cycles/limb
22 dnl with 8-way unrolling.
24 include(`../config.m4')
47 define(`numb_mask',`r21')
49 define(`NAIL_BITS',`GMP_NAIL_BITS')
50 define(`CYSH',`GMP_NUMB_BITS')
52 dnl This declaration is munged by configure
55 ifdef(`OPERATION_add_n', `
57 define(`CYSH',`GMP_NUMB_BITS')
58 define(`func', mpn_add_n)')
59 ifdef(`OPERATION_sub_n', `
62 define(`func', mpn_sub_n)')
64 MULFUNC_PROLOGUE(mpn_add_n mpn_sub_n)
68 lda numb_mask, -1(r31)
69 srl numb_mask, NAIL_BITS, numb_mask
76 L(lp0): ldq ul0, 0(up)
84 and rl0, numb_mask, r28
91 L(ge4): ldq ul0, 0(up)
104 OP ul0, vl0, rl0 C main-add 0
105 OP rl0, r20, rl0 C cy-add 0
106 OP ul1, vl1, rl1 C main-add 1
107 srl rl0, CYSH, r20 C gen cy 0
108 OP rl1, r20, rl1 C cy-add 1
109 and rl0,numb_mask, r27
112 L(ge8): OP ul0, vl0, rl0 C main-add 0
115 OP rl0, r20, rl0 C cy-add 0
116 OP ul1, vl1, rl1 C main-add 1
117 srl rl0, CYSH, r20 C gen cy 0
120 OP rl1, r20, rl1 C cy-add 1
121 and rl0,numb_mask, r27
122 OP ul2, vl2, rl2 C main-add 2
123 srl rl1, CYSH, r20 C gen cy 1
126 OP rl2, r20, rl2 C cy-add 2
127 and rl1,numb_mask, r28
129 OP ul3, vl3, rl3 C main-add 3
130 srl rl2, CYSH, r20 C gen cy 2
133 OP rl3, r20, rl3 C cy-add 3
134 and rl2,numb_mask, r27
143 L(top): OP ul0, vl0, rl0 C main-add 0
144 srl rl3, CYSH, r20 C gen cy 3
148 OP rl0, r20, rl0 C cy-add 0
149 and rl3,numb_mask, r28
153 OP ul1, vl1, rl1 C main-add 1
154 srl rl0, CYSH, r20 C gen cy 0
158 OP rl1, r20, rl1 C cy-add 1
159 and rl0,numb_mask, r27
163 OP ul2, vl2, rl2 C main-add 2
164 srl rl1, CYSH, r20 C gen cy 1
168 OP rl2, r20, rl2 C cy-add 2
169 and rl1,numb_mask, r28
173 OP ul3, vl3, rl3 C main-add 3
174 srl rl2, CYSH, r20 C gen cy 2
178 OP rl3, r20, rl3 C cy-add 3
179 and rl2,numb_mask, r27
193 L(end): OP ul0, vl0, rl0 C main-add 0
194 srl rl3, CYSH, r20 C gen cy 3
195 OP rl0, r20, rl0 C cy-add 0
196 and rl3,numb_mask, r28
198 OP ul1, vl1, rl1 C main-add 1
199 srl rl0, CYSH, r20 C gen cy 0
200 OP rl1, r20, rl1 C cy-add 1
201 and rl0,numb_mask, r27
203 L(cj0): OP ul2, vl2, rl2 C main-add 2
204 srl rl1, CYSH, r20 C gen cy 1
205 OP rl2, r20, rl2 C cy-add 2
206 and rl1,numb_mask, r28
208 OP ul3, vl3, rl3 C main-add 3
209 srl rl2, CYSH, r20 C gen cy 2
210 OP rl3, r20, rl3 C cy-add 3
211 and rl2,numb_mask, r27
214 srl rl3, CYSH, r20 C gen cy 3
215 and rl3,numb_mask, r28
219 L(ret): and r20, 1, r0