mips-dis.c

   1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003
   4    Free Software Foundation, Inc.
   5    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
   6
   7 This file is part of GDB, GAS, and the GNU binutils.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, write to the Free Software
  21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  22 MA 02110-1301, USA.  */
  23
  24 #include "dis-asm.h"
  25
  26 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
  27    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
  28    Free Software Foundation, Inc.
  29    Contributed by Ralph Campbell and OSF
  30    Commented and modified by Ian Lance Taylor, Cygnus Support
  31
  32 This file is part of GDB, GAS, and the GNU binutils.
  33
  34 GDB, GAS, and the GNU binutils are free software; you can redistribute
  35 them and/or modify them under the terms of the GNU General Public
  36 License as published by the Free Software Foundation; either version
  37 1, or (at your option) any later version.
  38
  39 GDB, GAS, and the GNU binutils are distributed in the hope that they
  40 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  41 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  42 the GNU General Public License for more details.
  43
  44 You should have received a copy of the GNU General Public License
  45 along with this file; see the file COPYING.  If not, write to the Free
  46 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  47
  48 /* These are bit masks and shift counts to use to access the various
  49    fields of an instruction.  To retrieve the X field of an
  50    instruction, use the expression
  51         (i >> OP_SH_X) & OP_MASK_X
  52    To set the same field (to j), use
  53         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  54
  55    Make sure you use fields that are appropriate for the instruction,
  56    of course.
  57
  58    The 'i' format uses OP, RS, RT and IMMEDIATE.
  59
  60    The 'j' format uses OP and TARGET.
  61
  62    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  63
  64    The 'b' format uses OP, RS, RT and DELTA.
  65
  66    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  67
  68    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  69
  70    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  71    breakpoint instruction are not defined; Kane says the breakpoint
  72    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  73    only use ten bits).  An optional two-operand form of break/sdbbp
  74    allows the lower ten bits to be set too, and MIPS32 and later
  75    architectures allow 20 bits to be set with a signal operand
  76    (using CODE20).
  77
  78    The syscall instruction uses CODE20.
  79
  80    The general coprocessor instructions use COPZ.  */
  81
  82 #define OP_MASK_OP              0x3f
  83 #define OP_SH_OP                26
  84 #define OP_MASK_RS              0x1f
  85 #define OP_SH_RS                21
  86 #define OP_MASK_FR              0x1f
  87 #define OP_SH_FR                21
  88 #define OP_MASK_FMT             0x1f
  89 #define OP_SH_FMT               21
  90 #define OP_MASK_BCC             0x7
  91 #define OP_SH_BCC               18
  92 #define OP_MASK_CODE            0x3ff
  93 #define OP_SH_CODE              16
  94 #define OP_MASK_CODE2           0x3ff
  95 #define OP_SH_CODE2             6
  96 #define OP_MASK_RT              0x1f
  97 #define OP_SH_RT                16
  98 #define OP_MASK_FT              0x1f
  99 #define OP_SH_FT                16
 100 #define OP_MASK_CACHE           0x1f
 101 #define OP_SH_CACHE             16
 102 #define OP_MASK_RD              0x1f
 103 #define OP_SH_RD                11
 104 #define OP_MASK_FS              0x1f
 105 #define OP_SH_FS                11
 106 #define OP_MASK_PREFX           0x1f
 107 #define OP_SH_PREFX             11
 108 #define OP_MASK_CCC             0x7
 109 #define OP_SH_CCC               8
 110 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
 111 #define OP_SH_CODE20            6
 112 #define OP_MASK_SHAMT           0x1f
 113 #define OP_SH_SHAMT             6
 114 #define OP_MASK_FD              0x1f
 115 #define OP_SH_FD                6
 116 #define OP_MASK_TARGET          0x3ffffff
 117 #define OP_SH_TARGET            0
 118 #define OP_MASK_COPZ            0x1ffffff
 119 #define OP_SH_COPZ              0
 120 #define OP_MASK_IMMEDIATE       0xffff
 121 #define OP_SH_IMMEDIATE         0
 122 #define OP_MASK_DELTA           0xffff
 123 #define OP_SH_DELTA             0
 124 #define OP_MASK_FUNCT           0x3f
 125 #define OP_SH_FUNCT             0
 126 #define OP_MASK_SPEC            0x3f
 127 #define OP_SH_SPEC              0
 128 #define OP_SH_LOCC              8       /* FP condition code.  */
 129 #define OP_SH_HICC              18      /* FP condition code.  */
 130 #define OP_MASK_CC              0x7
 131 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 132 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 133 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 134 #define OP_MASK_COP1SPEC        0xf
 135 #define OP_MASK_COP1SCLR        0x4
 136 #define OP_MASK_COP1CMP         0x3
 137 #define OP_SH_COP1CMP           4
 138 #define OP_SH_FORMAT            21      /* FP short format field.  */
 139 #define OP_MASK_FORMAT          0x7
 140 #define OP_SH_TRUE              16
 141 #define OP_MASK_TRUE            0x1
 142 #define OP_SH_GE                17
 143 #define OP_MASK_GE              0x01
 144 #define OP_SH_UNSIGNED          16
 145 #define OP_MASK_UNSIGNED        0x1
 146 #define OP_SH_HINT              16
 147 #define OP_MASK_HINT            0x1f
 148 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 149 #define OP_MASK_MMI             0x3f
 150 #define OP_SH_MMISUB            6
 151 #define OP_MASK_MMISUB          0x1f
 152 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 153 #define OP_SH_PERFREG           1
 154 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 155 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 156 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 157 #define OP_MASK_CODE19          0x7ffff
 158 #define OP_SH_ALN               21
 159 #define OP_MASK_ALN             0x7
 160 #define OP_SH_VSEL              21
 161 #define OP_MASK_VSEL            0x1f
 162 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 163                                            but 0x8-0xf don't select bytes.  */
 164 #define OP_SH_VECBYTE           22
 165 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 166 #define OP_SH_VECALIGN          21
 167 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 168 #define OP_SH_INSMSB            11
 169 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 170 #define OP_SH_EXTMSBD           11
 171
 172 #define OP_OP_COP0              0x10
 173 #define OP_OP_COP1              0x11
 174 #define OP_OP_COP2              0x12
 175 #define OP_OP_COP3              0x13
 176 #define OP_OP_LWC1              0x31
 177 #define OP_OP_LWC2              0x32
 178 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 179 #define OP_OP_LDC1              0x35
 180 #define OP_OP_LDC2              0x36
 181 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 182 #define OP_OP_SWC1              0x39
 183 #define OP_OP_SWC2              0x3a
 184 #define OP_OP_SWC3              0x3b
 185 #define OP_OP_SDC1              0x3d
 186 #define OP_OP_SDC2              0x3e
 187 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 188
 189 /* MIPS DSP ASE */
 190 #define OP_SH_DSPACC            11
 191 #define OP_MASK_DSPACC          0x3
 192 #define OP_SH_DSPACC_S          21
 193 #define OP_MASK_DSPACC_S        0x3
 194 #define OP_SH_DSPSFT            20
 195 #define OP_MASK_DSPSFT          0x3f
 196 #define OP_SH_DSPSFT_7          19
 197 #define OP_MASK_DSPSFT_7        0x7f
 198 #define OP_SH_SA3               21
 199 #define OP_MASK_SA3             0x7
 200 #define OP_SH_SA4               21
 201 #define OP_MASK_SA4             0xf
 202 #define OP_SH_IMM8              16
 203 #define OP_MASK_IMM8            0xff
 204 #define OP_SH_IMM10             16
 205 #define OP_MASK_IMM10           0x3ff
 206 #define OP_SH_WRDSP             11
 207 #define OP_MASK_WRDSP           0x3f
 208 #define OP_SH_RDDSP             16
 209 #define OP_MASK_RDDSP           0x3f
 210 #define OP_SH_BP                11
 211 #define OP_MASK_BP              0x3
 212
 213 /* MIPS MT ASE */
 214 #define OP_SH_MT_U              5
 215 #define OP_MASK_MT_U            0x1
 216 #define OP_SH_MT_H              4
 217 #define OP_MASK_MT_H            0x1
 218 #define OP_SH_MTACC_T           18
 219 #define OP_MASK_MTACC_T         0x3
 220 #define OP_SH_MTACC_D           13
 221 #define OP_MASK_MTACC_D         0x3
 222
 223 #define OP_OP_COP0              0x10
 224 #define OP_OP_COP1              0x11
 225 #define OP_OP_COP2              0x12
 226 #define OP_OP_COP3              0x13
 227 #define OP_OP_LWC1              0x31
 228 #define OP_OP_LWC2              0x32
 229 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 230 #define OP_OP_LDC1              0x35
 231 #define OP_OP_LDC2              0x36
 232 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 233 #define OP_OP_SWC1              0x39
 234 #define OP_OP_SWC2              0x3a
 235 #define OP_OP_SWC3              0x3b
 236 #define OP_OP_SDC1              0x3d
 237 #define OP_OP_SDC2              0x3e
 238 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 239
 240 /* Values in the 'VSEL' field.  */
 241 #define MDMX_FMTSEL_IMM_QH      0x1d
 242 #define MDMX_FMTSEL_IMM_OB      0x1e
 243 #define MDMX_FMTSEL_VEC_QH      0x15
 244 #define MDMX_FMTSEL_VEC_OB      0x16
 245
 246 /* UDI */
 247 #define OP_SH_UDI1              6
 248 #define OP_MASK_UDI1            0x1f
 249 #define OP_SH_UDI2              6
 250 #define OP_MASK_UDI2            0x3ff
 251 #define OP_SH_UDI3              6
 252 #define OP_MASK_UDI3            0x7fff
 253 #define OP_SH_UDI4              6
 254 #define OP_MASK_UDI4            0xfffff
 255 /* This structure holds information for a particular instruction.  */
 256
 257 struct mips_opcode
 258 {
 259   /* The name of the instruction.  */
 260   const char *name;
 261   /* A string describing the arguments for this instruction.  */
 262   const char *args;
 263   /* The basic opcode for the instruction.  When assembling, this
 264      opcode is modified by the arguments to produce the actual opcode
 265      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 266   unsigned long match;
 267   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 268      relevant portions of the opcode when disassembling.  If the
 269      actual opcode anded with the match field equals the opcode field,
 270      then we have found the correct instruction.  If pinfo is
 271      INSN_MACRO, then this field is the macro identifier.  */
 272   unsigned long mask;
 273   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 274      of bits describing the instruction, notably any relevant hazard
 275      information.  */
 276   unsigned long pinfo;
 277   /* A collection of additional bits describing the instruction. */
 278   unsigned long pinfo2;
 279   /* A collection of bits describing the instruction sets of which this
 280      instruction or macro is a member. */
 281   unsigned long membership;
 282 };
 283
 284 /* These are the characters which may appear in the args field of an
 285    instruction.  They appear in the order in which the fields appear
 286    when the instruction is used.  Commas and parentheses in the args
 287    string are ignored when assembling, and written into the output
 288    when disassembling.
 289
 290    Each of these characters corresponds to a mask field defined above.
 291
 292    "<" 5 bit shift amount (OP_*_SHAMT)
 293    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 294    "a" 26 bit target address (OP_*_TARGET)
 295    "b" 5 bit base register (OP_*_RS)
 296    "c" 10 bit breakpoint code (OP_*_CODE)
 297    "d" 5 bit destination register specifier (OP_*_RD)
 298    "h" 5 bit prefx hint (OP_*_PREFX)
 299    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 300    "j" 16 bit signed immediate (OP_*_DELTA)
 301    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 302        Also used for immediate operands in vr5400 vector insns.
 303    "o" 16 bit signed offset (OP_*_DELTA)
 304    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 305    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 306    "r" 5 bit same register used as both source and target (OP_*_RS)
 307    "s" 5 bit source register specifier (OP_*_RS)
 308    "t" 5 bit target register (OP_*_RT)
 309    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 310    "v" 5 bit same register used as both source and destination (OP_*_RS)
 311    "w" 5 bit same register used as both target and destination (OP_*_RT)
 312    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 313        (used by clo and clz)
 314    "C" 25 bit coprocessor function code (OP_*_COPZ)
 315    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 316    "J" 19 bit wait function code (OP_*_CODE19)
 317    "x" accept and ignore register name
 318    "z" must be zero register
 319    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 320    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
 321         LSB (OP_*_SHAMT).
 322         Enforces: 0 <= pos < 32.
 323    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
 324         Requires that "+A" or "+E" occur first to set position.
 325         Enforces: 0 < (pos+size) <= 32.
 326    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
 327         Requires that "+A" or "+E" occur first to set position.
 328         Enforces: 0 < (pos+size) <= 32.
 329         (Also used by "dext" w/ different limits, but limits for
 330         that are checked by the M_DEXT macro.)
 331    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
 332         Enforces: 32 <= pos < 64.
 333    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
 334         Requires that "+A" or "+E" occur first to set position.
 335         Enforces: 32 < (pos+size) <= 64.
 336    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 337         Requires that "+A" or "+E" occur first to set position.
 338         Enforces: 32 < (pos+size) <= 64.
 339    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 340         Requires that "+A" or "+E" occur first to set position.
 341         Enforces: 32 < (pos+size) <= 64.
 342
 343    Floating point instructions:
 344    "D" 5 bit destination register (OP_*_FD)
 345    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 346    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 347    "S" 5 bit fs source 1 register (OP_*_FS)
 348    "T" 5 bit ft source 2 register (OP_*_FT)
 349    "R" 5 bit fr source 3 register (OP_*_FR)
 350    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 351    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 352
 353    Coprocessor instructions:
 354    "E" 5 bit target register (OP_*_RT)
 355    "G" 5 bit destination register (OP_*_RD)
 356    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 357    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 358    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 359    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 360    see also "k" above
 361    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
 362         for pretty-printing in disassembly only.
 363
 364    Macro instructions:
 365    "A" General 32 bit expression
 366    "I" 32 bit immediate (value placed in imm_expr).
 367    "+I" 32 bit immediate (value placed in imm2_expr).
 368    "F" 64 bit floating point constant in .rdata
 369    "L" 64 bit floating point constant in .lit8
 370    "f" 32 bit floating point constant
 371    "l" 32 bit floating point constant in .lit4
 372
 373    MDMX instruction operands (note that while these use the FP register
 374    fields, they accept both $fN and $vN names for the registers):
 375    "O"  MDMX alignment offset (OP_*_ALN)
 376    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 377    "X"  MDMX destination register (OP_*_FD)
 378    "Y"  MDMX source register (OP_*_FS)
 379    "Z"  MDMX source register (OP_*_FT)
 380
 381    DSP ASE usage:
 382    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
 383    "3" 3 bit unsigned immediate (OP_*_SA3)
 384    "4" 4 bit unsigned immediate (OP_*_SA4)
 385    "5" 8 bit unsigned immediate (OP_*_IMM8)
 386    "6" 5 bit unsigned immediate (OP_*_RS)
 387    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
 388    "8" 6 bit unsigned immediate (OP_*_WRDSP)
 389    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
 390    "0" 6 bit signed immediate (OP_*_DSPSFT)
 391    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
 392    "'" 6 bit unsigned immediate (OP_*_RDDSP)
 393    "@" 10 bit signed immediate (OP_*_IMM10)
 394
 395    MT ASE usage:
 396    "!" 1 bit usermode flag (OP_*_MT_U)
 397    "$" 1 bit load high flag (OP_*_MT_H)
 398    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
 399    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
 400    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
 401    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 402    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 403
 404    UDI immediates:
 405    "+1" UDI immediate bits 6-10
 406    "+2" UDI immediate bits 6-15
 407    "+3" UDI immediate bits 6-20
 408    "+4" UDI immediate bits 6-25
 409
 410    Other:
 411    "()" parens surrounding optional value
 412    ","  separates operands
 413    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 414    "+"  Start of extension sequence.
 415
 416    Characters used so far, for quick reference when adding more:
 417    "234567890"
 418    "%[]<>(),+:'@!$*&"
 419    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 420    "abcdefghijklopqrstuvwxz"
 421
 422    Extension character sequences used so far ("+" followed by the
 423    following), for quick reference when adding more:
 424    "1234"
 425    "ABCDEFGHIT"
 426    "t"
 427 */
 428
 429 /* These are the bits which may be set in the pinfo field of an
 430    instructions, if it is not equal to INSN_MACRO.  */
 431
 432 /* Modifies the general purpose register in OP_*_RD.  */
 433 #define INSN_WRITE_GPR_D            0x00000001
 434 /* Modifies the general purpose register in OP_*_RT.  */
 435 #define INSN_WRITE_GPR_T            0x00000002
 436 /* Modifies general purpose register 31.  */
 437 #define INSN_WRITE_GPR_31           0x00000004
 438 /* Modifies the floating point register in OP_*_FD.  */
 439 #define INSN_WRITE_FPR_D            0x00000008
 440 /* Modifies the floating point register in OP_*_FS.  */
 441 #define INSN_WRITE_FPR_S            0x00000010
 442 /* Modifies the floating point register in OP_*_FT.  */
 443 #define INSN_WRITE_FPR_T            0x00000020
 444 /* Reads the general purpose register in OP_*_RS.  */
 445 #define INSN_READ_GPR_S             0x00000040
 446 /* Reads the general purpose register in OP_*_RT.  */
 447 #define INSN_READ_GPR_T             0x00000080
 448 /* Reads the floating point register in OP_*_FS.  */
 449 #define INSN_READ_FPR_S             0x00000100
 450 /* Reads the floating point register in OP_*_FT.  */
 451 #define INSN_READ_FPR_T             0x00000200
 452 /* Reads the floating point register in OP_*_FR.  */
 453 #define INSN_READ_FPR_R             0x00000400
 454 /* Modifies coprocessor condition code.  */
 455 #define INSN_WRITE_COND_CODE        0x00000800
 456 /* Reads coprocessor condition code.  */
 457 #define INSN_READ_COND_CODE         0x00001000
 458 /* TLB operation.  */
 459 #define INSN_TLB                    0x00002000
 460 /* Reads coprocessor register other than floating point register.  */
 461 #define INSN_COP                    0x00004000
 462 /* Instruction loads value from memory, requiring delay.  */
 463 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 464 /* Instruction loads value from coprocessor, requiring delay.  */
 465 #define INSN_LOAD_COPROC_DELAY      0x00010000
 466 /* Instruction has unconditional branch delay slot.  */
 467 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 468 /* Instruction has conditional branch delay slot.  */
 469 #define INSN_COND_BRANCH_DELAY      0x00040000
 470 /* Conditional branch likely: if branch not taken, insn nullified.  */
 471 #define INSN_COND_BRANCH_LIKELY     0x00080000
 472 /* Moves to coprocessor register, requiring delay.  */
 473 #define INSN_COPROC_MOVE_DELAY      0x00100000
 474 /* Loads coprocessor register from memory, requiring delay.  */
 475 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 476 /* Reads the HI register.  */
 477 #define INSN_READ_HI                0x00400000
 478 /* Reads the LO register.  */
 479 #define INSN_READ_LO                0x00800000
 480 /* Modifies the HI register.  */
 481 #define INSN_WRITE_HI               0x01000000
 482 /* Modifies the LO register.  */
 483 #define INSN_WRITE_LO               0x02000000
 484 /* Takes a trap (easier to keep out of delay slot).  */
 485 #define INSN_TRAP                   0x04000000
 486 /* Instruction stores value into memory.  */
 487 #define INSN_STORE_MEMORY           0x08000000
 488 /* Instruction uses single precision floating point.  */
 489 #define FP_S                        0x10000000
 490 /* Instruction uses double precision floating point.  */
 491 #define FP_D                        0x20000000
 492 /* Instruction is part of the tx39's integer multiply family.    */
 493 #define INSN_MULT                   0x40000000
 494 /* Instruction synchronize shared memory.  */
 495 #define INSN_SYNC                   0x80000000
 496
 497 /* These are the bits which may be set in the pinfo2 field of an
 498    instruction. */
 499
 500 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 501 #define INSN2_ALIAS                 0x00000001
 502 /* Instruction reads MDMX accumulator. */
 503 #define INSN2_READ_MDMX_ACC         0x00000002
 504 /* Instruction writes MDMX accumulator. */
 505 #define INSN2_WRITE_MDMX_ACC        0x00000004
 506
 507 /* Instruction is actually a macro.  It should be ignored by the
 508    disassembler, and requires special treatment by the assembler.  */
 509 #define INSN_MACRO                  0xffffffff
 510
 511 /* Masks used to mark instructions to indicate which MIPS ISA level
 512    they were introduced in.  ISAs, as defined below, are logical
 513    ORs of these bits, indicating that they support the instructions
 514    defined at the given level.  */
 515
 516 #define INSN_ISA_MASK             0x00000fff
 517 #define INSN_ISA1                 0x00000001
 518 #define INSN_ISA2                 0x00000002
 519 #define INSN_ISA3                 0x00000004
 520 #define INSN_ISA4                 0x00000008
 521 #define INSN_ISA5                 0x00000010
 522 #define INSN_ISA32                0x00000020
 523 #define INSN_ISA64                0x00000040
 524 #define INSN_ISA32R2              0x00000080
 525 #define INSN_ISA64R2              0x00000100
 526
 527 /* Masks used for MIPS-defined ASEs.  */
 528 #define INSN_ASE_MASK             0x0000f000
 529
 530 /* DSP ASE */
 531 #define INSN_DSP                  0x00001000
 532 #define INSN_DSP64                0x00002000
 533 /* MIPS 16 ASE */
 534 #define INSN_MIPS16               0x00004000
 535 /* MIPS-3D ASE */
 536 #define INSN_MIPS3D               0x00008000
 537
 538 /* Chip specific instructions.  These are bitmasks.  */
 539
 540 /* MIPS R4650 instruction.  */
 541 #define INSN_4650                 0x00010000
 542 /* LSI R4010 instruction.  */
 543 #define INSN_4010                 0x00020000
 544 /* NEC VR4100 instruction.  */
 545 #define INSN_4100                 0x00040000
 546 /* Toshiba R3900 instruction.  */
 547 #define INSN_3900                 0x00080000
 548 /* MIPS R10000 instruction.  */
 549 #define INSN_10000                0x00100000
 550 /* Broadcom SB-1 instruction.  */
 551 #define INSN_SB1                  0x00200000
 552 /* NEC VR4111/VR4181 instruction.  */
 553 #define INSN_4111                 0x00400000
 554 /* NEC VR4120 instruction.  */
 555 #define INSN_4120                 0x00800000
 556 /* NEC VR5400 instruction.  */
 557 #define INSN_5400                 0x01000000
 558 /* NEC VR5500 instruction.  */
 559 #define INSN_5500                 0x02000000
 560
 561 /* MDMX ASE */
 562 #define INSN_MDMX                 0x04000000
 563 /* MT ASE */
 564 #define INSN_MT                   0x08000000
 565 /* SmartMIPS ASE  */
 566 #define INSN_SMARTMIPS            0x10000000
 567 /* DSP R2 ASE  */
 568 #define INSN_DSPR2                0x20000000
 569
 570 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 571
 572 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 573 #define       ISA_MIPS1       (INSN_ISA1)
 574 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
 575 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 576 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 577 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
 578
 579 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 580 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 581
 582 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
 583 #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
 584
 585
 586 /* CPU defines, use instead of hardcoding processor number. Keep this
 587    in sync with bfd/archures.c in order for machine selection to work.  */
 588 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 589 #define CPU_R3000       3000
 590 #define CPU_R3900       3900
 591 #define CPU_R4000       4000
 592 #define CPU_R4010       4010
 593 #define CPU_VR4100      4100
 594 #define CPU_R4111       4111
 595 #define CPU_VR4120      4120
 596 #define CPU_R4300       4300
 597 #define CPU_R4400       4400
 598 #define CPU_R4600       4600
 599 #define CPU_R4650       4650
 600 #define CPU_R5000       5000
 601 #define CPU_VR5400      5400
 602 #define CPU_VR5500      5500
 603 #define CPU_R6000       6000
 604 #define CPU_RM7000      7000
 605 #define CPU_R8000       8000
 606 #define CPU_R10000      10000
 607 #define CPU_R12000      12000
 608 #define CPU_MIPS16      16
 609 #define CPU_MIPS32      32
 610 #define CPU_MIPS32R2    33
 611 #define CPU_MIPS5       5
 612 #define CPU_MIPS64      64
 613 #define CPU_MIPS64R2    65
 614 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 615
 616 /* Test for membership in an ISA including chip specific ISAs.  INSN
 617    is pointer to an element of the opcode table; ISA is the specified
 618    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 619    test, or zero if no CPU specific ISA test is desired.  */
 620
 621 #if 0
 622 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 623     (((insn)->membership & isa) != 0                                    \
 624      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 625      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)    \
 626      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)    \
 627      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 628      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)    \
 629      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 630      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
 631          && ((insn)->membership & INSN_10000) != 0)                     \
 632      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
 633      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)     \
 634      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)    \
 635      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)    \
 636      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)    \
 637      || 0)      /* Please keep this term for easier source merging.  */
 638 #else
 639 #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
 640     (1 != 0)
 641 #endif
 642
 643 /* This is a list of macro expanded instructions.
 644
 645    _I appended means immediate
 646    _A appended means address
 647    _AB appended means address with base register
 648    _D appended means 64 bit floating point constant
 649    _S appended means 32 bit floating point constant.  */
 650
 651 enum
 652 {
 653   M_ABS,
 654   M_ADD_I,
 655   M_ADDU_I,
 656   M_AND_I,
 657   M_BALIGN,
 658   M_BEQ,
 659   M_BEQ_I,
 660   M_BEQL_I,
 661   M_BGE,
 662   M_BGEL,
 663   M_BGE_I,
 664   M_BGEL_I,
 665   M_BGEU,
 666   M_BGEUL,
 667   M_BGEU_I,
 668   M_BGEUL_I,
 669   M_BGT,
 670   M_BGTL,
 671   M_BGT_I,
 672   M_BGTL_I,
 673   M_BGTU,
 674   M_BGTUL,
 675   M_BGTU_I,
 676   M_BGTUL_I,
 677   M_BLE,
 678   M_BLEL,
 679   M_BLE_I,
 680   M_BLEL_I,
 681   M_BLEU,
 682   M_BLEUL,
 683   M_BLEU_I,
 684   M_BLEUL_I,
 685   M_BLT,
 686   M_BLTL,
 687   M_BLT_I,
 688   M_BLTL_I,
 689   M_BLTU,
 690   M_BLTUL,
 691   M_BLTU_I,
 692   M_BLTUL_I,
 693   M_BNE,
 694   M_BNE_I,
 695   M_BNEL_I,
 696   M_CACHE_AB,
 697   M_DABS,
 698   M_DADD_I,
 699   M_DADDU_I,
 700   M_DDIV_3,
 701   M_DDIV_3I,
 702   M_DDIVU_3,
 703   M_DDIVU_3I,
 704   M_DEXT,
 705   M_DINS,
 706   M_DIV_3,
 707   M_DIV_3I,
 708   M_DIVU_3,
 709   M_DIVU_3I,
 710   M_DLA_AB,
 711   M_DLCA_AB,
 712   M_DLI,
 713   M_DMUL,
 714   M_DMUL_I,
 715   M_DMULO,
 716   M_DMULO_I,
 717   M_DMULOU,
 718   M_DMULOU_I,
 719   M_DREM_3,
 720   M_DREM_3I,
 721   M_DREMU_3,
 722   M_DREMU_3I,
 723   M_DSUB_I,
 724   M_DSUBU_I,
 725   M_DSUBU_I_2,
 726   M_J_A,
 727   M_JAL_1,
 728   M_JAL_2,
 729   M_JAL_A,
 730   M_L_DOB,
 731   M_L_DAB,
 732   M_LA_AB,
 733   M_LB_A,
 734   M_LB_AB,
 735   M_LBU_A,
 736   M_LBU_AB,
 737   M_LCA_AB,
 738   M_LD_A,
 739   M_LD_OB,
 740   M_LD_AB,
 741   M_LDC1_AB,
 742   M_LDC2_AB,
 743   M_LDC3_AB,
 744   M_LDL_AB,
 745   M_LDR_AB,
 746   M_LH_A,
 747   M_LH_AB,
 748   M_LHU_A,
 749   M_LHU_AB,
 750   M_LI,
 751   M_LI_D,
 752   M_LI_DD,
 753   M_LI_S,
 754   M_LI_SS,
 755   M_LL_AB,
 756   M_LLD_AB,
 757   M_LS_A,
 758   M_LW_A,
 759   M_LW_AB,
 760   M_LWC0_A,
 761   M_LWC0_AB,
 762   M_LWC1_A,
 763   M_LWC1_AB,
 764   M_LWC2_A,
 765   M_LWC2_AB,
 766   M_LWC3_A,
 767   M_LWC3_AB,
 768   M_LWL_A,
 769   M_LWL_AB,
 770   M_LWR_A,
 771   M_LWR_AB,
 772   M_LWU_AB,
 773   M_MOVE,
 774   M_MUL,
 775   M_MUL_I,
 776   M_MULO,
 777   M_MULO_I,
 778   M_MULOU,
 779   M_MULOU_I,
 780   M_NOR_I,
 781   M_OR_I,
 782   M_REM_3,
 783   M_REM_3I,
 784   M_REMU_3,
 785   M_REMU_3I,
 786   M_DROL,
 787   M_ROL,
 788   M_DROL_I,
 789   M_ROL_I,
 790   M_DROR,
 791   M_ROR,
 792   M_DROR_I,
 793   M_ROR_I,
 794   M_S_DA,
 795   M_S_DOB,
 796   M_S_DAB,
 797   M_S_S,
 798   M_SC_AB,
 799   M_SCD_AB,
 800   M_SD_A,
 801   M_SD_OB,
 802   M_SD_AB,
 803   M_SDC1_AB,
 804   M_SDC2_AB,
 805   M_SDC3_AB,
 806   M_SDL_AB,
 807   M_SDR_AB,
 808   M_SEQ,
 809   M_SEQ_I,
 810   M_SGE,
 811   M_SGE_I,
 812   M_SGEU,
 813   M_SGEU_I,
 814   M_SGT,
 815   M_SGT_I,
 816   M_SGTU,
 817   M_SGTU_I,
 818   M_SLE,
 819   M_SLE_I,
 820   M_SLEU,
 821   M_SLEU_I,
 822   M_SLT_I,
 823   M_SLTU_I,
 824   M_SNE,
 825   M_SNE_I,
 826   M_SB_A,
 827   M_SB_AB,
 828   M_SH_A,
 829   M_SH_AB,
 830   M_SW_A,
 831   M_SW_AB,
 832   M_SWC0_A,
 833   M_SWC0_AB,
 834   M_SWC1_A,
 835   M_SWC1_AB,
 836   M_SWC2_A,
 837   M_SWC2_AB,
 838   M_SWC3_A,
 839   M_SWC3_AB,
 840   M_SWL_A,
 841   M_SWL_AB,
 842   M_SWR_A,
 843   M_SWR_AB,
 844   M_SUB_I,
 845   M_SUBU_I,
 846   M_SUBU_I_2,
 847   M_TEQ_I,
 848   M_TGE_I,
 849   M_TGEU_I,
 850   M_TLT_I,
 851   M_TLTU_I,
 852   M_TNE_I,
 853   M_TRUNCWD,
 854   M_TRUNCWS,
 855   M_ULD,
 856   M_ULD_A,
 857   M_ULH,
 858   M_ULH_A,
 859   M_ULHU,
 860   M_ULHU_A,
 861   M_ULW,
 862   M_ULW_A,
 863   M_USH,
 864   M_USH_A,
 865   M_USW,
 866   M_USW_A,
 867   M_USD,
 868   M_USD_A,
 869   M_XOR_I,
 870   M_COP0,
 871   M_COP1,
 872   M_COP2,
 873   M_COP3,
 874   M_NUM_MACROS
 875 };
 876
 877
 878 /* The order of overloaded instructions matters.  Label arguments and
 879    register arguments look the same. Instructions that can have either
 880    for arguments must apear in the correct order in this table for the
 881    assembler to pick the right one. In other words, entries with
 882    immediate operands must apear after the same instruction with
 883    registers.
 884
 885    Many instructions are short hand for other instructions (i.e., The
 886    jal <register> instruction is short for jalr <register>).  */
 887
 888 extern const struct mips_opcode mips_builtin_opcodes[];
 889 extern const int bfd_mips_num_builtin_opcodes;
 890 extern struct mips_opcode *mips_opcodes;
 891 extern int bfd_mips_num_opcodes;
 892 #define NUMOPCODES bfd_mips_num_opcodes
 893
 894 \f
 895 /* The rest of this file adds definitions for the mips16 TinyRISC
 896    processor.  */
 897
 898 /* These are the bitmasks and shift counts used for the different
 899    fields in the instruction formats.  Other than OP, no masks are
 900    provided for the fixed portions of an instruction, since they are
 901    not needed.
 902
 903    The I format uses IMM11.
 904
 905    The RI format uses RX and IMM8.
 906
 907    The RR format uses RX, and RY.
 908
 909    The RRI format uses RX, RY, and IMM5.
 910
 911    The RRR format uses RX, RY, and RZ.
 912
 913    The RRI_A format uses RX, RY, and IMM4.
 914
 915    The SHIFT format uses RX, RY, and SHAMT.
 916
 917    The I8 format uses IMM8.
 918
 919    The I8_MOVR32 format uses RY and REGR32.
 920
 921    The IR_MOV32R format uses REG32R and MOV32Z.
 922
 923    The I64 format uses IMM8.
 924
 925    The RI64 format uses RY and IMM5.
 926    */
 927
 928 #define MIPS16OP_MASK_OP        0x1f
 929 #define MIPS16OP_SH_OP          11
 930 #define MIPS16OP_MASK_IMM11     0x7ff
 931 #define MIPS16OP_SH_IMM11       0
 932 #define MIPS16OP_MASK_RX        0x7
 933 #define MIPS16OP_SH_RX          8
 934 #define MIPS16OP_MASK_IMM8      0xff
 935 #define MIPS16OP_SH_IMM8        0
 936 #define MIPS16OP_MASK_RY        0x7
 937 #define MIPS16OP_SH_RY          5
 938 #define MIPS16OP_MASK_IMM5      0x1f
 939 #define MIPS16OP_SH_IMM5        0
 940 #define MIPS16OP_MASK_RZ        0x7
 941 #define MIPS16OP_SH_RZ          2
 942 #define MIPS16OP_MASK_IMM4      0xf
 943 #define MIPS16OP_SH_IMM4        0
 944 #define MIPS16OP_MASK_REGR32    0x1f
 945 #define MIPS16OP_SH_REGR32      0
 946 #define MIPS16OP_MASK_REG32R    0x1f
 947 #define MIPS16OP_SH_REG32R      3
 948 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 949 #define MIPS16OP_MASK_MOVE32Z   0x7
 950 #define MIPS16OP_SH_MOVE32Z     0
 951 #define MIPS16OP_MASK_IMM6      0x3f
 952 #define MIPS16OP_SH_IMM6        5
 953
 954 /* These are the characters which may appears in the args field of an
 955    instruction.  They appear in the order in which the fields appear
 956    when the instruction is used.  Commas and parentheses in the args
 957    string are ignored when assembling, and written into the output
 958    when disassembling.
 959
 960    "y" 3 bit register (MIPS16OP_*_RY)
 961    "x" 3 bit register (MIPS16OP_*_RX)
 962    "z" 3 bit register (MIPS16OP_*_RZ)
 963    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
 964    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
 965    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
 966    "0" zero register ($0)
 967    "S" stack pointer ($sp or $29)
 968    "P" program counter
 969    "R" return address register ($ra or $31)
 970    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
 971    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
 972    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
 973    "a" 26 bit jump address
 974    "e" 11 bit extension value
 975    "l" register list for entry instruction
 976    "L" register list for exit instruction
 977
 978    The remaining codes may be extended.  Except as otherwise noted,
 979    the full extended operand is a 16 bit signed value.
 980    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
 981    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
 982    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
 983    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
 984    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
 985    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
 986    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
 987    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
 988    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
 989    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
 990    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
 991    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
 992    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
 993    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
 994    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
 995    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
 996    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
 997    "q" 11 bit branch address (MIPS16OP_*_IMM11)
 998    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
 999    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1000    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1001    */
1002
1003 /* Save/restore encoding for the args field when all 4 registers are
1004    either saved as arguments or saved/restored as statics.  */
1005 #define MIPS16_ALL_ARGS    0xe
1006 #define MIPS16_ALL_STATICS 0xb
1007
1008 /* For the mips16, we use the same opcode table format and a few of
1009    the same flags.  However, most of the flags are different.  */
1010
1011 /* Modifies the register in MIPS16OP_*_RX.  */
1012 #define MIPS16_INSN_WRITE_X                 0x00000001
1013 /* Modifies the register in MIPS16OP_*_RY.  */
1014 #define MIPS16_INSN_WRITE_Y                 0x00000002
1015 /* Modifies the register in MIPS16OP_*_RZ.  */
1016 #define MIPS16_INSN_WRITE_Z                 0x00000004
1017 /* Modifies the T ($24) register.  */
1018 #define MIPS16_INSN_WRITE_T                 0x00000008
1019 /* Modifies the SP ($29) register.  */
1020 #define MIPS16_INSN_WRITE_SP                0x00000010
1021 /* Modifies the RA ($31) register.  */
1022 #define MIPS16_INSN_WRITE_31                0x00000020
1023 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1024 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1025 /* Reads the register in MIPS16OP_*_RX.  */
1026 #define MIPS16_INSN_READ_X                  0x00000080
1027 /* Reads the register in MIPS16OP_*_RY.  */
1028 #define MIPS16_INSN_READ_Y                  0x00000100
1029 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1030 #define MIPS16_INSN_READ_Z                  0x00000200
1031 /* Reads the T ($24) register.  */
1032 #define MIPS16_INSN_READ_T                  0x00000400
1033 /* Reads the SP ($29) register.  */
1034 #define MIPS16_INSN_READ_SP                 0x00000800
1035 /* Reads the RA ($31) register.  */
1036 #define MIPS16_INSN_READ_31                 0x00001000
1037 /* Reads the program counter.  */
1038 #define MIPS16_INSN_READ_PC                 0x00002000
1039 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1040 #define MIPS16_INSN_READ_GPR_X              0x00004000
1041 /* Is a branch insn. */
1042 #define MIPS16_INSN_BRANCH                  0x00010000
1043
1044 /* The following flags have the same value for the mips16 opcode
1045    table:
1046    INSN_UNCOND_BRANCH_DELAY
1047    INSN_COND_BRANCH_DELAY
1048    INSN_COND_BRANCH_LIKELY (never used)
1049    INSN_READ_HI
1050    INSN_READ_LO
1051    INSN_WRITE_HI
1052    INSN_WRITE_LO
1053    INSN_TRAP
1054    INSN_ISA3
1055    */
1056
1057 extern const struct mips_opcode mips16_opcodes[];
1058 extern const int bfd_mips16_num_opcodes;
1059
1060 /* Short hand so the lines aren't too long.  */
1061
1062 #define LDD     INSN_LOAD_MEMORY_DELAY
1063 #define LCD     INSN_LOAD_COPROC_DELAY
1064 #define UBD     INSN_UNCOND_BRANCH_DELAY
1065 #define CBD     INSN_COND_BRANCH_DELAY
1066 #define COD     INSN_COPROC_MOVE_DELAY
1067 #define CLD     INSN_COPROC_MEMORY_DELAY
1068 #define CBL     INSN_COND_BRANCH_LIKELY
1069 #define TRAP    INSN_TRAP
1070 #define SM      INSN_STORE_MEMORY
1071
1072 #define WR_d    INSN_WRITE_GPR_D
1073 #define WR_t    INSN_WRITE_GPR_T
1074 #define WR_31   INSN_WRITE_GPR_31
1075 #define WR_D    INSN_WRITE_FPR_D
1076 #define WR_T    INSN_WRITE_FPR_T
1077 #define WR_S    INSN_WRITE_FPR_S
1078 #define RD_s    INSN_READ_GPR_S
1079 #define RD_b    INSN_READ_GPR_S
1080 #define RD_t    INSN_READ_GPR_T
1081 #define RD_S    INSN_READ_FPR_S
1082 #define RD_T    INSN_READ_FPR_T
1083 #define RD_R    INSN_READ_FPR_R
1084 #define WR_CC   INSN_WRITE_COND_CODE
1085 #define RD_CC   INSN_READ_COND_CODE
1086 #define RD_C0   INSN_COP
1087 #define RD_C1   INSN_COP
1088 #define RD_C2   INSN_COP
1089 #define RD_C3   INSN_COP
1090 #define WR_C0   INSN_COP
1091 #define WR_C1   INSN_COP
1092 #define WR_C2   INSN_COP
1093 #define WR_C3   INSN_COP
1094
1095 #define WR_HI   INSN_WRITE_HI
1096 #define RD_HI   INSN_READ_HI
1097 #define MOD_HI  WR_HI|RD_HI
1098
1099 #define WR_LO   INSN_WRITE_LO
1100 #define RD_LO   INSN_READ_LO
1101 #define MOD_LO  WR_LO|RD_LO
1102
1103 #define WR_HILO WR_HI|WR_LO
1104 #define RD_HILO RD_HI|RD_LO
1105 #define MOD_HILO WR_HILO|RD_HILO
1106
1107 #define IS_M    INSN_MULT
1108
1109 #define WR_MACC INSN2_WRITE_MDMX_ACC
1110 #define RD_MACC INSN2_READ_MDMX_ACC
1111
1112 #define I1      INSN_ISA1
1113 #define I2      INSN_ISA2
1114 #define I3      INSN_ISA3
1115 #define I4      INSN_ISA4
1116 #define I5      INSN_ISA5
1117 #define I32     INSN_ISA32
1118 #define I64     INSN_ISA64
1119 #define I33     INSN_ISA32R2
1120 #define I65     INSN_ISA64R2
1121
1122 /* MIPS64 MIPS-3D ASE support.  */
1123 #define I16     INSN_MIPS16
1124
1125 /* MIPS32 SmartMIPS ASE support.  */
1126 #define SMT     INSN_SMARTMIPS
1127
1128 /* MIPS64 MIPS-3D ASE support.  */
1129 #define M3D     INSN_MIPS3D
1130
1131 /* MIPS64 MDMX ASE support.  */
1132 #define MX      INSN_MDMX
1133
1134 #define P3      INSN_4650
1135 #define L1      INSN_4010
1136 #define V1      (INSN_4100 | INSN_4111 | INSN_4120)
1137 #define T3      INSN_3900
1138 #define M1      INSN_10000
1139 #define SB1     INSN_SB1
1140 #define N411    INSN_4111
1141 #define N412    INSN_4120
1142 #define N5      (INSN_5400 | INSN_5500)
1143 #define N54     INSN_5400
1144 #define N55     INSN_5500
1145
1146 #define G1      (T3             \
1147                  )
1148
1149 #define G2      (T3             \
1150                  )
1151
1152 #define G3      (I4             \
1153                  )
1154
1155 /* MIPS DSP ASE support.
1156    NOTE:
1157    1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
1158    of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have
1159    the same structure as $ac0 (HI + LO).  For DSP instructions that write or
1160    read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1161    (RD_HILO) attributes, such that HILO dependencies are maintained
1162    conservatively.
1163
1164    2. For some mul. instructions that use integer registers as destinations
1165    but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1166
1167    3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1168    (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write
1169    certain fields of the DSP control register.  For simplicity, we decide not
1170    to track dependencies of these fields.
1171    However, "bposge32" is a branch instruction that depends on the "pos"
1172    field.  In order to make sure that GAS does not reorder DSP instructions
1173    that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1174    attribute to those instructions that write the "pos" field.  */
1175
1176 #define WR_a    WR_HILO /* Write dsp accumulators (reuse WR_HILO)  */
1177 #define RD_a    RD_HILO /* Read dsp accumulators (reuse RD_HILO)  */
1178 #define MOD_a   WR_a|RD_a
1179 #define DSP_VOLA        INSN_TRAP
1180 #define D32     INSN_DSP
1181 #define D33     INSN_DSPR2
1182 #define D64     INSN_DSP64
1183
1184 /* MIPS MT ASE support.  */
1185 #define MT32    INSN_MT
1186
1187 /* The order of overloaded instructions matters.  Label arguments and
1188    register arguments look the same. Instructions that can have either
1189    for arguments must apear in the correct order in this table for the
1190    assembler to pick the right one. In other words, entries with
1191    immediate operands must apear after the same instruction with
1192    registers.
1193
1194    Because of the lookup algorithm used, entries with the same opcode
1195    name must be contiguous.
1196
1197    Many instructions are short hand for other instructions (i.e., The
1198    jal <register> instruction is short for jalr <register>).  */
1199
1200 const struct mips_opcode mips_builtin_opcodes[] =
1201 {
1202 /* These instructions appear first so that the disassembler will find
1203    them first.  The assemblers uses a hash table based on the
1204    instruction name anyhow.  */
1205 /* name,    args,       match,      mask,       pinfo,                  membership */
1206 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                   0,              I4|I32|G3       },
1207 {"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t,              0,              I4|I33  },
1208 {"nop",     "",         0x00000000, 0xffffffff, 0,                      INSN2_ALIAS,    I1      }, /* sll */
1209 {"ssnop",   "",         0x00000040, 0xffffffff, 0,                      INSN2_ALIAS,    I32|N55 }, /* sll */
1210 {"ehb",     "",         0x000000c0, 0xffffffff, 0,                      INSN2_ALIAS,    I33     }, /* sll */
1211 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* addiu */
1212 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* ori */
1213 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO,             0,              I1      },
1214 {"move",    "d,s",      0,    (int) M_MOVE,     INSN_MACRO,             0,              I1      },
1215 {"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I3      },/* daddu */
1216 {"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* addu */
1217 {"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* or */
1218 {"b",       "p",        0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* beq 0,0 */
1219 {"b",       "p",        0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* bgez 0 */
1220 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,              INSN2_ALIAS,    I1      },/* bgezal 0*/
1221
1222 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO,             0,              I1      },
1223 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1224 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1225 {"abs.ps",  "D,V",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1226 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1227 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1      },
1228 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1229 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1230 {"add.ob",  "X,Y,Q",    0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1231 {"add.ob",  "D,S,T",    0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1232 {"add.ob",  "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1233 {"add.ob",  "D,S,k",    0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1234 {"add.ps",  "D,V,T",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1235 {"add.qh",  "X,Y,Q",    0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1236 {"adda.ob", "Y,Q",      0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1237 {"adda.qh", "Y,Q",      0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1238 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1239 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1240 {"addl.ob", "Y,Q",      0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1241 {"addl.qh", "Y,Q",      0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1242 {"addr.ps", "D,S,T",    0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
1243 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1244 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1      },
1245 {"alni.ob", "X,Y,Z,O",  0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1246 {"alni.ob", "D,S,T,%",  0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,              N54     },
1247 {"alni.qh", "X,Y,Z,O",  0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1248 {"alnv.ps", "D,V,T,s",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1249 {"alnv.ob", "X,Y,Z,s",  0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX|SB1  },
1250 {"alnv.qh", "X,Y,Z,s",  0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX      },
1251 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1252 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO,             0,              I1      },
1253 {"and.ob",  "X,Y,Q",    0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1254 {"and.ob",  "D,S,T",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1255 {"and.ob",  "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1256 {"and.ob",  "D,S,k",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1257 {"and.qh",  "X,Y,Q",    0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1258 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1259 /* b is at the top of the table.  */
1260 /* bal is at the top of the table.  */
1261 /* bc0[tf]l? are at the bottom of the table.  */
1262 {"bc1any2f", "N,p",     0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1263 {"bc1any2t", "N,p",     0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1264 {"bc1any4f", "N,p",     0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1265 {"bc1any4t", "N,p",     0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
1266 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
1267 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
1268 {"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
1269 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
1270 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
1271 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
1272 {"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
1273 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
1274 /* bc2* are at the bottom of the table.  */
1275 /* bc3* are at the bottom of the table.  */
1276 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1277 {"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1278 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
1279 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO,             0,              I1      },
1280 {"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
1281 {"beql",    "s,I,p",    0,    (int) M_BEQL_I,   INSN_MACRO,             0,              I2|T3   },
1282 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO,             0,              I1      },
1283 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO,             0,              I1      },
1284 {"bgel",    "s,t,p",    0,    (int) M_BGEL,     INSN_MACRO,             0,              I2|T3   },
1285 {"bgel",    "s,I,p",    0,    (int) M_BGEL_I,   INSN_MACRO,             0,              I2|T3   },
1286 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO,             0,              I1      },
1287 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO,             0,              I1      },
1288 {"bgeul",   "s,t,p",    0,    (int) M_BGEUL,    INSN_MACRO,             0,              I2|T3   },
1289 {"bgeul",   "s,I,p",    0,    (int) M_BGEUL_I,  INSN_MACRO,             0,              I2|T3   },
1290 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1291 {"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1292 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
1293 {"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
1294 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO,             0,              I1      },
1295 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO,             0,              I1      },
1296 {"bgtl",    "s,t,p",    0,    (int) M_BGTL,     INSN_MACRO,             0,              I2|T3   },
1297 {"bgtl",    "s,I,p",    0,    (int) M_BGTL_I,   INSN_MACRO,             0,              I2|T3   },
1298 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO,             0,              I1      },
1299 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO,             0,              I1      },
1300 {"bgtul",   "s,t,p",    0,    (int) M_BGTUL,    INSN_MACRO,             0,              I2|T3   },
1301 {"bgtul",   "s,I,p",    0,    (int) M_BGTUL_I,  INSN_MACRO,             0,              I2|T3   },
1302 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1303 {"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1304 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO,             0,              I1      },
1305 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO,             0,              I1      },
1306 {"blel",    "s,t,p",    0,    (int) M_BLEL,     INSN_MACRO,             0,              I2|T3   },
1307 {"blel",    "s,I,p",    0,    (int) M_BLEL_I,   INSN_MACRO,             0,              I2|T3   },
1308 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO,             0,              I1      },
1309 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO,             0,              I1      },
1310 {"bleul",   "s,t,p",    0,    (int) M_BLEUL,    INSN_MACRO,             0,              I2|T3   },
1311 {"bleul",   "s,I,p",    0,    (int) M_BLEUL_I,  INSN_MACRO,             0,              I2|T3   },
1312 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1313 {"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1314 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO,             0,              I1      },
1315 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO,             0,              I1      },
1316 {"bltl",    "s,t,p",    0,    (int) M_BLTL,     INSN_MACRO,             0,              I2|T3   },
1317 {"bltl",    "s,I,p",    0,    (int) M_BLTL_I,   INSN_MACRO,             0,              I2|T3   },
1318 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO,             0,              I1      },
1319 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO,             0,              I1      },
1320 {"bltul",   "s,t,p",    0,    (int) M_BLTUL,    INSN_MACRO,             0,              I2|T3   },
1321 {"bltul",   "s,I,p",    0,    (int) M_BLTUL_I,  INSN_MACRO,             0,              I2|T3   },
1322 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1323 {"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1324 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
1325 {"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
1326 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
1327 {"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
1328 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
1329 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO,             0,              I1      },
1330 {"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
1331 {"bnel",    "s,I,p",    0,    (int) M_BNEL_I,   INSN_MACRO,             0,              I2|T3   },
1332 {"break",   "",         0x0000000d, 0xffffffff, TRAP,                   0,              I1      },
1333 {"break",   "c",        0x0000000d, 0xfc00ffff, TRAP,                   0,              I1      },
1334 {"break",   "c,q",      0x0000000d, 0xfc00003f, TRAP,                   0,              I1      },
1335 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1336 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1337 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1338 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1339 {"c.f.ps",  "S,T",      0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1340 {"c.f.ps",  "M,S,T",    0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1341 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1342 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1343 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1344 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1345 {"c.un.ps", "S,T",      0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1346 {"c.un.ps", "M,S,T",    0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1347 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1348 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1349 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1350 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1351 {"c.eq.ob", "Y,Q",      0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
1352 {"c.eq.ob", "S,T",      0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1353 {"c.eq.ob", "S,T[e]",   0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1354 {"c.eq.ob", "S,k",      0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1355 {"c.eq.ps", "S,T",      0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1356 {"c.eq.ps", "M,S,T",    0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1357 {"c.eq.qh", "Y,Q",      0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
1358 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1359 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1360 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1361 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1362 {"c.ueq.ps","S,T",      0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1363 {"c.ueq.ps","M,S,T",    0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1364 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1365 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1366 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1367 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1368 {"c.olt.ps","S,T",      0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1369 {"c.olt.ps","M,S,T",    0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1370 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1371 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1372 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1373 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1374 {"c.ult.ps","S,T",      0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1375 {"c.ult.ps","M,S,T",    0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1376 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1377 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1378 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1379 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1380 {"c.ole.ps","S,T",      0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1381 {"c.ole.ps","M,S,T",    0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1382 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1383 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1384 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1385 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1386 {"c.ule.ps","S,T",      0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1387 {"c.ule.ps","M,S,T",    0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1388 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1389 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1390 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1391 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1392 {"c.sf.ps", "S,T",      0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1393 {"c.sf.ps", "M,S,T",    0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1394 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1395 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1396 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1397 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1398 {"c.ngle.ps","S,T",     0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1399 {"c.ngle.ps","M,S,T",   0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1400 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1401 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1402 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1403 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1404 {"c.seq.ps","S,T",      0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1405 {"c.seq.ps","M,S,T",    0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1406 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1407 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1408 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1409 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1410 {"c.ngl.ps","S,T",      0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1411 {"c.ngl.ps","M,S,T",    0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1412 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1413 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1414 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1415 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1416 {"c.lt.ob", "Y,Q",      0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
1417 {"c.lt.ob", "S,T",      0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1418 {"c.lt.ob", "S,T[e]",   0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1419 {"c.lt.ob", "S,k",      0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1420 {"c.lt.ps", "S,T",      0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1421 {"c.lt.ps", "M,S,T",    0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1422 {"c.lt.qh", "Y,Q",      0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
1423 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1424 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1425 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1426 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1427 {"c.nge.ps","S,T",      0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1428 {"c.nge.ps","M,S,T",    0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1429 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1430 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1431 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1432 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1433 {"c.le.ob", "Y,Q",      0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
1434 {"c.le.ob", "S,T",      0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1435 {"c.le.ob", "S,T[e]",   0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1436 {"c.le.ob", "S,k",      0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1437 {"c.le.ps", "S,T",      0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1438 {"c.le.ps", "M,S,T",    0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1439 {"c.le.qh", "Y,Q",      0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
1440 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
1441 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
1442 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
1443 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
1444 {"c.ngt.ps","S,T",      0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1445 {"c.ngt.ps","M,S,T",    0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
1446 {"cabs.eq.d",  "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1447 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1448 {"cabs.eq.s",  "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1449 {"cabs.f.d",   "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1450 {"cabs.f.ps",  "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1451 {"cabs.f.s",   "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1452 {"cabs.le.d",  "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1453 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1454 {"cabs.le.s",  "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1455 {"cabs.lt.d",  "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1456 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1457 {"cabs.lt.s",  "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1458 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1459 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1460 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1461 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1462 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1463 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1464 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1465 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1466 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1467 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1468 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1469 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1470 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1471 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1472 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1473 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1474 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1475 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1476 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1477 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1478 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1479 {"cabs.sf.d",  "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1480 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1481 {"cabs.sf.s",  "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1482 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1483 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1484 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1485 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1486 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1487 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1488 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1489 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1490 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1491 {"cabs.un.d",  "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1492 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
1493 {"cabs.un.s",  "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
1494 /* CW4010 instructions which are aliases for the cache instruction.  */
1495 {"flushi",  "",         0xbc010000, 0xffffffff, 0,                      0,              L1      },
1496 {"flushd",  "",         0xbc020000, 0xffffffff, 0,                      0,              L1      },
1497 {"flushid", "",         0xbc030000, 0xffffffff, 0,                      0,              L1      },
1498 {"wb",      "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                0,              L1      },
1499 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                   0,              I3|I32|T3},
1500 {"cache",   "k,A(b)",   0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3|I32|T3},
1501 {"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1502 {"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1503 {"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
1504 {"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
1505 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
1506 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
1507 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
1508 /* cfc2 is at the bottom of the table.  */
1509 /* cfc3 is at the bottom of the table.  */
1510 {"cftc1",   "d,E",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
1511 {"cftc1",   "d,T",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
1512 {"cftc2",   "d,E",      0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
1513 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
1514 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
1515 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
1516 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
1517 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
1518 /* ctc2 is at the bottom of the table.  */
1519 /* ctc3 is at the bottom of the table.  */
1520 {"cttc1",   "t,g",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
1521 {"cttc1",   "t,S",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
1522 {"cttc2",   "t,g",      0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32    },
1523 {"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1524 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1525 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1526 {"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1527 {"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1528 {"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1529 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1530 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1531 {"cvt.s.pl","D,S",      0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
1532 {"cvt.s.pu","D,S",      0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
1533 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
1534 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1535 {"cvt.ps.pw", "D,S",    0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
1536 {"cvt.ps.s","D,V,T",    0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,            I5|I33  },
1537 {"cvt.pw.ps", "D,S",    0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
1538 {"dabs",    "d,v",      0,    (int) M_DABS,     INSN_MACRO,             0,              I3      },
1539 {"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1540 {"dadd",    "t,r,I",    0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3      },
1541 {"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
1542 {"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
1543 {"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1544 {"daddu",   "t,r,I",    0,    (int) M_DADDU_I,  INSN_MACRO,             0,              I3      },
1545 {"dbreak",  "",         0x7000003f, 0xffffffff, 0,                      0,              N5      },
1546 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
1547 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
1548 /* dctr and dctw are used on the r5000.  */
1549 {"dctr",    "o(b)",     0xbc050000, 0xfc1f0000, RD_b,                   0,              I3      },
1550 {"dctw",    "o(b)",     0xbc090000, 0xfc1f0000, RD_b,                   0,              I3      },
1551 {"deret",   "",         0x4200001f, 0xffffffff, 0,                      0,              I32|G2  },
1552 {"dext",    "t,r,I,+I", 0,    (int) M_DEXT,     INSN_MACRO,             0,              I65     },
1553 {"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1554 {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1555 {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1556 /* For ddiv, see the comments about div.  */
1557 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1558 {"ddiv",    "d,v,t",    0,    (int) M_DDIV_3,   INSN_MACRO,             0,              I3      },
1559 {"ddiv",    "d,v,I",    0,    (int) M_DDIV_3I,  INSN_MACRO,             0,              I3      },
1560 /* For ddivu, see the comments about div.  */
1561 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1562 {"ddivu",   "d,v,t",    0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3      },
1563 {"ddivu",   "d,v,I",    0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3      },
1564 {"di",      "",         0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33     },
1565 {"di",      "t",        0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
1566 {"dins",    "t,r,I,+I", 0,    (int) M_DINS,     INSN_MACRO,             0,              I65     },
1567 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1568 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1569 {"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,             0,              I65     },
1570 /* The MIPS assembler treats the div opcode with two operands as
1571    though the first operand appeared twice (the first operand is both
1572    a source and a destination).  To get the div machine instruction,
1573    you must use an explicit destination of $0.  */
1574 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1575 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1576 {"div",     "d,v,t",    0,    (int) M_DIV_3,    INSN_MACRO,             0,              I1      },
1577 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO,             0,              I1      },
1578 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1579 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1580 {"div.ps",  "D,V,T",    0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
1581 /* For divu, see the comments about div.  */
1582 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1583 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
1584 {"divu",    "d,v,t",    0,    (int) M_DIVU_3,   INSN_MACRO,             0,              I1      },
1585 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO,             0,              I1      },
1586 {"dla",     "t,A(b)",   0,    (int) M_DLA_AB,   INSN_MACRO,             0,              I3      },
1587 {"dlca",    "t,A(b)",   0,    (int) M_DLCA_AB,  INSN_MACRO,             0,              I3      },
1588 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                   0,              I3      }, /* addiu */
1589 {"dli",     "t,i",      0x34000000, 0xffe00000, WR_t,                   0,              I3      }, /* ori */
1590 {"dli",     "t,I",      0,    (int) M_DLI,      INSN_MACRO,             0,              I3      },
1591 {"dmacc",   "d,s,t",    0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1592 {"dmacchi", "d,s,t",    0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1593 {"dmacchis", "d,s,t",   0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1594 {"dmacchiu", "d,s,t",   0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1595 {"dmacchius", "d,s,t",  0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1596 {"dmaccs",  "d,s,t",    0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1597 {"dmaccu",  "d,s,t",    0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1598 {"dmaccus", "d,s,t",    0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
1599 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,              N411    },
1600 {"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3      },
1601 {"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
1602 {"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
1603 {"dmt",     "",         0x41600bc1, 0xffffffff, TRAP,                   0,              MT32    },
1604 {"dmt",     "t",        0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1605 {"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3      },
1606 {"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
1607 {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
1608 {"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
1609 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
1610 {"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
1611 {"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
1612 /* dmfc2 is at the bottom of the table.  */
1613 /* dmtc2 is at the bottom of the table.  */
1614 /* dmfc3 is at the bottom of the table.  */
1615 /* dmtc3 is at the bottom of the table.  */
1616 {"dmul",    "d,v,t",    0,    (int) M_DMUL,     INSN_MACRO,             0,              I3      },
1617 {"dmul",    "d,v,I",    0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3      },
1618 {"dmulo",   "d,v,t",    0,    (int) M_DMULO,    INSN_MACRO,             0,              I3      },
1619 {"dmulo",   "d,v,I",    0,    (int) M_DMULO_I,  INSN_MACRO,             0,              I3      },
1620 {"dmulou",  "d,v,t",    0,    (int) M_DMULOU,   INSN_MACRO,             0,              I3      },
1621 {"dmulou",  "d,v,I",    0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3      },
1622 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1623 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1624 {"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsub 0 */
1625 {"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsubu 0*/
1626 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1627 {"drem",    "d,v,t",    3,    (int) M_DREM_3,   INSN_MACRO,             0,              I3      },
1628 {"drem",    "d,v,I",    3,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3      },
1629 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
1630 {"dremu",   "d,v,t",    3,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3      },
1631 {"dremu",   "d,v,I",    3,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3      },
1632 {"dret",    "",         0x7000003e, 0xffffffff, 0,                      0,              N5      },
1633 {"drol",    "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I3      },
1634 {"drol",    "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3      },
1635 {"dror",    "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I3      },
1636 {"dror",    "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I3      },
1637 {"dror",    "d,w,<",    0x0020003a, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
1638 {"drorv",   "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I65  },
1639 {"dror32",  "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
1640 {"drotl",   "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I65     },
1641 {"drotl",   "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I65     },
1642 {"drotr",   "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I65     },
1643 {"drotr",   "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I65     },
1644 {"drotrv",  "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I65     },
1645 {"drotr32", "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              I65     },
1646 {"dsbh",    "d,w",      0x7c0000a4, 0xffe007ff, WR_d|RD_t,              0,              I65     },
1647 {"dshd",    "d,w",      0x7c000164, 0xffe007ff, WR_d|RD_t,              0,              I65     },
1648 {"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
1649 {"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1650 {"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsllv */
1651 {"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsll32 */
1652 {"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1653 {"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
1654 {"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1655 {"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrav */
1656 {"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsra32 */
1657 {"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1658 {"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
1659 {"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1660 {"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrlv */
1661 {"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsrl32 */
1662 {"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t,              0,              I3      },
1663 {"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1664 {"dsub",    "d,v,I",    0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3      },
1665 {"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
1666 {"dsubu",   "d,v,I",    0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
1667 {"dvpe",    "",         0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
1668 {"dvpe",    "t",        0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1669 {"ei",      "",         0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33     },
1670 {"ei",      "t",        0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
1671 {"emt",     "",         0x41600be1, 0xffffffff, TRAP,                   0,              MT32    },
1672 {"emt",     "t",        0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1673 {"eret",    "",         0x42000018, 0xffffffff, 0,                      0,              I3|I32  },
1674 {"evpe",    "",         0x41600021, 0xffffffff, TRAP,                   0,              MT32    },
1675 {"evpe",    "t",        0x41600021, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
1676 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,             0,              I33     },
1677 {"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
1678 {"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
1679 {"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
1680 {"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
1681 {"hibernate","",        0x42000023, 0xffffffff, 0,                      0,              V1      },
1682 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,             0,              I33     },
1683 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      },
1684 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
1685    the same hazard barrier effect.  */
1686 {"jr.hb",   "s",        0x00000408, 0xfc1fffff, UBD|RD_s,               0,              I32     },
1687 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      }, /* jr */
1688 /* SVR4 PIC code requires special handling for j, so it must be a
1689    macro.  */
1690 {"j",       "a",        0,     (int) M_J_A,     INSN_MACRO,             0,              I1      },
1691 /* This form of j is used by the disassembler and internally by the
1692    assembler, but will never match user input (because the line above
1693    will match first).  */
1694 {"j",       "a",        0x08000000, 0xfc000000, UBD,                    0,              I1      },
1695 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I1      },
1696 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I1      },
1697 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
1698    with the same hazard barrier effect.  */
1699 {"jalr.hb", "s",        0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I32     },
1700 {"jalr.hb", "d,s",      0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I32     },
1701 /* SVR4 PIC code requires special handling for jal, so it must be a
1702    macro.  */
1703 {"jal",     "d,s",      0,     (int) M_JAL_2,   INSN_MACRO,             0,              I1      },
1704 {"jal",     "s",        0,     (int) M_JAL_1,   INSN_MACRO,             0,              I1      },
1705 {"jal",     "a",        0,     (int) M_JAL_A,   INSN_MACRO,             0,              I1      },
1706 /* This form of jal is used by the disassembler and internally by the
1707    assembler, but will never match user input (because the line above
1708    will match first).  */
1709 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31,              0,              I1      },
1710 {"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31,              0,              I16     },
1711 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1      },
1712 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1713 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO,             0,              I1      },
1714 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1715 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO,             0,              I1      },
1716 {"lca",     "t,A(b)",   0,    (int) M_LCA_AB,   INSN_MACRO,             0,              I1      },
1717 {"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,              0,              I3      },
1718 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO,             0,              I1      },
1719 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO,             0,              I1      },
1720 {"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
1721 {"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
1722 {"ldc1",    "T,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
1723 {"ldc1",    "E,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
1724 {"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      }, /* ldc1 */
1725 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO,             0,              I1      },
1726 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO,             0,              I1      },
1727 {"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
1728 {"ldc2",    "E,A(b)",   0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2      },
1729 {"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
1730 {"ldc3",    "E,A(b)",   0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2      },
1731 {"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
1732 {"ldl",     "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3      },
1733 {"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
1734 {"ldr",     "t,A(b)",   0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3      },
1735 {"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
1736 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1737 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO,             0,              I1      },
1738 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1739 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO,             0,              I1      },
1740 /* li is at the start of the table.  */
1741 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO,             0,              I1      },
1742 {"li.d",    "T,L",      0,    (int) M_LI_DD,    INSN_MACRO,             0,              I1      },
1743 {"li.s",    "t,f",      0,    (int) M_LI_S,     INSN_MACRO,             0,              I1      },
1744 {"li.s",    "T,l",      0,    (int) M_LI_SS,    INSN_MACRO,             0,              I1      },
1745 {"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      },
1746 {"ll",      "t,A(b)",   0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2      },
1747 {"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
1748 {"lld",     "t,A(b)",   0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3      },
1749 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t,                   0,              I1      },
1750 {"luxc1",   "D,t(b)",   0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I5|I33|N55},
1751 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1752 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1      },
1753 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
1754 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1      },
1755 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
1756 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
1757 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
1758 {"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
1759 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      }, /* lwc1 */
1760 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
1761 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
1762 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1      },
1763 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
1764 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1      },
1765 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1766 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1      },
1767 {"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
1768 {"lcache",  "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I2      }, /* as lwl */
1769 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
1770 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1      },
1771 {"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
1772 {"flush",   "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I2      }, /* as lwr */
1773 {"fork",    "d,s,t",    0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,              MT32    },
1774 {"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
1775 {"lwu",     "t,A(b)",   0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3      },
1776 {"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
1777 {"lwxs",    "d,t(b)",   0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d,     0,              SMT     },
1778 {"macc",    "d,s,t",    0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1779 {"macc",    "d,s,t",    0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1780 {"maccs",   "d,s,t",    0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1781 {"macchi",  "d,s,t",    0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1782 {"macchi",  "d,s,t",    0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1783 {"macchis", "d,s,t",    0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1784 {"macchiu", "d,s,t",    0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1785 {"macchiu", "d,s,t",    0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1786 {"macchius","d,s,t",    0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1787 {"maccu",   "d,s,t",    0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1788 {"maccu",   "d,s,t",    0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1789 {"maccus",  "d,s,t",    0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
1790 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
1791 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
1792 {"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4|I33  },
1793 {"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4|I33  },
1794 {"madd.ps", "D,R,S,T",  0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I5|I33  },
1795 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
1796 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
1797 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
1798 {"madd",    "7,s,t",    0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
1799 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
1800 {"maddp",   "s,t",      0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         SMT     },
1801 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
1802 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
1803 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
1804 {"maddu",   "7,s,t",    0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
1805 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
1806 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              N411    },
1807 {"max.ob",  "X,Y,Q",    0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1808 {"max.ob",  "D,S,T",    0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1809 {"max.ob",  "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1810 {"max.ob",  "D,S,k",    0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1811 {"max.qh",  "X,Y,Q",    0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1812 {"mfpc",    "t,P",      0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
1813 {"mfps",    "t,P",      0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
1814 {"mftacx",  "d",        0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
1815 {"mftacx",  "d,*",      0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
1816 {"mftc0",   "d,+t",     0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
1817 {"mftc0",   "d,+T",     0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
1818 {"mftc0",   "d,E,H",    0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
1819 {"mftc1",   "d,T",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
1820 {"mftc1",   "d,E",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
1821 {"mftc2",   "d,E",      0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
1822 {"mftdsp",  "d",        0x41100021, 0xffff07ff, TRAP|WR_d,              0,              MT32    },
1823 {"mftgpr",  "d,t",      0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
1824 {"mfthc1",  "d,T",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
1825 {"mfthc1",  "d,E",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
1826 {"mfthc2",  "d,E",      0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
1827 {"mfthi",   "d",        0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
1828 {"mfthi",   "d,*",      0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
1829 {"mftlo",   "d",        0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
1830 {"mftlo",   "d,*",      0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
1831 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,             0,              MT32    },
1832 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
1833 {"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
1834 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
1835 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
1836 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
1837 {"mfhc1",   "t,S",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
1838 {"mfhc1",   "t,G",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
1839 /* mfc2 is at the bottom of the table.  */
1840 /* mfhc2 is at the bottom of the table.  */
1841 /* mfc3 is at the bottom of the table.  */
1842 {"mfdr",    "t,G",      0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0,         0,              N5      },
1843 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI,             0,              I1      },
1844 {"mfhi",    "d,9",      0x00000010, 0xff9f07ff, WR_d|RD_HI,             0,              D32     },
1845 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO,             0,              I1      },
1846 {"mflo",    "d,9",      0x00000012, 0xff9f07ff, WR_d|RD_LO,             0,              D32     },
1847 {"mflhxu",  "d",        0x00000052, 0xffff07ff, WR_d|MOD_HILO,          0,              SMT     },
1848 {"min.ob",  "X,Y,Q",    0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1849 {"min.ob",  "D,S,T",    0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1850 {"min.ob",  "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1851 {"min.ob",  "D,S,k",    0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1852 {"min.qh",  "X,Y,Q",    0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1853 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1854 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1855 {"mov.ps",  "D,S",      0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1856 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
1857 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
1858 {"movf.l",  "D,S,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1859 {"movf.l",  "X,Y,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1860 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
1861 {"movf.ps", "D,S,N",    0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
1862 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
1863 {"ffc",     "d,v",      0x0000000b, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
1864 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
1865 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1866 {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1867 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
1868 {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
1869 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
1870 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
1871 {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1872 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
1873 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
1874 {"movt.ps", "D,S,N",    0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
1875 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
1876 {"ffs",     "d,v",      0x0000000a, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
1877 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
1878 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1879 {"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
1880 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
1881 {"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
1882 {"msac",    "d,s,t",    0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1883 {"msacu",   "d,s,t",    0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1884 {"msachi",  "d,s,t",    0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1885 {"msachiu", "d,s,t",    0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1886 /* move is at the top of the table.  */
1887 {"msgn.qh", "X,Y,Q",    0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1888 {"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
1889 {"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
1890 {"msub.ps", "D,R,S,T",  0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
1891 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
1892 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
1893 {"msub",    "7,s,t",    0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
1894 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
1895 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
1896 {"msubu",   "7,s,t",    0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
1897 {"mtpc",    "t,P",      0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
1898 {"mtps",    "t,P",      0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
1899 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1      },
1900 {"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
1901 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
1902 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
1903 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
1904 {"mthc1",   "t,S",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
1905 {"mthc1",   "t,G",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
1906 /* mtc2 is at the bottom of the table.  */
1907 /* mthc2 is at the bottom of the table.  */
1908 /* mtc3 is at the bottom of the table.  */
1909 {"mtdr",    "t,G",      0x7080003d, 0xffe007ff, COD|RD_t|WR_C0,         0,              N5      },
1910 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI,             0,              I1      },
1911 {"mthi",    "s,7",      0x00000011, 0xfc1fe7ff, RD_s|WR_HI,             0,              D32     },
1912 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO,             0,              I1      },
1913 {"mtlo",    "s,7",      0x00000013, 0xfc1fe7ff, RD_s|WR_LO,             0,              D32     },
1914 {"mtlhx",   "s",        0x00000053, 0xfc1fffff, RD_s|MOD_HILO,          0,              SMT     },
1915 {"mttc0",   "t,G",      0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
1916 {"mttc0",   "t,+D",     0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
1917 {"mttc0",   "t,G,H",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
1918 {"mttc1",   "t,S",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
1919 {"mttc1",   "t,G",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
1920 {"mttc2",   "t,g",      0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
1921 {"mttacx",  "t",        0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
1922 {"mttacx",  "t,&",      0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
1923 {"mttdsp",  "t",        0x41808021, 0xffe0ffff, TRAP|RD_t,              0,              MT32    },
1924 {"mttgpr",  "t,d",      0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
1925 {"mtthc1",  "t,S",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
1926 {"mtthc1",  "t,G",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
1927 {"mtthc2",  "t,g",      0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
1928 {"mtthi",   "t",        0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
1929 {"mtthi",   "t,&",      0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
1930 {"mttlo",   "t",        0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
1931 {"mttlo",   "t,&",      0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
1932 {"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,             0,              MT32    },
1933 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1934 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1935 {"mul.ob",  "X,Y,Q",    0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1936 {"mul.ob",  "D,S,T",    0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1937 {"mul.ob",  "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1938 {"mul.ob",  "D,S,k",    0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1939 {"mul.ps",  "D,V,T",    0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1940 {"mul.qh",  "X,Y,Q",    0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1941 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              I32|P3|N55},
1942 {"mul",     "d,s,t",    0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N54     },
1943 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO,             0,              I1      },
1944 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1      },
1945 {"mula.ob", "Y,Q",      0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1946 {"mula.ob", "S,T",      0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1947 {"mula.ob", "S,T[e]",   0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1948 {"mula.ob", "S,k",      0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1949 {"mula.qh", "Y,Q",      0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1950 {"mulhi",   "d,s,t",    0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1951 {"mulhiu",  "d,s,t",    0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1952 {"mull.ob", "Y,Q",      0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1953 {"mull.ob", "S,T",      0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1954 {"mull.ob", "S,T[e]",   0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1955 {"mull.ob", "S,k",      0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1956 {"mull.qh", "Y,Q",      0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1957 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO,             0,              I1      },
1958 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO,             0,              I1      },
1959 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO,             0,              I1      },
1960 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO,             0,              I1      },
1961 {"mulr.ps", "D,S,T",    0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
1962 {"muls",    "d,s,t",    0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1963 {"mulsu",   "d,s,t",    0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1964 {"mulshi",  "d,s,t",    0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1965 {"mulshiu", "d,s,t",    0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1966 {"muls.ob", "Y,Q",      0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1967 {"muls.ob", "S,T",      0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1968 {"muls.ob", "S,T[e]",   0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1969 {"muls.ob", "S,k",      0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1970 {"muls.qh", "Y,Q",      0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1971 {"mulsl.ob", "Y,Q",     0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1972 {"mulsl.ob", "S,T",     0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1973 {"mulsl.ob", "S,T[e]",  0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1974 {"mulsl.ob", "S,k",     0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
1975 {"mulsl.qh", "Y,Q",     0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1976 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
1977 {"mult",    "7,s,t",    0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
1978 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
1979 {"multp",   "s,t",      0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              SMT     },
1980 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
1981 {"multu",   "7,s,t",    0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
1982 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
1983 {"mulu",    "d,s,t",    0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
1984 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* sub 0 */
1985 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* subu 0 */
1986 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1987 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1988 {"neg.ps",  "D,V",      0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1989 {"nmadd.d", "D,R,S,T",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
1990 {"nmadd.s", "D,R,S,T",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
1991 {"nmadd.ps","D,R,S,T",  0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
1992 {"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
1993 {"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
1994 {"nmsub.ps","D,R,S,T",  0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
1995 /* nop is at the start of the table.  */
1996 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1997 {"nor",     "t,r,I",    0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1      },
1998 {"nor.ob",  "X,Y,Q",    0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1999 {"nor.ob",  "D,S,T",    0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2000 {"nor.ob",  "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2001 {"nor.ob",  "D,S,k",    0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2002 {"nor.qh",  "X,Y,Q",    0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2003 {"not",     "d,v",      0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         0,              I1      },/*nor d,s,0*/
2004 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2005 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO,             0,              I1      },
2006 {"or.ob",   "X,Y,Q",    0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2007 {"or.ob",   "D,S,T",    0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2008 {"or.ob",   "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2009 {"or.ob",   "D,S,k",    0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2010 {"or.qh",   "X,Y,Q",    0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2011 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2012 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2013 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1     },
2014 {"pavg.ob", "X,Y,Q",    0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2015 {"pickf.ob", "X,Y,Q",   0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2016 {"pickf.ob", "D,S,T",   0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2017 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2018 {"pickf.ob", "D,S,k",   0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2019 {"pickf.qh", "X,Y,Q",   0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2020 {"pickt.ob", "X,Y,Q",   0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2021 {"pickt.ob", "D,S,T",   0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2022 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2023 {"pickt.ob", "D,S,k",   0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2024 {"pickt.qh", "X,Y,Q",   0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2025 {"pll.ps",  "D,V,T",    0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2026 {"plu.ps",  "D,V,T",    0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2027   /* pref and prefx are at the start of the table.  */
2028 {"pul.ps",  "D,V,T",    0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2029 {"puu.ps",  "D,V,T",    0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2030 {"pperm",   "s,t",      0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              SMT     },
2031 {"rach.ob", "X",        0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2032 {"rach.ob", "D",        0x4a00003f, 0xfffff83f, WR_D,                   0,              N54     },
2033 {"rach.qh", "X",        0x7a20003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2034 {"racl.ob", "X",        0x7800003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2035 {"racl.ob", "D",        0x4800003f, 0xfffff83f, WR_D,                   0,              N54     },
2036 {"racl.qh", "X",        0x7820003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2037 {"racm.ob", "X",        0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2038 {"racm.ob", "D",        0x4900003f, 0xfffff83f, WR_D,                   0,              N54     },
2039 {"racm.qh", "X",        0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2040 {"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2041 {"recip.ps","D,S",      0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2042 {"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2043 {"recip1.d",  "D,S",    0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2044 {"recip1.ps", "D,S",    0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2045 {"recip1.s",  "D,S",    0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2046 {"recip2.d",  "D,S,T",  0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2047 {"recip2.ps", "D,S,T",  0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2048 {"recip2.s",  "D,S,T",  0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2049 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2050 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO,             0,              I1      },
2051 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO,             0,              I1      },
2052 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2053 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO,             0,              I1      },
2054 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO,             0,              I1      },
2055 {"rdhwr",   "t,K",      0x7c00003b, 0xffe007ff, WR_t,                   0,              I33     },
2056 {"rdpgpr",  "d,w",      0x41400000, 0xffe007ff, WR_d,                   0,              I33     },
2057 {"rfe",     "",         0x42000010, 0xffffffff, 0,                      0,              I1|T3   },
2058 {"rnas.qh", "X,Q",      0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2059 {"rnau.ob", "X,Q",      0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2060 {"rnau.qh", "X,Q",      0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2061 {"rnes.qh", "X,Q",      0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2062 {"rneu.ob", "X,Q",      0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2063 {"rneu.qh", "X,Q",      0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2064 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I1      },
2065 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I1      },
2066 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I1      },
2067 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I1      },
2068 {"ror",     "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              0,              N5|I33|SMT },
2069 {"rorv",    "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I33|SMT },
2070 {"rotl",    "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I33|SMT },
2071 {"rotl",    "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I33|SMT },
2072 {"rotr",    "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I33|SMT },
2073 {"rotr",    "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33|SMT },
2074 {"rotrv",   "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I33|SMT },
2075 {"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2076 {"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2077 {"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2078 {"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2079 {"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2080 {"rsqrt.ps","D,S",      0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2081 {"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2082 {"rsqrt1.d",  "D,S",    0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2083 {"rsqrt1.ps", "D,S",    0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2084 {"rsqrt1.s",  "D,S",    0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2085 {"rsqrt2.d",  "D,S,T",  0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2086 {"rsqrt2.ps", "D,S,T",  0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2087 {"rsqrt2.s",  "D,S,T",  0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2088 {"rzs.qh",  "X,Q",      0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2089 {"rzu.ob",  "X,Q",      0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2090 {"rzu.ob",  "D,k",      0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,         0,              N54     },
2091 {"rzu.qh",  "X,Q",      0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2092 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2093 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO,             0,              I1      },
2094 {"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I2      },
2095 {"sc",      "t,A(b)",   0,    (int) M_SC_AB,    INSN_MACRO,             0,              I2      },
2096 {"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I3      },
2097 {"scd",     "t,A(b)",   0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3      },
2098 {"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2099 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO,             0,              I1      },
2100 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO,             0,              I1      },
2101 {"sdbbp",   "",         0x0000000e, 0xffffffff, TRAP,                   0,              G2      },
2102 {"sdbbp",   "c",        0x0000000e, 0xfc00ffff, TRAP,                   0,              G2      },
2103 {"sdbbp",   "c,q",      0x0000000e, 0xfc00003f, TRAP,                   0,              G2      },
2104 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                   0,              I32     },
2105 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                   0,              I32     },
2106 {"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2107 {"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2108 {"sdc1",    "T,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2109 {"sdc1",    "E,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2110 {"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2      },
2111 {"sdc2",    "E,A(b)",   0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2      },
2112 {"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2      },
2113 {"sdc3",    "E,A(b)",   0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2      },
2114 {"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2115 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO,             0,              I1      },
2116 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO,             0,              I1      },
2117 {"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2118 {"sdl",     "t,A(b)",   0,    (int) M_SDL_AB,   INSN_MACRO,             0,              I3      },
2119 {"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2120 {"sdr",     "t,A(b)",   0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3      },
2121 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0,              I4|I33  },
2122 {"seb",     "d,w",      0x7c000420, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2123 {"seh",     "d,w",      0x7c000620, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2124 {"selsl",   "d,v,t",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2125 {"selsr",   "d,v,t",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2126 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO,             0,              I1      },
2127 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1      },
2128 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO,             0,              I1      },
2129 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1      },
2130 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO,             0,              I1      },
2131 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO,             0,              I1      },
2132 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO,             0,              I1      },
2133 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO,             0,              I1      },
2134 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO,             0,              I1      },
2135 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO,             0,              I1      },
2136 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2137 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO,             0,              I1      },
2138 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2139 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2140 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2141 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2142 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2143 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2144 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2145 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2146 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2147 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2148 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2149 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2150 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2151 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2152 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO,             0,              I1      },
2153 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1      },
2154 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO,             0,              I1      },
2155 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1      },
2156 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2157 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* sllv */
2158 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2159 {"sll.ob",  "X,Y,Q",    0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2160 {"sll.ob",  "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2161 {"sll.ob",  "D,S,k",    0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2162 {"sll.qh",  "X,Y,Q",    0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2163 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2164 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1      },
2165 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2166 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2167 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2168 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1      },
2169 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO,             0,              I1      },
2170 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1      },
2171 {"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
2172 {"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2173 {"sqrt.ps", "D,S",      0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2174 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2175 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srav */
2176 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2177 {"sra.qh",  "X,Y,Q",    0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2178 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2179 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srlv */
2180 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2181 {"srl.ob",  "X,Y,Q",    0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2182 {"srl.ob",  "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2183 {"srl.ob",  "D,S,k",    0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2184 {"srl.qh",  "X,Y,Q",    0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2185 /* ssnop is at the start of the table.  */
2186 {"standby", "",         0x42000021, 0xffffffff, 0,                      0,              V1      },
2187 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2188 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1      },
2189 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2190 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2191 {"sub.ob",  "X,Y,Q",    0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2192 {"sub.ob",  "D,S,T",    0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2193 {"sub.ob",  "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2194 {"sub.ob",  "D,S,k",    0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2195 {"sub.ps",  "D,V,T",    0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2196 {"sub.qh",  "X,Y,Q",    0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2197 {"suba.ob", "Y,Q",      0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2198 {"suba.qh", "Y,Q",      0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2199 {"subl.ob", "Y,Q",      0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2200 {"subl.qh", "Y,Q",      0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2201 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2202 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1      },
2203 {"suspend", "",         0x42000022, 0xffffffff, 0,                      0,              V1      },
2204 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      0,              I5|I33|N55},
2205 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2206 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO,             0,              I1      },
2207 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1      },
2208 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1      },
2209 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2210 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2211 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2212 {"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2213 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      }, /* swc1 */
2214 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2215 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1      },
2216 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1      },
2217 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1      },
2218 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1      },
2219 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2220 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1      },
2221 {"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2222 {"scache",  "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I2      }, /* as swl */
2223 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2224 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I1      },
2225 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2226 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I2      }, /* as swr */
2227 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0,              I4|I33  },
2228 {"sync",    "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2|G1   },
2229 {"sync.p",  "",         0x0000040f, 0xffffffff, INSN_SYNC,              0,              I2      },
2230 {"sync.l",  "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2      },
2231 {"synci",   "o(b)",     0x041f0000, 0xfc1f0000, SM|RD_b,                0,              I33     },
2232 {"syscall", "",         0x0000000c, 0xffffffff, TRAP,                   0,              I1      },
2233 {"syscall", "B",        0x0000000c, 0xfc00003f, TRAP,                   0,              I1      },
2234 {"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2235 {"teq",     "s,t",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2236 {"teq",     "s,t,q",    0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2237 {"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* teqi */
2238 {"teq",     "s,I",      0,    (int) M_TEQ_I,    INSN_MACRO,             0,              I2      },
2239 {"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2240 {"tge",     "s,t",      0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2241 {"tge",     "s,t,q",    0x00000030, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2242 {"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgei */
2243 {"tge",     "s,I",      0,    (int) M_TGE_I,    INSN_MACRO,             0,              I2      },
2244 {"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2245 {"tgeu",    "s,t",      0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2246 {"tgeu",    "s,t,q",    0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2247 {"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgeiu */
2248 {"tgeu",    "s,I",      0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2      },
2249 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,               0,              I1      },
2250 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,               0,              I1      },
2251 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,               0,              I1      },
2252 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,               0,              I1      },
2253 {"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2254 {"tlt",     "s,t",      0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2255 {"tlt",     "s,t,q",    0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2256 {"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tlti */
2257 {"tlt",     "s,I",      0,    (int) M_TLT_I,    INSN_MACRO,             0,              I2      },
2258 {"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2259 {"tltu",    "s,t",      0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2260 {"tltu",    "s,t,q",    0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2261 {"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tltiu */
2262 {"tltu",    "s,I",      0,    (int) M_TLTU_I,   INSN_MACRO,             0,              I2      },
2263 {"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2264 {"tne",     "s,t",      0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2265 {"tne",     "s,t,q",    0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2266 {"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tnei */
2267 {"tne",     "s,I",      0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2      },
2268 {"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2269 {"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2270 {"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2271 {"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2272 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO,             0,              I1      },
2273 {"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2274 {"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2275 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO,             0,              I1      },
2276 {"uld",     "t,o(b)",   0,    (int) M_ULD,      INSN_MACRO,             0,              I3      },
2277 {"uld",     "t,A(b)",   0,    (int) M_ULD_A,    INSN_MACRO,             0,              I3      },
2278 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO,             0,              I1      },
2279 {"ulh",     "t,A(b)",   0,    (int) M_ULH_A,    INSN_MACRO,             0,              I1      },
2280 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO,             0,              I1      },
2281 {"ulhu",    "t,A(b)",   0,    (int) M_ULHU_A,   INSN_MACRO,             0,              I1      },
2282 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO,             0,              I1      },
2283 {"ulw",     "t,A(b)",   0,    (int) M_ULW_A,    INSN_MACRO,             0,              I1      },
2284 {"usd",     "t,o(b)",   0,    (int) M_USD,      INSN_MACRO,             0,              I3      },
2285 {"usd",     "t,A(b)",   0,    (int) M_USD_A,    INSN_MACRO,             0,              I3      },
2286 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO,             0,              I1      },
2287 {"ush",     "t,A(b)",   0,    (int) M_USH_A,    INSN_MACRO,             0,              I1      },
2288 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO,             0,              I1      },
2289 {"usw",     "t,A(b)",   0,    (int) M_USW_A,    INSN_MACRO,             0,              I1      },
2290 {"wach.ob", "Y",        0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX|SB1  },
2291 {"wach.ob", "S",        0x4a00003e, 0xffff07ff, RD_S,                   0,              N54     },
2292 {"wach.qh", "Y",        0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX      },
2293 {"wacl.ob", "Y,Z",      0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2294 {"wacl.ob", "S,T",      0x4800003e, 0xffe007ff, RD_S|RD_T,              0,              N54     },
2295 {"wacl.qh", "Y,Z",      0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2296 {"wait",    "",         0x42000020, 0xffffffff, TRAP,                   0,              I3|I32  },
2297 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                   0,              I32|N55 },
2298 {"waiti",   "",         0x42000020, 0xffffffff, TRAP,                   0,              L1      },
2299 {"wrpgpr",  "d,w",      0x41c00000, 0xffe007ff, RD_t,                   0,              I33     },
2300 {"wsbh",    "d,w",      0x7c0000a0, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2301 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2302 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
2303 {"xor.ob",  "X,Y,Q",    0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2304 {"xor.ob",  "D,S,T",    0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2305 {"xor.ob",  "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2306 {"xor.ob",  "D,S,k",    0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2307 {"xor.qh",  "X,Y,Q",    0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2308 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2309 {"yield",   "s",        0x7c000009, 0xfc1fffff, TRAP|RD_s,              0,              MT32    },
2310 {"yield",   "d,s",      0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s,         0,              MT32    },
2311
2312 /* User Defined Instruction.  */
2313 {"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2314 {"udi0",     "s,t,+2",  0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2315 {"udi0",     "s,+3",    0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2316 {"udi0",     "+4",      0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2317 {"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2318 {"udi1",     "s,t,+2",  0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2319 {"udi1",     "s,+3",    0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2320 {"udi1",     "+4",      0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2321 {"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2322 {"udi2",     "s,t,+2",  0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2323 {"udi2",     "s,+3",    0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2324 {"udi2",     "+4",      0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2325 {"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2326 {"udi3",     "s,t,+2",  0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2327 {"udi3",     "s,+3",    0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2328 {"udi3",     "+4",      0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2329 {"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2330 {"udi4",     "s,t,+2",  0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2331 {"udi4",     "s,+3",    0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2332 {"udi4",     "+4",      0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2333 {"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2334 {"udi5",     "s,t,+2",  0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2335 {"udi5",     "s,+3",    0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2336 {"udi5",     "+4",      0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2337 {"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2338 {"udi6",     "s,t,+2",  0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2339 {"udi6",     "s,+3",    0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2340 {"udi6",     "+4",      0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2341 {"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2342 {"udi7",     "s,t,+2",  0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2343 {"udi7",     "s,+3",    0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2344 {"udi7",     "+4",      0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2345 {"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2346 {"udi8",     "s,t,+2",  0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2347 {"udi8",     "s,+3",    0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2348 {"udi8",     "+4",      0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2349 {"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2350 {"udi9",      "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2351 {"udi9",     "s,+3",    0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2352 {"udi9",     "+4",      0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2353 {"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2354 {"udi10",    "s,t,+2",  0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2355 {"udi10",    "s,+3",    0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2356 {"udi10",    "+4",      0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2357 {"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2358 {"udi11",    "s,t,+2",  0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2359 {"udi11",    "s,+3",    0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2360 {"udi11",    "+4",      0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2361 {"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2362 {"udi12",    "s,t,+2",  0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2363 {"udi12",    "s,+3",    0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2364 {"udi12",    "+4",      0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2365 {"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2366 {"udi13",    "s,t,+2",  0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2367 {"udi13",    "s,+3",    0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2368 {"udi13",    "+4",      0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2369 {"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2370 {"udi14",    "s,t,+2",  0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2371 {"udi14",    "s,+3",    0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2372 {"udi14",    "+4",      0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2373 {"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2374 {"udi15",    "s,t,+2",  0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2375 {"udi15",    "s,+3",    0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2376 {"udi15",    "+4",      0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
2377
2378 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
2379    instructions so they are here for the latters to take precedence.  */
2380 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2381 {"bc2f",    "N,p",      0x49000000, 0xffe30000, CBD|RD_CC,              0,              I32     },
2382 {"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2383 {"bc2fl",   "N,p",      0x49020000, 0xffe30000, CBL|RD_CC,              0,              I32     },
2384 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2385 {"bc2t",    "N,p",      0x49010000, 0xffe30000, CBD|RD_CC,              0,              I32     },
2386 {"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2387 {"bc2tl",   "N,p",      0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32     },
2388 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
2389 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
2390 {"dmfc2",   "t,G",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
2391 {"dmfc2",   "t,G,H",    0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
2392 {"dmtc2",   "t,G",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
2393 {"dmtc2",   "t,G,H",    0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
2394 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
2395 {"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32     },
2396 {"mfhc2",   "t,G",      0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33     },
2397 {"mfhc2",   "t,G,H",    0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I33     },
2398 {"mfhc2",   "t,i",      0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,              I33     },
2399 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I1      },
2400 {"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I32     },
2401 {"mthc2",   "t,G",      0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
2402 {"mthc2",   "t,G,H",    0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
2403 {"mthc2",   "t,i",      0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
2404
2405 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
2406    instructions, so they are here for the latters to take precedence.  */
2407 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2408 {"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2409 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2410 {"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2411 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
2412 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
2413 {"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I3      },
2414 {"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I3      },
2415 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
2416 {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,              I32     },
2417 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1      },
2418 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,              I32     },
2419
2420 /* No hazard protection on coprocessor instructions--they shouldn't
2421    change the state of the processor and if they do it's up to the
2422    user to put in nops as necessary.  These are at the end so that the
2423    disassembler recognizes more specific versions first.  */
2424 {"c0",      "C",        0x42000000, 0xfe000000, 0,                      0,              I1      },
2425 {"c1",      "C",        0x46000000, 0xfe000000, 0,                      0,              I1      },
2426 {"c2",      "C",        0x4a000000, 0xfe000000, 0,                      0,              I1      },
2427 {"c3",      "C",        0x4e000000, 0xfe000000, 0,                      0,              I1      },
2428 {"cop0",     "C",       0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
2429 {"cop1",     "C",       0,    (int) M_COP1,     INSN_MACRO,             0,              I1      },
2430 {"cop2",     "C",       0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
2431 {"cop3",     "C",       0,    (int) M_COP3,     INSN_MACRO,             0,              I1      },
2432   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
2433      4010 any more, so move this insn out of the way.  If the object
2434      format gave us more info, we could do this right.  */
2435 {"addciu",  "t,r,j",    0x70000000, 0xfc000000, WR_t|RD_s,              0,              L1      },
2436 /* MIPS DSP ASE */
2437 {"absq_s.ph", "d,t",    0x7c000252, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2438 {"absq_s.pw", "d,t",    0x7c000456, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2439 {"absq_s.qh", "d,t",    0x7c000256, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2440 {"absq_s.w", "d,t",     0x7c000452, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2441 {"addq.ph", "d,s,t",    0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2442 {"addq.pw", "d,s,t",    0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2443 {"addq.qh", "d,s,t",    0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2444 {"addq_s.ph", "d,s,t",  0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2445 {"addq_s.pw", "d,s,t",  0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2446 {"addq_s.qh", "d,s,t",  0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2447 {"addq_s.w", "d,s,t",   0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2448 {"addsc",   "d,s,t",    0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2449 {"addu.ob", "d,s,t",    0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2450 {"addu.qb", "d,s,t",    0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2451 {"addu_s.ob", "d,s,t",  0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2452 {"addu_s.qb", "d,s,t",  0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2453 {"addwc",   "d,s,t",    0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2454 {"bitrev",  "d,t",      0x7c0006d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2455 {"bposge32", "p",       0x041c0000, 0xffff0000, CBD,                    0,              D32     },
2456 {"bposge64", "p",       0x041d0000, 0xffff0000, CBD,                    0,              D64     },
2457 {"cmp.eq.ph", "s,t",    0x7c000211, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2458 {"cmp.eq.pw", "s,t",    0x7c000415, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2459 {"cmp.eq.qh", "s,t",    0x7c000215, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2460 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2461 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2462 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2463 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2464 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2465 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2466 {"cmp.le.ph", "s,t",    0x7c000291, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2467 {"cmp.le.pw", "s,t",    0x7c000495, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2468 {"cmp.le.qh", "s,t",    0x7c000295, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2469 {"cmp.lt.ph", "s,t",    0x7c000251, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2470 {"cmp.lt.pw", "s,t",    0x7c000455, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2471 {"cmp.lt.qh", "s,t",    0x7c000255, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2472 {"cmpu.eq.ob", "s,t",   0x7c000015, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2473 {"cmpu.eq.qb", "s,t",   0x7c000011, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2474 {"cmpu.le.ob", "s,t",   0x7c000095, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2475 {"cmpu.le.qb", "s,t",   0x7c000091, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2476 {"cmpu.lt.ob", "s,t",   0x7c000055, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
2477 {"cmpu.lt.qb", "s,t",   0x7c000051, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
2478 {"dextpdp", "t,7,6",    0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D64     },
2479 {"dextpdpv", "t,7,s",   0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D64     },
2480 {"dextp",   "t,7,6",    0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2481 {"dextpv",  "t,7,s",    0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2482 {"dextr.l", "t,7,6",    0x7c00043c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2483 {"dextr_r.l", "t,7,6",  0x7c00053c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2484 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2485 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2486 {"dextr_r.w", "t,7,6",  0x7c00013c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2487 {"dextr_s.h", "t,7,6",  0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2488 {"dextrv.l", "t,7,s",   0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2489 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2490 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
2491 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
2492 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2493 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2494 {"dextrv.w", "t,7,s",   0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
2495 {"dextr.w", "t,7,6",    0x7c00003c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
2496 {"dinsv",   "t,s",      0x7c00000d, 0xfc00ffff, WR_t|RD_s,              0,              D64     },
2497 {"dmadd",   "7,s,t",    0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2498 {"dmaddu",  "7,s,t",    0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2499 {"dmsub",   "7,s,t",    0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2500 {"dmsubu",  "7,s,t",    0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2501 {"dmthlip", "s,7",      0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D64     },
2502 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2503 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2504 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2505 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2506 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2507 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2508 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2509 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2510 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2511 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2512 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2513 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2514 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2515 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
2516 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2517 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
2518 {"dshilo",  "7,:",      0x7c0006bc, 0xfc07e7ff, MOD_a,                  0,              D64     },
2519 {"dshilov", "7,s",      0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,             0,              D64     },
2520 {"extpdp",  "t,7,6",    0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D32     },
2521 {"extpdpv", "t,7,s",    0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D32     },
2522 {"extp",    "t,7,6",    0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2523 {"extpv",   "t,7,s",    0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2524 {"extr_rs.w", "t,7,6",  0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2525 {"extr_r.w", "t,7,6",   0x7c000138, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2526 {"extr_s.h", "t,7,6",   0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2527 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2528 {"extrv_r.w", "t,7,s",  0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2529 {"extrv_s.h", "t,7,s",  0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2530 {"extrv.w", "t,7,s",    0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
2531 {"extr.w",  "t,7,6",    0x7c000038, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
2532 {"insv",    "t,s",      0x7c00000c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
2533 {"lbux",    "d,t(b)",   0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
2534 {"ldx",     "d,t(b)",   0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D64     },
2535 {"lhx",     "d,t(b)",   0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
2536 {"lwx",     "d,t(b)",   0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
2537 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
2538 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
2539 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2540 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2541 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2542 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2543 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2544 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
2545 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2546 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
2547 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2548 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2549 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2550 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
2551 {"modsub",  "d,s,t",    0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2552 {"mthlip",  "s,7",      0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D32     },
2553 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2554 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2555 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
2556 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
2557 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
2558 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
2559 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2560 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
2561 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D32     },
2562 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D64     },
2563 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2564 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D32     },
2565 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
2566 {"packrl.ph", "d,s,t",  0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2567 {"packrl.pw", "d,s,t",  0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2568 {"pick.ob", "d,s,t",    0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2569 {"pick.ph", "d,s,t",    0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2570 {"pick.pw", "d,s,t",    0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2571 {"pick.qb", "d,s,t",    0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2572 {"pick.qh", "d,s,t",    0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2573 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2574 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2575 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2576 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2577 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2578 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2579 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,           0,              D32     },
2580 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2581 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,           0,              D32     },
2582 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2583 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,           0,              D64     },
2584 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2585 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,           0,              D64     },
2586 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2587 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2588 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2589 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2590 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,             0,              D32     },
2591 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,            0,              D32     },
2592 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,             0,              D32     },
2593 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2594 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2595 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
2596 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,             0,              D64     },
2597 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
2598 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
2599 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
2600 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
2601 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
2602 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,     0,              D32     },
2603 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
2604 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
2605 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D32     },
2606 {"raddu.l.ob", "d,s",   0x7c000514, 0xfc1f07ff, WR_d|RD_s,              0,              D64     },
2607 {"raddu.w.qb", "d,s",   0x7c000510, 0xfc1f07ff, WR_d|RD_s,              0,              D32     },
2608 {"rddsp",   "d",        0x7fff04b8, 0xffff07ff, WR_d,                   0,              D32     },
2609 {"rddsp",   "d,'",      0x7c0004b8, 0xffc007ff, WR_d,                   0,              D32     },
2610 {"repl.ob", "d,5",      0x7c000096, 0xff0007ff, WR_d,                   0,              D64     },
2611 {"repl.ph", "d,@",      0x7c000292, 0xfc0007ff, WR_d,                   0,              D32     },
2612 {"repl.pw", "d,@",      0x7c000496, 0xfc0007ff, WR_d,                   0,              D64     },
2613 {"repl.qb", "d,5",      0x7c000092, 0xff0007ff, WR_d,                   0,              D32     },
2614 {"repl.qh", "d,@",      0x7c000296, 0xfc0007ff, WR_d,                   0,              D64     },
2615 {"replv.ob", "d,t",     0x7c0000d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2616 {"replv.ph", "d,t",     0x7c0002d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2617 {"replv.pw", "d,t",     0x7c0004d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2618 {"replv.qb", "d,t",     0x7c0000d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
2619 {"replv.qh", "d,t",     0x7c0002d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
2620 {"shilo",   "7,0",      0x7c0006b8, 0xfc0fe7ff, MOD_a,                  0,              D32     },
2621 {"shilov",  "7,s",      0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,             0,              D32     },
2622 {"shll.ob", "d,t,3",    0x7c000017, 0xff0007ff, WR_d|RD_t,              0,              D64     },
2623 {"shll.ph", "d,t,4",    0x7c000213, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2624 {"shll.pw", "d,t,6",    0x7c000417, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2625 {"shll.qb", "d,t,3",    0x7c000013, 0xff0007ff, WR_d|RD_t,              0,              D32     },
2626 {"shll.qh", "d,t,4",    0x7c000217, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2627 {"shll_s.ph", "d,t,4",  0x7c000313, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2628 {"shll_s.pw", "d,t,6",  0x7c000517, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2629 {"shll_s.qh", "d,t,4",  0x7c000317, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2630 {"shll_s.w", "d,t,6",   0x7c000513, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
2631 {"shllv.ob", "d,t,s",   0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2632 {"shllv.ph", "d,t,s",   0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2633 {"shllv.pw", "d,t,s",   0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2634 {"shllv.qb", "d,t,s",   0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2635 {"shllv.qh", "d,t,s",   0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2636 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2637 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2638 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2639 {"shllv_s.w", "d,t,s",  0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2640 {"shra.ph", "d,t,4",    0x7c000253, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2641 {"shra.pw", "d,t,6",    0x7c000457, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2642 {"shra.qh", "d,t,4",    0x7c000257, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2643 {"shra_r.ph", "d,t,4",  0x7c000353, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
2644 {"shra_r.pw", "d,t,6",  0x7c000557, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
2645 {"shra_r.qh", "d,t,4",  0x7c000357, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
2646 {"shra_r.w", "d,t,6",   0x7c000553, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
2647 {"shrav.ph", "d,t,s",   0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2648 {"shrav.pw", "d,t,s",   0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2649 {"shrav.qh", "d,t,s",   0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2650 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2651 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2652 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2653 {"shrav_r.w", "d,t,s",  0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2654 {"shrl.ob", "d,t,3",    0x7c000057, 0xff0007ff, WR_d|RD_t,              0,              D64     },
2655 {"shrl.qb", "d,t,3",    0x7c000053, 0xff0007ff, WR_d|RD_t,              0,              D32     },
2656 {"shrlv.ob", "d,t,s",   0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2657 {"shrlv.qb", "d,t,s",   0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2658 {"subq.ph", "d,s,t",    0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2659 {"subq.pw", "d,s,t",    0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2660 {"subq.qh", "d,s,t",    0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2661 {"subq_s.ph", "d,s,t",  0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2662 {"subq_s.pw", "d,s,t",  0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2663 {"subq_s.qh", "d,s,t",  0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2664 {"subq_s.w", "d,s,t",   0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2665 {"subu.ob", "d,s,t",    0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2666 {"subu.qb", "d,s,t",    0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2667 {"subu_s.ob", "d,s,t",  0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
2668 {"subu_s.qb", "d,s,t",  0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
2669 {"wrdsp",   "s",        0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,          0,              D32     },
2670 {"wrdsp",   "s,8",      0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,          0,              D32     },
2671 /* MIPS DSP ASE Rev2 */
2672 {"absq_s.qb", "d,t",    0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              D33     },
2673 {"addu.ph", "d,s,t",    0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2674 {"addu_s.ph", "d,s,t",  0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2675 {"adduh.qb", "d,s,t",   0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2676 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2677 {"append",  "t,s,h",    0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
2678 {"balign",  "t,s,I",    0,    (int) M_BALIGN,   INSN_MACRO,             0,              D33     },
2679 {"balign",  "t,s,2",    0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              D33     },
2680 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
2681 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
2682 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
2683 {"dpa.w.ph", "7,s,t",   0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2684 {"dps.w.ph", "7,s,t",   0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2685 {"mul.ph",  "d,s,t",    0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2686 {"mul_s.ph", "d,s,t",   0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2687 {"mulq_rs.w", "d,s,t",  0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2688 {"mulq_s.ph", "d,s,t",  0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2689 {"mulq_s.w", "d,s,t",   0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
2690 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2691 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D33     },
2692 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              D33     },
2693 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              D33     },
2694 {"prepend", "t,s,h",    0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
2695 {"shra.qb", "d,t,3",    0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              D33     },
2696 {"shra_r.qb", "d,t,3",  0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              D33     },
2697 {"shrav.qb", "d,t,s",   0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2698 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2699 {"shrl.ph", "d,t,4",    0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              D33     },
2700 {"shrlv.ph", "d,t,s",   0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2701 {"subu.ph", "d,s,t",    0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2702 {"subu_s.ph", "d,s,t",  0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2703 {"subuh.qb", "d,s,t",   0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2704 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2705 {"addqh.ph", "d,s,t",   0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2706 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2707 {"addqh.w", "d,s,t",    0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2708 {"addqh_r.w", "d,s,t",  0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2709 {"subqh.ph", "d,s,t",   0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2710 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2711 {"subqh.w", "d,s,t",    0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2712 {"subqh_r.w", "d,s,t",  0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
2713 {"dpax.w.ph", "7,s,t",  0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2714 {"dpsx.w.ph", "7,s,t",  0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2715 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
2716 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
2717 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
2718 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
2719 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
2720 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2721 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2722 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
2723 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
2724 };
2725
2726 #define MIPS_NUM_OPCODES \
2727         ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
2728 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
2729
2730 /* const removed from the following to allow for dynamic extensions to the
2731  * built-in instruction set. */
2732 struct mips_opcode *mips_opcodes =
2733   (struct mips_opcode *) mips_builtin_opcodes;
2734 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
2735 #undef MIPS_NUM_OPCODES
2736
2737 /* Mips instructions are at maximum this many bytes long.  */
2738 #define INSNLEN 4
2739
2740 \f
2741 /* FIXME: These should be shared with gdb somehow.  */
2742
2743 struct mips_cp0sel_name
2744 {
2745   unsigned int cp0reg;
2746   unsigned int sel;
2747   const char * const name;
2748 };
2749
2750 /* The mips16 registers.  */
2751 static const unsigned int mips16_to_32_reg_map[] =
2752 {
2753   16, 17, 2, 3, 4, 5, 6, 7
2754 };
2755
2756 #define mips16_reg_names(rn)    mips_gpr_names[mips16_to_32_reg_map[rn]]
2757
2758
2759 static const char * const mips_gpr_names_numeric[32] =
2760 {
2761   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
2762   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
2763   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
2764   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
2765 };
2766
2767 static const char * const mips_gpr_names_oldabi[32] =
2768 {
2769   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
2770   "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
2771   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
2772   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
2773 };
2774
2775 static const char * const mips_gpr_names_newabi[32] =
2776 {
2777   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
2778   "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
2779   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
2780   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
2781 };
2782
2783 static const char * const mips_fpr_names_numeric[32] =
2784 {
2785   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
2786   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
2787   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
2788   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
2789 };
2790
2791 static const char * const mips_fpr_names_32[32] =
2792 {
2793   "fv0",  "fv0f", "fv1",  "fv1f", "ft0",  "ft0f", "ft1",  "ft1f",
2794   "ft2",  "ft2f", "ft3",  "ft3f", "fa0",  "fa0f", "fa1",  "fa1f",
2795   "ft4",  "ft4f", "ft5",  "ft5f", "fs0",  "fs0f", "fs1",  "fs1f",
2796   "fs2",  "fs2f", "fs3",  "fs3f", "fs4",  "fs4f", "fs5",  "fs5f"
2797 };
2798
2799 static const char * const mips_fpr_names_n32[32] =
2800 {
2801   "fv0",  "ft14", "fv1",  "ft15", "ft0",  "ft1",  "ft2",  "ft3",
2802   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
2803   "fa4",  "fa5",  "fa6",  "fa7",  "fs0",  "ft8",  "fs1",  "ft9",
2804   "fs2",  "ft10", "fs3",  "ft11", "fs4",  "ft12", "fs5",  "ft13"
2805 };
2806
2807 static const char * const mips_fpr_names_64[32] =
2808 {
2809   "fv0",  "ft12", "fv1",  "ft13", "ft0",  "ft1",  "ft2",  "ft3",
2810   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
2811   "fa4",  "fa5",  "fa6",  "fa7",  "ft8",  "ft9",  "ft10", "ft11",
2812   "fs0",  "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7"
2813 };
2814
2815 static const char * const mips_cp0_names_numeric[32] =
2816 {
2817   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
2818   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
2819   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
2820   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
2821 };
2822
2823 static const char * const mips_cp0_names_mips3264[32] =
2824 {
2825   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
2826   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
2827   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
2828   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
2829   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
2830   "c0_xcontext",  "$21",          "$22",          "c0_debug",
2831   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
2832   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
2833 };
2834
2835 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
2836 {
2837   {  4, 1, "c0_contextconfig"   },
2838   {  0, 1, "c0_mvpcontrol"      },
2839   {  0, 2, "c0_mvpconf0"        },
2840   {  0, 3, "c0_mvpconf1"        },
2841   {  1, 1, "c0_vpecontrol"      },
2842   {  1, 2, "c0_vpeconf0"        },
2843   {  1, 3, "c0_vpeconf1"        },
2844   {  1, 4, "c0_yqmask"          },
2845   {  1, 5, "c0_vpeschedule"     },
2846   {  1, 6, "c0_vpeschefback"    },
2847   {  2, 1, "c0_tcstatus"        },
2848   {  2, 2, "c0_tcbind"          },
2849   {  2, 3, "c0_tcrestart"       },
2850   {  2, 4, "c0_tchalt"          },
2851   {  2, 5, "c0_tccontext"       },
2852   {  2, 6, "c0_tcschedule"      },
2853   {  2, 7, "c0_tcschefback"     },
2854   {  5, 1, "c0_pagegrain"       },
2855   {  6, 1, "c0_srsconf0"        },
2856   {  6, 2, "c0_srsconf1"        },
2857   {  6, 3, "c0_srsconf2"        },
2858   {  6, 4, "c0_srsconf3"        },
2859   {  6, 5, "c0_srsconf4"        },
2860   { 12, 1, "c0_intctl"          },
2861   { 12, 2, "c0_srsctl"          },
2862   { 12, 3, "c0_srsmap"          },
2863   { 15, 1, "c0_ebase"           },
2864   { 16, 1, "c0_config1"         },
2865   { 16, 2, "c0_config2"         },
2866   { 16, 3, "c0_config3"         },
2867   { 18, 1, "c0_watchlo,1"       },
2868   { 18, 2, "c0_watchlo,2"       },
2869   { 18, 3, "c0_watchlo,3"       },
2870   { 18, 4, "c0_watchlo,4"       },
2871   { 18, 5, "c0_watchlo,5"       },
2872   { 18, 6, "c0_watchlo,6"       },
2873   { 18, 7, "c0_watchlo,7"       },
2874   { 19, 1, "c0_watchhi,1"       },
2875   { 19, 2, "c0_watchhi,2"       },
2876   { 19, 3, "c0_watchhi,3"       },
2877   { 19, 4, "c0_watchhi,4"       },
2878   { 19, 5, "c0_watchhi,5"       },
2879   { 19, 6, "c0_watchhi,6"       },
2880   { 19, 7, "c0_watchhi,7"       },
2881   { 23, 1, "c0_tracecontrol"    },
2882   { 23, 2, "c0_tracecontrol2"   },
2883   { 23, 3, "c0_usertracedata"   },
2884   { 23, 4, "c0_tracebpc"        },
2885   { 25, 1, "c0_perfcnt,1"       },
2886   { 25, 2, "c0_perfcnt,2"       },
2887   { 25, 3, "c0_perfcnt,3"       },
2888   { 25, 4, "c0_perfcnt,4"       },
2889   { 25, 5, "c0_perfcnt,5"       },
2890   { 25, 6, "c0_perfcnt,6"       },
2891   { 25, 7, "c0_perfcnt,7"       },
2892   { 27, 1, "c0_cacheerr,1"      },
2893   { 27, 2, "c0_cacheerr,2"      },
2894   { 27, 3, "c0_cacheerr,3"      },
2895   { 28, 1, "c0_datalo"          },
2896   { 28, 2, "c0_taglo1"          },
2897   { 28, 3, "c0_datalo1"         },
2898   { 28, 4, "c0_taglo2"          },
2899   { 28, 5, "c0_datalo2"         },
2900   { 28, 6, "c0_taglo3"          },
2901   { 28, 7, "c0_datalo3"         },
2902   { 29, 1, "c0_datahi"          },
2903   { 29, 2, "c0_taghi1"          },
2904   { 29, 3, "c0_datahi1"         },
2905   { 29, 4, "c0_taghi2"          },
2906   { 29, 5, "c0_datahi2"         },
2907   { 29, 6, "c0_taghi3"          },
2908   { 29, 7, "c0_datahi3"         },
2909 };
2910
2911 static const char * const mips_cp0_names_mips3264r2[32] =
2912 {
2913   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
2914   "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
2915   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
2916   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
2917   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
2918   "c0_xcontext",  "$21",          "$22",          "c0_debug",
2919   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
2920   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
2921 };
2922
2923 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
2924 {
2925   {  4, 1, "c0_contextconfig"   },
2926   {  5, 1, "c0_pagegrain"       },
2927   { 12, 1, "c0_intctl"          },
2928   { 12, 2, "c0_srsctl"          },
2929   { 12, 3, "c0_srsmap"          },
2930   { 15, 1, "c0_ebase"           },
2931   { 16, 1, "c0_config1"         },
2932   { 16, 2, "c0_config2"         },
2933   { 16, 3, "c0_config3"         },
2934   { 18, 1, "c0_watchlo,1"       },
2935   { 18, 2, "c0_watchlo,2"       },
2936   { 18, 3, "c0_watchlo,3"       },
2937   { 18, 4, "c0_watchlo,4"       },
2938   { 18, 5, "c0_watchlo,5"       },
2939   { 18, 6, "c0_watchlo,6"       },
2940   { 18, 7, "c0_watchlo,7"       },
2941   { 19, 1, "c0_watchhi,1"       },
2942   { 19, 2, "c0_watchhi,2"       },
2943   { 19, 3, "c0_watchhi,3"       },
2944   { 19, 4, "c0_watchhi,4"       },
2945   { 19, 5, "c0_watchhi,5"       },
2946   { 19, 6, "c0_watchhi,6"       },
2947   { 19, 7, "c0_watchhi,7"       },
2948   { 23, 1, "c0_tracecontrol"    },
2949   { 23, 2, "c0_tracecontrol2"   },
2950   { 23, 3, "c0_usertracedata"   },
2951   { 23, 4, "c0_tracebpc"        },
2952   { 25, 1, "c0_perfcnt,1"       },
2953   { 25, 2, "c0_perfcnt,2"       },
2954   { 25, 3, "c0_perfcnt,3"       },
2955   { 25, 4, "c0_perfcnt,4"       },
2956   { 25, 5, "c0_perfcnt,5"       },
2957   { 25, 6, "c0_perfcnt,6"       },
2958   { 25, 7, "c0_perfcnt,7"       },
2959   { 27, 1, "c0_cacheerr,1"      },
2960   { 27, 2, "c0_cacheerr,2"      },
2961   { 27, 3, "c0_cacheerr,3"      },
2962   { 28, 1, "c0_datalo"          },
2963   { 28, 2, "c0_taglo1"          },
2964   { 28, 3, "c0_datalo1"         },
2965   { 28, 4, "c0_taglo2"          },
2966   { 28, 5, "c0_datalo2"         },
2967   { 28, 6, "c0_taglo3"          },
2968   { 28, 7, "c0_datalo3"         },
2969   { 29, 1, "c0_datahi"          },
2970   { 29, 2, "c0_taghi1"          },
2971   { 29, 3, "c0_datahi1"         },
2972   { 29, 4, "c0_taghi2"          },
2973   { 29, 5, "c0_datahi2"         },
2974   { 29, 6, "c0_taghi3"          },
2975   { 29, 7, "c0_datahi3"         },
2976 };
2977
2978 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
2979 static const char * const mips_cp0_names_sb1[32] =
2980 {
2981   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
2982   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
2983   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
2984   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
2985   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
2986   "c0_xcontext",  "$21",          "$22",          "c0_debug",
2987   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
2988   "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
2989 };
2990
2991 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
2992 {
2993   { 16, 1, "c0_config1"         },
2994   { 18, 1, "c0_watchlo,1"       },
2995   { 19, 1, "c0_watchhi,1"       },
2996   { 22, 0, "c0_perftrace"       },
2997   { 23, 3, "c0_edebug"          },
2998   { 25, 1, "c0_perfcnt,1"       },
2999   { 25, 2, "c0_perfcnt,2"       },
3000   { 25, 3, "c0_perfcnt,3"       },
3001   { 25, 4, "c0_perfcnt,4"       },
3002   { 25, 5, "c0_perfcnt,5"       },
3003   { 25, 6, "c0_perfcnt,6"       },
3004   { 25, 7, "c0_perfcnt,7"       },
3005   { 26, 1, "c0_buserr_pa"       },
3006   { 27, 1, "c0_cacheerr_d"      },
3007   { 27, 3, "c0_cacheerr_d_pa"   },
3008   { 28, 1, "c0_datalo_i"        },
3009   { 28, 2, "c0_taglo_d"         },
3010   { 28, 3, "c0_datalo_d"        },
3011   { 29, 1, "c0_datahi_i"        },
3012   { 29, 2, "c0_taghi_d"         },
3013   { 29, 3, "c0_datahi_d"        },
3014 };
3015
3016 static const char * const mips_hwr_names_numeric[32] =
3017 {
3018   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3019   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3020   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3021   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3022 };
3023
3024 static const char * const mips_hwr_names_mips3264r2[32] =
3025 {
3026   "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
3027   "$4",          "$5",            "$6",           "$7",
3028   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3029   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3030   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3031 };
3032
3033 struct mips_abi_choice
3034 {
3035   const char *name;
3036   const char * const *gpr_names;
3037   const char * const *fpr_names;
3038 };
3039
3040 struct mips_abi_choice mips_abi_choices[] =
3041 {
3042   { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
3043   { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
3044   { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
3045   { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
3046 };
3047
3048 struct mips_arch_choice
3049 {
3050   const char *name;
3051   int bfd_mach_valid;
3052   unsigned long bfd_mach;
3053   int processor;
3054   int isa;
3055   const char * const *cp0_names;
3056   const struct mips_cp0sel_name *cp0sel_names;
3057   unsigned int cp0sel_names_len;
3058   const char * const *hwr_names;
3059 };
3060
3061 #define bfd_mach_mips3000              3000
3062 #define bfd_mach_mips3900              3900
3063 #define bfd_mach_mips4000              4000
3064 #define bfd_mach_mips4010              4010
3065 #define bfd_mach_mips4100              4100
3066 #define bfd_mach_mips4111              4111
3067 #define bfd_mach_mips4120              4120
3068 #define bfd_mach_mips4300              4300
3069 #define bfd_mach_mips4400              4400
3070 #define bfd_mach_mips4600              4600
3071 #define bfd_mach_mips4650              4650
3072 #define bfd_mach_mips5000              5000
3073 #define bfd_mach_mips5400              5400
3074 #define bfd_mach_mips5500              5500
3075 #define bfd_mach_mips6000              6000
3076 #define bfd_mach_mips7000              7000
3077 #define bfd_mach_mips8000              8000
3078 #define bfd_mach_mips9000              9000
3079 #define bfd_mach_mips10000             10000
3080 #define bfd_mach_mips12000             12000
3081 #define bfd_mach_mips16                16
3082 #define bfd_mach_mips5                 5
3083 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
3084 #define bfd_mach_mipsisa32             32
3085 #define bfd_mach_mipsisa32r2           33
3086 #define bfd_mach_mipsisa64             64
3087 #define bfd_mach_mipsisa64r2           65
3088
3089 #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
3090
3091 const struct mips_arch_choice mips_arch_choices[] =
3092 {
3093   { "numeric",  0, 0, 0, 0,
3094     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3095
3096   { "r3000",    1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
3097     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3098   { "r3900",    1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
3099     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3100   { "r4000",    1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
3101     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3102   { "r4010",    1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
3103     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3104   { "vr4100",   1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
3105     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3106   { "vr4111",   1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
3107     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3108   { "vr4120",   1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
3109     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3110   { "r4300",    1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
3111     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3112   { "r4400",    1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
3113     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3114   { "r4600",    1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
3115     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3116   { "r4650",    1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
3117     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3118   { "r5000",    1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3119     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3120   { "vr5400",   1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3121     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3122   { "vr5500",   1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3123     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3124   { "r6000",    1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
3125     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3126   { "rm7000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3127     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3128   { "rm9000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3129     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3130   { "r8000",    1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3131     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3132   { "r10000",   1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3133     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3134   { "r12000",   1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
3135     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3136   { "mips5",    1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3137     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3138
3139   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3140      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
3141      _MIPS32 Architecture For Programmers Volume I: Introduction to the
3142      MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
3143      page 1.  */
3144   { "mips32",   1, bfd_mach_mipsisa32, CPU_MIPS32,
3145     ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
3146     mips_cp0_names_mips3264,
3147     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3148     mips_hwr_names_numeric },
3149
3150   { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
3151     (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
3152      | INSN_MIPS3D | INSN_MT),
3153     mips_cp0_names_mips3264r2,
3154     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3155     mips_hwr_names_mips3264r2 },
3156
3157   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
3158   { "mips64",   1, bfd_mach_mipsisa64, CPU_MIPS64,
3159     ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3160     mips_cp0_names_mips3264,
3161     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3162     mips_hwr_names_numeric },
3163
3164   { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
3165     (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3166      | INSN_DSP64 | INSN_MT | INSN_MDMX),
3167     mips_cp0_names_mips3264r2,
3168     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3169     mips_hwr_names_mips3264r2 },
3170
3171   { "sb1",      1, bfd_mach_mips_sb1, CPU_SB1,
3172     ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
3173     mips_cp0_names_sb1,
3174     mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
3175     mips_hwr_names_numeric },
3176
3177   /* This entry, mips16, is here only for ISA/processor selection; do
3178      not print its name.  */
3179   { "",         1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
3180     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3181 };
3182
3183 /* ISA and processor type to disassemble for, and register names to use.
3184    set_default_mips_dis_options and parse_mips_dis_options fill in these
3185    values.  */
3186 static int mips_processor;
3187 static int mips_isa;
3188 static const char * const *mips_gpr_names;
3189 static const char * const *mips_fpr_names;
3190 static const char * const *mips_cp0_names;
3191 static const struct mips_cp0sel_name *mips_cp0sel_names;
3192 static int mips_cp0sel_names_len;
3193 static const char * const *mips_hwr_names;
3194
3195 /* Other options */
3196 static int no_aliases;  /* If set disassemble as most general inst.  */
3197 \f
3198 static const struct mips_abi_choice *
3199 choose_abi_by_name (const char *name, unsigned int namelen)
3200 {
3201   const struct mips_abi_choice *c;
3202   unsigned int i;
3203
3204   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
3205     if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
3206         && strlen (mips_abi_choices[i].name) == namelen)
3207       c = &mips_abi_choices[i];
3208
3209   return c;
3210 }
3211
3212 static const struct mips_arch_choice *
3213 choose_arch_by_name (const char *name, unsigned int namelen)
3214 {
3215   const struct mips_arch_choice *c = NULL;
3216   unsigned int i;
3217
3218   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3219     if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
3220         && strlen (mips_arch_choices[i].name) == namelen)
3221       c = &mips_arch_choices[i];
3222
3223   return c;
3224 }
3225
3226 static const struct mips_arch_choice *
3227 choose_arch_by_number (unsigned long mach)
3228 {
3229   static unsigned long hint_bfd_mach;
3230   static const struct mips_arch_choice *hint_arch_choice;
3231   const struct mips_arch_choice *c;
3232   unsigned int i;
3233
3234   /* We optimize this because even if the user specifies no
3235      flags, this will be done for every instruction!  */
3236   if (hint_bfd_mach == mach
3237       && hint_arch_choice != NULL
3238       && hint_arch_choice->bfd_mach == hint_bfd_mach)
3239     return hint_arch_choice;
3240
3241   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3242     {
3243       if (mips_arch_choices[i].bfd_mach_valid
3244           && mips_arch_choices[i].bfd_mach == mach)
3245         {
3246           c = &mips_arch_choices[i];
3247           hint_bfd_mach = mach;
3248           hint_arch_choice = c;
3249         }
3250     }
3251   return c;
3252 }
3253
3254 static void
3255 set_default_mips_dis_options (struct disassemble_info *info)
3256 {
3257   const struct mips_arch_choice *chosen_arch;
3258
3259   /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
3260      and numeric FPR, CP0 register, and HWR names.  */
3261   mips_isa = ISA_MIPS3;
3262   mips_processor =  CPU_R3000;
3263   mips_gpr_names = mips_gpr_names_oldabi;
3264   mips_fpr_names = mips_fpr_names_numeric;
3265   mips_cp0_names = mips_cp0_names_numeric;
3266   mips_cp0sel_names = NULL;
3267   mips_cp0sel_names_len = 0;
3268   mips_hwr_names = mips_hwr_names_numeric;
3269   no_aliases = 0;
3270
3271   /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
3272 #if 0
3273   if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
3274     {
3275       Elf_Internal_Ehdr *header;
3276
3277       header = elf_elfheader (info->section->owner);
3278       if (is_newabi (header))
3279         mips_gpr_names = mips_gpr_names_newabi;
3280     }
3281 #endif
3282
3283   /* Set ISA, architecture, and cp0 register names as best we can.  */
3284 #if !defined(SYMTAB_AVAILABLE) && 0
3285   /* This is running out on a target machine, not in a host tool.
3286      FIXME: Where does mips_target_info come from?  */
3287   target_processor = mips_target_info.processor;
3288   mips_isa = mips_target_info.isa;
3289 #else
3290   chosen_arch = choose_arch_by_number (info->mach);
3291   if (chosen_arch != NULL)
3292     {
3293       mips_processor = chosen_arch->processor;
3294       mips_isa = chosen_arch->isa;
3295       mips_cp0_names = chosen_arch->cp0_names;
3296       mips_cp0sel_names = chosen_arch->cp0sel_names;
3297       mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3298       mips_hwr_names = chosen_arch->hwr_names;
3299     }
3300 #endif
3301 }
3302
3303 static void
3304 parse_mips_dis_option (const char *option, unsigned int len)
3305 {
3306   unsigned int i, optionlen, vallen;
3307   const char *val;
3308   const struct mips_abi_choice *chosen_abi;
3309   const struct mips_arch_choice *chosen_arch;
3310
3311   /* Look for the = that delimits the end of the option name.  */
3312   for (i = 0; i < len; i++)
3313     {
3314       if (option[i] == '=')
3315         break;
3316     }
3317   if (i == 0)           /* Invalid option: no name before '='.  */
3318     return;
3319   if (i == len)         /* Invalid option: no '='.  */
3320     return;
3321   if (i == (len - 1))   /* Invalid option: no value after '='.  */
3322     return;
3323
3324   optionlen = i;
3325   val = option + (optionlen + 1);
3326   vallen = len - (optionlen + 1);
3327
3328   if (strncmp("gpr-names", option, optionlen) == 0
3329       && strlen("gpr-names") == optionlen)
3330     {
3331       chosen_abi = choose_abi_by_name (val, vallen);
3332       if (chosen_abi != NULL)
3333         mips_gpr_names = chosen_abi->gpr_names;
3334       return;
3335     }
3336
3337   if (strncmp("fpr-names", option, optionlen) == 0
3338       && strlen("fpr-names") == optionlen)
3339     {
3340       chosen_abi = choose_abi_by_name (val, vallen);
3341       if (chosen_abi != NULL)
3342         mips_fpr_names = chosen_abi->fpr_names;
3343       return;
3344     }
3345
3346   if (strncmp("cp0-names", option, optionlen) == 0
3347       && strlen("cp0-names") == optionlen)
3348     {
3349       chosen_arch = choose_arch_by_name (val, vallen);
3350       if (chosen_arch != NULL)
3351         {
3352           mips_cp0_names = chosen_arch->cp0_names;
3353           mips_cp0sel_names = chosen_arch->cp0sel_names;
3354           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3355         }
3356       return;
3357     }
3358
3359   if (strncmp("hwr-names", option, optionlen) == 0
3360       && strlen("hwr-names") == optionlen)
3361     {
3362       chosen_arch = choose_arch_by_name (val, vallen);
3363       if (chosen_arch != NULL)
3364         mips_hwr_names = chosen_arch->hwr_names;
3365       return;
3366     }
3367
3368   if (strncmp("reg-names", option, optionlen) == 0
3369       && strlen("reg-names") == optionlen)
3370     {
3371       /* We check both ABI and ARCH here unconditionally, so
3372          that "numeric" will do the desirable thing: select
3373          numeric register names for all registers.  Other than
3374          that, a given name probably won't match both.  */
3375       chosen_abi = choose_abi_by_name (val, vallen);
3376       if (chosen_abi != NULL)
3377         {
3378           mips_gpr_names = chosen_abi->gpr_names;
3379           mips_fpr_names = chosen_abi->fpr_names;
3380         }
3381       chosen_arch = choose_arch_by_name (val, vallen);
3382       if (chosen_arch != NULL)
3383         {
3384           mips_cp0_names = chosen_arch->cp0_names;
3385           mips_cp0sel_names = chosen_arch->cp0sel_names;
3386           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3387           mips_hwr_names = chosen_arch->hwr_names;
3388         }
3389       return;
3390     }
3391
3392   /* Invalid option.  */
3393 }
3394
3395 static void
3396 parse_mips_dis_options (const char *options)
3397 {
3398   const char *option_end;
3399
3400   if (options == NULL)
3401     return;
3402
3403   while (*options != '\0')
3404     {
3405       /* Skip empty options.  */
3406       if (*options == ',')
3407         {
3408           options++;
3409           continue;
3410         }
3411
3412       /* We know that *options is neither NUL or a comma.  */
3413       option_end = options + 1;
3414       while (*option_end != ',' && *option_end != '\0')
3415         option_end++;
3416
3417       parse_mips_dis_option (options, option_end - options);
3418
3419       /* Go on to the next one.  If option_end points to a comma, it
3420          will be skipped above.  */
3421       options = option_end;
3422     }
3423 }
3424
3425 static const struct mips_cp0sel_name *
3426 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
3427                          unsigned int len,
3428                          unsigned int cp0reg,
3429                          unsigned int sel)
3430 {
3431   unsigned int i;
3432
3433   for (i = 0; i < len; i++)
3434     if (names[i].cp0reg == cp0reg && names[i].sel == sel)
3435       return &names[i];
3436   return NULL;
3437 }
3438 \f
3439 /* Print insn arguments for 32/64-bit code.  */
3440
3441 static void
3442 print_insn_args (const char *d,
3443                  register unsigned long int l,
3444                  bfd_vma pc,
3445                  struct disassemble_info *info,
3446                  const struct mips_opcode *opp)
3447 {
3448   int op, delta;
3449   unsigned int lsb, msb, msbd;
3450
3451   lsb = 0;
3452
3453   for (; *d != '\0'; d++)
3454     {
3455       switch (*d)
3456         {
3457         case ',':
3458         case '(':
3459         case ')':
3460         case '[':
3461         case ']':
3462           (*info->fprintf_func) (info->stream, "%c", *d);
3463           break;
3464
3465         case '+':
3466           /* Extension character; switch for second char.  */
3467           d++;
3468           switch (*d)
3469             {
3470             case '\0':
3471               /* xgettext:c-format */
3472               (*info->fprintf_func) (info->stream,
3473                                      _("# internal error, incomplete extension sequence (+)"));
3474               return;
3475
3476             case 'A':
3477               lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
3478               (*info->fprintf_func) (info->stream, "0x%x", lsb);
3479               break;
3480
3481             case 'B':
3482               msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
3483               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3484               break;
3485
3486             case '1':
3487               (*info->fprintf_func) (info->stream, "0x%lx",
3488                                      (l >> OP_SH_UDI1) & OP_MASK_UDI1);
3489               break;
3490
3491             case '2':
3492               (*info->fprintf_func) (info->stream, "0x%lx",
3493                                      (l >> OP_SH_UDI2) & OP_MASK_UDI2);
3494               break;
3495
3496             case '3':
3497               (*info->fprintf_func) (info->stream, "0x%lx",
3498                                      (l >> OP_SH_UDI3) & OP_MASK_UDI3);
3499               break;
3500
3501             case '4':
3502               (*info->fprintf_func) (info->stream, "0x%lx",
3503                                      (l >> OP_SH_UDI4) & OP_MASK_UDI4);
3504               break;
3505
3506             case 'C':
3507             case 'H':
3508               msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
3509               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3510               break;
3511
3512             case 'D':
3513               {
3514                 const struct mips_cp0sel_name *n;
3515                 unsigned int cp0reg, sel;
3516
3517                 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
3518                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3519
3520                 /* CP0 register including 'sel' code for mtcN (et al.), to be
3521                    printed textually if known.  If not known, print both
3522                    CP0 register name and sel numerically since CP0 register
3523                    with sel 0 may have a name unrelated to register being
3524                    printed.  */
3525                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3526                                             mips_cp0sel_names_len, cp0reg, sel);
3527                 if (n != NULL)
3528                   (*info->fprintf_func) (info->stream, "%s", n->name);
3529                 else
3530                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3531                 break;
3532               }
3533
3534             case 'E':
3535               lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
3536               (*info->fprintf_func) (info->stream, "0x%x", lsb);
3537               break;
3538
3539             case 'F':
3540               msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
3541               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3542               break;
3543
3544             case 'G':
3545               msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
3546               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3547               break;
3548
3549             case 't': /* Coprocessor 0 reg name */
3550               (*info->fprintf_func) (info->stream, "%s",
3551                                      mips_cp0_names[(l >> OP_SH_RT) &
3552                                                      OP_MASK_RT]);
3553               break;
3554
3555             case 'T': /* Coprocessor 0 reg name */
3556               {
3557                 const struct mips_cp0sel_name *n;
3558                 unsigned int cp0reg, sel;
3559
3560                 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
3561                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3562
3563                 /* CP0 register including 'sel' code for mftc0, to be
3564                    printed textually if known.  If not known, print both
3565                    CP0 register name and sel numerically since CP0 register
3566                    with sel 0 may have a name unrelated to register being
3567                    printed.  */
3568                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3569                                             mips_cp0sel_names_len, cp0reg, sel);
3570                 if (n != NULL)
3571                   (*info->fprintf_func) (info->stream, "%s", n->name);
3572                 else
3573                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3574                 break;
3575               }
3576
3577             default:
3578               /* xgettext:c-format */
3579               (*info->fprintf_func) (info->stream,
3580                                      _("# internal error, undefined extension sequence (+%c)"),
3581                                      *d);
3582               return;
3583             }
3584           break;
3585
3586         case '2':
3587           (*info->fprintf_func) (info->stream, "0x%lx",
3588                                  (l >> OP_SH_BP) & OP_MASK_BP);
3589           break;
3590
3591         case '3':
3592           (*info->fprintf_func) (info->stream, "0x%lx",
3593                                  (l >> OP_SH_SA3) & OP_MASK_SA3);
3594           break;
3595
3596         case '4':
3597           (*info->fprintf_func) (info->stream, "0x%lx",
3598                                  (l >> OP_SH_SA4) & OP_MASK_SA4);
3599           break;
3600
3601         case '5':
3602           (*info->fprintf_func) (info->stream, "0x%lx",
3603                                  (l >> OP_SH_IMM8) & OP_MASK_IMM8);
3604           break;
3605
3606         case '6':
3607           (*info->fprintf_func) (info->stream, "0x%lx",
3608                                  (l >> OP_SH_RS) & OP_MASK_RS);
3609           break;
3610
3611         case '7':
3612           (*info->fprintf_func) (info->stream, "$ac%ld",
3613                                  (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
3614           break;
3615
3616         case '8':
3617           (*info->fprintf_func) (info->stream, "0x%lx",
3618                                  (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
3619           break;
3620
3621         case '9':
3622           (*info->fprintf_func) (info->stream, "$ac%ld",
3623                                  (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
3624           break;
3625
3626         case '0': /* dsp 6-bit signed immediate in bit 20 */
3627           delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
3628           if (delta & 0x20) /* test sign bit */
3629             delta |= ~OP_MASK_DSPSFT;
3630           (*info->fprintf_func) (info->stream, "%d", delta);
3631           break;
3632
3633         case ':': /* dsp 7-bit signed immediate in bit 19 */
3634           delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
3635           if (delta & 0x40) /* test sign bit */
3636             delta |= ~OP_MASK_DSPSFT_7;
3637           (*info->fprintf_func) (info->stream, "%d", delta);
3638           break;
3639
3640         case '\'':
3641           (*info->fprintf_func) (info->stream, "0x%lx",
3642                                  (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
3643           break;
3644
3645         case '@': /* dsp 10-bit signed immediate in bit 16 */
3646           delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
3647           if (delta & 0x200) /* test sign bit */
3648             delta |= ~OP_MASK_IMM10;
3649           (*info->fprintf_func) (info->stream, "%d", delta);
3650           break;
3651
3652         case '!':
3653           (*info->fprintf_func) (info->stream, "%ld",
3654                                  (l >> OP_SH_MT_U) & OP_MASK_MT_U);
3655           break;
3656
3657         case '$':
3658           (*info->fprintf_func) (info->stream, "%ld",
3659                                  (l >> OP_SH_MT_H) & OP_MASK_MT_H);
3660           break;
3661
3662         case '*':
3663           (*info->fprintf_func) (info->stream, "$ac%ld",
3664                                  (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
3665           break;
3666
3667         case '&':
3668           (*info->fprintf_func) (info->stream, "$ac%ld",
3669                                  (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
3670           break;
3671
3672         case 'g':
3673           /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2.  */
3674           (*info->fprintf_func) (info->stream, "$%ld",
3675                                  (l >> OP_SH_RD) & OP_MASK_RD);
3676           break;
3677
3678         case 's':
3679         case 'b':
3680         case 'r':
3681         case 'v':
3682           (*info->fprintf_func) (info->stream, "%s",
3683                                  mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
3684           break;
3685
3686         case 't':
3687         case 'w':
3688           (*info->fprintf_func) (info->stream, "%s",
3689                                  mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3690           break;
3691
3692         case 'i':
3693         case 'u':
3694           (*info->fprintf_func) (info->stream, "0x%lx",
3695                                  (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
3696           break;
3697
3698         case 'j': /* Same as i, but sign-extended.  */
3699         case 'o':
3700           delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3701           if (delta & 0x8000)
3702             delta |= ~0xffff;
3703           (*info->fprintf_func) (info->stream, "%d",
3704                                  delta);
3705           break;
3706
3707         case 'h':
3708           (*info->fprintf_func) (info->stream, "0x%x",
3709                                  (unsigned int) ((l >> OP_SH_PREFX)
3710                                                  & OP_MASK_PREFX));
3711           break;
3712
3713         case 'k':
3714           (*info->fprintf_func) (info->stream, "0x%x",
3715                                  (unsigned int) ((l >> OP_SH_CACHE)
3716                                                  & OP_MASK_CACHE));
3717           break;
3718
3719         case 'a':
3720           info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
3721                           | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
3722           /* For gdb disassembler, force odd address on jalx.  */
3723           if (info->flavour == bfd_target_unknown_flavour
3724               && strcmp (opp->name, "jalx") == 0)
3725             info->target |= 1;
3726           (*info->print_address_func) (info->target, info);
3727           break;
3728
3729         case 'p':
3730           /* Sign extend the displacement.  */
3731           delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3732           if (delta & 0x8000)
3733             delta |= ~0xffff;
3734           info->target = (delta << 2) + pc + INSNLEN;
3735           (*info->print_address_func) (info->target, info);
3736           break;
3737
3738         case 'd':
3739           (*info->fprintf_func) (info->stream, "%s",
3740                                  mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3741           break;
3742
3743         case 'U':
3744           {
3745             /* First check for both rd and rt being equal.  */
3746             unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
3747             if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
3748               (*info->fprintf_func) (info->stream, "%s",
3749                                      mips_gpr_names[reg]);
3750             else
3751               {
3752                 /* If one is zero use the other.  */
3753                 if (reg == 0)
3754                   (*info->fprintf_func) (info->stream, "%s",
3755                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3756                 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
3757                   (*info->fprintf_func) (info->stream, "%s",
3758                                          mips_gpr_names[reg]);
3759                 else /* Bogus, result depends on processor.  */
3760                   (*info->fprintf_func) (info->stream, "%s or %s",
3761                                          mips_gpr_names[reg],
3762                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3763               }
3764           }
3765           break;
3766
3767         case 'z':
3768           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
3769           break;
3770
3771         case '<':
3772           (*info->fprintf_func) (info->stream, "0x%lx",
3773                                  (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
3774           break;
3775
3776         case 'c':
3777           (*info->fprintf_func) (info->stream, "0x%lx",
3778                                  (l >> OP_SH_CODE) & OP_MASK_CODE);
3779           break;
3780
3781         case 'q':
3782           (*info->fprintf_func) (info->stream, "0x%lx",
3783                                  (l >> OP_SH_CODE2) & OP_MASK_CODE2);
3784           break;
3785
3786         case 'C':
3787           (*info->fprintf_func) (info->stream, "0x%lx",
3788                                  (l >> OP_SH_COPZ) & OP_MASK_COPZ);
3789           break;
3790
3791         case 'B':
3792           (*info->fprintf_func) (info->stream, "0x%lx",
3793
3794                                  (l >> OP_SH_CODE20) & OP_MASK_CODE20);
3795           break;
3796
3797         case 'J':
3798           (*info->fprintf_func) (info->stream, "0x%lx",
3799                                  (l >> OP_SH_CODE19) & OP_MASK_CODE19);
3800           break;
3801
3802         case 'S':
3803         case 'V':
3804           (*info->fprintf_func) (info->stream, "%s",
3805                                  mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
3806           break;
3807
3808         case 'T':
3809         case 'W':
3810           (*info->fprintf_func) (info->stream, "%s",
3811                                  mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
3812           break;
3813
3814         case 'D':
3815           (*info->fprintf_func) (info->stream, "%s",
3816                                  mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
3817           break;
3818
3819         case 'R':
3820           (*info->fprintf_func) (info->stream, "%s",
3821                                  mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
3822           break;
3823
3824         case 'E':
3825           /* Coprocessor register for lwcN instructions, et al.
3826
3827              Note that there is no load/store cp0 instructions, and
3828              that FPU (cp1) instructions disassemble this field using
3829              'T' format.  Therefore, until we gain understanding of
3830              cp2 register names, we can simply print the register
3831              numbers.  */
3832           (*info->fprintf_func) (info->stream, "$%ld",
3833                                  (l >> OP_SH_RT) & OP_MASK_RT);
3834           break;
3835
3836         case 'G':
3837           /* Coprocessor register for mtcN instructions, et al.  Note
3838              that FPU (cp1) instructions disassemble this field using
3839              'S' format.  Therefore, we only need to worry about cp0,
3840              cp2, and cp3.  */
3841           op = (l >> OP_SH_OP) & OP_MASK_OP;
3842           if (op == OP_OP_COP0)
3843             (*info->fprintf_func) (info->stream, "%s",
3844                                    mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3845           else
3846             (*info->fprintf_func) (info->stream, "$%ld",
3847                                    (l >> OP_SH_RD) & OP_MASK_RD);
3848           break;
3849
3850         case 'K':
3851           (*info->fprintf_func) (info->stream, "%s",
3852                                  mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3853           break;
3854
3855         case 'N':
3856           (*info->fprintf_func) (info->stream,
3857                                  ((opp->pinfo & (FP_D | FP_S)) != 0
3858                                   ? "$fcc%ld" : "$cc%ld"),
3859                                  (l >> OP_SH_BCC) & OP_MASK_BCC);
3860           break;
3861
3862         case 'M':
3863           (*info->fprintf_func) (info->stream, "$fcc%ld",
3864                                  (l >> OP_SH_CCC) & OP_MASK_CCC);
3865           break;
3866
3867         case 'P':
3868           (*info->fprintf_func) (info->stream, "%ld",
3869                                  (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
3870           break;
3871
3872         case 'e':
3873           (*info->fprintf_func) (info->stream, "%ld",
3874                                  (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
3875           break;
3876
3877         case '%':
3878           (*info->fprintf_func) (info->stream, "%ld",
3879                                  (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
3880           break;
3881
3882         case 'H':
3883           (*info->fprintf_func) (info->stream, "%ld",
3884                                  (l >> OP_SH_SEL) & OP_MASK_SEL);
3885           break;
3886
3887         case 'O':
3888           (*info->fprintf_func) (info->stream, "%ld",
3889                                  (l >> OP_SH_ALN) & OP_MASK_ALN);
3890           break;
3891
3892         case 'Q':
3893           {
3894             unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
3895
3896             if ((vsel & 0x10) == 0)
3897               {
3898                 int fmt;
3899
3900                 vsel &= 0x0f;
3901                 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
3902                   if ((vsel & 1) == 0)
3903                     break;
3904                 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
3905                                        (l >> OP_SH_FT) & OP_MASK_FT,
3906                                        vsel >> 1);
3907               }
3908             else if ((vsel & 0x08) == 0)
3909               {
3910                 (*info->fprintf_func) (info->stream, "$v%ld",
3911                                        (l >> OP_SH_FT) & OP_MASK_FT);
3912               }
3913             else
3914               {
3915                 (*info->fprintf_func) (info->stream, "0x%lx",
3916                                        (l >> OP_SH_FT) & OP_MASK_FT);
3917               }
3918           }
3919           break;
3920
3921         case 'X':
3922           (*info->fprintf_func) (info->stream, "$v%ld",
3923                                  (l >> OP_SH_FD) & OP_MASK_FD);
3924           break;
3925
3926         case 'Y':
3927           (*info->fprintf_func) (info->stream, "$v%ld",
3928                                  (l >> OP_SH_FS) & OP_MASK_FS);
3929           break;
3930
3931         case 'Z':
3932           (*info->fprintf_func) (info->stream, "$v%ld",
3933                                  (l >> OP_SH_FT) & OP_MASK_FT);
3934           break;
3935
3936         default:
3937           /* xgettext:c-format */
3938           (*info->fprintf_func) (info->stream,
3939                                  _("# internal error, undefined modifier(%c)"),
3940                                  *d);
3941           return;
3942         }
3943     }
3944 }
3945 \f
3946 /* Check if the object uses NewABI conventions.  */
3947 #if 0
3948 static int
3949 is_newabi (header)
3950      Elf_Internal_Ehdr *header;
3951 {
3952   /* There are no old-style ABIs which use 64-bit ELF.  */
3953   if (header->e_ident[EI_CLASS] == ELFCLASS64)
3954     return 1;
3955
3956   /* If a 32-bit ELF file, n32 is a new-style ABI.  */
3957   if ((header->e_flags & EF_MIPS_ABI2) != 0)
3958     return 1;
3959
3960   return 0;
3961 }
3962 #endif
3963 \f
3964 /* Print the mips instruction at address MEMADDR in debugged memory,
3965    on using INFO.  Returns length of the instruction, in bytes, which is
3966    always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
3967    this is little-endian code.  */
3968
3969 static int
3970 print_insn_mips (bfd_vma memaddr,
3971                  unsigned long int word,
3972                  struct disassemble_info *info)
3973 {
3974   const struct mips_opcode *op;
3975   static bfd_boolean init = 0;
3976   static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
3977
3978   /* Build a hash table to shorten the search time.  */
3979   if (! init)
3980     {
3981       unsigned int i;
3982
3983       for (i = 0; i <= OP_MASK_OP; i++)
3984         {
3985           for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
3986             {
3987               if (op->pinfo == INSN_MACRO
3988                   || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
3989                 continue;
3990               if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
3991                 {
3992                   mips_hash[i] = op;
3993                   break;
3994                 }
3995             }
3996         }
3997
3998       init = 1;
3999     }
4000
4001   info->bytes_per_chunk = INSNLEN;
4002   info->display_endian = info->endian;
4003   info->insn_info_valid = 1;
4004   info->branch_delay_insns = 0;
4005   info->data_size = 0;
4006   info->insn_type = dis_nonbranch;
4007   info->target = 0;
4008   info->target2 = 0;
4009
4010   op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
4011   if (op != NULL)
4012     {
4013       for (; op < &mips_opcodes[NUMOPCODES]; op++)
4014         {
4015           if (op->pinfo != INSN_MACRO
4016               && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4017               && (word & op->mask) == op->match)
4018             {
4019               const char *d;
4020
4021               /* We always allow to disassemble the jalx instruction.  */
4022               if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
4023                   && strcmp (op->name, "jalx"))
4024                 continue;
4025
4026               /* Figure out instruction type and branch delay information.  */
4027               if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4028                 {
4029                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4030                     info->insn_type = dis_jsr;
4031                   else
4032                     info->insn_type = dis_branch;
4033                   info->branch_delay_insns = 1;
4034                 }
4035               else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
4036                                      | INSN_COND_BRANCH_LIKELY)) != 0)
4037                 {
4038                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4039                     info->insn_type = dis_condjsr;
4040                   else
4041                     info->insn_type = dis_condbranch;
4042                   info->branch_delay_insns = 1;
4043                 }
4044               else if ((op->pinfo & (INSN_STORE_MEMORY
4045                                      | INSN_LOAD_MEMORY_DELAY)) != 0)
4046                 info->insn_type = dis_dref;
4047
4048               (*info->fprintf_func) (info->stream, "%s", op->name);
4049
4050               d = op->args;
4051               if (d != NULL && *d != '\0')
4052                 {
4053                   (*info->fprintf_func) (info->stream, "\t");
4054                   print_insn_args (d, word, memaddr, info, op);
4055                 }
4056
4057               return INSNLEN;
4058             }
4059         }
4060     }
4061
4062   /* Handle undefined instructions.  */
4063   info->insn_type = dis_noninsn;
4064   (*info->fprintf_func) (info->stream, "0x%lx", word);
4065   return INSNLEN;
4066 }
4067 \f
4068 /* In an environment where we do not know the symbol type of the
4069    instruction we are forced to assume that the low order bit of the
4070    instructions' address may mark it as a mips16 instruction.  If we
4071    are single stepping, or the pc is within the disassembled function,
4072    this works.  Otherwise, we need a clue.  Sometimes.  */
4073
4074 static int
4075 _print_insn_mips (bfd_vma memaddr,
4076                   struct disassemble_info *info,
4077                   enum bfd_endian endianness)
4078 {
4079   bfd_byte buffer[INSNLEN];
4080   int status;
4081
4082   set_default_mips_dis_options (info);
4083   parse_mips_dis_options (info->disassembler_options);
4084
4085 #if 0
4086 #if 1
4087   /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
4088   /* Only a few tools will work this way.  */
4089   if (memaddr & 0x01)
4090     return print_insn_mips16 (memaddr, info);
4091 #endif
4092
4093 #if SYMTAB_AVAILABLE
4094   if (info->mach == bfd_mach_mips16
4095       || (info->flavour == bfd_target_elf_flavour
4096           && info->symbols != NULL
4097           && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
4098               == STO_MIPS16)))
4099     return print_insn_mips16 (memaddr, info);
4100 #endif
4101 #endif
4102
4103   status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
4104   if (status == 0)
4105     {
4106       unsigned long insn;
4107
4108       if (endianness == BFD_ENDIAN_BIG)
4109         insn = (unsigned long) bfd_getb32 (buffer);
4110       else
4111         insn = (unsigned long) bfd_getl32 (buffer);
4112
4113       return print_insn_mips (memaddr, insn, info);
4114     }
4115   else
4116     {
4117       (*info->memory_error_func) (status, memaddr, info);
4118       return -1;
4119     }
4120 }
4121
4122 int
4123 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
4124 {
4125   return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
4126 }
4127
4128 int
4129 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
4130 {
4131   return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
4132 }
4133 \f
4134 /* Disassemble mips16 instructions.  */
4135 #if 0
4136 static int
4137 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
4138 {
4139   int status;
4140   bfd_byte buffer[2];
4141   int length;
4142   int insn;
4143   bfd_boolean use_extend;
4144   int extend = 0;
4145   const struct mips_opcode *op, *opend;
4146
4147   info->bytes_per_chunk = 2;
4148   info->display_endian = info->endian;
4149   info->insn_info_valid = 1;
4150   info->branch_delay_insns = 0;
4151   info->data_size = 0;
4152   info->insn_type = dis_nonbranch;
4153   info->target = 0;
4154   info->target2 = 0;
4155
4156   status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4157   if (status != 0)
4158     {
4159       (*info->memory_error_func) (status, memaddr, info);
4160       return -1;
4161     }
4162
4163   length = 2;
4164
4165   if (info->endian == BFD_ENDIAN_BIG)
4166     insn = bfd_getb16 (buffer);
4167   else
4168     insn = bfd_getl16 (buffer);
4169
4170   /* Handle the extend opcode specially.  */
4171   use_extend = FALSE;
4172   if ((insn & 0xf800) == 0xf000)
4173     {
4174       use_extend = TRUE;
4175       extend = insn & 0x7ff;
4176
4177       memaddr += 2;
4178
4179       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4180       if (status != 0)
4181         {
4182           (*info->fprintf_func) (info->stream, "extend 0x%x",
4183                                  (unsigned int) extend);
4184           (*info->memory_error_func) (status, memaddr, info);
4185           return -1;
4186         }
4187
4188       if (info->endian == BFD_ENDIAN_BIG)
4189         insn = bfd_getb16 (buffer);
4190       else
4191         insn = bfd_getl16 (buffer);
4192
4193       /* Check for an extend opcode followed by an extend opcode.  */
4194       if ((insn & 0xf800) == 0xf000)
4195         {
4196           (*info->fprintf_func) (info->stream, "extend 0x%x",
4197                                  (unsigned int) extend);
4198           info->insn_type = dis_noninsn;
4199           return length;
4200         }
4201
4202       length += 2;
4203     }
4204
4205   /* FIXME: Should probably use a hash table on the major opcode here.  */
4206
4207   opend = mips16_opcodes + bfd_mips16_num_opcodes;
4208   for (op = mips16_opcodes; op < opend; op++)
4209     {
4210       if (op->pinfo != INSN_MACRO
4211           && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4212           && (insn & op->mask) == op->match)
4213         {
4214           const char *s;
4215
4216           if (strchr (op->args, 'a') != NULL)
4217             {
4218               if (use_extend)
4219                 {
4220                   (*info->fprintf_func) (info->stream, "extend 0x%x",
4221                                          (unsigned int) extend);
4222                   info->insn_type = dis_noninsn;
4223                   return length - 2;
4224                 }
4225
4226               use_extend = FALSE;
4227
4228               memaddr += 2;
4229
4230               status = (*info->read_memory_func) (memaddr, buffer, 2,
4231                                                   info);
4232               if (status == 0)
4233                 {
4234                   use_extend = TRUE;
4235                   if (info->endian == BFD_ENDIAN_BIG)
4236                     extend = bfd_getb16 (buffer);
4237                   else
4238                     extend = bfd_getl16 (buffer);
4239                   length += 2;
4240                 }
4241             }
4242
4243           (*info->fprintf_func) (info->stream, "%s", op->name);
4244           if (op->args[0] != '\0')
4245             (*info->fprintf_func) (info->stream, "\t");
4246
4247           for (s = op->args; *s != '\0'; s++)
4248             {
4249               if (*s == ','
4250                   && s[1] == 'w'
4251                   && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
4252                       == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
4253                 {
4254                   /* Skip the register and the comma.  */
4255                   ++s;
4256                   continue;
4257                 }
4258               if (*s == ','
4259                   && s[1] == 'v'
4260                   && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
4261                       == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
4262                 {
4263                   /* Skip the register and the comma.  */
4264                   ++s;
4265                   continue;
4266                 }
4267               print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
4268                                      info);
4269             }
4270
4271           if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4272             {
4273               info->branch_delay_insns = 1;
4274               if (info->insn_type != dis_jsr)
4275                 info->insn_type = dis_branch;
4276             }
4277
4278           return length;
4279         }
4280     }
4281
4282   if (use_extend)
4283     (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
4284   (*info->fprintf_func) (info->stream, "0x%x", insn);
4285   info->insn_type = dis_noninsn;
4286
4287   return length;
4288 }
4289
4290 /* Disassemble an operand for a mips16 instruction.  */
4291
4292 static void
4293 print_mips16_insn_arg (char type,
4294                        const struct mips_opcode *op,
4295                        int l,
4296                        bfd_boolean use_extend,
4297                        int extend,
4298                        bfd_vma memaddr,
4299                        struct disassemble_info *info)
4300 {
4301   switch (type)
4302     {
4303     case ',':
4304     case '(':
4305     case ')':
4306       (*info->fprintf_func) (info->stream, "%c", type);
4307       break;
4308
4309     case 'y':
4310     case 'w':
4311       (*info->fprintf_func) (info->stream, "%s",
4312                              mips16_reg_names(((l >> MIPS16OP_SH_RY)
4313                                                & MIPS16OP_MASK_RY)));
4314       break;
4315
4316     case 'x':
4317     case 'v':
4318       (*info->fprintf_func) (info->stream, "%s",
4319                              mips16_reg_names(((l >> MIPS16OP_SH_RX)
4320                                                & MIPS16OP_MASK_RX)));
4321       break;
4322
4323     case 'z':
4324       (*info->fprintf_func) (info->stream, "%s",
4325                              mips16_reg_names(((l >> MIPS16OP_SH_RZ)
4326                                                & MIPS16OP_MASK_RZ)));
4327       break;
4328
4329     case 'Z':
4330       (*info->fprintf_func) (info->stream, "%s",
4331                              mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
4332                                                & MIPS16OP_MASK_MOVE32Z)));
4333       break;
4334
4335     case '0':
4336       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
4337       break;
4338
4339     case 'S':
4340       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
4341       break;
4342
4343     case 'P':
4344       (*info->fprintf_func) (info->stream, "$pc");
4345       break;
4346
4347     case 'R':
4348       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
4349       break;
4350
4351     case 'X':
4352       (*info->fprintf_func) (info->stream, "%s",
4353                              mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
4354                                             & MIPS16OP_MASK_REGR32)]);
4355       break;
4356
4357     case 'Y':
4358       (*info->fprintf_func) (info->stream, "%s",
4359                              mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
4360       break;
4361
4362     case '<':
4363     case '>':
4364     case '[':
4365     case ']':
4366     case '4':
4367     case '5':
4368     case 'H':
4369     case 'W':
4370     case 'D':
4371     case 'j':
4372     case '6':
4373     case '8':
4374     case 'V':
4375     case 'C':
4376     case 'U':
4377     case 'k':
4378     case 'K':
4379     case 'p':
4380     case 'q':
4381     case 'A':
4382     case 'B':
4383     case 'E':
4384       {
4385         int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
4386
4387         shift = 0;
4388         signedp = 0;
4389         extbits = 16;
4390         pcrel = 0;
4391         extu = 0;
4392         branch = 0;
4393         switch (type)
4394           {
4395           case '<':
4396             nbits = 3;
4397             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4398             extbits = 5;
4399             extu = 1;
4400             break;
4401           case '>':
4402             nbits = 3;
4403             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4404             extbits = 5;
4405             extu = 1;
4406             break;
4407           case '[':
4408             nbits = 3;
4409             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4410             extbits = 6;
4411             extu = 1;
4412             break;
4413           case ']':
4414             nbits = 3;
4415             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4416             extbits = 6;
4417             extu = 1;
4418             break;
4419           case '4':
4420             nbits = 4;
4421             immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
4422             signedp = 1;
4423             extbits = 15;
4424             break;
4425           case '5':
4426             nbits = 5;
4427             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4428             info->insn_type = dis_dref;
4429             info->data_size = 1;
4430             break;
4431           case 'H':
4432             nbits = 5;
4433             shift = 1;
4434             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4435             info->insn_type = dis_dref;
4436             info->data_size = 2;
4437             break;
4438           case 'W':
4439             nbits = 5;
4440             shift = 2;
4441             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4442             if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
4443                 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
4444               {
4445                 info->insn_type = dis_dref;
4446                 info->data_size = 4;
4447               }
4448             break;
4449           case 'D':
4450             nbits = 5;
4451             shift = 3;
4452             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4453             info->insn_type = dis_dref;
4454             info->data_size = 8;
4455             break;
4456           case 'j':
4457             nbits = 5;
4458             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4459             signedp = 1;
4460             break;
4461           case '6':
4462             nbits = 6;
4463             immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4464             break;
4465           case '8':
4466             nbits = 8;
4467             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4468             break;
4469           case 'V':
4470             nbits = 8;
4471             shift = 2;
4472             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4473             /* FIXME: This might be lw, or it might be addiu to $sp or
4474                $pc.  We assume it's load.  */
4475             info->insn_type = dis_dref;
4476             info->data_size = 4;
4477             break;
4478           case 'C':
4479             nbits = 8;
4480             shift = 3;
4481             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4482             info->insn_type = dis_dref;
4483             info->data_size = 8;
4484             break;
4485           case 'U':
4486             nbits = 8;
4487             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4488             extu = 1;
4489             break;
4490           case 'k':
4491             nbits = 8;
4492             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4493             signedp = 1;
4494             break;
4495           case 'K':
4496             nbits = 8;
4497             shift = 3;
4498             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4499             signedp = 1;
4500             break;
4501           case 'p':
4502             nbits = 8;
4503             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4504             signedp = 1;
4505             pcrel = 1;
4506             branch = 1;
4507             info->insn_type = dis_condbranch;
4508             break;
4509           case 'q':
4510             nbits = 11;
4511             immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
4512             signedp = 1;
4513             pcrel = 1;
4514             branch = 1;
4515             info->insn_type = dis_branch;
4516             break;
4517           case 'A':
4518             nbits = 8;
4519             shift = 2;
4520             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4521             pcrel = 1;
4522             /* FIXME: This can be lw or la.  We assume it is lw.  */
4523             info->insn_type = dis_dref;
4524             info->data_size = 4;
4525             break;
4526           case 'B':
4527             nbits = 5;
4528             shift = 3;
4529             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4530             pcrel = 1;
4531             info->insn_type = dis_dref;
4532             info->data_size = 8;
4533             break;
4534           case 'E':
4535             nbits = 5;
4536             shift = 2;
4537             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4538             pcrel = 1;
4539             break;
4540           default:
4541             abort ();
4542           }
4543
4544         if (! use_extend)
4545           {
4546             if (signedp && immed >= (1 << (nbits - 1)))
4547               immed -= 1 << nbits;
4548             immed <<= shift;
4549             if ((type == '<' || type == '>' || type == '[' || type == ']')
4550                 && immed == 0)
4551               immed = 8;
4552           }
4553         else
4554           {
4555             if (extbits == 16)
4556               immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
4557             else if (extbits == 15)
4558               immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
4559             else
4560               immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
4561             immed &= (1 << extbits) - 1;
4562             if (! extu && immed >= (1 << (extbits - 1)))
4563               immed -= 1 << extbits;
4564           }
4565
4566         if (! pcrel)
4567           (*info->fprintf_func) (info->stream, "%d", immed);
4568         else
4569           {
4570             bfd_vma baseaddr;
4571
4572             if (branch)
4573               {
4574                 immed *= 2;
4575                 baseaddr = memaddr + 2;
4576               }
4577             else if (use_extend)
4578               baseaddr = memaddr - 2;
4579             else
4580               {
4581                 int status;
4582                 bfd_byte buffer[2];
4583
4584                 baseaddr = memaddr;
4585
4586                 /* If this instruction is in the delay slot of a jr
4587                    instruction, the base address is the address of the
4588                    jr instruction.  If it is in the delay slot of jalr
4589                    instruction, the base address is the address of the
4590                    jalr instruction.  This test is unreliable: we have
4591                    no way of knowing whether the previous word is
4592                    instruction or data.  */
4593                 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
4594                                                     info);
4595                 if (status == 0
4596                     && (((info->endian == BFD_ENDIAN_BIG
4597                           ? bfd_getb16 (buffer)
4598                           : bfd_getl16 (buffer))
4599                          & 0xf800) == 0x1800))
4600                   baseaddr = memaddr - 4;
4601                 else
4602                   {
4603                     status = (*info->read_memory_func) (memaddr - 2, buffer,
4604                                                         2, info);
4605                     if (status == 0
4606                         && (((info->endian == BFD_ENDIAN_BIG
4607                               ? bfd_getb16 (buffer)
4608                               : bfd_getl16 (buffer))
4609                              & 0xf81f) == 0xe800))
4610                       baseaddr = memaddr - 2;
4611                   }
4612               }
4613             info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
4614             if (pcrel && branch
4615                 && info->flavour == bfd_target_unknown_flavour)
4616               /* For gdb disassembler, maintain odd address.  */
4617               info->target |= 1;
4618             (*info->print_address_func) (info->target, info);
4619           }
4620       }
4621       break;
4622
4623     case 'a':
4624       {
4625         int jalx = l & 0x400;
4626
4627         if (! use_extend)
4628           extend = 0;
4629         l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
4630         if (!jalx && info->flavour == bfd_target_unknown_flavour)
4631           /* For gdb disassembler, maintain odd address.  */
4632           l |= 1;
4633       }
4634       info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
4635       (*info->print_address_func) (info->target, info);
4636       info->insn_type = dis_jsr;
4637       info->branch_delay_insns = 1;
4638       break;
4639
4640     case 'l':
4641     case 'L':
4642       {
4643         int need_comma, amask, smask;
4644
4645         need_comma = 0;
4646
4647         l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4648
4649         amask = (l >> 3) & 7;
4650
4651         if (amask > 0 && amask < 5)
4652           {
4653             (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4654             if (amask > 1)
4655               (*info->fprintf_func) (info->stream, "-%s",
4656                                      mips_gpr_names[amask + 3]);
4657             need_comma = 1;
4658           }
4659
4660         smask = (l >> 1) & 3;
4661         if (smask == 3)
4662           {
4663             (*info->fprintf_func) (info->stream, "%s??",
4664                                    need_comma ? "," : "");
4665             need_comma = 1;
4666           }
4667         else if (smask > 0)
4668           {
4669             (*info->fprintf_func) (info->stream, "%s%s",
4670                                    need_comma ? "," : "",
4671                                    mips_gpr_names[16]);
4672             if (smask > 1)
4673               (*info->fprintf_func) (info->stream, "-%s",
4674                                      mips_gpr_names[smask + 15]);
4675             need_comma = 1;
4676           }
4677
4678         if (l & 1)
4679           {
4680             (*info->fprintf_func) (info->stream, "%s%s",
4681                                    need_comma ? "," : "",
4682                                    mips_gpr_names[31]);
4683             need_comma = 1;
4684           }
4685
4686         if (amask == 5 || amask == 6)
4687           {
4688             (*info->fprintf_func) (info->stream, "%s$f0",
4689                                    need_comma ? "," : "");
4690             if (amask == 6)
4691               (*info->fprintf_func) (info->stream, "-$f1");
4692           }
4693       }
4694       break;
4695
4696     case 'm':
4697     case 'M':
4698       /* MIPS16e save/restore.  */
4699       {
4700       int need_comma = 0;
4701       int amask, args, statics;
4702       int nsreg, smask;
4703       int framesz;
4704       int i, j;
4705
4706       l = l & 0x7f;
4707       if (use_extend)
4708         l |= extend << 16;
4709
4710       amask = (l >> 16) & 0xf;
4711       if (amask == MIPS16_ALL_ARGS)
4712         {
4713           args = 4;
4714           statics = 0;
4715         }
4716       else if (amask == MIPS16_ALL_STATICS)
4717         {
4718           args = 0;
4719           statics = 4;
4720         }
4721       else
4722         {
4723           args = amask >> 2;
4724           statics = amask & 3;
4725         }
4726
4727       if (args > 0) {
4728           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4729           if (args > 1)
4730             (*info->fprintf_func) (info->stream, "-%s",
4731                                    mips_gpr_names[4 + args - 1]);
4732           need_comma = 1;
4733       }
4734
4735       framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
4736       if (framesz == 0 && !use_extend)
4737         framesz = 128;
4738
4739       (*info->fprintf_func) (info->stream, "%s%d",
4740                              need_comma ? "," : "",
4741                              framesz);
4742
4743       if (l & 0x40)                   /* $ra */
4744         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
4745
4746       nsreg = (l >> 24) & 0x7;
4747       smask = 0;
4748       if (l & 0x20)                   /* $s0 */
4749         smask |= 1 << 0;
4750       if (l & 0x10)                   /* $s1 */
4751         smask |= 1 << 1;
4752       if (nsreg > 0)                  /* $s2-$s8 */
4753         smask |= ((1 << nsreg) - 1) << 2;
4754
4755       /* Find first set static reg bit.  */
4756       for (i = 0; i < 9; i++)
4757         {
4758           if (smask & (1 << i))
4759             {
4760               (*info->fprintf_func) (info->stream, ",%s",
4761                                      mips_gpr_names[i == 8 ? 30 : (16 + i)]);
4762               /* Skip over string of set bits.  */
4763               for (j = i; smask & (2 << j); j++)
4764                 continue;
4765               if (j > i)
4766                 (*info->fprintf_func) (info->stream, "-%s",
4767                                        mips_gpr_names[j == 8 ? 30 : (16 + j)]);
4768               i = j + 1;
4769             }
4770         }
4771
4772       /* Statics $ax - $a3.  */
4773       if (statics == 1)
4774         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
4775       else if (statics > 0)
4776         (*info->fprintf_func) (info->stream, ",%s-%s",
4777                                mips_gpr_names[7 - statics + 1],
4778                                mips_gpr_names[7]);
4779       }
4780       break;
4781
4782     default:
4783       /* xgettext:c-format */
4784       (*info->fprintf_func)
4785         (info->stream,
4786          _("# internal disassembler error, unrecognised modifier (%c)"),
4787          type);
4788       abort ();
4789     }
4790 }
4791
4792 void
4793 print_mips_disassembler_options (FILE *stream)
4794 {
4795   unsigned int i;
4796
4797   fprintf (stream, _("\n\
4798 The following MIPS specific disassembler options are supported for use\n\
4799 with the -M switch (multiple options should be separated by commas):\n"));
4800
4801   fprintf (stream, _("\n\
4802   gpr-names=ABI            Print GPR names according to  specified ABI.\n\
4803                            Default: based on binary being disassembled.\n"));
4804
4805   fprintf (stream, _("\n\
4806   fpr-names=ABI            Print FPR names according to specified ABI.\n\
4807                            Default: numeric.\n"));
4808
4809   fprintf (stream, _("\n\
4810   cp0-names=ARCH           Print CP0 register names according to\n\
4811                            specified architecture.\n\
4812                            Default: based on binary being disassembled.\n"));
4813
4814   fprintf (stream, _("\n\
4815   hwr-names=ARCH           Print HWR names according to specified \n\
4816                            architecture.\n\
4817                            Default: based on binary being disassembled.\n"));
4818
4819   fprintf (stream, _("\n\
4820   reg-names=ABI            Print GPR and FPR names according to\n\
4821                            specified ABI.\n"));
4822
4823   fprintf (stream, _("\n\
4824   reg-names=ARCH           Print CP0 register and HWR names according to\n\
4825                            specified architecture.\n"));
4826
4827   fprintf (stream, _("\n\
4828   For the options above, the following values are supported for \"ABI\":\n\
4829    "));
4830   for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
4831     fprintf (stream, " %s", mips_abi_choices[i].name);
4832   fprintf (stream, _("\n"));
4833
4834   fprintf (stream, _("\n\
4835   For the options above, The following values are supported for \"ARCH\":\n\
4836    "));
4837   for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
4838     if (*mips_arch_choices[i].name != '\0')
4839       fprintf (stream, " %s", mips_arch_choices[i].name);
4840   fprintf (stream, _("\n"));
4841
4842   fprintf (stream, _("\n"));
4843 }
4844 #endif