1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+sve | FileCheck %s
4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
5 target triple = "aarch64-unknown-linux-gnu"
7 ; Make sure callers set up the arguments correctly - tests AArch64ISelLowering::LowerCALL
9 define float @foo1(double* %x0, double* %x1, double* %x2) nounwind {
11 ; CHECK: // %bb.0: // %entry
12 ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
13 ; CHECK-NEXT: addvl sp, sp, #-4
14 ; CHECK-NEXT: ptrue p0.b
15 ; CHECK-NEXT: fmov s0, #1.00000000
16 ; CHECK-NEXT: ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
17 ; CHECK-NEXT: ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1]
18 ; CHECK-NEXT: ld1d { z5.d }, p0/z, [x2]
19 ; CHECK-NEXT: mov x0, sp
20 ; CHECK-NEXT: ptrue p0.d
21 ; CHECK-NEXT: st1d { z16.d }, p0, [sp]
22 ; CHECK-NEXT: st1d { z17.d }, p0, [sp, #1, mul vl]
23 ; CHECK-NEXT: st1d { z18.d }, p0, [sp, #2, mul vl]
24 ; CHECK-NEXT: st1d { z19.d }, p0, [sp, #3, mul vl]
25 ; CHECK-NEXT: bl callee1
26 ; CHECK-NEXT: addvl sp, sp, #4
27 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
30 %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
31 %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
32 %2 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x0)
33 %3 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x1)
34 %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1> %1, double* %x2)
35 %call = call float @callee1(float 1.000000e+00, <vscale x 8 x double> %2, <vscale x 8 x double> %3, <vscale x 2 x double> %4)
39 define float @foo2(double* %x0, double* %x1) nounwind {
41 ; CHECK: // %bb.0: // %entry
42 ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
43 ; CHECK-NEXT: addvl sp, sp, #-4
44 ; CHECK-NEXT: sub sp, sp, #16
45 ; CHECK-NEXT: ptrue p0.b
46 ; CHECK-NEXT: add x9, sp, #16
47 ; CHECK-NEXT: ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
48 ; CHECK-NEXT: ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1]
49 ; CHECK-NEXT: ptrue p0.d
50 ; CHECK-NEXT: add x8, sp, #16
51 ; CHECK-NEXT: fmov s0, #1.00000000
52 ; CHECK-NEXT: mov w0, wzr
53 ; CHECK-NEXT: mov w1, #1
54 ; CHECK-NEXT: mov w2, #2
55 ; CHECK-NEXT: st1d { z16.d }, p0, [x9]
56 ; CHECK-NEXT: add x9, sp, #16
57 ; CHECK-NEXT: mov w3, #3
58 ; CHECK-NEXT: mov w4, #4
59 ; CHECK-NEXT: mov w5, #5
60 ; CHECK-NEXT: mov w6, #6
61 ; CHECK-NEXT: st1d { z17.d }, p0, [x9, #1, mul vl]
62 ; CHECK-NEXT: add x9, sp, #16
63 ; CHECK-NEXT: mov w7, #7
64 ; CHECK-NEXT: st1d { z18.d }, p0, [x9, #2, mul vl]
65 ; CHECK-NEXT: add x9, sp, #16
66 ; CHECK-NEXT: st1d { z19.d }, p0, [x9, #3, mul vl]
67 ; CHECK-NEXT: str x8, [sp]
68 ; CHECK-NEXT: bl callee2
69 ; CHECK-NEXT: addvl sp, sp, #4
70 ; CHECK-NEXT: add sp, sp, #16
71 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
74 %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
75 %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
76 %2 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x0)
77 %3 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x1)
78 %call = call float @callee2(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, float 1.000000e+00, <vscale x 8 x double> %2, <vscale x 8 x double> %3)
82 define float @foo3(double* %x0, double* %x1, double* %x2) nounwind {
84 ; CHECK: // %bb.0: // %entry
85 ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
86 ; CHECK-NEXT: addvl sp, sp, #-3
87 ; CHECK-NEXT: ptrue p0.b
88 ; CHECK-NEXT: fmov s0, #1.00000000
89 ; CHECK-NEXT: ld4d { z2.d, z3.d, z4.d, z5.d }, p0/z, [x0]
90 ; CHECK-NEXT: ld3d { z16.d, z17.d, z18.d }, p0/z, [x1]
91 ; CHECK-NEXT: ld1d { z6.d }, p0/z, [x2]
92 ; CHECK-NEXT: fmov s1, #2.00000000
93 ; CHECK-NEXT: mov x0, sp
94 ; CHECK-NEXT: ptrue p0.d
95 ; CHECK-NEXT: st1d { z16.d }, p0, [sp]
96 ; CHECK-NEXT: st1d { z17.d }, p0, [sp, #1, mul vl]
97 ; CHECK-NEXT: st1d { z18.d }, p0, [sp, #2, mul vl]
98 ; CHECK-NEXT: bl callee3
99 ; CHECK-NEXT: addvl sp, sp, #3
100 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
103 %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
104 %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
105 %2 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x0)
106 %3 = call <vscale x 6 x double> @llvm.aarch64.sve.ld3.nxv6f64.nxv2i1(<vscale x 2 x i1> %1, double* %x1)
107 %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1> %1, double* %x2)
108 %call = call float @callee3(float 1.000000e+00, float 2.000000e+00, <vscale x 8 x double> %2, <vscale x 6 x double> %3, <vscale x 2 x double> %4)
112 ; Make sure callees read the arguments correctly - tests AArch64ISelLowering::LowerFormalArguments
114 define double @foo4(double %x0, double * %ptr1, double * %ptr2, double * %ptr3, <vscale x 8 x double> %x1, <vscale x 8 x double> %x2, <vscale x 2 x double> %x3) nounwind {
116 ; CHECK: // %bb.0: // %entry
117 ; CHECK-NEXT: ptrue p0.d
118 ; CHECK-NEXT: ld1d { z6.d }, p0/z, [x3, #1, mul vl]
119 ; CHECK-NEXT: ld1d { z7.d }, p0/z, [x3]
120 ; CHECK-NEXT: ld1d { z24.d }, p0/z, [x3, #3, mul vl]
121 ; CHECK-NEXT: ld1d { z25.d }, p0/z, [x3, #2, mul vl]
122 ; CHECK-NEXT: st1d { z4.d }, p0, [x0, #3, mul vl]
123 ; CHECK-NEXT: st1d { z3.d }, p0, [x0, #2, mul vl]
124 ; CHECK-NEXT: st1d { z2.d }, p0, [x0, #1, mul vl]
125 ; CHECK-NEXT: st1d { z1.d }, p0, [x0]
126 ; CHECK-NEXT: st1d { z25.d }, p0, [x1, #2, mul vl]
127 ; CHECK-NEXT: st1d { z24.d }, p0, [x1, #3, mul vl]
128 ; CHECK-NEXT: st1d { z7.d }, p0, [x1]
129 ; CHECK-NEXT: st1d { z6.d }, p0, [x1, #1, mul vl]
130 ; CHECK-NEXT: st1d { z5.d }, p0, [x2]
133 %ptr1.bc = bitcast double * %ptr1 to <vscale x 8 x double> *
134 store volatile <vscale x 8 x double> %x1, <vscale x 8 x double>* %ptr1.bc
135 %ptr2.bc = bitcast double * %ptr2 to <vscale x 8 x double> *
136 store volatile <vscale x 8 x double> %x2, <vscale x 8 x double>* %ptr2.bc
137 %ptr3.bc = bitcast double * %ptr3 to <vscale x 2 x double> *
138 store volatile <vscale x 2 x double> %x3, <vscale x 2 x double>* %ptr3.bc
142 define double @foo5(i32 %i0, i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, double * %ptr1, double * %ptr2, double %x0, <vscale x 8 x double> %x1, <vscale x 8 x double> %x2) nounwind {
144 ; CHECK: // %bb.0: // %entry
145 ; CHECK-NEXT: ldr x8, [sp]
146 ; CHECK-NEXT: ptrue p0.d
147 ; CHECK-NEXT: ld1d { z5.d }, p0/z, [x8, #1, mul vl]
148 ; CHECK-NEXT: ld1d { z6.d }, p0/z, [x8]
149 ; CHECK-NEXT: ld1d { z7.d }, p0/z, [x8, #3, mul vl]
150 ; CHECK-NEXT: ld1d { z24.d }, p0/z, [x8, #2, mul vl]
151 ; CHECK-NEXT: st1d { z4.d }, p0, [x6, #3, mul vl]
152 ; CHECK-NEXT: st1d { z3.d }, p0, [x6, #2, mul vl]
153 ; CHECK-NEXT: st1d { z2.d }, p0, [x6, #1, mul vl]
154 ; CHECK-NEXT: st1d { z1.d }, p0, [x6]
155 ; CHECK-NEXT: st1d { z24.d }, p0, [x7, #2, mul vl]
156 ; CHECK-NEXT: st1d { z7.d }, p0, [x7, #3, mul vl]
157 ; CHECK-NEXT: st1d { z6.d }, p0, [x7]
158 ; CHECK-NEXT: st1d { z5.d }, p0, [x7, #1, mul vl]
161 %ptr1.bc = bitcast double * %ptr1 to <vscale x 8 x double> *
162 store volatile <vscale x 8 x double> %x1, <vscale x 8 x double>* %ptr1.bc
163 %ptr2.bc = bitcast double * %ptr2 to <vscale x 8 x double> *
164 store volatile <vscale x 8 x double> %x2, <vscale x 8 x double>* %ptr2.bc
168 define double @foo6(double %x0, double %x1, double * %ptr1, double * %ptr2, <vscale x 8 x double> %x2, <vscale x 6 x double> %x3) nounwind {
170 ; CHECK: // %bb.0: // %entry
171 ; CHECK-NEXT: ptrue p0.d
172 ; CHECK-NEXT: ld1d { z1.d }, p0/z, [x2]
173 ; CHECK-NEXT: ld1d { z6.d }, p0/z, [x2, #2, mul vl]
174 ; CHECK-NEXT: ld1d { z7.d }, p0/z, [x2, #1, mul vl]
175 ; CHECK-NEXT: st1d { z5.d }, p0, [x0, #3, mul vl]
176 ; CHECK-NEXT: st1d { z4.d }, p0, [x0, #2, mul vl]
177 ; CHECK-NEXT: st1d { z3.d }, p0, [x0, #1, mul vl]
178 ; CHECK-NEXT: st1d { z2.d }, p0, [x0]
179 ; CHECK-NEXT: st1d { z7.d }, p0, [x1, #1, mul vl]
180 ; CHECK-NEXT: st1d { z6.d }, p0, [x1, #2, mul vl]
181 ; CHECK-NEXT: st1d { z1.d }, p0, [x1]
184 %ptr1.bc = bitcast double * %ptr1 to <vscale x 8 x double> *
185 store volatile <vscale x 8 x double> %x2, <vscale x 8 x double>* %ptr1.bc
186 %ptr2.bc = bitcast double * %ptr2 to <vscale x 6 x double> *
187 store volatile <vscale x 6 x double> %x3, <vscale x 6 x double>* %ptr2.bc
191 ; Use AAVPCS, SVE register in z0-z7 used
193 define void @aavpcs1(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32 %s6, <vscale x 4 x i32> %s7, <vscale x 4 x i32> %s8, <vscale x 4 x i32> %s9, <vscale x 4 x i32> %s10, <vscale x 4 x i32> %s11, <vscale x 4 x i32> %s12, <vscale x 4 x i32> %s13, <vscale x 4 x i32> %s14, <vscale x 4 x i32> %s15, <vscale x 4 x i32> %s16, i32 * %ptr) nounwind {
194 ; CHECK-LABEL: aavpcs1:
195 ; CHECK: // %bb.0: // %entry
196 ; CHECK-NEXT: ldp x8, x9, [sp]
197 ; CHECK-NEXT: ptrue p0.s
198 ; CHECK-NEXT: ld1w { z3.s }, p0/z, [x8]
199 ; CHECK-NEXT: ld1w { z24.s }, p0/z, [x7]
200 ; CHECK-NEXT: st1w { z0.s }, p0, [x9]
201 ; CHECK-NEXT: st1w { z1.s }, p0, [x9]
202 ; CHECK-NEXT: st1w { z2.s }, p0, [x9]
203 ; CHECK-NEXT: st1w { z4.s }, p0, [x9]
204 ; CHECK-NEXT: st1w { z5.s }, p0, [x9]
205 ; CHECK-NEXT: st1w { z6.s }, p0, [x9]
206 ; CHECK-NEXT: st1w { z7.s }, p0, [x9]
207 ; CHECK-NEXT: st1w { z24.s }, p0, [x9]
208 ; CHECK-NEXT: st1w { z3.s }, p0, [x9]
211 %ptr1.bc = bitcast i32 * %ptr to <vscale x 4 x i32> *
212 store volatile <vscale x 4 x i32> %s7, <vscale x 4 x i32>* %ptr1.bc
213 store volatile <vscale x 4 x i32> %s8, <vscale x 4 x i32>* %ptr1.bc
214 store volatile <vscale x 4 x i32> %s9, <vscale x 4 x i32>* %ptr1.bc
215 store volatile <vscale x 4 x i32> %s11, <vscale x 4 x i32>* %ptr1.bc
216 store volatile <vscale x 4 x i32> %s12, <vscale x 4 x i32>* %ptr1.bc
217 store volatile <vscale x 4 x i32> %s13, <vscale x 4 x i32>* %ptr1.bc
218 store volatile <vscale x 4 x i32> %s14, <vscale x 4 x i32>* %ptr1.bc
219 store volatile <vscale x 4 x i32> %s15, <vscale x 4 x i32>* %ptr1.bc
220 store volatile <vscale x 4 x i32> %s16, <vscale x 4 x i32>* %ptr1.bc
224 ; Use AAVPCS, SVE register in z0-z7 used
226 define void @aavpcs2(float %s0, float %s1, float %s2, float %s3, float %s4, float %s5, float %s6, <vscale x 4 x float> %s7, <vscale x 4 x float> %s8, <vscale x 4 x float> %s9, <vscale x 4 x float> %s10, <vscale x 4 x float> %s11, <vscale x 4 x float> %s12,<vscale x 4 x float> %s13,<vscale x 4 x float> %s14,<vscale x 4 x float> %s15,<vscale x 4 x float> %s16,float * %ptr) nounwind {
227 ; CHECK-LABEL: aavpcs2:
228 ; CHECK: // %bb.0: // %entry
229 ; CHECK-NEXT: ldp x8, x9, [sp]
230 ; CHECK-NEXT: ptrue p0.s
231 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
232 ; CHECK-NEXT: ld1w { z1.s }, p0/z, [x7]
233 ; CHECK-NEXT: ld1w { z2.s }, p0/z, [x6]
234 ; CHECK-NEXT: ld1w { z3.s }, p0/z, [x5]
235 ; CHECK-NEXT: ld1w { z4.s }, p0/z, [x4]
236 ; CHECK-NEXT: ld1w { z5.s }, p0/z, [x3]
237 ; CHECK-NEXT: ld1w { z6.s }, p0/z, [x1]
238 ; CHECK-NEXT: ld1w { z24.s }, p0/z, [x0]
239 ; CHECK-NEXT: st1w { z7.s }, p0, [x9]
240 ; CHECK-NEXT: st1w { z24.s }, p0, [x9]
241 ; CHECK-NEXT: st1w { z6.s }, p0, [x9]
242 ; CHECK-NEXT: st1w { z5.s }, p0, [x9]
243 ; CHECK-NEXT: st1w { z4.s }, p0, [x9]
244 ; CHECK-NEXT: st1w { z3.s }, p0, [x9]
245 ; CHECK-NEXT: st1w { z2.s }, p0, [x9]
246 ; CHECK-NEXT: st1w { z1.s }, p0, [x9]
247 ; CHECK-NEXT: st1w { z0.s }, p0, [x9]
250 %ptr1.bc = bitcast float * %ptr to <vscale x 4 x float> *
251 store volatile <vscale x 4 x float> %s7, <vscale x 4 x float>* %ptr1.bc
252 store volatile <vscale x 4 x float> %s8, <vscale x 4 x float>* %ptr1.bc
253 store volatile <vscale x 4 x float> %s9, <vscale x 4 x float>* %ptr1.bc
254 store volatile <vscale x 4 x float> %s11, <vscale x 4 x float>* %ptr1.bc
255 store volatile <vscale x 4 x float> %s12, <vscale x 4 x float>* %ptr1.bc
256 store volatile <vscale x 4 x float> %s13, <vscale x 4 x float>* %ptr1.bc
257 store volatile <vscale x 4 x float> %s14, <vscale x 4 x float>* %ptr1.bc
258 store volatile <vscale x 4 x float> %s15, <vscale x 4 x float>* %ptr1.bc
259 store volatile <vscale x 4 x float> %s16, <vscale x 4 x float>* %ptr1.bc
263 ; Use AAVPCS, no SVE register in z0-z7 used (floats occupy z0-z7) but predicate arg is used
265 define void @aavpcs3(float %s0, float %s1, float %s2, float %s3, float %s4, float %s5, float %s6, float %s7, <vscale x 4 x float> %s8, <vscale x 4 x float> %s9, <vscale x 4 x float> %s10, <vscale x 4 x float> %s11, <vscale x 4 x float> %s12, <vscale x 4 x float> %s13, <vscale x 4 x float> %s14, <vscale x 4 x float> %s15, <vscale x 4 x float> %s16, <vscale x 4 x float> %s17, <vscale x 16 x i1> %p0, float * %ptr) nounwind {
266 ; CHECK-LABEL: aavpcs3:
267 ; CHECK: // %bb.0: // %entry
268 ; CHECK-NEXT: ldr x8, [sp]
269 ; CHECK-NEXT: ptrue p0.s
270 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
271 ; CHECK-NEXT: ld1w { z1.s }, p0/z, [x7]
272 ; CHECK-NEXT: ld1w { z2.s }, p0/z, [x6]
273 ; CHECK-NEXT: ld1w { z3.s }, p0/z, [x5]
274 ; CHECK-NEXT: ld1w { z4.s }, p0/z, [x4]
275 ; CHECK-NEXT: ld1w { z5.s }, p0/z, [x3]
276 ; CHECK-NEXT: ld1w { z6.s }, p0/z, [x2]
277 ; CHECK-NEXT: ld1w { z7.s }, p0/z, [x1]
278 ; CHECK-NEXT: ld1w { z24.s }, p0/z, [x0]
279 ; CHECK-NEXT: ldr x8, [sp, #16]
280 ; CHECK-NEXT: st1w { z24.s }, p0, [x8]
281 ; CHECK-NEXT: st1w { z7.s }, p0, [x8]
282 ; CHECK-NEXT: st1w { z6.s }, p0, [x8]
283 ; CHECK-NEXT: st1w { z5.s }, p0, [x8]
284 ; CHECK-NEXT: st1w { z4.s }, p0, [x8]
285 ; CHECK-NEXT: st1w { z3.s }, p0, [x8]
286 ; CHECK-NEXT: st1w { z2.s }, p0, [x8]
287 ; CHECK-NEXT: st1w { z1.s }, p0, [x8]
288 ; CHECK-NEXT: st1w { z0.s }, p0, [x8]
291 %ptr1.bc = bitcast float * %ptr to <vscale x 4 x float> *
292 store volatile <vscale x 4 x float> %s8, <vscale x 4 x float>* %ptr1.bc
293 store volatile <vscale x 4 x float> %s9, <vscale x 4 x float>* %ptr1.bc
294 store volatile <vscale x 4 x float> %s10, <vscale x 4 x float>* %ptr1.bc
295 store volatile <vscale x 4 x float> %s11, <vscale x 4 x float>* %ptr1.bc
296 store volatile <vscale x 4 x float> %s12, <vscale x 4 x float>* %ptr1.bc
297 store volatile <vscale x 4 x float> %s13, <vscale x 4 x float>* %ptr1.bc
298 store volatile <vscale x 4 x float> %s14, <vscale x 4 x float>* %ptr1.bc
299 store volatile <vscale x 4 x float> %s15, <vscale x 4 x float>* %ptr1.bc
300 store volatile <vscale x 4 x float> %s16, <vscale x 4 x float>* %ptr1.bc
304 ; use AAVPCS, SVE register in z0-z7 used (i32s dont occupy z0-z7)
306 define void @aavpcs4(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32 %s6, i32 %s7, <vscale x 4 x i32> %s8, <vscale x 4 x i32> %s9, <vscale x 4 x i32> %s10, <vscale x 4 x i32> %s11, <vscale x 4 x i32> %s12, <vscale x 4 x i32> %s13, <vscale x 4 x i32> %s14, <vscale x 4 x i32> %s15, <vscale x 4 x i32> %s16, <vscale x 4 x i32> %s17, i32 * %ptr) nounwind {
307 ; CHECK-LABEL: aavpcs4:
308 ; CHECK: // %bb.0: // %entry
309 ; CHECK-NEXT: ldr x8, [sp]
310 ; CHECK-NEXT: ptrue p0.s
311 ; CHECK-NEXT: ldr x9, [sp, #16]
312 ; CHECK-NEXT: ld1w { z24.s }, p0/z, [x8]
313 ; CHECK-NEXT: st1w { z0.s }, p0, [x9]
314 ; CHECK-NEXT: st1w { z1.s }, p0, [x9]
315 ; CHECK-NEXT: st1w { z2.s }, p0, [x9]
316 ; CHECK-NEXT: st1w { z3.s }, p0, [x9]
317 ; CHECK-NEXT: st1w { z4.s }, p0, [x9]
318 ; CHECK-NEXT: st1w { z5.s }, p0, [x9]
319 ; CHECK-NEXT: st1w { z6.s }, p0, [x9]
320 ; CHECK-NEXT: st1w { z7.s }, p0, [x9]
321 ; CHECK-NEXT: st1w { z24.s }, p0, [x9]
324 %ptr1.bc = bitcast i32 * %ptr to <vscale x 4 x i32> *
325 store volatile <vscale x 4 x i32> %s8, <vscale x 4 x i32>* %ptr1.bc
326 store volatile <vscale x 4 x i32> %s9, <vscale x 4 x i32>* %ptr1.bc
327 store volatile <vscale x 4 x i32> %s10, <vscale x 4 x i32>* %ptr1.bc
328 store volatile <vscale x 4 x i32> %s11, <vscale x 4 x i32>* %ptr1.bc
329 store volatile <vscale x 4 x i32> %s12, <vscale x 4 x i32>* %ptr1.bc
330 store volatile <vscale x 4 x i32> %s13, <vscale x 4 x i32>* %ptr1.bc
331 store volatile <vscale x 4 x i32> %s14, <vscale x 4 x i32>* %ptr1.bc
332 store volatile <vscale x 4 x i32> %s15, <vscale x 4 x i32>* %ptr1.bc
333 store volatile <vscale x 4 x i32> %s16, <vscale x 4 x i32>* %ptr1.bc
337 ; Use AAVPCS, SVE register used in return
339 define <vscale x 4 x float> @aavpcs5(float %s0, float %s1, float %s2, float %s3, float %s4, float %s5, float %s6, float %s7, <vscale x 4 x float> %s8, <vscale x 4 x float> %s9, <vscale x 4 x float> %s10, <vscale x 4 x float> %s11, <vscale x 4 x float> %s12, <vscale x 4 x float> %s13, <vscale x 4 x float> %s14, <vscale x 4 x float> %s15, <vscale x 4 x float> %s16, <vscale x 4 x float> %s17, float * %ptr) nounwind {
340 ; CHECK-LABEL: aavpcs5:
341 ; CHECK: // %bb.0: // %entry
342 ; CHECK-NEXT: ldr x8, [sp]
343 ; CHECK-NEXT: ptrue p0.s
344 ; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8]
345 ; CHECK-NEXT: ld1w { z2.s }, p0/z, [x7]
346 ; CHECK-NEXT: ld1w { z3.s }, p0/z, [x6]
347 ; CHECK-NEXT: ld1w { z4.s }, p0/z, [x5]
348 ; CHECK-NEXT: ld1w { z5.s }, p0/z, [x4]
349 ; CHECK-NEXT: ld1w { z6.s }, p0/z, [x3]
350 ; CHECK-NEXT: ld1w { z7.s }, p0/z, [x2]
351 ; CHECK-NEXT: ld1w { z24.s }, p0/z, [x1]
352 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
353 ; CHECK-NEXT: ldr x8, [sp, #16]
354 ; CHECK-NEXT: st1w { z0.s }, p0, [x8]
355 ; CHECK-NEXT: st1w { z24.s }, p0, [x8]
356 ; CHECK-NEXT: st1w { z7.s }, p0, [x8]
357 ; CHECK-NEXT: st1w { z6.s }, p0, [x8]
358 ; CHECK-NEXT: st1w { z5.s }, p0, [x8]
359 ; CHECK-NEXT: st1w { z4.s }, p0, [x8]
360 ; CHECK-NEXT: st1w { z3.s }, p0, [x8]
361 ; CHECK-NEXT: st1w { z2.s }, p0, [x8]
362 ; CHECK-NEXT: st1w { z1.s }, p0, [x8]
365 %ptr1.bc = bitcast float * %ptr to <vscale x 4 x float> *
366 store volatile <vscale x 4 x float> %s8, <vscale x 4 x float>* %ptr1.bc
367 store volatile <vscale x 4 x float> %s9, <vscale x 4 x float>* %ptr1.bc
368 store volatile <vscale x 4 x float> %s10, <vscale x 4 x float>* %ptr1.bc
369 store volatile <vscale x 4 x float> %s11, <vscale x 4 x float>* %ptr1.bc
370 store volatile <vscale x 4 x float> %s12, <vscale x 4 x float>* %ptr1.bc
371 store volatile <vscale x 4 x float> %s13, <vscale x 4 x float>* %ptr1.bc
372 store volatile <vscale x 4 x float> %s14, <vscale x 4 x float>* %ptr1.bc
373 store volatile <vscale x 4 x float> %s15, <vscale x 4 x float>* %ptr1.bc
374 store volatile <vscale x 4 x float> %s16, <vscale x 4 x float>* %ptr1.bc
375 ret <vscale x 4 x float> %s8
378 define void @aapcs1(float %s0, float %s1, float %s2, float %s3, float %s4, float %s5, float %s6, float %s7, <vscale x 4 x float> %s8, <vscale x 4 x float> %s9, <vscale x 4 x float> %s10, <vscale x 4 x float> %s11, <vscale x 4 x float> %s12, <vscale x 4 x float> %s13, <vscale x 4 x float> %s14, <vscale x 4 x float> %s15, <vscale x 4 x float> %s16, <vscale x 4 x float> %s17, float * %ptr) nounwind {
379 ; CHECK-LABEL: aapcs1:
380 ; CHECK: // %bb.0: // %entry
381 ; CHECK-NEXT: ldr x8, [sp]
382 ; CHECK-NEXT: ptrue p0.s
383 ; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
384 ; CHECK-NEXT: ld1w { z1.s }, p0/z, [x7]
385 ; CHECK-NEXT: ld1w { z2.s }, p0/z, [x6]
386 ; CHECK-NEXT: ld1w { z3.s }, p0/z, [x5]
387 ; CHECK-NEXT: ld1w { z4.s }, p0/z, [x4]
388 ; CHECK-NEXT: ld1w { z5.s }, p0/z, [x3]
389 ; CHECK-NEXT: ld1w { z6.s }, p0/z, [x2]
390 ; CHECK-NEXT: ld1w { z7.s }, p0/z, [x1]
391 ; CHECK-NEXT: ld1w { z16.s }, p0/z, [x0]
392 ; CHECK-NEXT: ldr x8, [sp, #16]
393 ; CHECK-NEXT: st1w { z16.s }, p0, [x8]
394 ; CHECK-NEXT: st1w { z7.s }, p0, [x8]
395 ; CHECK-NEXT: st1w { z6.s }, p0, [x8]
396 ; CHECK-NEXT: st1w { z5.s }, p0, [x8]
397 ; CHECK-NEXT: st1w { z4.s }, p0, [x8]
398 ; CHECK-NEXT: st1w { z3.s }, p0, [x8]
399 ; CHECK-NEXT: st1w { z2.s }, p0, [x8]
400 ; CHECK-NEXT: st1w { z1.s }, p0, [x8]
401 ; CHECK-NEXT: st1w { z0.s }, p0, [x8]
404 %ptr1.bc = bitcast float * %ptr to <vscale x 4 x float> *
405 store volatile <vscale x 4 x float> %s8, <vscale x 4 x float>* %ptr1.bc
406 store volatile <vscale x 4 x float> %s9, <vscale x 4 x float>* %ptr1.bc
407 store volatile <vscale x 4 x float> %s10, <vscale x 4 x float>* %ptr1.bc
408 store volatile <vscale x 4 x float> %s11, <vscale x 4 x float>* %ptr1.bc
409 store volatile <vscale x 4 x float> %s12, <vscale x 4 x float>* %ptr1.bc
410 store volatile <vscale x 4 x float> %s13, <vscale x 4 x float>* %ptr1.bc
411 store volatile <vscale x 4 x float> %s14, <vscale x 4 x float>* %ptr1.bc
412 store volatile <vscale x 4 x float> %s15, <vscale x 4 x float>* %ptr1.bc
413 store volatile <vscale x 4 x float> %s16, <vscale x 4 x float>* %ptr1.bc
417 declare void @non_sve_callee_high_range(float %f0, float %f1, float %f2, float %f3, float %f4, float %f5, float %f6, float %f7, <vscale x 4 x float> %v0, <vscale x 4 x float> %v1)
419 define void @non_sve_caller_non_sve_callee_high_range() {
420 ; CHECK-LABEL: non_sve_caller_non_sve_callee_high_range:
422 ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
423 ; CHECK-NEXT: .cfi_def_cfa_offset 16
424 ; CHECK-NEXT: .cfi_offset w30, -8
425 ; CHECK-NEXT: .cfi_offset w29, -16
426 ; CHECK-NEXT: addvl sp, sp, #-2
427 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
428 ; CHECK-NEXT: movi d0, #0000000000000000
429 ; CHECK-NEXT: fmov s1, #1.00000000
430 ; CHECK-NEXT: fmov s2, #2.00000000
431 ; CHECK-NEXT: fmov s3, #3.00000000
432 ; CHECK-NEXT: fmov s4, #4.00000000
433 ; CHECK-NEXT: fmov s5, #5.00000000
434 ; CHECK-NEXT: fmov s6, #6.00000000
435 ; CHECK-NEXT: fmov s7, #7.00000000
436 ; CHECK-NEXT: mov x1, sp
437 ; CHECK-NEXT: addvl x0, sp, #1
438 ; CHECK-NEXT: bl non_sve_callee_high_range
439 ; CHECK-NEXT: addvl sp, sp, #2
440 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
442 call void @non_sve_callee_high_range(float 0.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, <vscale x 4 x float> undef, <vscale x 4 x float> undef)
446 define void @non_sve_caller_high_range_non_sve_callee_high_range(float %f0, float %f1, float %f2, float %f3, float %f4, float %f5, float %f6, float %f7, <vscale x 4 x float> %v0, <vscale x 4 x float> %v1) {
447 ; CHECK-LABEL: non_sve_caller_high_range_non_sve_callee_high_range:
449 ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
450 ; CHECK-NEXT: .cfi_def_cfa_offset 16
451 ; CHECK-NEXT: .cfi_offset w30, -8
452 ; CHECK-NEXT: .cfi_offset w29, -16
453 ; CHECK-NEXT: addvl sp, sp, #-2
454 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
455 ; CHECK-NEXT: ptrue p0.s
456 ; CHECK-NEXT: movi d0, #0000000000000000
457 ; CHECK-NEXT: ld1w { z16.s }, p0/z, [x0]
458 ; CHECK-NEXT: ld1w { z17.s }, p0/z, [x1]
459 ; CHECK-NEXT: fmov s1, #1.00000000
460 ; CHECK-NEXT: fmov s2, #2.00000000
461 ; CHECK-NEXT: fmov s3, #3.00000000
462 ; CHECK-NEXT: fmov s4, #4.00000000
463 ; CHECK-NEXT: fmov s5, #5.00000000
464 ; CHECK-NEXT: fmov s6, #6.00000000
465 ; CHECK-NEXT: fmov s7, #7.00000000
466 ; CHECK-NEXT: mov x1, sp
467 ; CHECK-NEXT: addvl x0, sp, #1
468 ; CHECK-NEXT: st1w { z17.s }, p0, [sp]
469 ; CHECK-NEXT: st1w { z16.s }, p0, [sp, #1, mul vl]
470 ; CHECK-NEXT: bl non_sve_callee_high_range
471 ; CHECK-NEXT: addvl sp, sp, #2
472 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
474 call void @non_sve_callee_high_range(float 0.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, <vscale x 4 x float> %v0, <vscale x 4 x float> %v1)
478 define <vscale x 4 x float> @sve_caller_non_sve_callee_high_range(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1) {
479 ; CHECK-LABEL: sve_caller_non_sve_callee_high_range:
481 ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
482 ; CHECK-NEXT: .cfi_def_cfa_offset 16
483 ; CHECK-NEXT: .cfi_offset w30, -8
484 ; CHECK-NEXT: .cfi_offset w29, -16
485 ; CHECK-NEXT: addvl sp, sp, #-18
486 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x90, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 144 * VG
487 ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
488 ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
489 ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
490 ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
491 ; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Folded Spill
492 ; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Folded Spill
493 ; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Folded Spill
494 ; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Folded Spill
495 ; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Folded Spill
496 ; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Folded Spill
497 ; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Folded Spill
498 ; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Folded Spill
499 ; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
500 ; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
501 ; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
502 ; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
503 ; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
504 ; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
505 ; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
506 ; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
507 ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
508 ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
509 ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
510 ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
511 ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
512 ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
513 ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
514 ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
515 ; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG
516 ; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG
517 ; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x68, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d10 @ cfa - 16 - 24 * VG
518 ; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x60, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d11 @ cfa - 16 - 32 * VG
519 ; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x58, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d12 @ cfa - 16 - 40 * VG
520 ; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x50, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d13 @ cfa - 16 - 48 * VG
521 ; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x48, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d14 @ cfa - 16 - 56 * VG
522 ; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x40, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d15 @ cfa - 16 - 64 * VG
523 ; CHECK-NEXT: addvl sp, sp, #-3
524 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xa8, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 168 * VG
525 ; CHECK-NEXT: mov z25.d, z0.d
526 ; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
527 ; CHECK-NEXT: movi d0, #0000000000000000
528 ; CHECK-NEXT: mov z24.d, z1.d
529 ; CHECK-NEXT: fmov s1, #1.00000000
530 ; CHECK-NEXT: fmov s2, #2.00000000
531 ; CHECK-NEXT: fmov s3, #3.00000000
532 ; CHECK-NEXT: fmov s4, #4.00000000
533 ; CHECK-NEXT: fmov s5, #5.00000000
534 ; CHECK-NEXT: fmov s6, #6.00000000
535 ; CHECK-NEXT: fmov s7, #7.00000000
536 ; CHECK-NEXT: addvl x0, sp, #2
537 ; CHECK-NEXT: addvl x1, sp, #1
538 ; CHECK-NEXT: ptrue p0.s
539 ; CHECK-NEXT: st1w { z24.s }, p0, [sp, #1, mul vl]
540 ; CHECK-NEXT: st1w { z25.s }, p0, [sp, #2, mul vl]
541 ; CHECK-NEXT: bl non_sve_callee_high_range
542 ; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
543 ; CHECK-NEXT: addvl sp, sp, #3
544 ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
545 ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
546 ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
547 ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
548 ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
549 ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
550 ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
551 ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
552 ; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Folded Reload
553 ; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Folded Reload
554 ; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Folded Reload
555 ; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Folded Reload
556 ; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
557 ; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
558 ; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
559 ; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
560 ; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
561 ; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
562 ; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
563 ; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
564 ; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
565 ; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
566 ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
567 ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
568 ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
569 ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
570 ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
571 ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
572 ; CHECK-NEXT: addvl sp, sp, #18
573 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
575 call void @non_sve_callee_high_range(float 0.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, <vscale x 4 x float> %v0, <vscale x 4 x float> %v1)
576 ret <vscale x 4 x float> %v0
579 define <vscale x 4 x float> @sve_ret_caller_non_sve_callee_high_range() {
580 ; CHECK-LABEL: sve_ret_caller_non_sve_callee_high_range:
582 ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
583 ; CHECK-NEXT: .cfi_def_cfa_offset 16
584 ; CHECK-NEXT: .cfi_offset w30, -8
585 ; CHECK-NEXT: .cfi_offset w29, -16
586 ; CHECK-NEXT: addvl sp, sp, #-18
587 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x90, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 144 * VG
588 ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
589 ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
590 ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
591 ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
592 ; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Folded Spill
593 ; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Folded Spill
594 ; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Folded Spill
595 ; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Folded Spill
596 ; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Folded Spill
597 ; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Folded Spill
598 ; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Folded Spill
599 ; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Folded Spill
600 ; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
601 ; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
602 ; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
603 ; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
604 ; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
605 ; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
606 ; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
607 ; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
608 ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
609 ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
610 ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
611 ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
612 ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
613 ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
614 ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
615 ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
616 ; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG
617 ; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG
618 ; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x68, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d10 @ cfa - 16 - 24 * VG
619 ; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x60, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d11 @ cfa - 16 - 32 * VG
620 ; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x58, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d12 @ cfa - 16 - 40 * VG
621 ; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x50, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d13 @ cfa - 16 - 48 * VG
622 ; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x48, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d14 @ cfa - 16 - 56 * VG
623 ; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x40, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d15 @ cfa - 16 - 64 * VG
624 ; CHECK-NEXT: addvl sp, sp, #-2
625 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xa0, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 160 * VG
626 ; CHECK-NEXT: movi d0, #0000000000000000
627 ; CHECK-NEXT: fmov s1, #1.00000000
628 ; CHECK-NEXT: fmov s2, #2.00000000
629 ; CHECK-NEXT: fmov s3, #3.00000000
630 ; CHECK-NEXT: fmov s4, #4.00000000
631 ; CHECK-NEXT: fmov s5, #5.00000000
632 ; CHECK-NEXT: fmov s6, #6.00000000
633 ; CHECK-NEXT: fmov s7, #7.00000000
634 ; CHECK-NEXT: mov x1, sp
635 ; CHECK-NEXT: addvl x0, sp, #1
636 ; CHECK-NEXT: bl non_sve_callee_high_range
637 ; CHECK-NEXT: addvl sp, sp, #2
638 ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
639 ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
640 ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
641 ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
642 ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
643 ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
644 ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
645 ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
646 ; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Folded Reload
647 ; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Folded Reload
648 ; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Folded Reload
649 ; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Folded Reload
650 ; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
651 ; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
652 ; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
653 ; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
654 ; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
655 ; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
656 ; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
657 ; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
658 ; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
659 ; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
660 ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
661 ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
662 ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
663 ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
664 ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
665 ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
666 ; CHECK-NEXT: addvl sp, sp, #18
667 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
669 call void @non_sve_callee_high_range(float 0.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, <vscale x 4 x float> undef, <vscale x 4 x float> undef)
670 ret <vscale x 4 x float> undef
673 declare float @callee1(float, <vscale x 8 x double>, <vscale x 8 x double>, <vscale x 2 x double>)
674 declare float @callee2(i32, i32, i32, i32, i32, i32, i32, i32, float, <vscale x 8 x double>, <vscale x 8 x double>)
675 declare float @callee3(float, float, <vscale x 8 x double>, <vscale x 6 x double>, <vscale x 2 x double>)
677 declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)
678 declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)
679 declare <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1>, double*)
680 declare <vscale x 6 x double> @llvm.aarch64.sve.ld3.nxv6f64.nxv2i1(<vscale x 2 x i1>, double*)
681 declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1>, double*)
682 declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)
683 declare <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv8f64(<vscale x 8 x double>, i32 immarg)
684 declare <vscale x 2 x double> @llvm.aarch64.sve.tuple.get.nxv2f64.nxv6f64(<vscale x 6 x double>, i32 immarg)