1 //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements the SelectionDAG::Legalize method.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/FloatingPointMode.h"
17 #include "llvm/ADT/SetVector.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/Analysis/TargetLibraryInfo.h"
22 #include "llvm/CodeGen/ISDOpcodes.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/RuntimeLibcalls.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGNodes.h"
29 #include "llvm/CodeGen/TargetFrameLowering.h"
30 #include "llvm/CodeGen/TargetLowering.h"
31 #include "llvm/CodeGen/TargetSubtargetInfo.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DataLayout.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/Metadata.h"
39 #include "llvm/IR/Type.h"
40 #include "llvm/Support/Casting.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MachineValueType.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/raw_ostream.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetOptions.h"
56 #define DEBUG_TYPE "legalizedag"
60 /// Keeps track of state when getting the sign of a floating-point value as an
62 struct FloatSignAsInt {
67 MachinePointerInfo IntPointerInfo;
68 MachinePointerInfo FloatPointerInfo;
74 //===----------------------------------------------------------------------===//
75 /// This takes an arbitrary SelectionDAG as input and
76 /// hacks on it until the target machine can handle it. This involves
77 /// eliminating value sizes the machine cannot handle (promoting small sizes to
78 /// large sizes or splitting up large values into small values) as well as
79 /// eliminating operations the machine cannot handle.
81 /// This code also does a small amount of optimization and recognition of idioms
82 /// as part of its processing. For example, if a target does not support a
83 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
84 /// will attempt merge setcc and brc instructions into brcc's.
85 class SelectionDAGLegalize {
86 const TargetMachine &TM;
87 const TargetLowering &TLI;
90 /// The set of nodes which have already been legalized. We hold a
91 /// reference to it in order to update as necessary on node deletion.
92 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
94 /// A set of all the nodes updated during legalization.
95 SmallSetVector<SDNode *, 16> *UpdatedNodes;
97 EVT getSetCCResultType(EVT VT) const {
98 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
101 // Libcall insertion helpers.
104 SelectionDAGLegalize(SelectionDAG &DAG,
105 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
106 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
107 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
108 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
110 /// Legalizes the given operation.
111 void LegalizeOp(SDNode *Node);
114 SDValue OptimizeFloatStore(StoreSDNode *ST);
116 void LegalizeLoadOps(SDNode *Node);
117 void LegalizeStoreOps(SDNode *Node);
119 /// Some targets cannot handle a variable
120 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
121 /// is necessary to spill the vector being inserted into to memory, perform
122 /// the insert there, and then read the result back.
123 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
125 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx,
128 /// Return a vector shuffle operation which
129 /// performs the same shuffe in terms of order or result bytes, but on a type
130 /// whose vector element type is narrower than the original shuffle type.
131 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
132 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
133 SDValue N1, SDValue N2,
134 ArrayRef<int> Mask) const;
136 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
138 void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall LC,
139 SmallVectorImpl<SDValue> &Results);
140 void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
141 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
142 RTLIB::Libcall Call_F128,
143 RTLIB::Libcall Call_PPCF128,
144 SmallVectorImpl<SDValue> &Results);
145 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I8,
146 RTLIB::Libcall Call_I16, RTLIB::Libcall Call_I32,
147 RTLIB::Libcall Call_I64, RTLIB::Libcall Call_I128,
148 RTLIB::Libcall Call_IEXT);
149 void ExpandArgFPLibCall(SDNode *Node,
150 RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
151 RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
152 RTLIB::Libcall Call_PPCF128,
153 SmallVectorImpl<SDValue> &Results);
154 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
155 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
157 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
160 const SDLoc &dl, SDValue ChainIn);
161 SDValue ExpandBUILD_VECTOR(SDNode *Node);
162 SDValue ExpandSPLAT_VECTOR(SDNode *Node);
163 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
164 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
165 SmallVectorImpl<SDValue> &Results);
166 void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
167 SDValue Value) const;
168 SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
169 SDValue NewIntValue) const;
170 SDValue ExpandFCOPYSIGN(SDNode *Node) const;
171 SDValue ExpandFABS(SDNode *Node) const;
172 SDValue ExpandFNEG(SDNode *Node) const;
173 SDValue ExpandLegalINT_TO_FP(SDNode *Node, SDValue &Chain);
174 void PromoteLegalINT_TO_FP(SDNode *N, const SDLoc &dl,
175 SmallVectorImpl<SDValue> &Results);
176 void PromoteLegalFP_TO_INT(SDNode *N, const SDLoc &dl,
177 SmallVectorImpl<SDValue> &Results);
178 SDValue PromoteLegalFP_TO_INT_SAT(SDNode *Node, const SDLoc &dl);
180 SDValue ExpandPARITY(SDValue Op, const SDLoc &dl);
182 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
183 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
184 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
186 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
187 SDValue ExpandConstant(ConstantSDNode *CP);
189 // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
190 bool ExpandNode(SDNode *Node);
191 void ConvertNodeToLibcall(SDNode *Node);
192 void PromoteNode(SDNode *Node);
195 // Node replacement helpers
197 void ReplacedNode(SDNode *N) {
198 LegalizedNodes.erase(N);
200 UpdatedNodes->insert(N);
203 void ReplaceNode(SDNode *Old, SDNode *New) {
204 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
205 dbgs() << " with: "; New->dump(&DAG));
207 assert(Old->getNumValues() == New->getNumValues() &&
208 "Replacing one node with another that produces a different number "
210 DAG.ReplaceAllUsesWith(Old, New);
212 UpdatedNodes->insert(New);
216 void ReplaceNode(SDValue Old, SDValue New) {
217 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
218 dbgs() << " with: "; New->dump(&DAG));
220 DAG.ReplaceAllUsesWith(Old, New);
222 UpdatedNodes->insert(New.getNode());
223 ReplacedNode(Old.getNode());
226 void ReplaceNode(SDNode *Old, const SDValue *New) {
227 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
229 DAG.ReplaceAllUsesWith(Old, New);
230 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
231 LLVM_DEBUG(dbgs() << (i == 0 ? " with: " : " and: ");
234 UpdatedNodes->insert(New[i].getNode());
239 void ReplaceNodeWithValue(SDValue Old, SDValue New) {
240 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
241 dbgs() << " with: "; New->dump(&DAG));
243 DAG.ReplaceAllUsesOfValueWith(Old, New);
245 UpdatedNodes->insert(New.getNode());
246 ReplacedNode(Old.getNode());
250 } // end anonymous namespace
252 /// Return a vector shuffle operation which
253 /// performs the same shuffle in terms of order or result bytes, but on a type
254 /// whose vector element type is narrower than the original shuffle type.
255 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
256 SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
257 EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
258 ArrayRef<int> Mask) const {
259 unsigned NumMaskElts = VT.getVectorNumElements();
260 unsigned NumDestElts = NVT.getVectorNumElements();
261 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
263 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
265 if (NumEltsGrowth == 1)
266 return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
268 SmallVector<int, 8> NewMask;
269 for (unsigned i = 0; i != NumMaskElts; ++i) {
271 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
273 NewMask.push_back(-1);
275 NewMask.push_back(Idx * NumEltsGrowth + j);
278 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
279 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
280 return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask);
283 /// Expands the ConstantFP node to an integer constant or
284 /// a load from the constant pool.
286 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
290 // If a FP immediate is precise when represented as a float and if the
291 // target can do an extending load from float to double, we put it into
292 // the constant pool as a float, even if it's is statically typed as a
293 // double. This shrinks FP constants and canonicalizes them for targets where
294 // an FP extending load is the same cost as a normal load (such as on the x87
295 // fp stack or PPC FP unit).
296 EVT VT = CFP->getValueType(0);
297 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
299 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
300 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
301 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
304 APFloat APF = CFP->getValueAPF();
308 // We don't want to shrink SNaNs. Converting the SNaN back to its real type
309 // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
310 if (!APF.isSignaling()) {
311 while (SVT != MVT::f32 && SVT != MVT::f16) {
312 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
313 if (ConstantFPSDNode::isValueValidForType(SVT, APF) &&
314 // Only do this if the target has a native EXTLOAD instruction from
316 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
317 TLI.ShouldShrinkFPConstant(OrigVT)) {
318 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
319 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
327 DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
328 Align Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlign();
330 SDValue Result = DAG.getExtLoad(
331 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
332 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
336 SDValue Result = DAG.getLoad(
337 OrigVT, dl, DAG.getEntryNode(), CPIdx,
338 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
342 /// Expands the Constant node to a load from the constant pool.
343 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
345 EVT VT = CP->getValueType(0);
346 SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
347 TLI.getPointerTy(DAG.getDataLayout()));
348 Align Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlign();
349 SDValue Result = DAG.getLoad(
350 VT, dl, DAG.getEntryNode(), CPIdx,
351 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
355 /// Some target cannot handle a variable insertion index for the
356 /// INSERT_VECTOR_ELT instruction. In this case, it
357 /// is necessary to spill the vector being inserted into to memory, perform
358 /// the insert there, and then read the result back.
359 SDValue SelectionDAGLegalize::PerformInsertVectorEltInMemory(SDValue Vec,
367 // If the target doesn't support this, we have to spill the input vector
368 // to a temporary stack slot, update the element, then reload it. This is
369 // badness. We could also load the value into a vector register (either
370 // with a "move to register" or "extload into register" instruction, then
371 // permute it into place, if the idx is a constant and if the idx is
372 // supported by the target.
373 EVT VT = Tmp1.getValueType();
374 EVT EltVT = VT.getVectorElementType();
375 SDValue StackPtr = DAG.CreateStackTemporary(VT);
377 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
380 SDValue Ch = DAG.getStore(
381 DAG.getEntryNode(), dl, Tmp1, StackPtr,
382 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
384 SDValue StackPtr2 = TLI.getVectorElementPointer(DAG, StackPtr, VT, Tmp3);
386 // Store the scalar value.
387 Ch = DAG.getTruncStore(
388 Ch, dl, Tmp2, StackPtr2,
389 MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), EltVT);
390 // Load the updated vector.
391 return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
392 DAG.getMachineFunction(), SPFI));
395 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
398 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
399 // SCALAR_TO_VECTOR requires that the type of the value being inserted
400 // match the element type of the vector being created, except for
401 // integers in which case the inserted value can be over width.
402 EVT EltVT = Vec.getValueType().getVectorElementType();
403 if (Val.getValueType() == EltVT ||
404 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
405 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
406 Vec.getValueType(), Val);
408 unsigned NumElts = Vec.getValueType().getVectorNumElements();
409 // We generate a shuffle of InVec and ScVec, so the shuffle mask
410 // should be 0,1,2,3,4,5... with the appropriate element replaced with
412 SmallVector<int, 8> ShufOps;
413 for (unsigned i = 0; i != NumElts; ++i)
414 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
416 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, ShufOps);
419 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
422 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
423 if (!ISD::isNormalStore(ST))
426 LLVM_DEBUG(dbgs() << "Optimizing float store operations\n");
427 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
428 // FIXME: move this to the DAG Combiner! Note that we can't regress due
429 // to phase ordering between legalized code and the dag combiner. This
430 // probably means that we need to integrate dag combiner and legalizer
432 // We generally can't do this one for long doubles.
433 SDValue Chain = ST->getChain();
434 SDValue Ptr = ST->getBasePtr();
435 SDValue Value = ST->getValue();
436 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
437 AAMDNodes AAInfo = ST->getAAInfo();
440 // Don't optimise TargetConstantFP
441 if (Value.getOpcode() == ISD::TargetConstantFP)
444 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
445 if (CFP->getValueType(0) == MVT::f32 &&
446 TLI.isTypeLegal(MVT::i32)) {
447 SDValue Con = DAG.getConstant(CFP->getValueAPF().
448 bitcastToAPInt().zextOrTrunc(32),
449 SDLoc(CFP), MVT::i32);
450 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
451 ST->getOriginalAlign(), MMOFlags, AAInfo);
454 if (CFP->getValueType(0) == MVT::f64) {
455 // If this target supports 64-bit registers, do a single 64-bit store.
456 if (TLI.isTypeLegal(MVT::i64)) {
457 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
458 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
459 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
460 ST->getOriginalAlign(), MMOFlags, AAInfo);
463 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
464 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
465 // stores. If the target supports neither 32- nor 64-bits, this
466 // xform is certainly not worth it.
467 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
468 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
469 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
470 if (DAG.getDataLayout().isBigEndian())
473 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(),
474 ST->getOriginalAlign(), MMOFlags, AAInfo);
475 Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(4), dl);
476 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
477 ST->getPointerInfo().getWithOffset(4),
478 ST->getOriginalAlign(), MMOFlags, AAInfo);
480 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
487 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
488 StoreSDNode *ST = cast<StoreSDNode>(Node);
489 SDValue Chain = ST->getChain();
490 SDValue Ptr = ST->getBasePtr();
493 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
494 AAMDNodes AAInfo = ST->getAAInfo();
496 if (!ST->isTruncatingStore()) {
497 LLVM_DEBUG(dbgs() << "Legalizing store operation\n");
498 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
499 ReplaceNode(ST, OptStore);
503 SDValue Value = ST->getValue();
504 MVT VT = Value.getSimpleValueType();
505 switch (TLI.getOperationAction(ISD::STORE, VT)) {
506 default: llvm_unreachable("This action is not supported yet!");
507 case TargetLowering::Legal: {
508 // If this is an unaligned store and the target doesn't support it,
510 EVT MemVT = ST->getMemoryVT();
511 const DataLayout &DL = DAG.getDataLayout();
512 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT,
513 *ST->getMemOperand())) {
514 LLVM_DEBUG(dbgs() << "Expanding unsupported unaligned store\n");
515 SDValue Result = TLI.expandUnalignedStore(ST, DAG);
516 ReplaceNode(SDValue(ST, 0), Result);
518 LLVM_DEBUG(dbgs() << "Legal store\n");
521 case TargetLowering::Custom: {
522 LLVM_DEBUG(dbgs() << "Trying custom lowering\n");
523 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
524 if (Res && Res != SDValue(Node, 0))
525 ReplaceNode(SDValue(Node, 0), Res);
528 case TargetLowering::Promote: {
529 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
530 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
531 "Can only promote stores to same size type");
532 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
533 SDValue Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
534 ST->getOriginalAlign(), MMOFlags, AAInfo);
535 ReplaceNode(SDValue(Node, 0), Result);
542 LLVM_DEBUG(dbgs() << "Legalizing truncating store operations\n");
543 SDValue Value = ST->getValue();
544 EVT StVT = ST->getMemoryVT();
545 TypeSize StWidth = StVT.getSizeInBits();
546 TypeSize StSize = StVT.getStoreSizeInBits();
547 auto &DL = DAG.getDataLayout();
549 if (StWidth != StSize) {
550 // Promote to a byte-sized store with upper bits zero if not
551 // storing an integral number of bytes. For example, promote
552 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
553 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StSize.getFixedSize());
554 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
556 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
557 ST->getOriginalAlign(), MMOFlags, AAInfo);
558 ReplaceNode(SDValue(Node, 0), Result);
559 } else if (!StVT.isVector() && !isPowerOf2_64(StWidth.getFixedSize())) {
560 // If not storing a power-of-2 number of bits, expand as two stores.
561 assert(!StVT.isVector() && "Unsupported truncstore!");
562 unsigned StWidthBits = StWidth.getFixedSize();
563 unsigned LogStWidth = Log2_32(StWidthBits);
564 assert(LogStWidth < 32);
565 unsigned RoundWidth = 1 << LogStWidth;
566 assert(RoundWidth < StWidthBits);
567 unsigned ExtraWidth = StWidthBits - RoundWidth;
568 assert(ExtraWidth < RoundWidth);
569 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
570 "Store size not an integral number of bytes!");
571 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
572 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
574 unsigned IncrementSize;
576 if (DL.isLittleEndian()) {
577 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
578 // Store the bottom RoundWidth bits.
579 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
580 RoundVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
582 // Store the remaining ExtraWidth bits.
583 IncrementSize = RoundWidth / 8;
584 Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
586 ISD::SRL, dl, Value.getValueType(), Value,
587 DAG.getConstant(RoundWidth, dl,
588 TLI.getShiftAmountTy(Value.getValueType(), DL)));
589 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
590 ST->getPointerInfo().getWithOffset(IncrementSize),
591 ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
593 // Big endian - avoid unaligned stores.
594 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
595 // Store the top RoundWidth bits.
597 ISD::SRL, dl, Value.getValueType(), Value,
598 DAG.getConstant(ExtraWidth, dl,
599 TLI.getShiftAmountTy(Value.getValueType(), DL)));
600 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), RoundVT,
601 ST->getOriginalAlign(), MMOFlags, AAInfo);
603 // Store the remaining ExtraWidth bits.
604 IncrementSize = RoundWidth / 8;
605 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
606 DAG.getConstant(IncrementSize, dl,
607 Ptr.getValueType()));
608 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
609 ST->getPointerInfo().getWithOffset(IncrementSize),
610 ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
613 // The order of the stores doesn't matter.
614 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
615 ReplaceNode(SDValue(Node, 0), Result);
617 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
618 default: llvm_unreachable("This action is not supported yet!");
619 case TargetLowering::Legal: {
620 EVT MemVT = ST->getMemoryVT();
621 // If this is an unaligned store and the target doesn't support it,
623 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT,
624 *ST->getMemOperand())) {
625 SDValue Result = TLI.expandUnalignedStore(ST, DAG);
626 ReplaceNode(SDValue(ST, 0), Result);
630 case TargetLowering::Custom: {
631 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
632 if (Res && Res != SDValue(Node, 0))
633 ReplaceNode(SDValue(Node, 0), Res);
636 case TargetLowering::Expand:
637 assert(!StVT.isVector() &&
638 "Vector Stores are handled in LegalizeVectorOps");
642 // TRUNCSTORE:i16 i32 -> STORE i16
643 if (TLI.isTypeLegal(StVT)) {
644 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
645 Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
646 ST->getOriginalAlign(), MMOFlags, AAInfo);
648 // The in-memory type isn't legal. Truncate to the type it would promote
649 // to, and then do a truncstore.
650 Value = DAG.getNode(ISD::TRUNCATE, dl,
651 TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
654 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), StVT,
655 ST->getOriginalAlign(), MMOFlags, AAInfo);
658 ReplaceNode(SDValue(Node, 0), Result);
664 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
665 LoadSDNode *LD = cast<LoadSDNode>(Node);
666 SDValue Chain = LD->getChain(); // The chain.
667 SDValue Ptr = LD->getBasePtr(); // The base pointer.
668 SDValue Value; // The value returned by the load op.
671 ISD::LoadExtType ExtType = LD->getExtensionType();
672 if (ExtType == ISD::NON_EXTLOAD) {
673 LLVM_DEBUG(dbgs() << "Legalizing non-extending load operation\n");
674 MVT VT = Node->getSimpleValueType(0);
675 SDValue RVal = SDValue(Node, 0);
676 SDValue RChain = SDValue(Node, 1);
678 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
679 default: llvm_unreachable("This action is not supported yet!");
680 case TargetLowering::Legal: {
681 EVT MemVT = LD->getMemoryVT();
682 const DataLayout &DL = DAG.getDataLayout();
683 // If this is an unaligned load and the target doesn't support it,
685 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT,
686 *LD->getMemOperand())) {
687 std::tie(RVal, RChain) = TLI.expandUnalignedLoad(LD, DAG);
691 case TargetLowering::Custom:
692 if (SDValue Res = TLI.LowerOperation(RVal, DAG)) {
694 RChain = Res.getValue(1);
698 case TargetLowering::Promote: {
699 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
700 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
701 "Can only promote loads to same size type");
703 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
704 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
705 RChain = Res.getValue(1);
709 if (RChain.getNode() != Node) {
710 assert(RVal.getNode() != Node && "Load must be completely replaced");
711 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
712 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
714 UpdatedNodes->insert(RVal.getNode());
715 UpdatedNodes->insert(RChain.getNode());
722 LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n");
723 EVT SrcVT = LD->getMemoryVT();
724 TypeSize SrcWidth = SrcVT.getSizeInBits();
725 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
726 AAMDNodes AAInfo = LD->getAAInfo();
728 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
729 // Some targets pretend to have an i1 loading operation, and actually
730 // load an i8. This trick is correct for ZEXTLOAD because the top 7
731 // bits are guaranteed to be zero; it helps the optimizers understand
732 // that these bits are zero. It is also useful for EXTLOAD, since it
733 // tells the optimizers that those bits are undefined. It would be
734 // nice to have an effective generic way of getting these benefits...
735 // Until such a way is found, don't insist on promoting i1 here.
737 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
738 TargetLowering::Promote)) {
739 // Promote to a byte-sized load if not loading an integral number of
740 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
741 unsigned NewWidth = SrcVT.getStoreSizeInBits();
742 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
745 // The extra bits are guaranteed to be zero, since we stored them that
746 // way. A zext load from NVT thus automatically gives zext from SrcVT.
748 ISD::LoadExtType NewExtType =
749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
751 SDValue Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
752 Chain, Ptr, LD->getPointerInfo(), NVT,
753 LD->getOriginalAlign(), MMOFlags, AAInfo);
755 Ch = Result.getValue(1); // The chain.
757 if (ExtType == ISD::SEXTLOAD)
758 // Having the top bits zero doesn't help when sign extending.
759 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
760 Result.getValueType(),
761 Result, DAG.getValueType(SrcVT));
762 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
763 // All the top bits are guaranteed to be zero - inform the optimizers.
764 Result = DAG.getNode(ISD::AssertZext, dl,
765 Result.getValueType(), Result,
766 DAG.getValueType(SrcVT));
770 } else if (!isPowerOf2_64(SrcWidth.getKnownMinSize())) {
771 // If not loading a power-of-2 number of bits, expand as two loads.
772 assert(!SrcVT.isVector() && "Unsupported extload!");
773 unsigned SrcWidthBits = SrcWidth.getFixedSize();
774 unsigned LogSrcWidth = Log2_32(SrcWidthBits);
775 assert(LogSrcWidth < 32);
776 unsigned RoundWidth = 1 << LogSrcWidth;
777 assert(RoundWidth < SrcWidthBits);
778 unsigned ExtraWidth = SrcWidthBits - RoundWidth;
779 assert(ExtraWidth < RoundWidth);
780 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
781 "Load size not an integral number of bytes!");
782 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
783 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
785 unsigned IncrementSize;
786 auto &DL = DAG.getDataLayout();
788 if (DL.isLittleEndian()) {
789 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
790 // Load the bottom RoundWidth bits.
791 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
792 LD->getPointerInfo(), RoundVT, LD->getOriginalAlign(),
795 // Load the remaining ExtraWidth bits.
796 IncrementSize = RoundWidth / 8;
797 Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
798 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
799 LD->getPointerInfo().getWithOffset(IncrementSize),
800 ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
802 // Build a factor node to remember that this load is independent of
804 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
807 // Move the top bits to the right place.
809 ISD::SHL, dl, Hi.getValueType(), Hi,
810 DAG.getConstant(RoundWidth, dl,
811 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
813 // Join the hi and lo parts.
814 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
816 // Big endian - avoid unaligned loads.
817 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
818 // Load the top RoundWidth bits.
819 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
820 LD->getPointerInfo(), RoundVT, LD->getOriginalAlign(),
823 // Load the remaining ExtraWidth bits.
824 IncrementSize = RoundWidth / 8;
825 Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
826 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
827 LD->getPointerInfo().getWithOffset(IncrementSize),
828 ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
830 // Build a factor node to remember that this load is independent of
832 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
835 // Move the top bits to the right place.
837 ISD::SHL, dl, Hi.getValueType(), Hi,
838 DAG.getConstant(ExtraWidth, dl,
839 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
841 // Join the hi and lo parts.
842 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
847 bool isCustom = false;
848 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
849 SrcVT.getSimpleVT())) {
850 default: llvm_unreachable("This action is not supported yet!");
851 case TargetLowering::Custom:
854 case TargetLowering::Legal:
855 Value = SDValue(Node, 0);
856 Chain = SDValue(Node, 1);
859 if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
861 Chain = Res.getValue(1);
864 // If this is an unaligned load and the target doesn't support it,
866 EVT MemVT = LD->getMemoryVT();
867 const DataLayout &DL = DAG.getDataLayout();
868 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT,
869 *LD->getMemOperand())) {
870 std::tie(Value, Chain) = TLI.expandUnalignedLoad(LD, DAG);
875 case TargetLowering::Expand: {
876 EVT DestVT = Node->getValueType(0);
877 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
878 // If the source type is not legal, see if there is a legal extload to
879 // an intermediate type that we can then extend further.
880 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
881 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
882 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
883 // If we are loading a legal type, this is a non-extload followed by a
885 ISD::LoadExtType MidExtType =
886 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
888 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
889 SrcVT, LD->getMemOperand());
891 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
892 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
893 Chain = Load.getValue(1);
897 // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
898 // normal undefined upper bits behavior to allow using an in-reg extend
899 // with the illegal FP type, so load as an integer and do the
900 // from-integer conversion.
901 if (SrcVT.getScalarType() == MVT::f16) {
902 EVT ISrcVT = SrcVT.changeTypeToInteger();
903 EVT IDestVT = DestVT.changeTypeToInteger();
904 EVT ILoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
906 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, ILoadVT, Chain,
907 Ptr, ISrcVT, LD->getMemOperand());
908 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
909 Chain = Result.getValue(1);
914 assert(!SrcVT.isVector() &&
915 "Vector Loads are handled in LegalizeVectorOps");
917 // FIXME: This does not work for vectors on most targets. Sign-
918 // and zero-extend operations are currently folded into extending
919 // loads, whether they are legal or not, and then we end up here
920 // without any support for legalizing them.
921 assert(ExtType != ISD::EXTLOAD &&
922 "EXTLOAD should always be supported!");
923 // Turn the unsupported load into an EXTLOAD followed by an
924 // explicit zero/sign extend inreg.
925 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
926 Node->getValueType(0),
928 LD->getMemOperand());
930 if (ExtType == ISD::SEXTLOAD)
931 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
932 Result.getValueType(),
933 Result, DAG.getValueType(SrcVT));
935 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
937 Chain = Result.getValue(1);
943 // Since loads produce two values, make sure to remember that we legalized
945 if (Chain.getNode() != Node) {
946 assert(Value.getNode() != Node && "Load must be completely replaced");
947 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
948 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
950 UpdatedNodes->insert(Value.getNode());
951 UpdatedNodes->insert(Chain.getNode());
957 /// Return a legal replacement for the given operation, with all legal operands.
958 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
959 LLVM_DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
961 // Allow illegal target nodes and illegal registers.
962 if (Node->getOpcode() == ISD::TargetConstant ||
963 Node->getOpcode() == ISD::Register)
967 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
968 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
969 TargetLowering::TypeLegal &&
970 "Unexpected illegal type!");
972 for (const SDValue &Op : Node->op_values())
973 assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
974 TargetLowering::TypeLegal ||
975 Op.getOpcode() == ISD::TargetConstant ||
976 Op.getOpcode() == ISD::Register) &&
977 "Unexpected illegal type!");
980 // Figure out the correct action; the way to query this varies by opcode
981 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
982 bool SimpleFinishLegalizing = true;
983 switch (Node->getOpcode()) {
984 case ISD::INTRINSIC_W_CHAIN:
985 case ISD::INTRINSIC_WO_CHAIN:
986 case ISD::INTRINSIC_VOID:
988 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
990 case ISD::GET_DYNAMIC_AREA_OFFSET:
991 Action = TLI.getOperationAction(Node->getOpcode(),
992 Node->getValueType(0));
995 Action = TLI.getOperationAction(Node->getOpcode(),
996 Node->getValueType(0));
997 if (Action != TargetLowering::Promote)
998 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1000 case ISD::FP_TO_FP16:
1001 case ISD::FP_TO_BF16:
1002 case ISD::SINT_TO_FP:
1003 case ISD::UINT_TO_FP:
1004 case ISD::EXTRACT_VECTOR_ELT:
1009 Action = TLI.getOperationAction(Node->getOpcode(),
1010 Node->getOperand(0).getValueType());
1012 case ISD::STRICT_FP_TO_FP16:
1013 case ISD::STRICT_SINT_TO_FP:
1014 case ISD::STRICT_UINT_TO_FP:
1015 case ISD::STRICT_LRINT:
1016 case ISD::STRICT_LLRINT:
1017 case ISD::STRICT_LROUND:
1018 case ISD::STRICT_LLROUND:
1019 // These pseudo-ops are the same as the other STRICT_ ops except
1020 // they are registered with setOperationAction() using the input type
1021 // instead of the output type.
1022 Action = TLI.getOperationAction(Node->getOpcode(),
1023 Node->getOperand(1).getValueType());
1025 case ISD::SIGN_EXTEND_INREG: {
1026 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1027 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1030 case ISD::ATOMIC_STORE:
1031 Action = TLI.getOperationAction(Node->getOpcode(),
1032 Node->getOperand(2).getValueType());
1034 case ISD::SELECT_CC:
1035 case ISD::STRICT_FSETCC:
1036 case ISD::STRICT_FSETCCS:
1040 unsigned Opc = Node->getOpcode();
1041 unsigned CCOperand = Opc == ISD::SELECT_CC ? 4
1042 : Opc == ISD::STRICT_FSETCC ? 3
1043 : Opc == ISD::STRICT_FSETCCS ? 3
1044 : (Opc == ISD::SETCC || Opc == ISD::VP_SETCC) ? 2
1046 unsigned CompareOperand = Opc == ISD::BR_CC ? 2
1047 : Opc == ISD::STRICT_FSETCC ? 1
1048 : Opc == ISD::STRICT_FSETCCS ? 1
1050 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1051 ISD::CondCode CCCode =
1052 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1053 Action = TLI.getCondCodeAction(CCCode, OpVT);
1054 if (Action == TargetLowering::Legal) {
1055 if (Node->getOpcode() == ISD::SELECT_CC)
1056 Action = TLI.getOperationAction(Node->getOpcode(),
1057 Node->getValueType(0));
1059 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1065 // FIXME: Model these properly. LOAD and STORE are complicated, and
1066 // STORE expects the unlegalized operand in some cases.
1067 SimpleFinishLegalizing = false;
1069 case ISD::CALLSEQ_START:
1070 case ISD::CALLSEQ_END:
1071 // FIXME: This shouldn't be necessary. These nodes have special properties
1072 // dealing with the recursive nature of legalization. Removing this
1073 // special case should be done as part of making LegalizeDAG non-recursive.
1074 SimpleFinishLegalizing = false;
1076 case ISD::EXTRACT_ELEMENT:
1077 case ISD::FLT_ROUNDS_:
1078 case ISD::MERGE_VALUES:
1079 case ISD::EH_RETURN:
1080 case ISD::FRAME_TO_ARGS_OFFSET:
1081 case ISD::EH_DWARF_CFA:
1082 case ISD::EH_SJLJ_SETJMP:
1083 case ISD::EH_SJLJ_LONGJMP:
1084 case ISD::EH_SJLJ_SETUP_DISPATCH:
1085 // These operations lie about being legal: when they claim to be legal,
1086 // they should actually be expanded.
1087 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1088 if (Action == TargetLowering::Legal)
1089 Action = TargetLowering::Expand;
1091 case ISD::INIT_TRAMPOLINE:
1092 case ISD::ADJUST_TRAMPOLINE:
1093 case ISD::FRAMEADDR:
1094 case ISD::RETURNADDR:
1095 case ISD::ADDROFRETURNADDR:
1096 case ISD::SPONENTRY:
1097 // These operations lie about being legal: when they claim to be legal,
1098 // they should actually be custom-lowered.
1099 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1100 if (Action == TargetLowering::Legal)
1101 Action = TargetLowering::Custom;
1103 case ISD::READCYCLECOUNTER:
1104 // READCYCLECOUNTER returns an i64, even if type legalization might have
1105 // expanded that to several smaller types.
1106 Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1108 case ISD::READ_REGISTER:
1109 case ISD::WRITE_REGISTER:
1110 // Named register is legal in the DAG, but blocked by register name
1111 // selection if not implemented by target (to chose the correct register)
1112 // They'll be converted to Copy(To/From)Reg.
1113 Action = TargetLowering::Legal;
1115 case ISD::UBSANTRAP:
1116 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1117 if (Action == TargetLowering::Expand) {
1118 // replace ISD::UBSANTRAP with ISD::TRAP
1120 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1121 Node->getOperand(0));
1122 ReplaceNode(Node, NewVal.getNode());
1123 LegalizeOp(NewVal.getNode());
1127 case ISD::DEBUGTRAP:
1128 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1129 if (Action == TargetLowering::Expand) {
1130 // replace ISD::DEBUGTRAP with ISD::TRAP
1132 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1133 Node->getOperand(0));
1134 ReplaceNode(Node, NewVal.getNode());
1135 LegalizeOp(NewVal.getNode());
1145 case ISD::FP_TO_SINT_SAT:
1146 case ISD::FP_TO_UINT_SAT:
1147 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1150 case ISD::SMULFIXSAT:
1152 case ISD::UMULFIXSAT:
1154 case ISD::SDIVFIXSAT:
1156 case ISD::UDIVFIXSAT: {
1157 unsigned Scale = Node->getConstantOperandVal(2);
1158 Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
1159 Node->getValueType(0), Scale);
1163 Action = TLI.getOperationAction(Node->getOpcode(),
1164 cast<MaskedScatterSDNode>(Node)->getValue().getValueType());
1167 Action = TLI.getOperationAction(Node->getOpcode(),
1168 cast<MaskedStoreSDNode>(Node)->getValue().getValueType());
1170 case ISD::VP_SCATTER:
1171 Action = TLI.getOperationAction(
1173 cast<VPScatterSDNode>(Node)->getValue().getValueType());
1176 Action = TLI.getOperationAction(
1178 cast<VPStoreSDNode>(Node)->getValue().getValueType());
1180 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
1181 Action = TLI.getOperationAction(
1183 cast<VPStridedStoreSDNode>(Node)->getValue().getValueType());
1185 case ISD::VECREDUCE_FADD:
1186 case ISD::VECREDUCE_FMUL:
1187 case ISD::VECREDUCE_ADD:
1188 case ISD::VECREDUCE_MUL:
1189 case ISD::VECREDUCE_AND:
1190 case ISD::VECREDUCE_OR:
1191 case ISD::VECREDUCE_XOR:
1192 case ISD::VECREDUCE_SMAX:
1193 case ISD::VECREDUCE_SMIN:
1194 case ISD::VECREDUCE_UMAX:
1195 case ISD::VECREDUCE_UMIN:
1196 case ISD::VECREDUCE_FMAX:
1197 case ISD::VECREDUCE_FMIN:
1198 case ISD::IS_FPCLASS:
1199 Action = TLI.getOperationAction(
1200 Node->getOpcode(), Node->getOperand(0).getValueType());
1202 case ISD::VECREDUCE_SEQ_FADD:
1203 case ISD::VECREDUCE_SEQ_FMUL:
1204 case ISD::VP_REDUCE_FADD:
1205 case ISD::VP_REDUCE_FMUL:
1206 case ISD::VP_REDUCE_ADD:
1207 case ISD::VP_REDUCE_MUL:
1208 case ISD::VP_REDUCE_AND:
1209 case ISD::VP_REDUCE_OR:
1210 case ISD::VP_REDUCE_XOR:
1211 case ISD::VP_REDUCE_SMAX:
1212 case ISD::VP_REDUCE_SMIN:
1213 case ISD::VP_REDUCE_UMAX:
1214 case ISD::VP_REDUCE_UMIN:
1215 case ISD::VP_REDUCE_FMAX:
1216 case ISD::VP_REDUCE_FMIN:
1217 case ISD::VP_REDUCE_SEQ_FADD:
1218 case ISD::VP_REDUCE_SEQ_FMUL:
1219 Action = TLI.getOperationAction(
1220 Node->getOpcode(), Node->getOperand(1).getValueType());
1223 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1224 Action = TLI.getCustomOperationAction(*Node);
1226 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1231 if (SimpleFinishLegalizing) {
1232 SDNode *NewNode = Node;
1233 switch (Node->getOpcode()) {
1240 // Legalizing shifts/rotates requires adjusting the shift amount
1241 // to the appropriate width.
1242 SDValue Op0 = Node->getOperand(0);
1243 SDValue Op1 = Node->getOperand(1);
1244 if (!Op1.getValueType().isVector()) {
1245 SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op1);
1246 // The getShiftAmountOperand() may create a new operand node or
1247 // return the existing one. If new operand is created we need
1248 // to update the parent node.
1249 // Do not try to legalize SAO here! It will be automatically legalized
1250 // in the next round.
1252 NewNode = DAG.UpdateNodeOperands(Node, Op0, SAO);
1258 case ISD::SRL_PARTS:
1259 case ISD::SRA_PARTS:
1260 case ISD::SHL_PARTS: {
1261 // Legalizing shifts/rotates requires adjusting the shift amount
1262 // to the appropriate width.
1263 SDValue Op0 = Node->getOperand(0);
1264 SDValue Op1 = Node->getOperand(1);
1265 SDValue Op2 = Node->getOperand(2);
1266 if (!Op2.getValueType().isVector()) {
1267 SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op2);
1268 // The getShiftAmountOperand() may create a new operand node or
1269 // return the existing one. If new operand is created we need
1270 // to update the parent node.
1272 NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO);
1278 if (NewNode != Node) {
1279 ReplaceNode(Node, NewNode);
1283 case TargetLowering::Legal:
1284 LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
1286 case TargetLowering::Custom:
1287 LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
1288 // FIXME: The handling for custom lowering with multiple results is
1290 if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
1291 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1294 if (Node->getNumValues() == 1) {
1295 // Verify the new types match the original. Glue is waived because
1296 // ISD::ADDC can be legalized by replacing Glue with an integer type.
1297 assert((Res.getValueType() == Node->getValueType(0) ||
1298 Node->getValueType(0) == MVT::Glue) &&
1299 "Type mismatch for custom legalized operation");
1300 LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1301 // We can just directly replace this node with the lowered value.
1302 ReplaceNode(SDValue(Node, 0), Res);
1306 SmallVector<SDValue, 8> ResultVals;
1307 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1308 // Verify the new types match the original. Glue is waived because
1309 // ISD::ADDC can be legalized by replacing Glue with an integer type.
1310 assert((Res->getValueType(i) == Node->getValueType(i) ||
1311 Node->getValueType(i) == MVT::Glue) &&
1312 "Type mismatch for custom legalized operation");
1313 ResultVals.push_back(Res.getValue(i));
1315 LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1316 ReplaceNode(Node, ResultVals.data());
1319 LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
1321 case TargetLowering::Expand:
1322 if (ExpandNode(Node))
1325 case TargetLowering::LibCall:
1326 ConvertNodeToLibcall(Node);
1328 case TargetLowering::Promote:
1334 switch (Node->getOpcode()) {
1341 llvm_unreachable("Do not know how to legalize this operator!");
1343 case ISD::CALLSEQ_START:
1344 case ISD::CALLSEQ_END:
1347 return LegalizeLoadOps(Node);
1349 return LegalizeStoreOps(Node);
1353 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1354 SDValue Vec = Op.getOperand(0);
1355 SDValue Idx = Op.getOperand(1);
1358 // Before we generate a new store to a temporary stack slot, see if there is
1359 // already one that we can use. There often is because when we scalarize
1360 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1361 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1362 // the vector. If all are expanded here, we don't want one store per vector
1365 // Caches for hasPredecessorHelper
1366 SmallPtrSet<const SDNode *, 32> Visited;
1367 SmallVector<const SDNode *, 16> Worklist;
1368 Visited.insert(Op.getNode());
1369 Worklist.push_back(Idx.getNode());
1370 SDValue StackPtr, Ch;
1371 for (SDNode *User : Vec.getNode()->uses()) {
1372 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1373 if (ST->isIndexed() || ST->isTruncatingStore() ||
1374 ST->getValue() != Vec)
1377 // Make sure that nothing else could have stored into the destination of
1379 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1382 // If the index is dependent on the store we will introduce a cycle when
1383 // creating the load (the load uses the index, and by replacing the chain
1384 // we will make the index dependent on the load). Also, the store might be
1385 // dependent on the extractelement and introduce a cycle when creating
1387 if (SDNode::hasPredecessorHelper(ST, Visited, Worklist) ||
1388 ST->hasPredecessor(Op.getNode()))
1391 StackPtr = ST->getBasePtr();
1392 Ch = SDValue(ST, 0);
1397 EVT VecVT = Vec.getValueType();
1399 if (!Ch.getNode()) {
1400 // Store the value to a temporary stack slot, then LOAD the returned part.
1401 StackPtr = DAG.CreateStackTemporary(VecVT);
1402 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1403 MachinePointerInfo());
1407 Align ElementAlignment =
1408 std::min(cast<StoreSDNode>(Ch)->getAlign(),
1409 DAG.getDataLayout().getPrefTypeAlign(
1410 Op.getValueType().getTypeForEVT(*DAG.getContext())));
1412 if (Op.getValueType().isVector()) {
1413 StackPtr = TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT,
1414 Op.getValueType(), Idx);
1415 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,
1416 MachinePointerInfo(), ElementAlignment);
1418 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1419 NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1420 MachinePointerInfo(), VecVT.getVectorElementType(),
1424 // Replace the chain going out of the store, by the one out of the load.
1425 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1427 // We introduced a cycle though, so update the loads operands, making sure
1428 // to use the original store's chain as an incoming chain.
1429 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1431 NewLoadOperands[0] = Ch;
1433 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1437 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1438 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1440 SDValue Vec = Op.getOperand(0);
1441 SDValue Part = Op.getOperand(1);
1442 SDValue Idx = Op.getOperand(2);
1445 // Store the value to a temporary stack slot, then LOAD the returned part.
1446 EVT VecVT = Vec.getValueType();
1447 EVT SubVecVT = Part.getValueType();
1448 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1449 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1450 MachinePointerInfo PtrInfo =
1451 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1453 // First store the whole vector.
1454 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1456 // Then store the inserted part.
1457 SDValue SubStackPtr =
1458 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx);
1460 // Store the subvector.
1462 Ch, dl, Part, SubStackPtr,
1463 MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()));
1465 // Finally, load the updated vector.
1466 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo);
1469 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1470 assert((Node->getOpcode() == ISD::BUILD_VECTOR ||
1471 Node->getOpcode() == ISD::CONCAT_VECTORS) &&
1472 "Unexpected opcode!");
1474 // We can't handle this case efficiently. Allocate a sufficiently
1475 // aligned object on the stack, store each operand into it, then load
1476 // the result as a vector.
1477 // Create the stack frame object.
1478 EVT VT = Node->getValueType(0);
1479 EVT MemVT = isa<BuildVectorSDNode>(Node) ? VT.getVectorElementType()
1480 : Node->getOperand(0).getValueType();
1482 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1483 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1484 MachinePointerInfo PtrInfo =
1485 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1487 // Emit a store of each element to the stack slot.
1488 SmallVector<SDValue, 8> Stores;
1489 unsigned TypeByteSize = MemVT.getSizeInBits() / 8;
1490 assert(TypeByteSize > 0 && "Vector element type too small for stack store!");
1492 // If the destination vector element type of a BUILD_VECTOR is narrower than
1493 // the source element type, only store the bits necessary.
1494 bool Truncate = isa<BuildVectorSDNode>(Node) &&
1495 MemVT.bitsLT(Node->getOperand(0).getValueType());
1497 // Store (in the right endianness) the elements to memory.
1498 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1499 // Ignore undef elements.
1500 if (Node->getOperand(i).isUndef()) continue;
1502 unsigned Offset = TypeByteSize*i;
1504 SDValue Idx = DAG.getMemBasePlusOffset(FIPtr, TypeSize::Fixed(Offset), dl);
1507 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1508 Node->getOperand(i), Idx,
1509 PtrInfo.getWithOffset(Offset), MemVT));
1511 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1512 Idx, PtrInfo.getWithOffset(Offset)));
1516 if (!Stores.empty()) // Not all undef elements?
1517 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1519 StoreChain = DAG.getEntryNode();
1521 // Result is a load from the stack slot.
1522 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo);
1525 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1526 /// containing the sign bit if the target has no integer value capable of
1527 /// holding all bits of the floating-point value.
1528 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1530 SDValue Value) const {
1531 EVT FloatVT = Value.getValueType();
1532 unsigned NumBits = FloatVT.getScalarSizeInBits();
1533 State.FloatVT = FloatVT;
1534 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1535 // Convert to an integer of the same size.
1536 if (TLI.isTypeLegal(IVT)) {
1537 State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1538 State.SignMask = APInt::getSignMask(NumBits);
1539 State.SignBit = NumBits - 1;
1543 auto &DataLayout = DAG.getDataLayout();
1544 // Store the float to memory, then load the sign part out as an integer.
1545 MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1546 // First create a temporary that is aligned for both the load and store.
1547 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1548 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1549 // Then store the float to it.
1550 State.FloatPtr = StackPtr;
1551 MachineFunction &MF = DAG.getMachineFunction();
1552 State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1553 State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1554 State.FloatPointerInfo);
1557 if (DataLayout.isBigEndian()) {
1558 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1559 // Load out a legal integer with the same sign bit as the float.
1561 State.IntPointerInfo = State.FloatPointerInfo;
1563 // Advance the pointer so that the loaded byte will contain the sign bit.
1564 unsigned ByteOffset = (NumBits / 8) - 1;
1566 DAG.getMemBasePlusOffset(StackPtr, TypeSize::Fixed(ByteOffset), DL);
1567 State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1571 State.IntPtr = IntPtr;
1572 State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr,
1573 State.IntPointerInfo, MVT::i8);
1574 State.SignMask = APInt::getOneBitSet(LoadTy.getScalarSizeInBits(), 7);
1578 /// Replace the integer value produced by getSignAsIntValue() with a new value
1579 /// and cast the result back to a floating-point type.
1580 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1582 SDValue NewIntValue) const {
1584 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1586 // Override the part containing the sign bit in the value stored on the stack.
1587 SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1588 State.IntPointerInfo, MVT::i8);
1589 return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1590 State.FloatPointerInfo);
1593 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1595 SDValue Mag = Node->getOperand(0);
1596 SDValue Sign = Node->getOperand(1);
1598 // Get sign bit into an integer value.
1599 FloatSignAsInt SignAsInt;
1600 getSignAsIntValue(SignAsInt, DL, Sign);
1602 EVT IntVT = SignAsInt.IntValue.getValueType();
1603 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1604 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1607 // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1608 EVT FloatVT = Mag.getValueType();
1609 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1610 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1611 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1612 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1613 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1614 DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1615 return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1618 // Transform Mag value to integer, and clear the sign bit.
1619 FloatSignAsInt MagAsInt;
1620 getSignAsIntValue(MagAsInt, DL, Mag);
1621 EVT MagVT = MagAsInt.IntValue.getValueType();
1622 SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
1623 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1626 // Get the signbit at the right position for MagAsInt.
1627 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1628 EVT ShiftVT = IntVT;
1629 if (SignBit.getScalarValueSizeInBits() <
1630 ClearedSign.getScalarValueSizeInBits()) {
1631 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
1634 if (ShiftAmount > 0) {
1635 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT);
1636 SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst);
1637 } else if (ShiftAmount < 0) {
1638 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT);
1639 SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst);
1641 if (SignBit.getScalarValueSizeInBits() >
1642 ClearedSign.getScalarValueSizeInBits()) {
1643 SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
1646 // Store the part with the modified sign and convert back to float.
1647 SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1648 return modifySignAsInt(MagAsInt, DL, CopiedSign);
1651 SDValue SelectionDAGLegalize::ExpandFNEG(SDNode *Node) const {
1652 // Get the sign bit as an integer.
1654 FloatSignAsInt SignAsInt;
1655 getSignAsIntValue(SignAsInt, DL, Node->getOperand(0));
1656 EVT IntVT = SignAsInt.IntValue.getValueType();
1659 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1661 DAG.getNode(ISD::XOR, DL, IntVT, SignAsInt.IntValue, SignMask);
1663 // Convert back to float.
1664 return modifySignAsInt(SignAsInt, DL, SignFlip);
1667 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1669 SDValue Value = Node->getOperand(0);
1671 // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1672 EVT FloatVT = Value.getValueType();
1673 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1674 SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1675 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1678 // Transform value to integer, clear the sign bit and transform back.
1679 FloatSignAsInt ValueAsInt;
1680 getSignAsIntValue(ValueAsInt, DL, Value);
1681 EVT IntVT = ValueAsInt.IntValue.getValueType();
1682 SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1683 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1685 return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1688 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1689 SmallVectorImpl<SDValue> &Results) {
1690 Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
1691 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1692 " not tell us which reg is the stack pointer!");
1694 EVT VT = Node->getValueType(0);
1695 SDValue Tmp1 = SDValue(Node, 0);
1696 SDValue Tmp2 = SDValue(Node, 1);
1697 SDValue Tmp3 = Node->getOperand(2);
1698 SDValue Chain = Tmp1.getOperand(0);
1700 // Chain the dynamic stack allocation so that it doesn't modify the stack
1701 // pointer when other instructions are using the stack.
1702 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
1704 SDValue Size = Tmp2.getOperand(1);
1705 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1706 Chain = SP.getValue(1);
1707 Align Alignment = cast<ConstantSDNode>(Tmp3)->getAlignValue();
1708 const TargetFrameLowering *TFL = DAG.getSubtarget().getFrameLowering();
1710 TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp ?
1711 ISD::ADD : ISD::SUB;
1713 Align StackAlign = TFL->getStackAlign();
1714 Tmp1 = DAG.getNode(Opc, dl, VT, SP, Size); // Value
1715 if (Alignment > StackAlign)
1716 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1717 DAG.getConstant(-Alignment.value(), dl, VT));
1718 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1720 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1721 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1723 Results.push_back(Tmp1);
1724 Results.push_back(Tmp2);
1727 /// Emit a store/load combination to the stack. This stores
1728 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1729 /// a load from the stack slot to DestVT, extending it if needed.
1730 /// The resultant code need not be legal.
1731 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1732 EVT DestVT, const SDLoc &dl) {
1733 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode());
1736 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1737 EVT DestVT, const SDLoc &dl,
1739 EVT SrcVT = SrcOp.getValueType();
1740 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1741 Align DestAlign = DAG.getDataLayout().getPrefTypeAlign(DestType);
1743 // Don't convert with stack if the load/store is expensive.
1744 if ((SrcVT.bitsGT(SlotVT) &&
1745 !TLI.isTruncStoreLegalOrCustom(SrcOp.getValueType(), SlotVT)) ||
1746 (SlotVT.bitsLT(DestVT) &&
1747 !TLI.isLoadExtLegalOrCustom(ISD::EXTLOAD, DestVT, SlotVT)))
1750 // Create the stack frame object.
1751 Align SrcAlign = DAG.getDataLayout().getPrefTypeAlign(
1752 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1753 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT.getStoreSize(), SrcAlign);
1755 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1756 int SPFI = StackPtrFI->getIndex();
1757 MachinePointerInfo PtrInfo =
1758 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1760 // Emit a store to the stack slot. Use a truncstore if the input value is
1761 // later than DestVT.
1764 if (SrcVT.bitsGT(SlotVT))
1765 Store = DAG.getTruncStore(Chain, dl, SrcOp, FIPtr, PtrInfo,
1768 assert(SrcVT.bitsEq(SlotVT) && "Invalid store");
1769 Store = DAG.getStore(Chain, dl, SrcOp, FIPtr, PtrInfo, SrcAlign);
1772 // Result is a load from the stack slot.
1773 if (SlotVT.bitsEq(DestVT))
1774 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, DestAlign);
1776 assert(SlotVT.bitsLT(DestVT) && "Unknown extension!");
1777 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT,
1781 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1783 // Create a vector sized/aligned stack slot, store the value to element #0,
1784 // then load the whole vector back out.
1785 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1787 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1788 int SPFI = StackPtrFI->getIndex();
1790 SDValue Ch = DAG.getTruncStore(
1791 DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1792 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1793 Node->getValueType(0).getVectorElementType());
1795 Node->getValueType(0), dl, Ch, StackPtr,
1796 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
1800 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1801 const TargetLowering &TLI, SDValue &Res) {
1802 unsigned NumElems = Node->getNumOperands();
1804 EVT VT = Node->getValueType(0);
1806 // Try to group the scalars into pairs, shuffle the pairs together, then
1807 // shuffle the pairs of pairs together, etc. until the vector has
1808 // been built. This will work only if all of the necessary shuffle masks
1811 // We do this in two phases; first to check the legality of the shuffles,
1812 // and next, assuming that all shuffles are legal, to create the new nodes.
1813 for (int Phase = 0; Phase < 2; ++Phase) {
1814 SmallVector<std::pair<SDValue, SmallVector<int, 16>>, 16> IntermedVals,
1816 for (unsigned i = 0; i < NumElems; ++i) {
1817 SDValue V = Node->getOperand(i);
1823 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1824 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1827 while (IntermedVals.size() > 2) {
1828 NewIntermedVals.clear();
1829 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1830 // This vector and the next vector are shuffled together (simply to
1831 // append the one to the other).
1832 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1834 SmallVector<int, 16> FinalIndices;
1835 FinalIndices.reserve(IntermedVals[i].second.size() +
1836 IntermedVals[i+1].second.size());
1839 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1842 FinalIndices.push_back(IntermedVals[i].second[j]);
1844 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1846 ShuffleVec[k] = NumElems + j;
1847 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1852 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1853 IntermedVals[i+1].first,
1855 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1857 NewIntermedVals.push_back(
1858 std::make_pair(Shuffle, std::move(FinalIndices)));
1861 // If we had an odd number of defined values, then append the last
1862 // element to the array of new vectors.
1863 if ((IntermedVals.size() & 1) != 0)
1864 NewIntermedVals.push_back(IntermedVals.back());
1866 IntermedVals.swap(NewIntermedVals);
1869 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1870 "Invalid number of intermediate vectors");
1871 SDValue Vec1 = IntermedVals[0].first;
1873 if (IntermedVals.size() > 1)
1874 Vec2 = IntermedVals[1].first;
1876 Vec2 = DAG.getUNDEF(VT);
1878 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1879 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1880 ShuffleVec[IntermedVals[0].second[i]] = i;
1881 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1882 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1885 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1886 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1893 /// Expand a BUILD_VECTOR node on targets that don't
1894 /// support the operation, but do support the resultant vector type.
1895 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1896 unsigned NumElems = Node->getNumOperands();
1897 SDValue Value1, Value2;
1899 EVT VT = Node->getValueType(0);
1900 EVT OpVT = Node->getOperand(0).getValueType();
1901 EVT EltVT = VT.getVectorElementType();
1903 // If the only non-undef value is the low element, turn this into a
1904 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1905 bool isOnlyLowElement = true;
1906 bool MoreThanTwoValues = false;
1907 bool isConstant = true;
1908 for (unsigned i = 0; i < NumElems; ++i) {
1909 SDValue V = Node->getOperand(i);
1913 isOnlyLowElement = false;
1914 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1917 if (!Value1.getNode()) {
1919 } else if (!Value2.getNode()) {
1922 } else if (V != Value1 && V != Value2) {
1923 MoreThanTwoValues = true;
1927 if (!Value1.getNode())
1928 return DAG.getUNDEF(VT);
1930 if (isOnlyLowElement)
1931 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1933 // If all elements are constants, create a load from the constant pool.
1935 SmallVector<Constant*, 16> CV;
1936 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1937 if (ConstantFPSDNode *V =
1938 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1939 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1940 } else if (ConstantSDNode *V =
1941 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1943 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1945 // If OpVT and EltVT don't match, EltVT is not legal and the
1946 // element values have been promoted/truncated earlier. Undo this;
1947 // we don't want a v16i8 to become a v16i32 for example.
1948 const ConstantInt *CI = V->getConstantIntValue();
1949 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1950 CI->getZExtValue()));
1953 assert(Node->getOperand(i).isUndef());
1954 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1955 CV.push_back(UndefValue::get(OpNTy));
1958 Constant *CP = ConstantVector::get(CV);
1960 DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
1961 Align Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlign();
1963 VT, dl, DAG.getEntryNode(), CPIdx,
1964 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
1968 SmallSet<SDValue, 16> DefinedValues;
1969 for (unsigned i = 0; i < NumElems; ++i) {
1970 if (Node->getOperand(i).isUndef())
1972 DefinedValues.insert(Node->getOperand(i));
1975 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1976 if (!MoreThanTwoValues) {
1977 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1978 for (unsigned i = 0; i < NumElems; ++i) {
1979 SDValue V = Node->getOperand(i);
1982 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1984 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1985 // Get the splatted value into the low element of a vector register.
1986 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1988 if (Value2.getNode())
1989 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1991 Vec2 = DAG.getUNDEF(VT);
1993 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1994 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1998 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2003 // Otherwise, we can't handle this case efficiently.
2004 return ExpandVectorBuildThroughStack(Node);
2007 SDValue SelectionDAGLegalize::ExpandSPLAT_VECTOR(SDNode *Node) {
2009 EVT VT = Node->getValueType(0);
2010 SDValue SplatVal = Node->getOperand(0);
2012 return DAG.getSplatBuildVector(VT, DL, SplatVal);
2015 // Expand a node into a call to a libcall. If the result value
2016 // does not fit into a register, return the lo part and set the hi part to the
2017 // by-reg argument. If it does fit into a single register, return the result
2018 // and leave the Hi part unset.
2019 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2021 TargetLowering::ArgListTy Args;
2022 TargetLowering::ArgListEntry Entry;
2023 for (const SDValue &Op : Node->op_values()) {
2024 EVT ArgVT = Op.getValueType();
2025 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2028 Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2029 Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2030 Args.push_back(Entry);
2032 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2033 TLI.getPointerTy(DAG.getDataLayout()));
2035 EVT RetVT = Node->getValueType(0);
2036 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2038 // By default, the input chain to this libcall is the entry node of the
2039 // function. If the libcall is going to be emitted as a tail call then
2040 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2041 // node which is being folded has a non-entry input chain.
2042 SDValue InChain = DAG.getEntryNode();
2044 // isTailCall may be true since the callee does not reference caller stack
2045 // frame. Check if it's in the right position and that the return types match.
2046 SDValue TCChain = InChain;
2047 const Function &F = DAG.getMachineFunction().getFunction();
2049 TLI.isInTailCallPosition(DAG, Node, TCChain) &&
2050 (RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
2054 TargetLowering::CallLoweringInfo CLI(DAG);
2055 bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
2056 CLI.setDebugLoc(SDLoc(Node))
2058 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2060 .setTailCall(isTailCall)
2061 .setSExtResult(signExtend)
2062 .setZExtResult(!signExtend)
2063 .setIsPostTypeLegalization(true);
2065 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2067 if (!CallInfo.second.getNode()) {
2068 LLVM_DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump(&DAG));
2069 // It's a tailcall, return the chain (which is the DAG root).
2070 return DAG.getRoot();
2073 LLVM_DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump(&DAG));
2074 return CallInfo.first;
2077 void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2079 SmallVectorImpl<SDValue> &Results) {
2080 if (LC == RTLIB::UNKNOWN_LIBCALL)
2081 llvm_unreachable("Can't create an unknown libcall!");
2083 if (Node->isStrictFPOpcode()) {
2084 EVT RetVT = Node->getValueType(0);
2085 SmallVector<SDValue, 4> Ops(drop_begin(Node->ops()));
2086 TargetLowering::MakeLibCallOptions CallOptions;
2087 // FIXME: This doesn't support tail calls.
2088 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
2091 Node->getOperand(0));
2092 Results.push_back(Tmp.first);
2093 Results.push_back(Tmp.second);
2095 SDValue Tmp = ExpandLibCall(LC, Node, false);
2096 Results.push_back(Tmp);
2100 /// Expand the node to a libcall based on the result type.
2101 void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2102 RTLIB::Libcall Call_F32,
2103 RTLIB::Libcall Call_F64,
2104 RTLIB::Libcall Call_F80,
2105 RTLIB::Libcall Call_F128,
2106 RTLIB::Libcall Call_PPCF128,
2107 SmallVectorImpl<SDValue> &Results) {
2108 RTLIB::Libcall LC = RTLIB::getFPLibCall(Node->getSimpleValueType(0),
2109 Call_F32, Call_F64, Call_F80,
2110 Call_F128, Call_PPCF128);
2111 ExpandFPLibCall(Node, LC, Results);
2114 SDValue SelectionDAGLegalize::ExpandIntLibCall(
2115 SDNode *Node, bool isSigned, RTLIB::Libcall Call_I8,
2116 RTLIB::Libcall Call_I16, RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64,
2117 RTLIB::Libcall Call_I128, RTLIB::Libcall Call_IEXT) {
2119 switch (Node->getSimpleValueType(0).SimpleTy) {
2125 case MVT::i8: LC = Call_I8; break;
2126 case MVT::i16: LC = Call_I16; break;
2127 case MVT::i32: LC = Call_I32; break;
2128 case MVT::i64: LC = Call_I64; break;
2129 case MVT::i128: LC = Call_I128; break;
2131 return ExpandLibCall(LC, Node, isSigned);
2134 /// Expand the node to a libcall based on first argument type (for instance
2135 /// lround and its variant).
2136 void SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
2137 RTLIB::Libcall Call_F32,
2138 RTLIB::Libcall Call_F64,
2139 RTLIB::Libcall Call_F80,
2140 RTLIB::Libcall Call_F128,
2141 RTLIB::Libcall Call_PPCF128,
2142 SmallVectorImpl<SDValue> &Results) {
2143 EVT InVT = Node->getOperand(Node->isStrictFPOpcode() ? 1 : 0).getValueType();
2144 RTLIB::Libcall LC = RTLIB::getFPLibCall(InVT.getSimpleVT(),
2145 Call_F32, Call_F64, Call_F80,
2146 Call_F128, Call_PPCF128);
2147 ExpandFPLibCall(Node, LC, Results);
2150 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2152 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2153 SmallVectorImpl<SDValue> &Results) {
2154 unsigned Opcode = Node->getOpcode();
2155 bool isSigned = Opcode == ISD::SDIVREM;
2158 switch (Node->getSimpleValueType(0).SimpleTy) {
2161 LC = isSigned ? RTLIB::SDIVREM_IEXT : RTLIB::UDIVREM_IEXT;
2164 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2165 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2166 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2167 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2168 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2171 // The input chain to this libcall is the entry node of the function.
2172 // Legalizing the call will automatically add the previous call to the
2174 SDValue InChain = DAG.getEntryNode();
2176 EVT RetVT = Node->getValueType(0);
2177 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2179 TargetLowering::ArgListTy Args;
2180 TargetLowering::ArgListEntry Entry;
2181 for (const SDValue &Op : Node->op_values()) {
2182 EVT ArgVT = Op.getValueType();
2183 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2186 Entry.IsSExt = isSigned;
2187 Entry.IsZExt = !isSigned;
2188 Args.push_back(Entry);
2191 // Also pass the return address of the remainder.
2192 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2194 Entry.Ty = RetTy->getPointerTo();
2195 Entry.IsSExt = isSigned;
2196 Entry.IsZExt = !isSigned;
2197 Args.push_back(Entry);
2199 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2200 TLI.getPointerTy(DAG.getDataLayout()));
2203 TargetLowering::CallLoweringInfo CLI(DAG);
2206 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2208 .setSExtResult(isSigned)
2209 .setZExtResult(!isSigned);
2211 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2213 // Remainder is loaded back from the stack frame.
2215 DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, MachinePointerInfo());
2216 Results.push_back(CallInfo.first);
2217 Results.push_back(Rem);
2220 /// Return true if sincos libcall is available.
2221 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2223 switch (Node->getSimpleValueType(0).SimpleTy) {
2224 default: llvm_unreachable("Unexpected request for libcall!");
2225 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2226 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2227 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2228 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2229 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2231 return TLI.getLibcallName(LC) != nullptr;
2234 /// Only issue sincos libcall if both sin and cos are needed.
2235 static bool useSinCos(SDNode *Node) {
2236 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2237 ? ISD::FCOS : ISD::FSIN;
2239 SDValue Op0 = Node->getOperand(0);
2240 for (const SDNode *User : Op0.getNode()->uses()) {
2243 // The other user might have been turned into sincos already.
2244 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2250 /// Issue libcalls to sincos to compute sin / cos pairs.
2252 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2253 SmallVectorImpl<SDValue> &Results) {
2255 switch (Node->getSimpleValueType(0).SimpleTy) {
2256 default: llvm_unreachable("Unexpected request for libcall!");
2257 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2258 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2259 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2260 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2261 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2264 // The input chain to this libcall is the entry node of the function.
2265 // Legalizing the call will automatically add the previous call to the
2267 SDValue InChain = DAG.getEntryNode();
2269 EVT RetVT = Node->getValueType(0);
2270 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2272 TargetLowering::ArgListTy Args;
2273 TargetLowering::ArgListEntry Entry;
2275 // Pass the argument.
2276 Entry.Node = Node->getOperand(0);
2278 Entry.IsSExt = false;
2279 Entry.IsZExt = false;
2280 Args.push_back(Entry);
2282 // Pass the return address of sin.
2283 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2284 Entry.Node = SinPtr;
2285 Entry.Ty = RetTy->getPointerTo();
2286 Entry.IsSExt = false;
2287 Entry.IsZExt = false;
2288 Args.push_back(Entry);
2290 // Also pass the return address of the cos.
2291 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2292 Entry.Node = CosPtr;
2293 Entry.Ty = RetTy->getPointerTo();
2294 Entry.IsSExt = false;
2295 Entry.IsZExt = false;
2296 Args.push_back(Entry);
2298 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2299 TLI.getPointerTy(DAG.getDataLayout()));
2302 TargetLowering::CallLoweringInfo CLI(DAG);
2303 CLI.setDebugLoc(dl).setChain(InChain).setLibCallee(
2304 TLI.getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), Callee,
2307 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2310 DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr, MachinePointerInfo()));
2312 DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr, MachinePointerInfo()));
2315 /// This function is responsible for legalizing a
2316 /// INT_TO_FP operation of the specified operand when the target requests that
2317 /// we expand it. At this point, we know that the result and operand types are
2318 /// legal for the target.
2319 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(SDNode *Node,
2321 bool isSigned = (Node->getOpcode() == ISD::STRICT_SINT_TO_FP ||
2322 Node->getOpcode() == ISD::SINT_TO_FP);
2323 EVT DestVT = Node->getValueType(0);
2325 unsigned OpNo = Node->isStrictFPOpcode() ? 1 : 0;
2326 SDValue Op0 = Node->getOperand(OpNo);
2327 EVT SrcVT = Op0.getValueType();
2329 // TODO: Should any fast-math-flags be set for the created nodes?
2330 LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n");
2331 if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64) &&
2332 (DestVT.bitsLE(MVT::f64) ||
2333 TLI.isOperationLegal(Node->isStrictFPOpcode() ? ISD::STRICT_FP_EXTEND
2336 LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double "
2339 // Get the stack frame index of a 8 byte buffer.
2340 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2343 // if signed map to unsigned space
2345 // Invert sign bit (signed to unsigned mapping).
2346 Lo = DAG.getNode(ISD::XOR, dl, MVT::i32, Lo,
2347 DAG.getConstant(0x80000000u, dl, MVT::i32));
2349 // Initial hi portion of constructed double.
2350 SDValue Hi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2352 // If this a big endian target, swap the lo and high data.
2353 if (DAG.getDataLayout().isBigEndian())
2356 SDValue MemChain = DAG.getEntryNode();
2358 // Store the lo of the constructed double.
2359 SDValue Store1 = DAG.getStore(MemChain, dl, Lo, StackSlot,
2360 MachinePointerInfo());
2361 // Store the hi of the constructed double.
2362 SDValue HiPtr = DAG.getMemBasePlusOffset(StackSlot, TypeSize::Fixed(4), dl);
2364 DAG.getStore(MemChain, dl, Hi, HiPtr, MachinePointerInfo());
2365 MemChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
2367 // load the constructed double
2369 DAG.getLoad(MVT::f64, dl, MemChain, StackSlot, MachinePointerInfo());
2370 // FP constant to bias correct the final result
2371 SDValue Bias = DAG.getConstantFP(isSigned ?
2372 BitsToDouble(0x4330000080000000ULL) :
2373 BitsToDouble(0x4330000000000000ULL),
2375 // Subtract the bias and get the final result.
2378 if (Node->isStrictFPOpcode()) {
2379 Sub = DAG.getNode(ISD::STRICT_FSUB, dl, {MVT::f64, MVT::Other},
2380 {Node->getOperand(0), Load, Bias});
2381 Chain = Sub.getValue(1);
2382 if (DestVT != Sub.getValueType()) {
2383 std::pair<SDValue, SDValue> ResultPair;
2385 DAG.getStrictFPExtendOrRound(Sub, Chain, dl, DestVT);
2386 Result = ResultPair.first;
2387 Chain = ResultPair.second;
2392 Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2393 Result = DAG.getFPExtendOrRound(Sub, dl, DestVT);
2401 // TODO: Generalize this for use with other types.
2402 if (((SrcVT == MVT::i32 || SrcVT == MVT::i64) && DestVT == MVT::f32) ||
2403 (SrcVT == MVT::i64 && DestVT == MVT::f64)) {
2404 LLVM_DEBUG(dbgs() << "Converting unsigned i32/i64 to f32/f64\n");
2405 // For unsigned conversions, convert them to signed conversions using the
2406 // algorithm from the x86_64 __floatundisf in compiler_rt. That method
2407 // should be valid for i32->f32 as well.
2409 // More generally this transform should be valid if there are 3 more bits
2410 // in the integer type than the significand. Rounding uses the first bit
2411 // after the width of the significand and the OR of all bits after that. So
2412 // we need to be able to OR the shifted out bit into one of the bits that
2413 // participate in the OR.
2415 // TODO: This really should be implemented using a branch rather than a
2416 // select. We happen to get lucky and machinesink does the right
2417 // thing most of the time. This would be a good candidate for a
2418 // pseudo-op, or, even better, for whole-function isel.
2419 EVT SetCCVT = getSetCCResultType(SrcVT);
2421 SDValue SignBitTest = DAG.getSetCC(
2422 dl, SetCCVT, Op0, DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2424 EVT ShiftVT = TLI.getShiftAmountTy(SrcVT, DAG.getDataLayout());
2425 SDValue ShiftConst = DAG.getConstant(1, dl, ShiftVT);
2426 SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst);
2427 SDValue AndConst = DAG.getConstant(1, dl, SrcVT);
2428 SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Op0, AndConst);
2429 SDValue Or = DAG.getNode(ISD::OR, dl, SrcVT, And, Shr);
2432 if (Node->isStrictFPOpcode()) {
2433 // In strict mode, we must avoid spurious exceptions, and therefore
2434 // must make sure to only emit a single STRICT_SINT_TO_FP.
2435 SDValue InCvt = DAG.getSelect(dl, SrcVT, SignBitTest, Or, Op0);
2436 Fast = DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, { DestVT, MVT::Other },
2437 { Node->getOperand(0), InCvt });
2438 Slow = DAG.getNode(ISD::STRICT_FADD, dl, { DestVT, MVT::Other },
2439 { Fast.getValue(1), Fast, Fast });
2440 Chain = Slow.getValue(1);
2441 // The STRICT_SINT_TO_FP inherits the exception mode from the
2442 // incoming STRICT_UINT_TO_FP node; the STRICT_FADD node can
2443 // never raise any exception.
2445 Flags.setNoFPExcept(Node->getFlags().hasNoFPExcept());
2446 Fast->setFlags(Flags);
2447 Flags.setNoFPExcept(true);
2448 Slow->setFlags(Flags);
2450 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Or);
2451 Slow = DAG.getNode(ISD::FADD, dl, DestVT, SignCvt, SignCvt);
2452 Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2455 return DAG.getSelect(dl, DestVT, SignBitTest, Slow, Fast);
2458 // Don't expand it if there isn't cheap fadd.
2459 if (!TLI.isOperationLegalOrCustom(
2460 Node->isStrictFPOpcode() ? ISD::STRICT_FADD : ISD::FADD, DestVT))
2463 // The following optimization is valid only if every value in SrcVT (when
2464 // treated as signed) is representable in DestVT. Check that the mantissa
2465 // size of DestVT is >= than the number of bits in SrcVT -1.
2466 assert(APFloat::semanticsPrecision(DAG.EVTToAPFloatSemantics(DestVT)) >=
2467 SrcVT.getSizeInBits() - 1 &&
2468 "Cannot perform lossless SINT_TO_FP!");
2471 if (Node->isStrictFPOpcode()) {
2472 Tmp1 = DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, { DestVT, MVT::Other },
2473 { Node->getOperand(0), Op0 });
2475 Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2477 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
2478 DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2479 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2480 Four = DAG.getIntPtrConstant(4, dl);
2481 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2482 SignSet, Four, Zero);
2484 // If the sign bit of the integer is set, the large number will be treated
2485 // as a negative number. To counteract this, the dynamic code adds an
2486 // offset depending on the data type.
2488 switch (SrcVT.getSimpleVT().SimpleTy) {
2491 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2492 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2493 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2494 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2496 if (DAG.getDataLayout().isLittleEndian())
2498 Constant *FudgeFactor = ConstantInt::get(
2499 Type::getInt64Ty(*DAG.getContext()), FF);
2502 DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2503 Align Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlign();
2504 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2505 Alignment = commonAlignment(Alignment, 4);
2507 if (DestVT == MVT::f32)
2508 FudgeInReg = DAG.getLoad(
2509 MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2510 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2513 SDValue Load = DAG.getExtLoad(
2514 ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2515 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2517 HandleSDNode Handle(Load);
2518 LegalizeOp(Load.getNode());
2519 FudgeInReg = Handle.getValue();
2522 if (Node->isStrictFPOpcode()) {
2523 SDValue Result = DAG.getNode(ISD::STRICT_FADD, dl, { DestVT, MVT::Other },
2524 { Tmp1.getValue(1), Tmp1, FudgeInReg });
2525 Chain = Result.getValue(1);
2529 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2532 /// This function is responsible for legalizing a
2533 /// *INT_TO_FP operation of the specified operand when the target requests that
2534 /// we promote it. At this point, we know that the result and operand types are
2535 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2536 /// operation that takes a larger input.
2537 void SelectionDAGLegalize::PromoteLegalINT_TO_FP(
2538 SDNode *N, const SDLoc &dl, SmallVectorImpl<SDValue> &Results) {
2539 bool IsStrict = N->isStrictFPOpcode();
2540 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
2541 N->getOpcode() == ISD::STRICT_SINT_TO_FP;
2542 EVT DestVT = N->getValueType(0);
2543 SDValue LegalOp = N->getOperand(IsStrict ? 1 : 0);
2544 unsigned UIntOp = IsStrict ? ISD::STRICT_UINT_TO_FP : ISD::UINT_TO_FP;
2545 unsigned SIntOp = IsStrict ? ISD::STRICT_SINT_TO_FP : ISD::SINT_TO_FP;
2547 // First step, figure out the appropriate *INT_TO_FP operation to use.
2548 EVT NewInTy = LegalOp.getValueType();
2550 unsigned OpToUse = 0;
2552 // Scan for the appropriate larger type to use.
2554 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2555 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2557 // If the target supports SINT_TO_FP of this type, use it.
2558 if (TLI.isOperationLegalOrCustom(SIntOp, NewInTy)) {
2565 // If the target supports UINT_TO_FP of this type, use it.
2566 if (TLI.isOperationLegalOrCustom(UIntOp, NewInTy)) {
2571 // Otherwise, try a larger type.
2574 // Okay, we found the operation and type to use. Zero extend our input to the
2575 // desired type then run the operation on it.
2578 DAG.getNode(OpToUse, dl, {DestVT, MVT::Other},
2580 DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2581 dl, NewInTy, LegalOp)});
2582 Results.push_back(Res);
2583 Results.push_back(Res.getValue(1));
2588 DAG.getNode(OpToUse, dl, DestVT,
2589 DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2590 dl, NewInTy, LegalOp)));
2593 /// This function is responsible for legalizing a
2594 /// FP_TO_*INT operation of the specified operand when the target requests that
2595 /// we promote it. At this point, we know that the result and operand types are
2596 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2597 /// operation that returns a larger result.
2598 void SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDNode *N, const SDLoc &dl,
2599 SmallVectorImpl<SDValue> &Results) {
2600 bool IsStrict = N->isStrictFPOpcode();
2601 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
2602 N->getOpcode() == ISD::STRICT_FP_TO_SINT;
2603 EVT DestVT = N->getValueType(0);
2604 SDValue LegalOp = N->getOperand(IsStrict ? 1 : 0);
2605 // First step, figure out the appropriate FP_TO*INT operation to use.
2606 EVT NewOutTy = DestVT;
2608 unsigned OpToUse = 0;
2610 // Scan for the appropriate larger type to use.
2612 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2613 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2615 // A larger signed type can hold all unsigned values of the requested type,
2616 // so using FP_TO_SINT is valid
2617 OpToUse = IsStrict ? ISD::STRICT_FP_TO_SINT : ISD::FP_TO_SINT;
2618 if (TLI.isOperationLegalOrCustom(OpToUse, NewOutTy))
2621 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2622 OpToUse = IsStrict ? ISD::STRICT_FP_TO_UINT : ISD::FP_TO_UINT;
2623 if (!IsSigned && TLI.isOperationLegalOrCustom(OpToUse, NewOutTy))
2626 // Otherwise, try a larger type.
2629 // Okay, we found the operation and type to use.
2632 SDVTList VTs = DAG.getVTList(NewOutTy, MVT::Other);
2633 Operation = DAG.getNode(OpToUse, dl, VTs, N->getOperand(0), LegalOp);
2635 Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2637 // Truncate the result of the extended FP_TO_*INT operation to the desired
2639 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2640 Results.push_back(Trunc);
2642 Results.push_back(Operation.getValue(1));
2645 /// Promote FP_TO_*INT_SAT operation to a larger result type. At this point
2646 /// the result and operand types are legal and there must be a legal
2647 /// FP_TO_*INT_SAT operation for a larger result type.
2648 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT_SAT(SDNode *Node,
2650 unsigned Opcode = Node->getOpcode();
2652 // Scan for the appropriate larger type to use.
2653 EVT NewOutTy = Node->getValueType(0);
2655 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy + 1);
2656 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2658 if (TLI.isOperationLegalOrCustom(Opcode, NewOutTy))
2662 // Saturation width is determined by second operand, so we don't have to
2663 // perform any fixup and can directly truncate the result.
2664 SDValue Result = DAG.getNode(Opcode, dl, NewOutTy, Node->getOperand(0),
2665 Node->getOperand(1));
2666 return DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
2669 /// Open code the operations for PARITY of the specified operation.
2670 SDValue SelectionDAGLegalize::ExpandPARITY(SDValue Op, const SDLoc &dl) {
2671 EVT VT = Op.getValueType();
2672 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2673 unsigned Sz = VT.getScalarSizeInBits();
2675 // If CTPOP is legal, use it. Otherwise use shifts and xor.
2677 if (TLI.isOperationLegalOrPromote(ISD::CTPOP, VT)) {
2678 Result = DAG.getNode(ISD::CTPOP, dl, VT, Op);
2681 for (unsigned i = Log2_32_Ceil(Sz); i != 0;) {
2682 SDValue Shift = DAG.getNode(ISD::SRL, dl, VT, Result,
2683 DAG.getConstant(1ULL << (--i), dl, ShVT));
2684 Result = DAG.getNode(ISD::XOR, dl, VT, Result, Shift);
2688 return DAG.getNode(ISD::AND, dl, VT, Result, DAG.getConstant(1, dl, VT));
2691 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2692 LLVM_DEBUG(dbgs() << "Trying to expand node\n");
2693 SmallVector<SDValue, 8> Results;
2695 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2697 switch (Node->getOpcode()) {
2699 if ((Tmp1 = TLI.expandABS(Node, DAG)))
2700 Results.push_back(Tmp1);
2703 if ((Tmp1 = TLI.expandCTPOP(Node, DAG)))
2704 Results.push_back(Tmp1);
2707 case ISD::CTLZ_ZERO_UNDEF:
2708 if ((Tmp1 = TLI.expandCTLZ(Node, DAG)))
2709 Results.push_back(Tmp1);
2712 case ISD::CTTZ_ZERO_UNDEF:
2713 if ((Tmp1 = TLI.expandCTTZ(Node, DAG)))
2714 Results.push_back(Tmp1);
2716 case ISD::BITREVERSE:
2717 if ((Tmp1 = TLI.expandBITREVERSE(Node, DAG)))
2718 Results.push_back(Tmp1);
2721 if ((Tmp1 = TLI.expandBSWAP(Node, DAG)))
2722 Results.push_back(Tmp1);
2725 Results.push_back(ExpandPARITY(Node->getOperand(0), dl));
2727 case ISD::FRAMEADDR:
2728 case ISD::RETURNADDR:
2729 case ISD::FRAME_TO_ARGS_OFFSET:
2730 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2732 case ISD::EH_DWARF_CFA: {
2733 SDValue CfaArg = DAG.getSExtOrTrunc(Node->getOperand(0), dl,
2734 TLI.getPointerTy(DAG.getDataLayout()));
2735 SDValue Offset = DAG.getNode(ISD::ADD, dl,
2736 CfaArg.getValueType(),
2737 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
2738 CfaArg.getValueType()),
2740 SDValue FA = DAG.getNode(
2741 ISD::FRAMEADDR, dl, TLI.getPointerTy(DAG.getDataLayout()),
2742 DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())));
2743 Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(),
2747 case ISD::FLT_ROUNDS_:
2748 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2749 Results.push_back(Node->getOperand(0));
2751 case ISD::EH_RETURN:
2755 case ISD::EH_SJLJ_LONGJMP:
2756 // If the target didn't expand these, there's nothing to do, so just
2757 // preserve the chain and be done.
2758 Results.push_back(Node->getOperand(0));
2760 case ISD::READCYCLECOUNTER:
2761 // If the target didn't expand this, just return 'zero' and preserve the
2763 Results.append(Node->getNumValues() - 1,
2764 DAG.getConstant(0, dl, Node->getValueType(0)));
2765 Results.push_back(Node->getOperand(0));
2767 case ISD::EH_SJLJ_SETJMP:
2768 // If the target didn't expand this, just return 'zero' and preserve the
2770 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2771 Results.push_back(Node->getOperand(0));
2773 case ISD::ATOMIC_LOAD: {
2774 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2775 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2776 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2777 SDValue Swap = DAG.getAtomicCmpSwap(
2778 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2779 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2780 cast<AtomicSDNode>(Node)->getMemOperand());
2781 Results.push_back(Swap.getValue(0));
2782 Results.push_back(Swap.getValue(1));
2785 case ISD::ATOMIC_STORE: {
2786 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2787 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2788 cast<AtomicSDNode>(Node)->getMemoryVT(),
2789 Node->getOperand(0),
2790 Node->getOperand(1), Node->getOperand(2),
2791 cast<AtomicSDNode>(Node)->getMemOperand());
2792 Results.push_back(Swap.getValue(1));
2795 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2796 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2797 // splits out the success value as a comparison. Expanding the resulting
2798 // ATOMIC_CMP_SWAP will produce a libcall.
2799 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2800 SDValue Res = DAG.getAtomicCmpSwap(
2801 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2802 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2803 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand());
2805 SDValue ExtRes = Res;
2807 SDValue RHS = Node->getOperand(1);
2809 EVT AtomicType = cast<AtomicSDNode>(Node)->getMemoryVT();
2810 EVT OuterType = Node->getValueType(0);
2811 switch (TLI.getExtendForAtomicOps()) {
2812 case ISD::SIGN_EXTEND:
2813 LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
2814 DAG.getValueType(AtomicType));
2815 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType,
2816 Node->getOperand(2), DAG.getValueType(AtomicType));
2819 case ISD::ZERO_EXTEND:
2820 LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
2821 DAG.getValueType(AtomicType));
2822 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2825 case ISD::ANY_EXTEND:
2826 LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType);
2827 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2830 llvm_unreachable("Invalid atomic op extension");
2834 DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
2836 Results.push_back(ExtRes.getValue(0));
2837 Results.push_back(Success);
2838 Results.push_back(Res.getValue(1));
2841 case ISD::DYNAMIC_STACKALLOC:
2842 ExpandDYNAMIC_STACKALLOC(Node, Results);
2844 case ISD::MERGE_VALUES:
2845 for (unsigned i = 0; i < Node->getNumValues(); i++)
2846 Results.push_back(Node->getOperand(i));
2849 EVT VT = Node->getValueType(0);
2851 Results.push_back(DAG.getConstant(0, dl, VT));
2853 assert(VT.isFloatingPoint() && "Unknown value type!");
2854 Results.push_back(DAG.getConstantFP(0, dl, VT));
2858 case ISD::STRICT_FP_ROUND:
2859 // When strict mode is enforced we can't do expansion because it
2860 // does not honor the "strict" properties. Only libcall is allowed.
2861 if (TLI.isStrictFPEnabled())
2863 // We might as well mutate to FP_ROUND when FP_ROUND operation is legal
2864 // since this operation is more efficient than stack operation.
2865 if (TLI.getStrictFPOperationAction(Node->getOpcode(),
2866 Node->getValueType(0))
2867 == TargetLowering::Legal)
2869 // We fall back to use stack operation when the FP_ROUND operation
2871 if ((Tmp1 = EmitStackConvert(Node->getOperand(1), Node->getValueType(0),
2872 Node->getValueType(0), dl,
2873 Node->getOperand(0)))) {
2874 ReplaceNode(Node, Tmp1.getNode());
2875 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_ROUND node\n");
2881 if ((Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2882 Node->getValueType(0), dl)))
2883 Results.push_back(Tmp1);
2885 case ISD::STRICT_FP_EXTEND:
2886 // When strict mode is enforced we can't do expansion because it
2887 // does not honor the "strict" properties. Only libcall is allowed.
2888 if (TLI.isStrictFPEnabled())
2890 // We might as well mutate to FP_EXTEND when FP_EXTEND operation is legal
2891 // since this operation is more efficient than stack operation.
2892 if (TLI.getStrictFPOperationAction(Node->getOpcode(),
2893 Node->getValueType(0))
2894 == TargetLowering::Legal)
2896 // We fall back to use stack operation when the FP_EXTEND operation
2898 if ((Tmp1 = EmitStackConvert(
2899 Node->getOperand(1), Node->getOperand(1).getValueType(),
2900 Node->getValueType(0), dl, Node->getOperand(0)))) {
2901 ReplaceNode(Node, Tmp1.getNode());
2902 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_EXTEND node\n");
2906 case ISD::FP_EXTEND:
2907 if ((Tmp1 = EmitStackConvert(Node->getOperand(0),
2908 Node->getOperand(0).getValueType(),
2909 Node->getValueType(0), dl)))
2910 Results.push_back(Tmp1);
2912 case ISD::BF16_TO_FP: {
2913 // Always expand bf16 to f32 casts, they lower to ext + shift.
2914 SDValue Op = DAG.getNode(ISD::BITCAST, dl, MVT::i16, Node->getOperand(0));
2915 Op = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op);
2917 ISD::SHL, dl, MVT::i32, Op,
2918 DAG.getConstant(16, dl,
2919 TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout())));
2920 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op);
2921 Results.push_back(Op);
2924 case ISD::SIGN_EXTEND_INREG: {
2925 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2926 EVT VT = Node->getValueType(0);
2928 // An in-register sign-extend of a boolean is a negation:
2929 // 'true' (1) sign-extended is -1.
2930 // 'false' (0) sign-extended is 0.
2931 // However, we must mask the high bits of the source operand because the
2932 // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
2934 // TODO: Do this for vectors too?
2935 if (ExtraVT.isScalarInteger() && ExtraVT.getSizeInBits() == 1) {
2936 SDValue One = DAG.getConstant(1, dl, VT);
2937 SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
2938 SDValue Zero = DAG.getConstant(0, dl, VT);
2939 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
2940 Results.push_back(Neg);
2944 // NOTE: we could fall back on load/store here too for targets without
2945 // SRA. However, it is doubtful that any exist.
2946 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2947 unsigned BitsDiff = VT.getScalarSizeInBits() -
2948 ExtraVT.getScalarSizeInBits();
2949 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
2950 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2951 Node->getOperand(0), ShiftCst);
2952 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2953 Results.push_back(Tmp1);
2956 case ISD::UINT_TO_FP:
2957 case ISD::STRICT_UINT_TO_FP:
2958 if (TLI.expandUINT_TO_FP(Node, Tmp1, Tmp2, DAG)) {
2959 Results.push_back(Tmp1);
2960 if (Node->isStrictFPOpcode())
2961 Results.push_back(Tmp2);
2965 case ISD::SINT_TO_FP:
2966 case ISD::STRICT_SINT_TO_FP:
2967 if ((Tmp1 = ExpandLegalINT_TO_FP(Node, Tmp2))) {
2968 Results.push_back(Tmp1);
2969 if (Node->isStrictFPOpcode())
2970 Results.push_back(Tmp2);
2973 case ISD::FP_TO_SINT:
2974 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
2975 Results.push_back(Tmp1);
2977 case ISD::STRICT_FP_TO_SINT:
2978 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG)) {
2979 ReplaceNode(Node, Tmp1.getNode());
2980 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_TO_SINT node\n");
2984 case ISD::FP_TO_UINT:
2985 if (TLI.expandFP_TO_UINT(Node, Tmp1, Tmp2, DAG))
2986 Results.push_back(Tmp1);
2988 case ISD::STRICT_FP_TO_UINT:
2989 if (TLI.expandFP_TO_UINT(Node, Tmp1, Tmp2, DAG)) {
2990 // Relink the chain.
2991 DAG.ReplaceAllUsesOfValueWith(SDValue(Node,1), Tmp2);
2992 // Replace the new UINT result.
2993 ReplaceNodeWithValue(SDValue(Node, 0), Tmp1);
2994 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_TO_UINT node\n");
2998 case ISD::FP_TO_SINT_SAT:
2999 case ISD::FP_TO_UINT_SAT:
3000 Results.push_back(TLI.expandFP_TO_INT_SAT(Node, DAG));
3003 Results.push_back(DAG.expandVAArg(Node));
3004 Results.push_back(Results[0].getValue(1));
3007 Results.push_back(DAG.expandVACopy(Node));
3009 case ISD::EXTRACT_VECTOR_ELT:
3010 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3011 // This must be an access of the only element. Return it.
3012 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3013 Node->getOperand(0));
3015 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3016 Results.push_back(Tmp1);
3018 case ISD::EXTRACT_SUBVECTOR:
3019 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3021 case ISD::INSERT_SUBVECTOR:
3022 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3024 case ISD::CONCAT_VECTORS:
3025 Results.push_back(ExpandVectorBuildThroughStack(Node));
3027 case ISD::SCALAR_TO_VECTOR:
3028 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3030 case ISD::INSERT_VECTOR_ELT:
3031 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3032 Node->getOperand(1),
3033 Node->getOperand(2), dl));
3035 case ISD::VECTOR_SHUFFLE: {
3036 SmallVector<int, 32> NewMask;
3037 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3039 EVT VT = Node->getValueType(0);
3040 EVT EltVT = VT.getVectorElementType();
3041 SDValue Op0 = Node->getOperand(0);
3042 SDValue Op1 = Node->getOperand(1);
3043 if (!TLI.isTypeLegal(EltVT)) {
3044 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3046 // BUILD_VECTOR operands are allowed to be wider than the element type.
3047 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3049 if (NewEltVT.bitsLT(EltVT)) {
3050 // Convert shuffle node.
3051 // If original node was v4i64 and the new EltVT is i32,
3052 // cast operands to v8i32 and re-build the mask.
3054 // Calculate new VT, the size of the new VT should be equal to original.
3056 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3057 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3058 assert(NewVT.bitsEq(VT));
3060 // cast operands to new VT
3061 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3062 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3064 // Convert the shuffle mask
3065 unsigned int factor =
3066 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3068 // EltVT gets smaller
3071 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3073 for (unsigned fi = 0; fi < factor; ++fi)
3074 NewMask.push_back(Mask[i]);
3077 for (unsigned fi = 0; fi < factor; ++fi)
3078 NewMask.push_back(Mask[i]*factor+fi);
3086 unsigned NumElems = VT.getVectorNumElements();
3087 SmallVector<SDValue, 16> Ops;
3088 for (unsigned i = 0; i != NumElems; ++i) {
3090 Ops.push_back(DAG.getUNDEF(EltVT));
3093 unsigned Idx = Mask[i];
3095 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3096 DAG.getVectorIdxConstant(Idx, dl)));
3099 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3100 DAG.getVectorIdxConstant(Idx - NumElems, dl)));
3103 Tmp1 = DAG.getBuildVector(VT, dl, Ops);
3104 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3105 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3106 Results.push_back(Tmp1);
3109 case ISD::VECTOR_SPLICE: {
3110 Results.push_back(TLI.expandVectorSplice(Node, DAG));
3113 case ISD::EXTRACT_ELEMENT: {
3114 EVT OpTy = Node->getOperand(0).getValueType();
3115 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3117 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3118 DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3119 TLI.getShiftAmountTy(
3120 Node->getOperand(0).getValueType(),
3121 DAG.getDataLayout())));
3122 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3125 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3126 Node->getOperand(0));
3128 Results.push_back(Tmp1);
3131 case ISD::STACKSAVE:
3132 // Expand to CopyFromReg if the target set
3133 // StackPointerRegisterToSaveRestore.
3134 if (Register SP = TLI.getStackPointerRegisterToSaveRestore()) {
3135 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3136 Node->getValueType(0)));
3137 Results.push_back(Results[0].getValue(1));
3139 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3140 Results.push_back(Node->getOperand(0));
3143 case ISD::STACKRESTORE:
3144 // Expand to CopyToReg if the target set
3145 // StackPointerRegisterToSaveRestore.
3146 if (Register SP = TLI.getStackPointerRegisterToSaveRestore()) {
3147 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3148 Node->getOperand(1)));
3150 Results.push_back(Node->getOperand(0));
3153 case ISD::GET_DYNAMIC_AREA_OFFSET:
3154 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3155 Results.push_back(Results[0].getValue(0));
3157 case ISD::FCOPYSIGN:
3158 Results.push_back(ExpandFCOPYSIGN(Node));
3161 Results.push_back(ExpandFNEG(Node));
3164 Results.push_back(ExpandFABS(Node));
3166 case ISD::IS_FPCLASS: {
3167 auto CNode = cast<ConstantSDNode>(Node->getOperand(1));
3168 auto Test = static_cast<FPClassTest>(CNode->getZExtValue());
3169 if (SDValue Expanded =
3170 TLI.expandIS_FPCLASS(Node->getValueType(0), Node->getOperand(0),
3171 Test, Node->getFlags(), SDLoc(Node), DAG))
3172 Results.push_back(Expanded);
3179 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3181 switch (Node->getOpcode()) {
3182 default: llvm_unreachable("How did we get here?");
3183 case ISD::SMAX: Pred = ISD::SETGT; break;
3184 case ISD::SMIN: Pred = ISD::SETLT; break;
3185 case ISD::UMAX: Pred = ISD::SETUGT; break;
3186 case ISD::UMIN: Pred = ISD::SETULT; break;
3188 Tmp1 = Node->getOperand(0);
3189 Tmp2 = Node->getOperand(1);
3190 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3191 Results.push_back(Tmp1);
3195 case ISD::FMAXNUM: {
3196 if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Node, DAG))
3197 Results.push_back(Expanded);
3202 EVT VT = Node->getValueType(0);
3203 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3204 // fcos which share the same operand and both are used.
3205 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3206 isSinCosLibcallAvailable(Node, TLI))
3207 && useSinCos(Node)) {
3208 SDVTList VTs = DAG.getVTList(VT, VT);
3209 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3210 if (Node->getOpcode() == ISD::FCOS)
3211 Tmp1 = Tmp1.getValue(1);
3212 Results.push_back(Tmp1);
3217 llvm_unreachable("Illegal fmad should never be formed");
3219 case ISD::FP16_TO_FP:
3220 if (Node->getValueType(0) != MVT::f32) {
3221 // We can extend to types bigger than f32 in two steps without changing
3222 // the result. Since "f16 -> f32" is much more commonly available, give
3223 // CodeGen the option of emitting that before resorting to a libcall.
3225 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3227 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3230 case ISD::STRICT_FP16_TO_FP:
3231 if (Node->getValueType(0) != MVT::f32) {
3232 // We can extend to types bigger than f32 in two steps without changing
3233 // the result. Since "f16 -> f32" is much more commonly available, give
3234 // CodeGen the option of emitting that before resorting to a libcall.
3236 DAG.getNode(ISD::STRICT_FP16_TO_FP, dl, {MVT::f32, MVT::Other},
3237 {Node->getOperand(0), Node->getOperand(1)});
3238 Res = DAG.getNode(ISD::STRICT_FP_EXTEND, dl,
3239 {Node->getValueType(0), MVT::Other},
3240 {Res.getValue(1), Res});
3241 Results.push_back(Res);
3242 Results.push_back(Res.getValue(1));
3245 case ISD::FP_TO_FP16:
3246 LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
3247 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3248 SDValue Op = Node->getOperand(0);
3249 MVT SVT = Op.getSimpleValueType();
3250 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3251 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3252 // Under fastmath, we can expand this node into a fround followed by
3253 // a float-half conversion.
3254 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3255 DAG.getIntPtrConstant(0, dl));
3257 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal));
3261 case ISD::ConstantFP: {
3262 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3263 // Check to see if this FP immediate is already legal.
3264 // If this is a legal constant, turn it into a TargetConstantFP node.
3265 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0),
3266 DAG.shouldOptForSize()))
3267 Results.push_back(ExpandConstantFP(CFP, true));
3270 case ISD::Constant: {
3271 ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3272 Results.push_back(ExpandConstant(CP));
3276 EVT VT = Node->getValueType(0);
3277 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3278 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3279 const SDNodeFlags Flags = Node->getFlags();
3280 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3281 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3282 Results.push_back(Tmp1);
3287 EVT VT = Node->getValueType(0);
3288 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3289 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3290 "Don't know how to expand this subtraction!");
3291 Tmp1 = DAG.getNOT(dl, Node->getOperand(1), VT);
3292 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3293 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3298 if (TLI.expandREM(Node, Tmp1, DAG))
3299 Results.push_back(Tmp1);
3303 bool isSigned = Node->getOpcode() == ISD::SDIV;
3304 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3305 EVT VT = Node->getValueType(0);
3306 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3307 SDVTList VTs = DAG.getVTList(VT, VT);
3308 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3309 Node->getOperand(1));
3310 Results.push_back(Tmp1);
3316 unsigned ExpandOpcode =
3317 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3318 EVT VT = Node->getValueType(0);
3319 SDVTList VTs = DAG.getVTList(VT, VT);
3321 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3322 Node->getOperand(1));
3323 Results.push_back(Tmp1.getValue(1));
3326 case ISD::UMUL_LOHI:
3327 case ISD::SMUL_LOHI: {
3328 SDValue LHS = Node->getOperand(0);
3329 SDValue RHS = Node->getOperand(1);
3330 MVT VT = LHS.getSimpleValueType();
3331 unsigned MULHOpcode =
3332 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3334 if (TLI.isOperationLegalOrCustom(MULHOpcode, VT)) {
3335 Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3336 Results.push_back(DAG.getNode(MULHOpcode, dl, VT, LHS, RHS));
3340 SmallVector<SDValue, 4> Halves;
3341 EVT HalfType = EVT(VT).getHalfSizedIntegerVT(*DAG.getContext());
3342 assert(TLI.isTypeLegal(HalfType));
3343 if (TLI.expandMUL_LOHI(Node->getOpcode(), VT, dl, LHS, RHS, Halves,
3345 TargetLowering::MulExpansionKind::Always)) {
3346 for (unsigned i = 0; i < 2; ++i) {
3347 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3348 SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3349 SDValue Shift = DAG.getConstant(
3350 HalfType.getScalarSizeInBits(), dl,
3351 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3352 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3353 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3360 EVT VT = Node->getValueType(0);
3361 SDVTList VTs = DAG.getVTList(VT, VT);
3362 // See if multiply or divide can be lowered using two-result operations.
3363 // We just need the low half of the multiply; try both the signed
3364 // and unsigned forms. If the target supports both SMUL_LOHI and
3365 // UMUL_LOHI, form a preference by checking which forms of plain
3366 // MULH it supports.
3367 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3368 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3369 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3370 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3371 unsigned OpToUse = 0;
3372 if (HasSMUL_LOHI && !HasMULHS) {
3373 OpToUse = ISD::SMUL_LOHI;
3374 } else if (HasUMUL_LOHI && !HasMULHU) {
3375 OpToUse = ISD::UMUL_LOHI;
3376 } else if (HasSMUL_LOHI) {
3377 OpToUse = ISD::SMUL_LOHI;
3378 } else if (HasUMUL_LOHI) {
3379 OpToUse = ISD::UMUL_LOHI;
3382 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3383 Node->getOperand(1)));
3388 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3389 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3390 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3391 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3392 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3393 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG,
3394 TargetLowering::MulExpansionKind::OnlyLegalOrCustom)) {
3395 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3396 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3398 DAG.getConstant(HalfType.getSizeInBits(), dl,
3399 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3400 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3401 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3407 if (SDValue Expanded = TLI.expandFunnelShift(Node, DAG))
3408 Results.push_back(Expanded);
3412 if (SDValue Expanded = TLI.expandROT(Node, true /*AllowVectorOps*/, DAG))
3413 Results.push_back(Expanded);
3419 Results.push_back(TLI.expandAddSubSat(Node, DAG));
3423 Results.push_back(TLI.expandShlSat(Node, DAG));
3426 case ISD::SMULFIXSAT:
3428 case ISD::UMULFIXSAT:
3429 Results.push_back(TLI.expandFixedPointMul(Node, DAG));
3432 case ISD::SDIVFIXSAT:
3434 case ISD::UDIVFIXSAT:
3435 if (SDValue V = TLI.expandFixedPointDiv(Node->getOpcode(), SDLoc(Node),
3436 Node->getOperand(0),
3437 Node->getOperand(1),
3438 Node->getConstantOperandVal(2),
3440 Results.push_back(V);
3443 // FIXME: We might want to retry here with a wider type if we fail, if that
3445 // FIXME: Technically, so long as we only have sdivfixes where BW+Scale is
3446 // <= 128 (which is the case for all of the default Embedded-C types),
3447 // we will only get here with types and scales that we could always expand
3448 // if we were allowed to generate libcalls to division functions of illegal
3449 // type. But we cannot do that.
3450 llvm_unreachable("Cannot expand DIVFIX!");
3452 case ISD::SUBCARRY: {
3453 SDValue LHS = Node->getOperand(0);
3454 SDValue RHS = Node->getOperand(1);
3455 SDValue Carry = Node->getOperand(2);
3457 bool IsAdd = Node->getOpcode() == ISD::ADDCARRY;
3459 // Initial add of the 2 operands.
3460 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
3461 EVT VT = LHS.getValueType();
3462 SDValue Sum = DAG.getNode(Op, dl, VT, LHS, RHS);
3464 // Initial check for overflow.
3465 EVT CarryType = Node->getValueType(1);
3466 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3467 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
3468 SDValue Overflow = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3470 // Add of the sum and the carry.
3471 SDValue One = DAG.getConstant(1, dl, VT);
3473 DAG.getNode(ISD::AND, dl, VT, DAG.getZExtOrTrunc(Carry, dl, VT), One);
3474 SDValue Sum2 = DAG.getNode(Op, dl, VT, Sum, CarryExt);
3476 // Second check for overflow. If we are adding, we can only overflow if the
3477 // initial sum is all 1s ang the carry is set, resulting in a new sum of 0.
3478 // If we are subtracting, we can only overflow if the initial sum is 0 and
3479 // the carry is set, resulting in a new sum of all 1s.
3480 SDValue Zero = DAG.getConstant(0, dl, VT);
3482 IsAdd ? DAG.getSetCC(dl, SetCCType, Sum2, Zero, ISD::SETEQ)
3483 : DAG.getSetCC(dl, SetCCType, Sum, Zero, ISD::SETEQ);
3484 Overflow2 = DAG.getNode(ISD::AND, dl, SetCCType, Overflow2,
3485 DAG.getZExtOrTrunc(Carry, dl, SetCCType));
3487 SDValue ResultCarry =
3488 DAG.getNode(ISD::OR, dl, SetCCType, Overflow, Overflow2);
3490 Results.push_back(Sum2);
3491 Results.push_back(DAG.getBoolExtOrTrunc(ResultCarry, dl, CarryType, VT));
3496 SDValue Result, Overflow;
3497 TLI.expandSADDSUBO(Node, Result, Overflow, DAG);
3498 Results.push_back(Result);
3499 Results.push_back(Overflow);
3504 SDValue Result, Overflow;
3505 TLI.expandUADDSUBO(Node, Result, Overflow, DAG);
3506 Results.push_back(Result);
3507 Results.push_back(Overflow);
3512 SDValue Result, Overflow;
3513 if (TLI.expandMULO(Node, Result, Overflow, DAG)) {
3514 Results.push_back(Result);
3515 Results.push_back(Overflow);
3519 case ISD::BUILD_PAIR: {
3520 EVT PairTy = Node->getValueType(0);
3521 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3522 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3524 ISD::SHL, dl, PairTy, Tmp2,
3525 DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3526 TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3527 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3531 Tmp1 = Node->getOperand(0);
3532 Tmp2 = Node->getOperand(1);
3533 Tmp3 = Node->getOperand(2);
3534 if (Tmp1.getOpcode() == ISD::SETCC) {
3535 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3537 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3539 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3540 DAG.getConstant(0, dl, Tmp1.getValueType()),
3541 Tmp2, Tmp3, ISD::SETNE);
3543 Tmp1->setFlags(Node->getFlags());
3544 Results.push_back(Tmp1);
3547 SDValue Chain = Node->getOperand(0);
3548 SDValue Table = Node->getOperand(1);
3549 SDValue Index = Node->getOperand(2);
3551 const DataLayout &TD = DAG.getDataLayout();
3552 EVT PTy = TLI.getPointerTy(TD);
3554 unsigned EntrySize =
3555 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3557 // For power-of-two jumptable entry sizes convert multiplication to a shift.
3558 // This transformation needs to be done here since otherwise the MIPS
3559 // backend will end up emitting a three instruction multiply sequence
3560 // instead of a single shift and MSP430 will call a runtime function.
3561 if (llvm::isPowerOf2_32(EntrySize))
3562 Index = DAG.getNode(
3563 ISD::SHL, dl, Index.getValueType(), Index,
3564 DAG.getConstant(llvm::Log2_32(EntrySize), dl, Index.getValueType()));
3566 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3567 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3568 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3571 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3572 SDValue LD = DAG.getExtLoad(
3573 ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3574 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
3576 if (TLI.isJumpTableRelative()) {
3577 // For PIC, the sequence is:
3578 // BRIND(load(Jumptable + index) + RelocBase)
3579 // RelocBase can be JumpTable, GOT or some sort of global base.
3580 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3581 TLI.getPICJumpTableRelocBase(Table, DAG));
3584 Tmp1 = TLI.expandIndirectJTBranch(dl, LD.getValue(1), Addr, DAG);
3585 Results.push_back(Tmp1);
3589 // Expand brcond's setcc into its constituent parts and create a BR_CC
3591 Tmp1 = Node->getOperand(0);
3592 Tmp2 = Node->getOperand(1);
3593 if (Tmp2.getOpcode() == ISD::SETCC &&
3594 TLI.isOperationLegalOrCustom(ISD::BR_CC,
3595 Tmp2.getOperand(0).getValueType())) {
3596 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, Tmp2.getOperand(2),
3597 Tmp2.getOperand(0), Tmp2.getOperand(1),
3598 Node->getOperand(2));
3600 // We test only the i1 bit. Skip the AND if UNDEF or another AND.
3601 if (Tmp2.isUndef() ||
3602 (Tmp2.getOpcode() == ISD::AND &&
3603 isa<ConstantSDNode>(Tmp2.getOperand(1)) &&
3604 cast<ConstantSDNode>(Tmp2.getOperand(1))->getZExtValue() == 1))
3607 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3608 DAG.getConstant(1, dl, Tmp2.getValueType()));
3609 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3610 DAG.getCondCode(ISD::SETNE), Tmp3,
3611 DAG.getConstant(0, dl, Tmp3.getValueType()),
3612 Node->getOperand(2));
3614 Results.push_back(Tmp1);
3618 case ISD::STRICT_FSETCC:
3619 case ISD::STRICT_FSETCCS: {
3620 bool IsVP = Node->getOpcode() == ISD::VP_SETCC;
3621 bool IsStrict = Node->getOpcode() == ISD::STRICT_FSETCC ||
3622 Node->getOpcode() == ISD::STRICT_FSETCCS;
3623 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS;
3624 SDValue Chain = IsStrict ? Node->getOperand(0) : SDValue();
3625 unsigned Offset = IsStrict ? 1 : 0;
3626 Tmp1 = Node->getOperand(0 + Offset);
3627 Tmp2 = Node->getOperand(1 + Offset);
3628 Tmp3 = Node->getOperand(2 + Offset);
3631 Mask = Node->getOperand(3 + Offset);
3632 EVL = Node->getOperand(4 + Offset);
3634 bool Legalized = TLI.LegalizeSetCCCondCode(
3635 DAG, Node->getValueType(0), Tmp1, Tmp2, Tmp3, Mask, EVL, NeedInvert, dl,
3636 Chain, IsSignaling);
3639 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3640 // condition code, create a new SETCC node.
3641 if (Tmp3.getNode()) {
3643 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getVTList(),
3644 {Chain, Tmp1, Tmp2, Tmp3}, Node->getFlags());
3645 Chain = Tmp1.getValue(1);
3647 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0),
3648 {Tmp1, Tmp2, Tmp3, Mask, EVL}, Node->getFlags());
3650 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1,
3651 Tmp2, Tmp3, Node->getFlags());
3655 // If we expanded the SETCC by inverting the condition code, then wrap
3656 // the existing SETCC in a NOT to restore the intended condition.
3659 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3662 DAG.getVPLogicalNOT(dl, Tmp1, Mask, EVL, Tmp1->getValueType(0));
3665 Results.push_back(Tmp1);
3667 Results.push_back(Chain);
3672 // FIXME: It seems Legalized is false iff CCCode is Legal. I don't
3673 // understand if this code is useful for strict nodes.
3674 assert(!IsStrict && "Don't know how to expand for strict nodes.");
3676 // Otherwise, SETCC for the given comparison type must be completely
3677 // illegal; expand it into a SELECT_CC.
3678 // FIXME: This drops the mask/evl for VP_SETCC.
3679 EVT VT = Node->getValueType(0);
3680 EVT Tmp1VT = Tmp1.getValueType();
3681 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3682 DAG.getBoolConstant(true, dl, VT, Tmp1VT),
3683 DAG.getBoolConstant(false, dl, VT, Tmp1VT), Tmp3);
3684 Tmp1->setFlags(Node->getFlags());
3685 Results.push_back(Tmp1);
3688 case ISD::SELECT_CC: {
3689 // TODO: need to add STRICT_SELECT_CC and STRICT_SELECT_CCS
3690 Tmp1 = Node->getOperand(0); // LHS
3691 Tmp2 = Node->getOperand(1); // RHS
3692 Tmp3 = Node->getOperand(2); // True
3693 Tmp4 = Node->getOperand(3); // False
3694 EVT VT = Node->getValueType(0);
3696 SDValue CC = Node->getOperand(4);
3697 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3699 if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) {
3700 // If the condition code is legal, then we need to expand this
3701 // node using SETCC and SELECT.
3702 EVT CmpVT = Tmp1.getValueType();
3703 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3704 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3706 EVT CCVT = getSetCCResultType(CmpVT);
3707 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC, Node->getFlags());
3708 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3712 // SELECT_CC is legal, so the condition code must not be.
3713 bool Legalized = false;
3714 // Try to legalize by inverting the condition. This is for targets that
3715 // might support an ordered version of a condition, but not the unordered
3716 // version (or vice versa).
3717 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp, Tmp1.getValueType());
3718 if (TLI.isCondCodeLegalOrCustom(InvCC, Tmp1.getSimpleValueType())) {
3719 // Use the new condition code and swap true and false
3721 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3722 Tmp1->setFlags(Node->getFlags());
3724 // If The inverse is not legal, then try to swap the arguments using
3725 // the inverse condition code.
3726 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3727 if (TLI.isCondCodeLegalOrCustom(SwapInvCC, Tmp1.getSimpleValueType())) {
3728 // The swapped inverse condition is legal, so swap true and false,
3731 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3732 Tmp1->setFlags(Node->getFlags());
3737 Legalized = TLI.LegalizeSetCCCondCode(
3738 DAG, getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC,
3739 /*Mask*/ SDValue(), /*EVL*/ SDValue(), NeedInvert, dl, Chain);
3741 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3743 // If we expanded the SETCC by inverting the condition code, then swap
3744 // the True/False operands to match.
3746 std::swap(Tmp3, Tmp4);
3748 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3749 // condition code, create a new SELECT_CC node.
3751 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3752 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3754 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3755 CC = DAG.getCondCode(ISD::SETNE);
3756 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3757 Tmp2, Tmp3, Tmp4, CC);
3759 Tmp1->setFlags(Node->getFlags());
3761 Results.push_back(Tmp1);
3765 // TODO: need to add STRICT_BR_CC and STRICT_BR_CCS
3767 Tmp1 = Node->getOperand(0); // Chain
3768 Tmp2 = Node->getOperand(2); // LHS
3769 Tmp3 = Node->getOperand(3); // RHS
3770 Tmp4 = Node->getOperand(1); // CC
3772 bool Legalized = TLI.LegalizeSetCCCondCode(
3773 DAG, getSetCCResultType(Tmp2.getValueType()), Tmp2, Tmp3, Tmp4,
3774 /*Mask*/ SDValue(), /*EVL*/ SDValue(), NeedInvert, dl, Chain);
3776 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3778 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3780 if (Tmp4.getNode()) {
3781 assert(!NeedInvert && "Don't know how to invert BR_CC!");
3783 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3784 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3786 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3787 Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE);
3788 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3789 Tmp2, Tmp3, Node->getOperand(4));
3791 Results.push_back(Tmp1);
3794 case ISD::BUILD_VECTOR:
3795 Results.push_back(ExpandBUILD_VECTOR(Node));
3797 case ISD::SPLAT_VECTOR:
3798 Results.push_back(ExpandSPLAT_VECTOR(Node));
3803 // Scalarize vector SRA/SRL/SHL.
3804 EVT VT = Node->getValueType(0);
3805 assert(VT.isVector() && "Unable to legalize non-vector shift");
3806 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3807 unsigned NumElem = VT.getVectorNumElements();
3809 SmallVector<SDValue, 8> Scalars;
3810 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3812 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(),
3813 Node->getOperand(0), DAG.getVectorIdxConstant(Idx, dl));
3815 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(),
3816 Node->getOperand(1), DAG.getVectorIdxConstant(Idx, dl));
3817 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3818 VT.getScalarType(), Ex, Sh));
3821 SDValue Result = DAG.getBuildVector(Node->getValueType(0), dl, Scalars);
3822 Results.push_back(Result);
3825 case ISD::VECREDUCE_FADD:
3826 case ISD::VECREDUCE_FMUL:
3827 case ISD::VECREDUCE_ADD:
3828 case ISD::VECREDUCE_MUL:
3829 case ISD::VECREDUCE_AND:
3830 case ISD::VECREDUCE_OR:
3831 case ISD::VECREDUCE_XOR:
3832 case ISD::VECREDUCE_SMAX:
3833 case ISD::VECREDUCE_SMIN:
3834 case ISD::VECREDUCE_UMAX:
3835 case ISD::VECREDUCE_UMIN:
3836 case ISD::VECREDUCE_FMAX:
3837 case ISD::VECREDUCE_FMIN:
3838 Results.push_back(TLI.expandVecReduce(Node, DAG));
3840 case ISD::GLOBAL_OFFSET_TABLE:
3841 case ISD::GlobalAddress:
3842 case ISD::GlobalTLSAddress:
3843 case ISD::ExternalSymbol:
3844 case ISD::ConstantPool:
3845 case ISD::JumpTable:
3846 case ISD::INTRINSIC_W_CHAIN:
3847 case ISD::INTRINSIC_WO_CHAIN:
3848 case ISD::INTRINSIC_VOID:
3849 // FIXME: Custom lowering for these operations shouldn't return null!
3850 // Return true so that we don't call ConvertNodeToLibcall which also won't
3855 if (!TLI.isStrictFPEnabled() && Results.empty() && Node->isStrictFPOpcode()) {
3856 // FIXME: We were asked to expand a strict floating-point operation,
3857 // but there is currently no expansion implemented that would preserve
3858 // the "strict" properties. For now, we just fall back to the non-strict
3859 // version if that is legal on the target. The actual mutation of the
3860 // operation will happen in SelectionDAGISel::DoInstructionSelection.
3861 switch (Node->getOpcode()) {
3863 if (TLI.getStrictFPOperationAction(Node->getOpcode(),
3864 Node->getValueType(0))
3865 == TargetLowering::Legal)
3868 case ISD::STRICT_FSUB: {
3869 if (TLI.getStrictFPOperationAction(
3870 ISD::STRICT_FSUB, Node->getValueType(0)) == TargetLowering::Legal)
3872 if (TLI.getStrictFPOperationAction(
3873 ISD::STRICT_FADD, Node->getValueType(0)) != TargetLowering::Legal)
3876 EVT VT = Node->getValueType(0);
3877 const SDNodeFlags Flags = Node->getFlags();
3878 SDValue Neg = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(2), Flags);
3879 SDValue Fadd = DAG.getNode(ISD::STRICT_FADD, dl, Node->getVTList(),
3880 {Node->getOperand(0), Node->getOperand(1), Neg},
3883 Results.push_back(Fadd);
3884 Results.push_back(Fadd.getValue(1));
3887 case ISD::STRICT_SINT_TO_FP:
3888 case ISD::STRICT_UINT_TO_FP:
3889 case ISD::STRICT_LRINT:
3890 case ISD::STRICT_LLRINT:
3891 case ISD::STRICT_LROUND:
3892 case ISD::STRICT_LLROUND:
3893 // These are registered by the operand type instead of the value
3894 // type. Reflect that here.
3895 if (TLI.getStrictFPOperationAction(Node->getOpcode(),
3896 Node->getOperand(1).getValueType())
3897 == TargetLowering::Legal)
3903 // Replace the original node with the legalized result.
3904 if (Results.empty()) {
3905 LLVM_DEBUG(dbgs() << "Cannot expand node\n");
3909 LLVM_DEBUG(dbgs() << "Successfully expanded node\n");
3910 ReplaceNode(Node, Results.data());
3914 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3915 LLVM_DEBUG(dbgs() << "Trying to convert node to libcall\n");
3916 SmallVector<SDValue, 8> Results;
3918 // FIXME: Check flags on the node to see if we can use a finite call.
3919 unsigned Opc = Node->getOpcode();
3921 case ISD::ATOMIC_FENCE: {
3922 // If the target didn't lower this, lower it to '__sync_synchronize()' call
3923 // FIXME: handle "fence singlethread" more efficiently.
3924 TargetLowering::ArgListTy Args;
3926 TargetLowering::CallLoweringInfo CLI(DAG);
3928 .setChain(Node->getOperand(0))
3930 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3931 DAG.getExternalSymbol("__sync_synchronize",
3932 TLI.getPointerTy(DAG.getDataLayout())),
3935 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3937 Results.push_back(CallResult.second);
3940 // By default, atomic intrinsics are marked Legal and lowered. Targets
3941 // which don't support them directly, however, may want libcalls, in which
3942 // case they mark them Expand, and we get here.
3943 case ISD::ATOMIC_SWAP:
3944 case ISD::ATOMIC_LOAD_ADD:
3945 case ISD::ATOMIC_LOAD_SUB:
3946 case ISD::ATOMIC_LOAD_AND:
3947 case ISD::ATOMIC_LOAD_CLR:
3948 case ISD::ATOMIC_LOAD_OR:
3949 case ISD::ATOMIC_LOAD_XOR:
3950 case ISD::ATOMIC_LOAD_NAND:
3951 case ISD::ATOMIC_LOAD_MIN:
3952 case ISD::ATOMIC_LOAD_MAX:
3953 case ISD::ATOMIC_LOAD_UMIN:
3954 case ISD::ATOMIC_LOAD_UMAX:
3955 case ISD::ATOMIC_CMP_SWAP: {
3956 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3957 AtomicOrdering Order = cast<AtomicSDNode>(Node)->getMergedOrdering();
3958 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order, VT);
3959 EVT RetVT = Node->getValueType(0);
3960 TargetLowering::MakeLibCallOptions CallOptions;
3961 SmallVector<SDValue, 4> Ops;
3962 if (TLI.getLibcallName(LC)) {
3963 // If outline atomic available, prepare its arguments and expand.
3964 Ops.append(Node->op_begin() + 2, Node->op_end());
3965 Ops.push_back(Node->getOperand(1));
3968 LC = RTLIB::getSYNC(Opc, VT);
3969 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3970 "Unexpected atomic op or value type!");
3971 // Arguments for expansion to sync libcall
3972 Ops.append(Node->op_begin() + 1, Node->op_end());
3974 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
3977 Node->getOperand(0));
3978 Results.push_back(Tmp.first);
3979 Results.push_back(Tmp.second);
3983 // If this operation is not supported, lower it to 'abort()' call
3984 TargetLowering::ArgListTy Args;
3985 TargetLowering::CallLoweringInfo CLI(DAG);
3987 .setChain(Node->getOperand(0))
3988 .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3989 DAG.getExternalSymbol(
3990 "abort", TLI.getPointerTy(DAG.getDataLayout())),
3992 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3994 Results.push_back(CallResult.second);
3998 case ISD::STRICT_FMINNUM:
3999 ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
4000 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
4001 RTLIB::FMIN_PPCF128, Results);
4004 case ISD::STRICT_FMAXNUM:
4005 ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
4006 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
4007 RTLIB::FMAX_PPCF128, Results);
4010 case ISD::STRICT_FSQRT:
4011 ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
4012 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
4013 RTLIB::SQRT_PPCF128, Results);
4016 ExpandFPLibCall(Node, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
4017 RTLIB::CBRT_F80, RTLIB::CBRT_F128,
4018 RTLIB::CBRT_PPCF128, Results);
4021 case ISD::STRICT_FSIN:
4022 ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
4023 RTLIB::SIN_F80, RTLIB::SIN_F128,
4024 RTLIB::SIN_PPCF128, Results);
4027 case ISD::STRICT_FCOS:
4028 ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
4029 RTLIB::COS_F80, RTLIB::COS_F128,
4030 RTLIB::COS_PPCF128, Results);
4033 // Expand into sincos libcall.
4034 ExpandSinCosLibCall(Node, Results);
4037 case ISD::STRICT_FLOG:
4038 ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, RTLIB::LOG_F80,
4039 RTLIB::LOG_F128, RTLIB::LOG_PPCF128, Results);
4042 case ISD::STRICT_FLOG2:
4043 ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, RTLIB::LOG2_F80,
4044 RTLIB::LOG2_F128, RTLIB::LOG2_PPCF128, Results);
4047 case ISD::STRICT_FLOG10:
4048 ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, RTLIB::LOG10_F80,
4049 RTLIB::LOG10_F128, RTLIB::LOG10_PPCF128, Results);
4052 case ISD::STRICT_FEXP:
4053 ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, RTLIB::EXP_F80,
4054 RTLIB::EXP_F128, RTLIB::EXP_PPCF128, Results);
4057 case ISD::STRICT_FEXP2:
4058 ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, RTLIB::EXP2_F80,
4059 RTLIB::EXP2_F128, RTLIB::EXP2_PPCF128, Results);
4062 case ISD::STRICT_FTRUNC:
4063 ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
4064 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
4065 RTLIB::TRUNC_PPCF128, Results);
4068 case ISD::STRICT_FFLOOR:
4069 ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
4070 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
4071 RTLIB::FLOOR_PPCF128, Results);
4074 case ISD::STRICT_FCEIL:
4075 ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
4076 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
4077 RTLIB::CEIL_PPCF128, Results);
4080 case ISD::STRICT_FRINT:
4081 ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
4082 RTLIB::RINT_F80, RTLIB::RINT_F128,
4083 RTLIB::RINT_PPCF128, Results);
4085 case ISD::FNEARBYINT:
4086 case ISD::STRICT_FNEARBYINT:
4087 ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
4088 RTLIB::NEARBYINT_F64,
4089 RTLIB::NEARBYINT_F80,
4090 RTLIB::NEARBYINT_F128,
4091 RTLIB::NEARBYINT_PPCF128, Results);
4094 case ISD::STRICT_FROUND:
4095 ExpandFPLibCall(Node, RTLIB::ROUND_F32,
4099 RTLIB::ROUND_PPCF128, Results);
4101 case ISD::FROUNDEVEN:
4102 case ISD::STRICT_FROUNDEVEN:
4103 ExpandFPLibCall(Node, RTLIB::ROUNDEVEN_F32,
4104 RTLIB::ROUNDEVEN_F64,
4105 RTLIB::ROUNDEVEN_F80,
4106 RTLIB::ROUNDEVEN_F128,
4107 RTLIB::ROUNDEVEN_PPCF128, Results);
4110 case ISD::STRICT_FPOWI: {
4111 RTLIB::Libcall LC = RTLIB::getPOWI(Node->getSimpleValueType(0));
4112 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fpowi.");
4113 if (!TLI.getLibcallName(LC)) {
4114 // Some targets don't have a powi libcall; use pow instead.
4115 if (Node->isStrictFPOpcode()) {
4117 DAG.getNode(ISD::STRICT_SINT_TO_FP, SDLoc(Node),
4118 {Node->getValueType(0), Node->getValueType(1)},
4119 {Node->getOperand(0), Node->getOperand(2)});
4121 DAG.getNode(ISD::STRICT_FPOW, SDLoc(Node),
4122 {Node->getValueType(0), Node->getValueType(1)},
4123 {Exponent.getValue(1), Node->getOperand(1), Exponent});
4124 Results.push_back(FPOW);
4125 Results.push_back(FPOW.getValue(1));
4128 DAG.getNode(ISD::SINT_TO_FP, SDLoc(Node), Node->getValueType(0),
4129 Node->getOperand(1));
4130 Results.push_back(DAG.getNode(ISD::FPOW, SDLoc(Node),
4131 Node->getValueType(0),
4132 Node->getOperand(0), Exponent));
4136 unsigned Offset = Node->isStrictFPOpcode() ? 1 : 0;
4137 bool ExponentHasSizeOfInt =
4138 DAG.getLibInfo().getIntSize() ==
4139 Node->getOperand(1 + Offset).getValueType().getSizeInBits();
4140 if (!ExponentHasSizeOfInt) {
4141 // If the exponent does not match with sizeof(int) a libcall to
4142 // RTLIB::POWI would use the wrong type for the argument.
4143 DAG.getContext()->emitError("POWI exponent does not match sizeof(int)");
4144 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
4147 ExpandFPLibCall(Node, LC, Results);
4151 case ISD::STRICT_FPOW:
4152 ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
4153 RTLIB::POW_F128, RTLIB::POW_PPCF128, Results);
4156 case ISD::STRICT_LROUND:
4157 ExpandArgFPLibCall(Node, RTLIB::LROUND_F32,
4158 RTLIB::LROUND_F64, RTLIB::LROUND_F80,
4160 RTLIB::LROUND_PPCF128, Results);
4163 case ISD::STRICT_LLROUND:
4164 ExpandArgFPLibCall(Node, RTLIB::LLROUND_F32,
4165 RTLIB::LLROUND_F64, RTLIB::LLROUND_F80,
4166 RTLIB::LLROUND_F128,
4167 RTLIB::LLROUND_PPCF128, Results);
4170 case ISD::STRICT_LRINT:
4171 ExpandArgFPLibCall(Node, RTLIB::LRINT_F32,
4172 RTLIB::LRINT_F64, RTLIB::LRINT_F80,
4174 RTLIB::LRINT_PPCF128, Results);
4177 case ISD::STRICT_LLRINT:
4178 ExpandArgFPLibCall(Node, RTLIB::LLRINT_F32,
4179 RTLIB::LLRINT_F64, RTLIB::LLRINT_F80,
4181 RTLIB::LLRINT_PPCF128, Results);
4184 case ISD::STRICT_FDIV:
4185 ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
4186 RTLIB::DIV_F80, RTLIB::DIV_F128,
4187 RTLIB::DIV_PPCF128, Results);
4190 case ISD::STRICT_FREM:
4191 ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
4192 RTLIB::REM_F80, RTLIB::REM_F128,
4193 RTLIB::REM_PPCF128, Results);
4196 case ISD::STRICT_FMA:
4197 ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
4198 RTLIB::FMA_F80, RTLIB::FMA_F128,
4199 RTLIB::FMA_PPCF128, Results);
4202 case ISD::STRICT_FADD:
4203 ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
4204 RTLIB::ADD_F80, RTLIB::ADD_F128,
4205 RTLIB::ADD_PPCF128, Results);
4208 case ISD::STRICT_FMUL:
4209 ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
4210 RTLIB::MUL_F80, RTLIB::MUL_F128,
4211 RTLIB::MUL_PPCF128, Results);
4213 case ISD::FP16_TO_FP:
4214 if (Node->getValueType(0) == MVT::f32) {
4215 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
4218 case ISD::STRICT_FP16_TO_FP: {
4219 if (Node->getValueType(0) == MVT::f32) {
4220 TargetLowering::MakeLibCallOptions CallOptions;
4221 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
4222 DAG, RTLIB::FPEXT_F16_F32, MVT::f32, Node->getOperand(1), CallOptions,
4223 SDLoc(Node), Node->getOperand(0));
4224 Results.push_back(Tmp.first);
4225 Results.push_back(Tmp.second);
4229 case ISD::FP_TO_FP16: {
4231 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
4232 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4233 Results.push_back(ExpandLibCall(LC, Node, false));
4236 case ISD::FP_TO_BF16: {
4238 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::bf16);
4239 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_bf16");
4240 Results.push_back(ExpandLibCall(LC, Node, false));
4243 case ISD::STRICT_SINT_TO_FP:
4244 case ISD::STRICT_UINT_TO_FP:
4245 case ISD::SINT_TO_FP:
4246 case ISD::UINT_TO_FP: {
4247 // TODO - Common the code with DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP
4248 bool IsStrict = Node->isStrictFPOpcode();
4249 bool Signed = Node->getOpcode() == ISD::SINT_TO_FP ||
4250 Node->getOpcode() == ISD::STRICT_SINT_TO_FP;
4251 EVT SVT = Node->getOperand(IsStrict ? 1 : 0).getValueType();
4252 EVT RVT = Node->getValueType(0);
4256 // Even if the input is legal, no libcall may exactly match, eg. we don't
4257 // have i1 -> fp conversions. So, it needs to be promoted to a larger type,
4258 // eg: i13 -> fp. Then, look for an appropriate libcall.
4259 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4260 for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
4261 t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL;
4263 NVT = (MVT::SimpleValueType)t;
4264 // The source needs to big enough to hold the operand.
4265 if (NVT.bitsGE(SVT))
4266 LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT)
4267 : RTLIB::getUINTTOFP(NVT, RVT);
4269 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
4271 SDValue Chain = IsStrict ? Node->getOperand(0) : SDValue();
4272 // Sign/zero extend the argument if the libcall takes a larger type.
4273 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
4274 NVT, Node->getOperand(IsStrict ? 1 : 0));
4275 TargetLowering::MakeLibCallOptions CallOptions;
4276 CallOptions.setSExt(Signed);
4277 std::pair<SDValue, SDValue> Tmp =
4278 TLI.makeLibCall(DAG, LC, RVT, Op, CallOptions, dl, Chain);
4279 Results.push_back(Tmp.first);
4281 Results.push_back(Tmp.second);
4284 case ISD::FP_TO_SINT:
4285 case ISD::FP_TO_UINT:
4286 case ISD::STRICT_FP_TO_SINT:
4287 case ISD::STRICT_FP_TO_UINT: {
4288 // TODO - Common the code with DAGTypeLegalizer::SoftenFloatOp_FP_TO_XINT.
4289 bool IsStrict = Node->isStrictFPOpcode();
4290 bool Signed = Node->getOpcode() == ISD::FP_TO_SINT ||
4291 Node->getOpcode() == ISD::STRICT_FP_TO_SINT;
4293 SDValue Op = Node->getOperand(IsStrict ? 1 : 0);
4294 EVT SVT = Op.getValueType();
4295 EVT RVT = Node->getValueType(0);
4299 // Even if the result is legal, no libcall may exactly match, eg. we don't
4300 // have fp -> i1 conversions. So, it needs to be promoted to a larger type,
4301 // eg: fp -> i32. Then, look for an appropriate libcall.
4302 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4303 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE;
4304 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL;
4306 NVT = (MVT::SimpleValueType)IntVT;
4307 // The type needs to big enough to hold the result.
4308 if (NVT.bitsGE(RVT))
4309 LC = Signed ? RTLIB::getFPTOSINT(SVT, NVT)
4310 : RTLIB::getFPTOUINT(SVT, NVT);
4312 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
4314 SDValue Chain = IsStrict ? Node->getOperand(0) : SDValue();
4315 TargetLowering::MakeLibCallOptions CallOptions;
4316 std::pair<SDValue, SDValue> Tmp =
4317 TLI.makeLibCall(DAG, LC, NVT, Op, CallOptions, dl, Chain);
4319 // Truncate the result if the libcall returns a larger type.
4320 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, RVT, Tmp.first));
4322 Results.push_back(Tmp.second);
4327 case ISD::STRICT_FP_ROUND: {
4328 // X = FP_ROUND(Y, TRUNC)
4329 // TRUNC is a flag, which is always an integer that is zero or one.
4330 // If TRUNC is 0, this is a normal rounding, if it is 1, this FP_ROUND
4331 // is known to not change the value of Y.
4332 // We can only expand it into libcall if the TRUNC is 0.
4333 bool IsStrict = Node->isStrictFPOpcode();
4334 SDValue Op = Node->getOperand(IsStrict ? 1 : 0);
4335 SDValue Chain = IsStrict ? Node->getOperand(0) : SDValue();
4336 EVT VT = Node->getValueType(0);
4337 assert(cast<ConstantSDNode>(Node->getOperand(IsStrict ? 2 : 1))->isZero() &&
4338 "Unable to expand as libcall if it is not normal rounding");
4340 RTLIB::Libcall LC = RTLIB::getFPROUND(Op.getValueType(), VT);
4341 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
4343 TargetLowering::MakeLibCallOptions CallOptions;
4344 std::pair<SDValue, SDValue> Tmp =
4345 TLI.makeLibCall(DAG, LC, VT, Op, CallOptions, SDLoc(Node), Chain);
4346 Results.push_back(Tmp.first);
4348 Results.push_back(Tmp.second);
4351 case ISD::FP_EXTEND: {
4353 ExpandLibCall(RTLIB::getFPEXT(Node->getOperand(0).getValueType(),
4354 Node->getValueType(0)),
4358 case ISD::STRICT_FP_EXTEND:
4359 case ISD::STRICT_FP_TO_FP16: {
4361 Node->getOpcode() == ISD::STRICT_FP_TO_FP16
4362 ? RTLIB::getFPROUND(Node->getOperand(1).getValueType(), MVT::f16)
4363 : RTLIB::getFPEXT(Node->getOperand(1).getValueType(),
4364 Node->getValueType(0));
4365 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
4367 TargetLowering::MakeLibCallOptions CallOptions;
4368 std::pair<SDValue, SDValue> Tmp =
4369 TLI.makeLibCall(DAG, LC, Node->getValueType(0), Node->getOperand(1),
4370 CallOptions, SDLoc(Node), Node->getOperand(0));
4371 Results.push_back(Tmp.first);
4372 Results.push_back(Tmp.second);
4376 case ISD::STRICT_FSUB:
4377 ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4378 RTLIB::SUB_F80, RTLIB::SUB_F128,
4379 RTLIB::SUB_PPCF128, Results);
4382 Results.push_back(ExpandIntLibCall(
4383 Node, true, RTLIB::SREM_I8, RTLIB::SREM_I16, RTLIB::SREM_I32,
4384 RTLIB::SREM_I64, RTLIB::SREM_I128, RTLIB::SREM_IEXT));
4387 Results.push_back(ExpandIntLibCall(
4388 Node, false, RTLIB::UREM_I8, RTLIB::UREM_I16, RTLIB::UREM_I32,
4389 RTLIB::UREM_I64, RTLIB::UREM_I128, RTLIB::UREM_IEXT));
4392 Results.push_back(ExpandIntLibCall(
4393 Node, true, RTLIB::SDIV_I8, RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4394 RTLIB::SDIV_I64, RTLIB::SDIV_I128, RTLIB::SDIV_IEXT));
4397 Results.push_back(ExpandIntLibCall(
4398 Node, false, RTLIB::UDIV_I8, RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4399 RTLIB::UDIV_I64, RTLIB::UDIV_I128, RTLIB::UDIV_IEXT));
4403 // Expand into divrem libcall
4404 ExpandDivRemLibCall(Node, Results);
4407 Results.push_back(ExpandIntLibCall(
4408 Node, false, RTLIB::MUL_I8, RTLIB::MUL_I16, RTLIB::MUL_I32,
4409 RTLIB::MUL_I64, RTLIB::MUL_I128, RTLIB::MUL_IEXT));
4411 case ISD::CTLZ_ZERO_UNDEF:
4412 switch (Node->getSimpleValueType(0).SimpleTy) {
4414 llvm_unreachable("LibCall explicitly requested, but not available");
4416 Results.push_back(ExpandLibCall(RTLIB::CTLZ_I32, Node, false));
4419 Results.push_back(ExpandLibCall(RTLIB::CTLZ_I64, Node, false));
4422 Results.push_back(ExpandLibCall(RTLIB::CTLZ_I128, Node, false));
4428 // Replace the original node with the legalized result.
4429 if (!Results.empty()) {
4430 LLVM_DEBUG(dbgs() << "Successfully converted node to libcall\n");
4431 ReplaceNode(Node, Results.data());
4433 LLVM_DEBUG(dbgs() << "Could not convert node to libcall\n");
4436 // Determine the vector type to use in place of an original scalar element when
4437 // promoting equally sized vectors.
4438 static MVT getPromotedVectorElementType(const TargetLowering &TLI,
4439 MVT EltVT, MVT NewEltVT) {
4440 unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4441 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4442 assert(TLI.isTypeLegal(MidVT) && "unexpected");
4446 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4447 LLVM_DEBUG(dbgs() << "Trying to promote node\n");
4448 SmallVector<SDValue, 8> Results;
4449 MVT OVT = Node->getSimpleValueType(0);
4450 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4451 Node->getOpcode() == ISD::SINT_TO_FP ||
4452 Node->getOpcode() == ISD::SETCC ||
4453 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4454 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4455 OVT = Node->getOperand(0).getSimpleValueType();
4457 if (Node->getOpcode() == ISD::STRICT_UINT_TO_FP ||
4458 Node->getOpcode() == ISD::STRICT_SINT_TO_FP ||
4459 Node->getOpcode() == ISD::STRICT_FSETCC ||
4460 Node->getOpcode() == ISD::STRICT_FSETCCS)
4461 OVT = Node->getOperand(1).getSimpleValueType();
4462 if (Node->getOpcode() == ISD::BR_CC ||
4463 Node->getOpcode() == ISD::SELECT_CC)
4464 OVT = Node->getOperand(2).getSimpleValueType();
4465 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4467 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
4468 switch (Node->getOpcode()) {
4470 case ISD::CTTZ_ZERO_UNDEF:
4472 case ISD::CTLZ_ZERO_UNDEF:
4474 // Zero extend the argument unless its cttz, then use any_extend.
4475 if (Node->getOpcode() == ISD::CTTZ ||
4476 Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF)
4477 Tmp1 = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
4479 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4481 if (Node->getOpcode() == ISD::CTTZ) {
4482 // The count is the same in the promoted type except if the original
4483 // value was zero. This can be handled by setting the bit just off
4484 // the top of the original type.
4485 auto TopBit = APInt::getOneBitSet(NVT.getSizeInBits(),
4486 OVT.getSizeInBits());
4487 Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
4488 DAG.getConstant(TopBit, dl, NVT));
4490 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4491 // already the correct result.
4492 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4493 if (Node->getOpcode() == ISD::CTLZ ||
4494 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4495 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4496 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4497 DAG.getConstant(NVT.getSizeInBits() -
4498 OVT.getSizeInBits(), dl, NVT));
4500 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4502 case ISD::BITREVERSE:
4504 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4505 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4506 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4508 ISD::SRL, dl, NVT, Tmp1,
4509 DAG.getConstant(DiffBits, dl,
4510 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4512 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4515 case ISD::FP_TO_UINT:
4516 case ISD::STRICT_FP_TO_UINT:
4517 case ISD::FP_TO_SINT:
4518 case ISD::STRICT_FP_TO_SINT:
4519 PromoteLegalFP_TO_INT(Node, dl, Results);
4521 case ISD::FP_TO_UINT_SAT:
4522 case ISD::FP_TO_SINT_SAT:
4523 Results.push_back(PromoteLegalFP_TO_INT_SAT(Node, dl));
4525 case ISD::UINT_TO_FP:
4526 case ISD::STRICT_UINT_TO_FP:
4527 case ISD::SINT_TO_FP:
4528 case ISD::STRICT_SINT_TO_FP:
4529 PromoteLegalINT_TO_FP(Node, dl, Results);
4532 SDValue Chain = Node->getOperand(0); // Get the chain.
4533 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4536 if (OVT.isVector()) {
4537 TruncOp = ISD::BITCAST;
4539 assert(OVT.isInteger()
4540 && "VAARG promotion is supported only for vectors or integer types");
4541 TruncOp = ISD::TRUNCATE;
4544 // Perform the larger operation, then convert back
4545 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4546 Node->getConstantOperandVal(3));
4547 Chain = Tmp1.getValue(1);
4549 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4551 // Modified the chain result - switch anything that used the old chain to
4553 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4554 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4556 UpdatedNodes->insert(Tmp2.getNode());
4557 UpdatedNodes->insert(Chain.getNode());
4570 unsigned ExtOp, TruncOp;
4571 if (OVT.isVector()) {
4572 ExtOp = ISD::BITCAST;
4573 TruncOp = ISD::BITCAST;
4575 assert(OVT.isInteger() && "Cannot promote logic operation");
4577 switch (Node->getOpcode()) {
4579 ExtOp = ISD::ANY_EXTEND;
4583 ExtOp = ISD::SIGN_EXTEND;
4587 ExtOp = ISD::ZERO_EXTEND;
4590 TruncOp = ISD::TRUNCATE;
4592 // Promote each of the values to the new type.
4593 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4594 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4595 // Perform the larger operation, then convert back
4596 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4597 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4600 case ISD::UMUL_LOHI:
4601 case ISD::SMUL_LOHI: {
4602 // Promote to a multiply in a wider integer type.
4603 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4605 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4606 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4607 Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4609 auto &DL = DAG.getDataLayout();
4610 unsigned OriginalSize = OVT.getScalarSizeInBits();
4612 ISD::SRL, dl, NVT, Tmp1,
4613 DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
4614 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4615 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
4619 unsigned ExtOp, TruncOp;
4620 if (Node->getValueType(0).isVector() ||
4621 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4622 ExtOp = ISD::BITCAST;
4623 TruncOp = ISD::BITCAST;
4624 } else if (Node->getValueType(0).isInteger()) {
4625 ExtOp = ISD::ANY_EXTEND;
4626 TruncOp = ISD::TRUNCATE;
4628 ExtOp = ISD::FP_EXTEND;
4629 TruncOp = ISD::FP_ROUND;
4631 Tmp1 = Node->getOperand(0);
4632 // Promote each of the values to the new type.
4633 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4634 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4635 // Perform the larger operation, then round down.
4636 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4637 Tmp1->setFlags(Node->getFlags());
4638 if (TruncOp != ISD::FP_ROUND)
4639 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4641 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4642 DAG.getIntPtrConstant(0, dl));
4643 Results.push_back(Tmp1);
4646 case ISD::VECTOR_SHUFFLE: {
4647 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4649 // Cast the two input vectors.
4650 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4651 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4653 // Convert the shuffle mask to the right # elements.
4654 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4655 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4656 Results.push_back(Tmp1);
4659 case ISD::VECTOR_SPLICE: {
4660 Tmp1 = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
4661 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(1));
4662 Tmp3 = DAG.getNode(ISD::VECTOR_SPLICE, dl, NVT, Tmp1, Tmp2,
4663 Node->getOperand(2));
4664 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp3));
4667 case ISD::SELECT_CC: {
4668 SDValue Cond = Node->getOperand(4);
4669 ISD::CondCode CCCode = cast<CondCodeSDNode>(Cond)->get();
4670 // Type of the comparison operands.
4671 MVT CVT = Node->getSimpleValueType(0);
4672 assert(CVT == OVT && "not handled");
4674 unsigned ExtOp = ISD::FP_EXTEND;
4675 if (NVT.isInteger()) {
4676 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4679 // Promote the comparison operands, if needed.
4680 if (TLI.isCondCodeLegal(CCCode, CVT)) {
4681 Tmp1 = Node->getOperand(0);
4682 Tmp2 = Node->getOperand(1);
4684 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4685 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4687 // Cast the true/false operands.
4688 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4689 Tmp4 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4691 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, NVT, {Tmp1, Tmp2, Tmp3, Tmp4, Cond},
4694 // Cast the result back to the original type.
4695 if (ExtOp != ISD::FP_EXTEND)
4696 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1);
4698 Tmp1 = DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp1,
4699 DAG.getIntPtrConstant(0, dl));
4701 Results.push_back(Tmp1);
4705 case ISD::STRICT_FSETCC:
4706 case ISD::STRICT_FSETCCS: {
4707 unsigned ExtOp = ISD::FP_EXTEND;
4708 if (NVT.isInteger()) {
4709 ISD::CondCode CCCode = cast<CondCodeSDNode>(Node->getOperand(2))->get();
4710 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4712 if (Node->isStrictFPOpcode()) {
4713 SDValue InChain = Node->getOperand(0);
4714 std::tie(Tmp1, std::ignore) =
4715 DAG.getStrictFPExtendOrRound(Node->getOperand(1), InChain, dl, NVT);
4716 std::tie(Tmp2, std::ignore) =
4717 DAG.getStrictFPExtendOrRound(Node->getOperand(2), InChain, dl, NVT);
4718 SmallVector<SDValue, 2> TmpChains = {Tmp1.getValue(1), Tmp2.getValue(1)};
4719 SDValue OutChain = DAG.getTokenFactor(dl, TmpChains);
4720 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
4721 Results.push_back(DAG.getNode(Node->getOpcode(), dl, VTs,
4722 {OutChain, Tmp1, Tmp2, Node->getOperand(3)},
4724 Results.push_back(Results.back().getValue(1));
4727 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4728 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4729 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), Tmp1,
4730 Tmp2, Node->getOperand(2), Node->getFlags()));
4734 unsigned ExtOp = ISD::FP_EXTEND;
4735 if (NVT.isInteger()) {
4736 ISD::CondCode CCCode =
4737 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4738 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4740 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4741 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4742 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4743 Node->getOperand(0), Node->getOperand(1),
4744 Tmp1, Tmp2, Node->getOperand(4)));
4755 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4756 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4757 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4759 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4760 Tmp3, DAG.getIntPtrConstant(0, dl)));
4762 case ISD::STRICT_FADD:
4763 case ISD::STRICT_FSUB:
4764 case ISD::STRICT_FMUL:
4765 case ISD::STRICT_FDIV:
4766 case ISD::STRICT_FMINNUM:
4767 case ISD::STRICT_FMAXNUM:
4768 case ISD::STRICT_FREM:
4769 case ISD::STRICT_FPOW:
4770 Tmp1 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
4771 {Node->getOperand(0), Node->getOperand(1)});
4772 Tmp2 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
4773 {Node->getOperand(0), Node->getOperand(2)});
4774 Tmp3 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1.getValue(1),
4776 Tmp1 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
4777 {Tmp3, Tmp1, Tmp2});
4778 Tmp1 = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {OVT, MVT::Other},
4779 {Tmp1.getValue(1), Tmp1, DAG.getIntPtrConstant(0, dl)});
4780 Results.push_back(Tmp1);
4781 Results.push_back(Tmp1.getValue(1));
4784 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4785 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4786 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4788 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4789 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4790 DAG.getIntPtrConstant(0, dl)));
4792 case ISD::STRICT_FMA:
4793 Tmp1 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
4794 {Node->getOperand(0), Node->getOperand(1)});
4795 Tmp2 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
4796 {Node->getOperand(0), Node->getOperand(2)});
4797 Tmp3 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
4798 {Node->getOperand(0), Node->getOperand(3)});
4799 Tmp4 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1.getValue(1),
4800 Tmp2.getValue(1), Tmp3.getValue(1));
4801 Tmp4 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
4802 {Tmp4, Tmp1, Tmp2, Tmp3});
4803 Tmp4 = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {OVT, MVT::Other},
4804 {Tmp4.getValue(1), Tmp4, DAG.getIntPtrConstant(0, dl)});
4805 Results.push_back(Tmp4);
4806 Results.push_back(Tmp4.getValue(1));
4808 case ISD::FCOPYSIGN:
4810 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4811 Tmp2 = Node->getOperand(1);
4812 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4814 // fcopysign doesn't change anything but the sign bit, so
4815 // (fp_round (fcopysign (fpext a), b))
4817 // (fp_round (fpext a))
4818 // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4819 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4820 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4821 Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4824 case ISD::STRICT_FPOWI:
4825 Tmp1 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
4826 {Node->getOperand(0), Node->getOperand(1)});
4827 Tmp2 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
4828 {Tmp1.getValue(1), Tmp1, Node->getOperand(2)});
4829 Tmp3 = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {OVT, MVT::Other},
4830 {Tmp2.getValue(1), Tmp2, DAG.getIntPtrConstant(0, dl)});
4831 Results.push_back(Tmp3);
4832 Results.push_back(Tmp3.getValue(1));
4837 case ISD::FNEARBYINT:
4839 case ISD::FROUNDEVEN:
4851 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4852 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4853 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4854 Tmp2, DAG.getIntPtrConstant(0, dl)));
4856 case ISD::STRICT_FFLOOR:
4857 case ISD::STRICT_FCEIL:
4858 case ISD::STRICT_FRINT:
4859 case ISD::STRICT_FNEARBYINT:
4860 case ISD::STRICT_FROUND:
4861 case ISD::STRICT_FROUNDEVEN:
4862 case ISD::STRICT_FTRUNC:
4863 case ISD::STRICT_FSQRT:
4864 case ISD::STRICT_FSIN:
4865 case ISD::STRICT_FCOS:
4866 case ISD::STRICT_FLOG:
4867 case ISD::STRICT_FLOG2:
4868 case ISD::STRICT_FLOG10:
4869 case ISD::STRICT_FEXP:
4870 case ISD::STRICT_FEXP2:
4871 Tmp1 = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NVT, MVT::Other},
4872 {Node->getOperand(0), Node->getOperand(1)});
4873 Tmp2 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
4874 {Tmp1.getValue(1), Tmp1});
4875 Tmp3 = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {OVT, MVT::Other},
4876 {Tmp2.getValue(1), Tmp2, DAG.getIntPtrConstant(0, dl)});
4877 Results.push_back(Tmp3);
4878 Results.push_back(Tmp3.getValue(1));
4880 case ISD::BUILD_VECTOR: {
4881 MVT EltVT = OVT.getVectorElementType();
4882 MVT NewEltVT = NVT.getVectorElementType();
4884 // Handle bitcasts to a different vector type with the same total bit size
4886 // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4888 // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4890 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4891 "Invalid promote type for build_vector");
4892 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4894 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4896 SmallVector<SDValue, 8> NewOps;
4897 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4898 SDValue Op = Node->getOperand(I);
4899 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4903 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4904 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4905 Results.push_back(CvtVec);
4908 case ISD::EXTRACT_VECTOR_ELT: {
4909 MVT EltVT = OVT.getVectorElementType();
4910 MVT NewEltVT = NVT.getVectorElementType();
4912 // Handle bitcasts to a different vector type with the same total bit size.
4914 // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4916 // v4i32:castx = bitcast x:v2i64
4919 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4920 // (i32 (extract_vector_elt castx, (2 * y + 1)))
4923 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4924 "Invalid promote type for extract_vector_elt");
4925 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4927 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4928 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4930 SDValue Idx = Node->getOperand(1);
4931 EVT IdxVT = Idx.getValueType();
4933 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4934 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4936 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4938 SmallVector<SDValue, 8> NewOps;
4939 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4940 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4941 SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4943 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4945 NewOps.push_back(Elt);
4948 SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps);
4949 Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4952 case ISD::INSERT_VECTOR_ELT: {
4953 MVT EltVT = OVT.getVectorElementType();
4954 MVT NewEltVT = NVT.getVectorElementType();
4956 // Handle bitcasts to a different vector type with the same total bit size
4958 // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4960 // v4i32:castx = bitcast x:v2i64
4961 // v2i32:casty = bitcast y:i64
4964 // (v4i32 insert_vector_elt
4965 // (v4i32 insert_vector_elt v4i32:castx,
4966 // (extract_vector_elt casty, 0), 2 * z),
4967 // (extract_vector_elt casty, 1), (2 * z + 1))
4969 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4970 "Invalid promote type for insert_vector_elt");
4971 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4973 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4974 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4976 SDValue Val = Node->getOperand(1);
4977 SDValue Idx = Node->getOperand(2);
4978 EVT IdxVT = Idx.getValueType();
4981 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4982 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4984 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4985 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4987 SDValue NewVec = CastVec;
4988 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4989 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4990 SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4992 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4993 CastVal, IdxOffset);
4995 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4996 NewVec, Elt, InEltIdx);
4999 Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
5002 case ISD::SCALAR_TO_VECTOR: {
5003 MVT EltVT = OVT.getVectorElementType();
5004 MVT NewEltVT = NVT.getVectorElementType();
5006 // Handle bitcasts to different vector type with the same total bit size.
5008 // e.g. v2i64 = scalar_to_vector x:i64
5010 // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
5013 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
5014 SDValue Val = Node->getOperand(0);
5017 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
5018 SDValue Undef = DAG.getUNDEF(MidVT);
5020 SmallVector<SDValue, 8> NewElts;
5021 NewElts.push_back(CastVal);
5022 for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
5023 NewElts.push_back(Undef);
5025 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
5026 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
5027 Results.push_back(CvtVec);
5030 case ISD::ATOMIC_SWAP: {
5031 AtomicSDNode *AM = cast<AtomicSDNode>(Node);
5033 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NVT, AM->getVal());
5034 assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
5035 "unexpected promotion type");
5036 assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
5037 "unexpected atomic_swap with illegal type");
5040 = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, NVT,
5041 DAG.getVTList(NVT, MVT::Other),
5042 { AM->getChain(), AM->getBasePtr(), CastVal },
5043 AM->getMemOperand());
5044 Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewAtomic));
5045 Results.push_back(NewAtomic.getValue(1));
5050 // Replace the original node with the legalized result.
5051 if (!Results.empty()) {
5052 LLVM_DEBUG(dbgs() << "Successfully promoted node\n");
5053 ReplaceNode(Node, Results.data());
5055 LLVM_DEBUG(dbgs() << "Could not promote node\n");
5058 /// This is the entry point for the file.
5059 void SelectionDAG::Legalize() {
5060 AssignTopologicalOrder();
5062 SmallPtrSet<SDNode *, 16> LegalizedNodes;
5063 // Use a delete listener to remove nodes which were deleted during
5064 // legalization from LegalizeNodes. This is needed to handle the situation
5065 // where a new node is allocated by the object pool to the same address of a
5066 // previously deleted node.
5067 DAGNodeDeletedListener DeleteListener(
5069 [&LegalizedNodes](SDNode *N, SDNode *E) { LegalizedNodes.erase(N); });
5071 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
5073 // Visit all the nodes. We start in topological order, so that we see
5074 // nodes with their original operands intact. Legalization can produce
5075 // new nodes which may themselves need to be legalized. Iterate until all
5076 // nodes have been legalized.
5078 bool AnyLegalized = false;
5079 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
5083 if (N->use_empty() && N != getRoot().getNode()) {
5089 if (LegalizedNodes.insert(N).second) {
5090 AnyLegalized = true;
5091 Legalizer.LegalizeOp(N);
5093 if (N->use_empty() && N != getRoot().getNode()) {
5104 // Remove dead nodes now.
5108 bool SelectionDAG::LegalizeOp(SDNode *N,
5109 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
5110 SmallPtrSet<SDNode *, 16> LegalizedNodes;
5111 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
5113 // Directly insert the node in question, and legalize it. This will recurse
5114 // as needed through operands.
5115 LegalizedNodes.insert(N);
5116 Legalizer.LegalizeOp(N);
5118 return LegalizedNodes.count(N);