1 /****************************************************************************
2 * Copyright (C) 2003-2006 by XGI Technology, Taiwan.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation on the rights to use, copy, modify, merge,
10 * publish, distribute, sublicense, and/or sell copies of the Software,
11 * and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * XGI AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 ***************************************************************************/
31 void xgi_gart_flush(struct drm_device *dev)
33 struct xgi_info *const info = dev->dev_private;
39 temp = DRM_READ8(info->mmio_map, 0xB00C);
40 DRM_WRITE8(info->mmio_map, 0xB00C, temp & ~0x02);
42 /* Set GART base address to HW */
43 DRM_WRITE32(info->mmio_map, 0xB034, info->gart_info.bus_addr);
45 /* Flush GART table. */
46 DRM_WRITE8(info->mmio_map, 0xB03F, 0x40);
47 DRM_WRITE8(info->mmio_map, 0xB03F, 0x00);
51 int xgi_pcie_heap_init(struct xgi_info * info)
55 struct drm_scatter_gather request;
57 /* Get current FB aperture size */
58 temp = IN3X5B(info->mmio_map, 0x27);
59 DRM_INFO("In3x5(0x27): 0x%x \n", temp);
61 if (temp & 0x01) { /* 256MB; Jong 06/05/2006; 0x10000000 */
62 info->pcie.base = 256 * 1024 * 1024;
63 } else { /* 128MB; Jong 06/05/2006; 0x08000000 */
64 info->pcie.base = 128 * 1024 * 1024;
68 DRM_INFO("info->pcie.base: 0x%lx\n", (unsigned long) info->pcie.base);
70 /* Get current lookup table page size */
71 temp = DRM_READ8(info->mmio_map, 0xB00C);
72 if (temp & 0x04) { /* 8KB */
73 info->lutPageSize = 8 * 1024;
75 info->lutPageSize = 4 * 1024;
78 DRM_INFO("info->lutPageSize: 0x%x \n", info->lutPageSize);
81 request.size = info->pcie.size;
82 err = drm_sg_alloc(info->dev, & request);
84 DRM_ERROR("cannot allocate PCIE GART backing store! "
85 "size = %d\n", info->pcie.size);
89 info->gart_info.table_mask = DMA_BIT_MASK(32);
90 info->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
91 info->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
92 info->gart_info.table_size = info->dev->sg->pages * sizeof(u32);
94 if (!drm_ati_pcigart_init(info->dev, &info->gart_info)) {
95 DRM_ERROR("failed to init PCI GART!\n");
100 xgi_gart_flush(info->dev);
102 mutex_lock(&info->dev->struct_mutex);
103 err = drm_sman_set_range(&info->sman, XGI_MEMLOC_NON_LOCAL,
105 mutex_unlock(&info->dev->struct_mutex);
107 drm_ati_pcigart_cleanup(info->dev, &info->gart_info);
110 info->pcie_heap_initialized = (err == 0);
117 * @address: GE HW address
119 * Returns CPU virtual address. Assumes the CPU VAddr is continuous in not
122 void *xgi_find_pcie_virt(struct xgi_info * info, u32 address)
124 const unsigned long offset = address - info->pcie.base;
126 return ((u8 *) info->dev->sg->virtual) + offset;