2 /****************************************************************************
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3 * Copyright (C) 2003-2006 by XGI Technology, Taiwan.
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5 * All Rights Reserved. *
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7 * Permission is hereby granted, free of charge, to any person obtaining
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8 * a copy of this software and associated documentation files (the
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9 * "Software"), to deal in the Software without restriction, including
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10 * without limitation on the rights to use, copy, modify, merge,
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11 * publish, distribute, sublicense, and/or sell copies of the Software,
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12 * and to permit persons to whom the Software is furnished to do so,
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13 * subject to the following conditions:
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15 * The above copyright notice and this permission notice (including the
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16 * next paragraph) shall be included in all copies or substantial
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17 * portions of the Software.
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19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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22 * NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
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23 * ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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26 * DEALINGS IN THE SOFTWARE.
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27 ***************************************************************************/
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32 #define XGI_MAJOR_VERSION 0
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33 #define XGI_MINOR_VERSION 7
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34 #define XGI_PATCHLEVEL 5
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36 #define XGI_DRV_VERSION "0.7.5"
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38 #ifndef XGI_DRV_NAME
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39 #define XGI_DRV_NAME "xgi"
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43 * xgi reserved major device number, Set this to 0 to
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44 * request dynamic major number allocation.
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46 #ifndef XGI_DEV_MAJOR
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47 #define XGI_DEV_MAJOR 0
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50 #ifndef XGI_MAX_DEVICES
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51 #define XGI_MAX_DEVICES 1
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54 /* Jong 06/06/2006 */
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55 /* #define XGI_DEBUG */
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57 #ifndef PCI_VENDOR_ID_XGI
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59 #define PCI_VENDOR_ID_XGI 0x1023
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61 #define PCI_VENDOR_ID_XGI 0x18CA
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65 #ifndef PCI_DEVICE_ID_XP5
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66 #define PCI_DEVICE_ID_XP5 0x2200
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69 #ifndef PCI_DEVICE_ID_XG47
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70 #define PCI_DEVICE_ID_XG47 0x0047
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73 /* Macros to make printk easier */
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74 #define XGI_ERROR(fmt, arg...) \
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75 printk(KERN_ERR "[" XGI_DRV_NAME ":%s] *ERROR* " fmt, __FUNCTION__, ##arg)
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77 #define XGI_MEM_ERROR(area, fmt, arg...) \
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78 printk(KERN_ERR "[" XGI_DRV_NAME ":%s] *ERROR* " fmt, __FUNCTION__, ##arg)
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80 /* #define XGI_DEBUG */
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83 #define XGI_INFO(fmt, arg...) \
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84 printk(KERN_ALERT "[" XGI_DRV_NAME ":%s] " fmt, __FUNCTION__, ##arg)
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85 /* printk(KERN_INFO "[" XGI_DRV_NAME ":%s] " fmt, __FUNCTION__, ##arg) */
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87 #define XGI_INFO(fmt, arg...) do { } while (0)
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90 /* device name length; must be atleast 8 */
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91 #define XGI_DEVICE_NAME_LENGTH 40
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93 /* need a fake device number for control device; just to flag it for msgs */
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94 #define XGI_CONTROL_DEVICE_NUMBER 100
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97 U32 base; // pcie base is different from fb base
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102 typedef struct xgi_screen_info_s {
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108 } xgi_screen_info_t;
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110 typedef struct xgi_sarea_info_s {
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113 } xgi_sarea_info_t;
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115 typedef struct xgi_info_s {
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116 struct pci_dev *dev;
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119 int bus; /* PCI config info */
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125 /* physical characteristics */
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126 xgi_aperture_t mmio;
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128 xgi_aperture_t pcie;
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129 xgi_screen_info_t scrn_info;
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130 xgi_sarea_info_t sarea_info;
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132 /* look up table parameters */
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143 atomic_t use_count;
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145 /* keep track of any pending bottom halfes */
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146 struct tasklet_struct tasklet;
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148 spinlock_t info_lock;
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150 struct semaphore info_sem;
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151 struct semaphore fb_sem;
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152 struct semaphore pcie_sem;
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155 typedef struct xgi_ioctl_post_vbios {
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158 } xgi_ioctl_post_vbios_t;
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160 typedef enum xgi_mem_location_s
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164 INVALID = 0x7fffffff
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165 } xgi_mem_location_t;
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171 PCIE_3D should not begin with 1,
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172 2D alloc pcie memory will use owner 1.
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174 PCIE_3D = 11,/*vetex buf*/
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175 PCIE_3D_CMDLIST = 12,
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176 PCIE_3D_SCRATCHPAD = 13,
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177 PCIE_3D_TEXTURE = 14,
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178 PCIE_INVALID = 0x7fffffff
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181 typedef struct xgi_mem_req_s {
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182 xgi_mem_location_t location;
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183 unsigned long size;
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184 unsigned long is_front;
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185 enum PcieOwner owner;
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189 typedef struct xgi_mem_alloc_s {
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190 xgi_mem_location_t location;
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191 unsigned long size;
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192 unsigned long bus_addr;
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193 unsigned long hw_addr;
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197 typedef struct xgi_chip_info_s {
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199 char device_name[32];
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201 U32 curr_display_mode; //Singe, DualView(Contained), MHS
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203 U32 sarea_bus_addr;
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207 typedef struct xgi_opengl_cmd_s {
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209 } xgi_opengl_cmd_t;
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211 typedef struct xgi_mmio_info_s {
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212 xgi_opengl_cmd_t cmd_head;
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222 BTYPE_NONE = 0x7fffffff
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225 typedef struct xgi_cmd_info_s {
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226 BATCH_TYPE _firstBeginType;
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227 U32 _firstBeginAddr;
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230 U32 _lastBeginAddr;
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234 typedef struct xgi_state_info_s {
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237 } xgi_state_info_t;
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239 typedef struct cpu_info_s {
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246 typedef struct xgi_mem_pid_s {
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247 struct list_head list;
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248 xgi_mem_location_t location;
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249 unsigned long bus_addr;
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254 * Ioctl definitions
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257 #define XGI_IOCTL_MAGIC 'x' /* use 'x' as magic number */
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259 #define XGI_IOCTL_BASE 0
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260 #define XGI_ESC_DEVICE_INFO (XGI_IOCTL_BASE + 0)
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261 #define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 1)
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263 #define XGI_ESC_FB_INIT (XGI_IOCTL_BASE + 2)
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264 #define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 3)
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265 #define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 4)
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266 #define XGI_ESC_PCIE_INIT (XGI_IOCTL_BASE + 5)
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267 #define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 6)
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268 #define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 7)
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269 #define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 8)
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270 #define XGI_ESC_PUT_SCREEN_INFO (XGI_IOCTL_BASE + 9)
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271 #define XGI_ESC_GET_SCREEN_INFO (XGI_IOCTL_BASE + 10)
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272 #define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 11)
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273 #define XGI_ESC_SAREA_INFO (XGI_IOCTL_BASE + 12)
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274 #define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 13)
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275 #define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 14)
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276 #define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 16)
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277 #define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 17)
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278 #define XGI_ESC_MMIO_INFO (XGI_IOCTL_BASE + 18)
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279 #define XGI_ESC_PCIE_CHECK (XGI_IOCTL_BASE + 19)
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280 #define XGI_ESC_CPUID (XGI_IOCTL_BASE + 20)
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281 #define XGI_ESC_MEM_COLLECT (XGI_IOCTL_BASE + 21)
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283 #define XGI_IOCTL_DEVICE_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_DEVICE_INFO, xgi_chip_info_t)
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284 #define XGI_IOCTL_POST_VBIOS _IO(XGI_IOCTL_MAGIC, XGI_ESC_POST_VBIOS)
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286 #define XGI_IOCTL_FB_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_FB_INIT)
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287 #define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, xgi_mem_req_t)
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288 #define XGI_IOCTL_FB_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_FB_FREE, unsigned long)
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290 #define XGI_IOCTL_PCIE_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_INIT)
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291 #define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, xgi_mem_req_t)
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292 #define XGI_IOCTL_PCIE_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_FREE, unsigned long)
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294 #define XGI_IOCTL_PUT_SCREEN_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PUT_SCREEN_INFO, xgi_screen_info_t)
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295 #define XGI_IOCTL_GET_SCREEN_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_GET_SCREEN_INFO, xgi_screen_info_t)
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297 #define XGI_IOCTL_GE_RESET _IO(XGI_IOCTL_MAGIC, XGI_ESC_GE_RESET)
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298 #define XGI_IOCTL_SAREA_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_SAREA_INFO, xgi_sarea_info_t)
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299 #define XGI_IOCTL_DUMP_REGISTER _IO(XGI_IOCTL_MAGIC, XGI_ESC_DUMP_REGISTER)
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300 #define XGI_IOCTL_DEBUG_INFO _IO(XGI_IOCTL_MAGIC, XGI_ESC_DEBUG_INFO)
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301 #define XGI_IOCTL_MMIO_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_MMIO_INFO, xgi_mmio_info_t)
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303 #define XGI_IOCTL_SUBMIT_CMDLIST _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_SUBMIT_CMDLIST, xgi_cmd_info_t)
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304 #define XGI_IOCTL_TEST_RWINKERNEL _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_TEST_RWINKERNEL, unsigned long)
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305 #define XGI_IOCTL_STATE_CHANGE _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_STATE_CHANGE, xgi_state_info_t)
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307 #define XGI_IOCTL_PCIE_CHECK _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_CHECK)
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308 #define XGI_IOCTL_CPUID _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_CPUID, cpu_info_t)
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309 #define XGI_IOCTL_MAXNR 30
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314 #define XGI_FLAG_OPEN 0x0001
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315 #define XGI_FLAG_NEEDS_POSTING 0x0002
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316 #define XGI_FLAG_WAS_POSTED 0x0004
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317 #define XGI_FLAG_CONTROL 0x0010
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318 #define XGI_FLAG_MAP_REGS_EARLY 0x0200
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320 /* mmap(2) offsets */
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322 #define IS_IO_OFFSET(info, offset, length) \
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323 (((offset) >= (info)->mmio.base) \
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324 && (((offset) + (length)) <= (info)->mmio.base + (info)->mmio.size))
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326 /* Jong 06/14/2006 */
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327 /* (info)->fb.base is a base address for physical (bus) address space */
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328 /* what's the definition of offest? on physical (bus) address space or HW address space */
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329 /* Jong 06/15/2006; use HW address space */
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330 #define IS_FB_OFFSET(info, offset, length) \
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332 && (((offset) + (length)) <= (info)->fb.size))
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334 #define IS_FB_OFFSET(info, offset, length) \
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335 (((offset) >= (info)->fb.base) \
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336 && (((offset) + (length)) <= (info)->fb.base + (info)->fb.size))
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339 #define IS_PCIE_OFFSET(info, offset, length) \
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340 (((offset) >= (info)->pcie.base) \
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341 && (((offset) + (length)) <= (info)->pcie.base + (info)->pcie.size))
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343 extern int xgi_fb_heap_init(xgi_info_t *info);
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344 extern void xgi_fb_heap_cleanup(xgi_info_t *info);
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346 extern void xgi_fb_alloc(xgi_info_t *info, xgi_mem_req_t *req, xgi_mem_alloc_t *alloc);
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347 extern void xgi_fb_free(xgi_info_t *info, unsigned long offset);
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348 extern void xgi_mem_collect(xgi_info_t *info, unsigned int *pcnt);
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350 extern int xgi_pcie_heap_init(xgi_info_t *info);
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351 extern void xgi_pcie_heap_cleanup(xgi_info_t *info);
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353 extern void xgi_pcie_alloc(xgi_info_t *info, unsigned long size, enum PcieOwner owner, xgi_mem_alloc_t *alloc);
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354 extern void xgi_pcie_free(xgi_info_t *info, unsigned long offset);
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355 extern void xgi_pcie_heap_check(void);
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356 extern void *xgi_find_pcie_block(xgi_info_t *info, unsigned long address);
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357 extern void *xgi_find_pcie_virt(xgi_info_t *info, unsigned long address);
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359 extern void xgi_read_pcie_mem(xgi_info_t *info, xgi_mem_req_t *req);
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360 extern void xgi_write_pcie_mem(xgi_info_t *info, xgi_mem_req_t *req);
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362 extern void xgi_test_rwinkernel(xgi_info_t *info, unsigned long address);
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