2 /****************************************************************************
3 * Copyright (C) 2003-2006 by XGI Technology, Taiwan.
5 * All Rights Reserved. *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
23 * ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 ***************************************************************************/
32 #define XGI_MAJOR_VERSION 0
33 #define XGI_MINOR_VERSION 7
34 #define XGI_PATCHLEVEL 5
36 #define XGI_DRV_VERSION "0.7.5"
39 #define XGI_DRV_NAME "xgi"
43 * xgi reserved major device number, Set this to 0 to
44 * request dynamic major number allocation.
47 #define XGI_DEV_MAJOR 0
50 #ifndef XGI_MAX_DEVICES
51 #define XGI_MAX_DEVICES 1
55 /* #define XGI_DEBUG */
57 #ifndef PCI_VENDOR_ID_XGI
59 #define PCI_VENDOR_ID_XGI 0x1023
61 #define PCI_VENDOR_ID_XGI 0x18CA
65 #ifndef PCI_DEVICE_ID_XP5
66 #define PCI_DEVICE_ID_XP5 0x2200
69 #ifndef PCI_DEVICE_ID_XG47
70 #define PCI_DEVICE_ID_XG47 0x0047
73 /* Macros to make printk easier */
74 #define XGI_ERROR(fmt, arg...) \
75 printk(KERN_ERR "[" XGI_DRV_NAME ":%s] *ERROR* " fmt, __FUNCTION__, ##arg)
77 #define XGI_MEM_ERROR(area, fmt, arg...) \
78 printk(KERN_ERR "[" XGI_DRV_NAME ":%s] *ERROR* " fmt, __FUNCTION__, ##arg)
80 /* #define XGI_DEBUG */
83 #define XGI_INFO(fmt, arg...) \
84 printk(KERN_ALERT "[" XGI_DRV_NAME ":%s] " fmt, __FUNCTION__, ##arg)
85 /* printk(KERN_INFO "[" XGI_DRV_NAME ":%s] " fmt, __FUNCTION__, ##arg) */
87 #define XGI_INFO(fmt, arg...) do { } while (0)
90 /* device name length; must be atleast 8 */
91 #define XGI_DEVICE_NAME_LENGTH 40
93 /* need a fake device number for control device; just to flag it for msgs */
94 #define XGI_CONTROL_DEVICE_NUMBER 100
97 U32 base; // pcie base is different from fb base
102 typedef struct xgi_screen_info_s {
110 typedef struct xgi_sarea_info_s {
115 typedef struct xgi_info_s {
119 int bus; /* PCI config info */
125 /* physical characteristics */
129 xgi_screen_info_t scrn_info;
130 xgi_sarea_info_t sarea_info;
132 /* look up table parameters */
145 /* keep track of any pending bottom halfes */
146 struct tasklet_struct tasklet;
148 spinlock_t info_lock;
150 struct semaphore info_sem;
151 struct semaphore fb_sem;
152 struct semaphore pcie_sem;
155 typedef struct xgi_ioctl_post_vbios {
158 } xgi_ioctl_post_vbios_t;
160 typedef enum xgi_mem_location_s {
164 } xgi_mem_location_t;
169 PCIE_3D should not begin with 1,
170 2D alloc pcie memory will use owner 1.
172 PCIE_3D = 11, /*vetex buf */
173 PCIE_3D_CMDLIST = 12,
174 PCIE_3D_SCRATCHPAD = 13,
175 PCIE_3D_TEXTURE = 14,
176 PCIE_INVALID = 0x7fffffff
179 typedef struct xgi_mem_req_s {
180 xgi_mem_location_t location;
182 unsigned long is_front;
183 enum PcieOwner owner;
187 typedef struct xgi_mem_alloc_s {
188 xgi_mem_location_t location;
190 unsigned long bus_addr;
191 unsigned long hw_addr;
195 typedef struct xgi_chip_info_s {
197 char device_name[32];
199 U32 curr_display_mode; //Singe, DualView(Contained), MHS
205 typedef struct xgi_opengl_cmd_s {
209 typedef struct xgi_mmio_info_s {
210 xgi_opengl_cmd_t cmd_head;
220 BTYPE_NONE = 0x7fffffff
223 typedef struct xgi_cmd_info_s {
224 BATCH_TYPE _firstBeginType;
232 typedef struct xgi_state_info_s {
237 typedef struct cpu_info_s {
244 typedef struct xgi_mem_pid_s {
245 struct list_head list;
246 xgi_mem_location_t location;
247 unsigned long bus_addr;
255 #define XGI_IOCTL_MAGIC 'x' /* use 'x' as magic number */
257 #define XGI_IOCTL_BASE 0
258 #define XGI_ESC_DEVICE_INFO (XGI_IOCTL_BASE + 0)
259 #define XGI_ESC_POST_VBIOS (XGI_IOCTL_BASE + 1)
261 #define XGI_ESC_FB_INIT (XGI_IOCTL_BASE + 2)
262 #define XGI_ESC_FB_ALLOC (XGI_IOCTL_BASE + 3)
263 #define XGI_ESC_FB_FREE (XGI_IOCTL_BASE + 4)
264 #define XGI_ESC_PCIE_INIT (XGI_IOCTL_BASE + 5)
265 #define XGI_ESC_PCIE_ALLOC (XGI_IOCTL_BASE + 6)
266 #define XGI_ESC_PCIE_FREE (XGI_IOCTL_BASE + 7)
267 #define XGI_ESC_SUBMIT_CMDLIST (XGI_IOCTL_BASE + 8)
268 #define XGI_ESC_PUT_SCREEN_INFO (XGI_IOCTL_BASE + 9)
269 #define XGI_ESC_GET_SCREEN_INFO (XGI_IOCTL_BASE + 10)
270 #define XGI_ESC_GE_RESET (XGI_IOCTL_BASE + 11)
271 #define XGI_ESC_SAREA_INFO (XGI_IOCTL_BASE + 12)
272 #define XGI_ESC_DUMP_REGISTER (XGI_IOCTL_BASE + 13)
273 #define XGI_ESC_DEBUG_INFO (XGI_IOCTL_BASE + 14)
274 #define XGI_ESC_TEST_RWINKERNEL (XGI_IOCTL_BASE + 16)
275 #define XGI_ESC_STATE_CHANGE (XGI_IOCTL_BASE + 17)
276 #define XGI_ESC_MMIO_INFO (XGI_IOCTL_BASE + 18)
277 #define XGI_ESC_PCIE_CHECK (XGI_IOCTL_BASE + 19)
278 #define XGI_ESC_CPUID (XGI_IOCTL_BASE + 20)
279 #define XGI_ESC_MEM_COLLECT (XGI_IOCTL_BASE + 21)
281 #define XGI_IOCTL_DEVICE_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_DEVICE_INFO, xgi_chip_info_t)
282 #define XGI_IOCTL_POST_VBIOS _IO(XGI_IOCTL_MAGIC, XGI_ESC_POST_VBIOS)
284 #define XGI_IOCTL_FB_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_FB_INIT)
285 #define XGI_IOCTL_FB_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_FB_ALLOC, xgi_mem_req_t)
286 #define XGI_IOCTL_FB_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_FB_FREE, unsigned long)
288 #define XGI_IOCTL_PCIE_INIT _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_INIT)
289 #define XGI_IOCTL_PCIE_ALLOC _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_ALLOC, xgi_mem_req_t)
290 #define XGI_IOCTL_PCIE_FREE _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_FREE, unsigned long)
292 #define XGI_IOCTL_PUT_SCREEN_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_PUT_SCREEN_INFO, xgi_screen_info_t)
293 #define XGI_IOCTL_GET_SCREEN_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_GET_SCREEN_INFO, xgi_screen_info_t)
295 #define XGI_IOCTL_GE_RESET _IO(XGI_IOCTL_MAGIC, XGI_ESC_GE_RESET)
296 #define XGI_IOCTL_SAREA_INFO _IOW(XGI_IOCTL_MAGIC, XGI_ESC_SAREA_INFO, xgi_sarea_info_t)
297 #define XGI_IOCTL_DUMP_REGISTER _IO(XGI_IOCTL_MAGIC, XGI_ESC_DUMP_REGISTER)
298 #define XGI_IOCTL_DEBUG_INFO _IO(XGI_IOCTL_MAGIC, XGI_ESC_DEBUG_INFO)
299 #define XGI_IOCTL_MMIO_INFO _IOR(XGI_IOCTL_MAGIC, XGI_ESC_MMIO_INFO, xgi_mmio_info_t)
301 #define XGI_IOCTL_SUBMIT_CMDLIST _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_SUBMIT_CMDLIST, xgi_cmd_info_t)
302 #define XGI_IOCTL_TEST_RWINKERNEL _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_TEST_RWINKERNEL, unsigned long)
303 #define XGI_IOCTL_STATE_CHANGE _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_STATE_CHANGE, xgi_state_info_t)
305 #define XGI_IOCTL_PCIE_CHECK _IO(XGI_IOCTL_MAGIC, XGI_ESC_PCIE_CHECK)
306 #define XGI_IOCTL_CPUID _IOWR(XGI_IOCTL_MAGIC, XGI_ESC_CPUID, cpu_info_t)
307 #define XGI_IOCTL_MAXNR 30
312 #define XGI_FLAG_OPEN 0x0001
313 #define XGI_FLAG_NEEDS_POSTING 0x0002
314 #define XGI_FLAG_WAS_POSTED 0x0004
315 #define XGI_FLAG_CONTROL 0x0010
316 #define XGI_FLAG_MAP_REGS_EARLY 0x0200
318 /* mmap(2) offsets */
320 #define IS_IO_OFFSET(info, offset, length) \
321 (((offset) >= (info)->mmio.base) \
322 && (((offset) + (length)) <= (info)->mmio.base + (info)->mmio.size))
324 /* Jong 06/14/2006 */
325 /* (info)->fb.base is a base address for physical (bus) address space */
326 /* what's the definition of offest? on physical (bus) address space or HW address space */
327 /* Jong 06/15/2006; use HW address space */
328 #define IS_FB_OFFSET(info, offset, length) \
330 && (((offset) + (length)) <= (info)->fb.size))
332 #define IS_FB_OFFSET(info, offset, length) \
333 (((offset) >= (info)->fb.base) \
334 && (((offset) + (length)) <= (info)->fb.base + (info)->fb.size))
337 #define IS_PCIE_OFFSET(info, offset, length) \
338 (((offset) >= (info)->pcie.base) \
339 && (((offset) + (length)) <= (info)->pcie.base + (info)->pcie.size))
341 extern int xgi_fb_heap_init(xgi_info_t * info);
342 extern void xgi_fb_heap_cleanup(xgi_info_t * info);
344 extern void xgi_fb_alloc(xgi_info_t * info, xgi_mem_req_t * req,
345 xgi_mem_alloc_t * alloc);
346 extern void xgi_fb_free(xgi_info_t * info, unsigned long offset);
347 extern void xgi_mem_collect(xgi_info_t * info, unsigned int *pcnt);
349 extern int xgi_pcie_heap_init(xgi_info_t * info);
350 extern void xgi_pcie_heap_cleanup(xgi_info_t * info);
352 extern void xgi_pcie_alloc(xgi_info_t * info, unsigned long size,
353 enum PcieOwner owner, xgi_mem_alloc_t * alloc);
354 extern void xgi_pcie_free(xgi_info_t * info, unsigned long offset);
355 extern void xgi_pcie_heap_check(void);
356 extern struct xgi_pcie_block_s *xgi_find_pcie_block(xgi_info_t * info,
357 unsigned long address);
358 extern void *xgi_find_pcie_virt(xgi_info_t * info, unsigned long address);
360 extern void xgi_read_pcie_mem(xgi_info_t * info, xgi_mem_req_t * req);
361 extern void xgi_write_pcie_mem(xgi_info_t * info, xgi_mem_req_t * req);
363 extern void xgi_test_rwinkernel(xgi_info_t * info, unsigned long address);