1 /****************************************************************************
2 * Copyright (C) 2003-2006 by XGI Technology, Taiwan.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation on the rights to use, copy, modify, merge,
10 * publish, distribute, sublicense, and/or sell copies of the Software,
11 * and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * XGI AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 ***************************************************************************/
32 #include "xgi_cmdlist.h"
34 #include "drm_pciids.h"
36 static struct pci_device_id pciidlist[] = {
40 extern struct drm_fence_driver xgi_fence_driver;
42 int xgi_bootstrap(struct drm_device *, void *, struct drm_file *);
44 static struct drm_ioctl_desc xgi_ioctls[] = {
45 DRM_IOCTL_DEF(DRM_XGI_BOOTSTRAP, xgi_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
46 DRM_IOCTL_DEF(DRM_XGI_ALLOC, xgi_alloc_ioctl, DRM_AUTH),
47 DRM_IOCTL_DEF(DRM_XGI_FREE, xgi_free_ioctl, DRM_AUTH),
48 DRM_IOCTL_DEF(DRM_XGI_SUBMIT_CMDLIST, xgi_submit_cmdlist, DRM_AUTH),
49 DRM_IOCTL_DEF(DRM_XGI_STATE_CHANGE, xgi_state_change_ioctl, DRM_AUTH|DRM_MASTER),
52 static const int xgi_max_ioctl = DRM_ARRAY_SIZE(xgi_ioctls);
54 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
55 static int xgi_driver_load(struct drm_device *dev, unsigned long flags);
56 static int xgi_driver_unload(struct drm_device *dev);
57 static void xgi_driver_lastclose(struct drm_device * dev);
58 static void xgi_reclaim_buffers_locked(struct drm_device * dev,
59 struct drm_file * filp);
60 static irqreturn_t xgi_kern_isr(DRM_IRQ_ARGS);
63 static struct drm_driver driver = {
65 DRIVER_PCI_DMA | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ |
66 DRIVER_IRQ_SHARED | DRIVER_SG,
67 .dev_priv_size = sizeof(struct xgi_info),
68 .load = xgi_driver_load,
69 .unload = xgi_driver_unload,
70 .lastclose = xgi_driver_lastclose,
71 .dma_quiescent = NULL,
72 .irq_preinstall = NULL,
73 .irq_postinstall = NULL,
74 .irq_uninstall = NULL,
75 .irq_handler = xgi_kern_isr,
76 .reclaim_buffers = drm_core_reclaim_buffers,
77 .reclaim_buffers_idlelocked = xgi_reclaim_buffers_locked,
78 .get_map_ofs = drm_core_get_map_ofs,
79 .get_reg_ofs = drm_core_get_reg_ofs,
86 .release = drm_release,
91 #if defined(CONFIG_COMPAT) && LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
92 .compat_ioctl = xgi_compat_ioctl,
98 .id_table = pciidlist,
100 .remove = __devexit_p(drm_cleanup_pci),
103 .fence_driver = &xgi_fence_driver,
108 .major = DRIVER_MAJOR,
109 .minor = DRIVER_MINOR,
110 .patchlevel = DRIVER_PATCHLEVEL,
114 static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
116 return drm_get_dev(pdev, ent, &driver);
120 static int __init xgi_init(void)
122 driver.num_ioctls = xgi_max_ioctl;
123 return drm_init(&driver, pciidlist);
126 static void __exit xgi_exit(void)
131 module_init(xgi_init);
132 module_exit(xgi_exit);
134 MODULE_AUTHOR(DRIVER_AUTHOR);
135 MODULE_DESCRIPTION(DRIVER_DESC);
136 MODULE_LICENSE("GPL and additional rights");
139 void xgi_engine_init(struct xgi_info * info)
144 OUT3C5B(info->mmio_map, 0x11, 0x92);
146 /* -------> copy from OT2D
147 * PCI Retry Control Register.
148 * disable PCI read retry & enable write retry in mem. (10xx xxxx)b
150 temp = IN3X5B(info->mmio_map, 0x55);
151 OUT3X5B(info->mmio_map, 0x55, (temp & 0xbf) | 0x80);
155 /* Enable linear addressing of the card. */
156 temp = IN3X5B(info->mmio_map, 0x21);
157 OUT3X5B(info->mmio_map, 0x21, temp | 0x20);
159 /* Enable 32-bit internal data path */
160 temp = IN3X5B(info->mmio_map, 0x2A);
161 OUT3X5B(info->mmio_map, 0x2A, temp | 0x40);
163 /* Enable PCI burst write ,disable burst read and enable MMIO. */
165 * 0x3D4.39 Enable PCI burst write, disable burst read and enable MMIO.
166 * 7 ---- Pixel Data Format 1: big endian 0: little endian
167 * 6 5 4 3---- Memory Data with Big Endian Format, BE[3:0]# with Big Endian Format
168 * 2 ---- PCI Burst Write Enable
169 * 1 ---- PCI Burst Read Enable
170 * 0 ---- MMIO Control
172 temp = IN3X5B(info->mmio_map, 0x39);
173 OUT3X5B(info->mmio_map, 0x39, (temp | 0x05) & 0xfd);
175 /* enable GEIO decode */
176 /* temp = IN3X5B(info->mmio_map, 0x29);
177 * OUT3X5B(info->mmio_map, 0x29, temp | 0x08);
180 /* Enable graphic engine I/O PCI retry function*/
181 /* temp = IN3X5B(info->mmio_map, 0x62);
182 * OUT3X5B(info->mmio_map, 0x62, temp | 0x50);
185 /* protect all register except which protected by 3c5.0e.7 */
186 /* OUT3C5B(info->mmio_map, 0x11, 0x87); */
190 int xgi_bootstrap(struct drm_device * dev, void * data,
191 struct drm_file * filp)
193 struct xgi_info *info = dev->dev_private;
194 struct xgi_bootstrap * bs = (struct xgi_bootstrap *) data;
195 struct drm_map_list *maplist;
199 DRM_SPININIT(&info->fence_lock, "fence lock");
200 info->next_sequence = 0;
201 info->complete_sequence = 0;
203 if (info->mmio_map == NULL) {
204 err = drm_addmap(dev, info->mmio.base, info->mmio.size,
205 _DRM_REGISTERS, _DRM_KERNEL,
208 DRM_ERROR("Unable to map MMIO region: %d\n", err);
212 xgi_enable_mmio(info);
213 xgi_engine_init(info);
217 info->fb.size = IN3CFB(info->mmio_map, 0x54) * 8 * 1024 * 1024;
219 DRM_INFO("fb base: 0x%lx, size: 0x%x (probed)\n",
220 (unsigned long) info->fb.base, info->fb.size);
223 if ((info->fb.base == 0) || (info->fb.size == 0)) {
224 DRM_ERROR("framebuffer appears to be wrong: 0x%lx 0x%x\n",
225 (unsigned long) info->fb.base, info->fb.size);
230 /* Init the resource manager */
231 if (!info->fb_heap_initialized) {
232 err = xgi_fb_heap_init(info);
234 DRM_ERROR("Unable to initialize FB heap.\n");
240 info->pcie.size = bs->gart.size;
242 /* Init the resource manager */
243 if (!info->pcie_heap_initialized) {
244 err = xgi_pcie_heap_init(info);
246 DRM_ERROR("Unable to initialize GART heap.\n");
250 /* Alloc 1M bytes for cmdbuffer which is flush2D batch array */
251 err = xgi_cmdlist_initialize(info, 0x100000, filp);
253 DRM_ERROR("xgi_cmdlist_initialize() failed\n");
259 if (info->pcie_map == NULL) {
260 err = drm_addmap(info->dev, 0, info->pcie.size,
261 _DRM_SCATTER_GATHER, _DRM_LOCKED,
264 DRM_ERROR("Could not add map for GART backing "
271 maplist = drm_find_matching_map(dev, info->pcie_map);
272 if (maplist == NULL) {
273 DRM_ERROR("Could not find GART backing store map.\n");
277 bs->gart = *info->pcie_map;
278 bs->gart.handle = (void *)(unsigned long) maplist->user_token;
283 void xgi_driver_lastclose(struct drm_device * dev)
285 struct xgi_info * info = dev->dev_private;
288 if (info->mmio_map != NULL) {
289 xgi_cmdlist_cleanup(info);
290 xgi_disable_ge(info);
291 xgi_disable_mmio(info);
294 /* The core DRM lastclose routine will destroy all of our
295 * mappings for us. NULL out the pointers here so that
296 * xgi_bootstrap can do the right thing.
298 info->pcie_map = NULL;
299 info->mmio_map = NULL;
302 if (info->pcie_heap_initialized) {
303 drm_ati_pcigart_cleanup(dev, &info->gart_info);
306 if (info->fb_heap_initialized
307 || info->pcie_heap_initialized) {
308 drm_sman_cleanup(&info->sman);
310 info->fb_heap_initialized = false;
311 info->pcie_heap_initialized = false;
317 void xgi_reclaim_buffers_locked(struct drm_device * dev,
318 struct drm_file * filp)
320 struct xgi_info * info = dev->dev_private;
322 mutex_lock(&info->dev->struct_mutex);
323 if (drm_sman_owner_clean(&info->sman, (unsigned long) filp)) {
324 mutex_unlock(&info->dev->struct_mutex);
328 if (dev->driver->dma_quiescent) {
329 dev->driver->dma_quiescent(dev);
332 drm_sman_owner_cleanup(&info->sman, (unsigned long) filp);
333 mutex_unlock(&info->dev->struct_mutex);
339 * driver receives an interrupt if someone waiting, then hand it off.
341 irqreturn_t xgi_kern_isr(DRM_IRQ_ARGS)
343 struct drm_device *dev = (struct drm_device *) arg;
344 struct xgi_info *info = dev->dev_private;
345 const u32 irq_bits = le32_to_cpu(DRM_READ32(info->mmio_map,
347 + M2REG_AUTO_LINK_STATUS_ADDRESS)))
348 & (M2REG_ACTIVE_TIMER_INTERRUPT_MASK
349 | M2REG_ACTIVE_INTERRUPT_0_MASK
350 | M2REG_ACTIVE_INTERRUPT_2_MASK
351 | M2REG_ACTIVE_INTERRUPT_3_MASK);
355 DRM_WRITE32(info->mmio_map,
356 0x2800 + M2REG_AUTO_LINK_SETTING_ADDRESS,
357 cpu_to_le32(M2REG_AUTO_LINK_SETTING_COMMAND | irq_bits));
358 xgi_fence_handler(dev);
366 int xgi_driver_load(struct drm_device *dev, unsigned long flags)
368 struct xgi_info *info = drm_alloc(sizeof(*info), DRM_MEM_DRIVER);
374 (void) memset(info, 0, sizeof(*info));
375 dev->dev_private = info;
378 info->mmio.base = drm_get_resource_start(dev, 1);
379 info->mmio.size = drm_get_resource_len(dev, 1);
381 DRM_INFO("mmio base: 0x%lx, size: 0x%x\n",
382 (unsigned long) info->mmio.base, info->mmio.size);
385 if ((info->mmio.base == 0) || (info->mmio.size == 0)) {
386 DRM_ERROR("mmio appears to be wrong: 0x%lx 0x%x\n",
387 (unsigned long) info->mmio.base, info->mmio.size);
393 info->fb.base = drm_get_resource_start(dev, 0);
394 info->fb.size = drm_get_resource_len(dev, 0);
396 DRM_INFO("fb base: 0x%lx, size: 0x%x\n",
397 (unsigned long) info->fb.base, info->fb.size);
400 err = drm_sman_init(&info->sman, 2, 12, 8);
409 drm_free(info, sizeof(*info), DRM_MEM_DRIVER);
413 int xgi_driver_unload(struct drm_device *dev)
415 struct xgi_info * info = dev->dev_private;
417 drm_sman_takedown(&info->sman);
418 drm_free(info, sizeof(*info), DRM_MEM_DRIVER);
419 dev->dev_private = NULL;