2 /****************************************************************************
3 * Copyright (C) 2003-2006 by XGI Technology, Taiwan.
5 * All Rights Reserved. *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
23 * ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 ***************************************************************************/
29 #ifndef _XGI_CMDLIST_H_
30 #define _XGI_CMDLIST_H_
32 #define ONE_BIT_MASK 0x1
33 #define TWENTY_BIT_MASK 0xfffff
34 #define M2REG_FLUSH_2D_ENGINE_MASK (ONE_BIT_MASK<<20)
35 #define M2REG_FLUSH_3D_ENGINE_MASK TWENTY_BIT_MASK
36 #define M2REG_FLUSH_FLIP_ENGINE_MASK (ONE_BIT_MASK<<21)
37 #define BASE_3D_ENG 0x2800
38 #define M2REG_AUTO_LINK_SETTING_ADDRESS 0x10
39 #define M2REG_CLEAR_COUNTERS_MASK (ONE_BIT_MASK<<4)
40 #define M2REG_PCI_TRIGGER_MODE_MASK (ONE_BIT_MASK<<1)
41 #define BEGIN_VALID_MASK (ONE_BIT_MASK<<20)
42 #define BEGIN_LINK_ENABLE_MASK (ONE_BIT_MASK<<31)
43 #define BEGIN_BEGIN_IDENTIFICATION_MASK (TWENTY_BIT_MASK<<0)
44 #define M2REG_PCI_TRIGGER_REGISTER_ADDRESS 0x14
47 FLUSH_2D = M2REG_FLUSH_2D_ENGINE_MASK,
48 FLUSH_3D = M2REG_FLUSH_3D_ENGINE_MASK,
49 FLUSH_FLIP = M2REG_FLUSH_FLIP_ENGINE_MASK
53 AGPCMDLIST_SCRATCH_SIZE = 0x100,
54 AGPCMDLIST_BEGIN_SIZE = 0x004,
55 AGPCMDLIST_3D_SCRATCH_CMD_SIZE = 0x004,
56 AGPCMDLIST_2D_SCRATCH_CMD_SIZE = 0x00c,
57 AGPCMDLIST_FLUSH_CMD_LEN = 0x004,
58 AGPCMDLIST_DUMY_END_BATCH_LEN = AGPCMDLIST_BEGIN_SIZE
61 struct xgi_cmdring_info {
63 * Kernel space pointer to the base of the command ring.
68 * Size, in bytes, of the command ring.
73 * Base address of the command ring from the hardware's PoV.
75 unsigned int ring_hw_base;
78 * Offset, in bytes, from the base of PCI-e GART space to the start
81 unsigned long ring_gart_base;
86 * Offset, in bytes, from the start of the ring to the next available
87 * location to store a command.
89 unsigned int ring_offset;
93 extern int xgi_cmdlist_initialize(struct xgi_info * info, size_t size);
95 extern int xgi_state_change(struct xgi_info * info, unsigned int to,
98 extern void xgi_cmdlist_cleanup(struct xgi_info * info);
100 #endif /* _XGI_CMDLIST_H_ */