linux-core/via_fence.c

   1 /**************************************************************************
   2  *
   3  * Copyright (c) 2007 Tungsten Graphics, Inc., Cedar Park, TX., USA,
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  18  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  19  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  *
  26  *
  27  **************************************************************************/
  28 /*
  29  * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "via_drm.h"
  34 #include "via_drv.h"
  35
  36 /*
  37  * DRM_FENCE_TYPE_EXE guarantees that all command buffers can be evicted.
  38  * DRM_VIA_FENCE_TYPE_ACCEL guarantees that all 2D & 3D rendering is complete.
  39  */
  40
  41 static void via_fence_poll(struct drm_device *dev, uint32_t class,
  42                            uint32_t waiting_types)
  43 {
  44         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
  45         uint32_t signaled_flush_types = 0;
  46         uint32_t status;
  47
  48         if (class != 0)
  49                 return;
  50
  51         if (unlikely(!dev_priv))
  52                 return;
  53
  54         spin_lock(&dev_priv->fence_lock);
  55         if (waiting_types) {
  56
  57                 /*
  58                  * Take the idlelock. This guarantees that the next time a client tries
  59                  * to grab the lock, it will stall until the idlelock is released. This
  60                  * guarantees that eventually, the GPU engines will be idle, but nothing
  61                  * else. It cannot be used to protect the hardware.
  62                  */
  63
  64
  65                 if (!dev_priv->have_idlelock) {
  66                         drm_idlelock_take(&dev->lock);
  67                         dev_priv->have_idlelock = 1;
  68                 }
  69
  70                 /*
  71                  * Check if AGP command reader is idle.
  72                  */
  73
  74                 if (waiting_types & DRM_FENCE_TYPE_EXE)
  75                         if (VIA_READ(0x41C) & 0x80000000)
  76                                 signaled_flush_types |= DRM_FENCE_TYPE_EXE;
  77
  78                 /*
  79                  * Check VRAM command queue empty and 2D + 3D engines idle.
  80                  */
  81
  82                 if (waiting_types & DRM_VIA_FENCE_TYPE_ACCEL) {
  83                         status = VIA_READ(VIA_REG_STATUS);
  84                         if ((status & VIA_VR_QUEUE_BUSY) &&
  85                             !(status & (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)))
  86                                 signaled_flush_types |= DRM_VIA_FENCE_TYPE_ACCEL;
  87                 }
  88
  89                 if (signaled_flush_types) {
  90                         waiting_types &= ~signaled_flush_types;
  91                         if (!waiting_types && dev_priv->have_idlelock) {
  92                                 drm_idlelock_release(&dev->lock);
  93                                 dev_priv->have_idlelock = 0;
  94                         }
  95                         drm_fence_handler(dev, 0, dev_priv->emit_0_sequence,
  96                                           signaled_flush_types, 0);
  97                 }
  98         }
  99
 100         spin_unlock(&dev_priv->fence_lock);
 101
 102         return;
 103 }
 104
 105
 106 /**
 107  * Emit a fence sequence.
 108  */
 109
 110 static int via_fence_emit_sequence(struct drm_device * dev, uint32_t class, uint32_t flags,
 111                                    uint32_t * sequence, uint32_t * native_type)
 112 {
 113         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 114         int ret = 0;
 115
 116         if (!dev_priv)
 117                 return -EINVAL;
 118
 119         switch(class) {
 120         case 0: /* AGP command stream */
 121
 122                 /*
 123                  * The sequence number isn't really used by the hardware yet.
 124                  */
 125
 126                 spin_lock(&dev_priv->fence_lock);
 127                 *sequence = ++dev_priv->emit_0_sequence;
 128                 spin_unlock(&dev_priv->fence_lock);
 129
 130                 /*
 131                  * When drm_fence_handler() is called with flush type 0x01, and a
 132                  * sequence number, That means that the EXE flag is expired.
 133                  * Nothing else. No implicit flushing or other engines idle.
 134                  */
 135
 136                 *native_type = DRM_FENCE_TYPE_EXE;
 137                 break;
 138         default:
 139                 ret = -EINVAL;
 140                 break;
 141         }
 142         return ret;
 143 }
 144
 145 /**
 146  * No irq fence expirations implemented yet.
 147  * Although both the HQV engines and PCI dmablit engines signal
 148  * idle with an IRQ, we haven't implemented this yet.
 149  * This means that the drm fence manager will always poll for engine idle,
 150  * unless the caller wanting to wait for a fence object has indicated a lazy wait.
 151  */
 152
 153 static int via_fence_has_irq(struct drm_device * dev, uint32_t class,
 154                              uint32_t flags)
 155 {
 156         return 0;
 157 }
 158
 159 struct drm_fence_driver via_fence_driver = {
 160         .num_classes = 1,
 161         .wrap_diff = (1 << 30),
 162         .flush_diff = (1 << 20),
 163         .sequence_mask = 0xffffffffU,
 164         .has_irq = via_fence_has_irq,
 165         .emit = via_fence_emit_sequence,
 166         .poll = via_fence_poll,
 167         .needed_flush = NULL,
 168         .wait = NULL
 169 };