2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
31 * Kevin E. Martin <martin@xfree86.org>
32 * Rickard E. Faith <faith@valinux.com>
33 * Alan Hourihane <alanh@fairlite.demon.co.uk>
38 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
39 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
43 * RAGE 128 Software Development Manual (Technical Reference Manual P/N
44 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
48 /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
49 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
50 * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
52 #ifndef _RADEON_REG_H_
53 #define _RADEON_REG_H_
55 #define ATI_DATATYPE_VQ 0
56 #define ATI_DATATYPE_CI4 1
57 #define ATI_DATATYPE_CI8 2
58 #define ATI_DATATYPE_ARGB1555 3
59 #define ATI_DATATYPE_RGB565 4
60 #define ATI_DATATYPE_RGB888 5
61 #define ATI_DATATYPE_ARGB8888 6
62 #define ATI_DATATYPE_RGB332 7
63 #define ATI_DATATYPE_Y8 8
64 #define ATI_DATATYPE_RGB8 9
65 #define ATI_DATATYPE_CI16 10
66 #define ATI_DATATYPE_VYUY_422 11
67 #define ATI_DATATYPE_YVYU_422 12
68 #define ATI_DATATYPE_AYUV_444 14
69 #define ATI_DATATYPE_ARGB4444 15
71 /* Registers for 2D/Video/Overlay */
72 #define RADEON_ADAPTER_ID 0x0f2c /* PCI */
73 #define RADEON_AGP_BASE 0x0170
74 #define RADEON_AGP_CNTL 0x0174
75 # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
76 # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
77 # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
78 # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
79 # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
80 # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
81 # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
82 # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
83 #define RADEON_STATUS_PCI_CONFIG 0x06
84 # define RADEON_CAP_LIST 0x100000
85 #define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
86 # define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
87 # define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
88 # define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
89 # define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
90 #define RADEON_AGP_COMMAND 0x0f60 /* PCI */
91 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
92 # define RADEON_AGP_ENABLE (1<<8)
93 #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
94 #define RADEON_AGP_STATUS 0x0f5c /* PCI */
95 # define RADEON_AGP_1X_MODE 0x01
96 # define RADEON_AGP_2X_MODE 0x02
97 # define RADEON_AGP_4X_MODE 0x04
98 # define RADEON_AGP_FW_MODE 0x10
99 # define RADEON_AGP_MODE_MASK 0x17
100 # define RADEON_AGPv3_MODE 0x08
101 # define RADEON_AGPv3_4X_MODE 0x01
102 # define RADEON_AGPv3_8X_MODE 0x02
103 #define RADEON_ATTRDR 0x03c1 /* VGA */
104 #define RADEON_ATTRDW 0x03c0 /* VGA */
105 #define RADEON_ATTRX 0x03c0 /* VGA */
106 #define RADEON_AUX_SC_CNTL 0x1660
107 # define RADEON_AUX1_SC_EN (1 << 0)
108 # define RADEON_AUX1_SC_MODE_OR (0 << 1)
109 # define RADEON_AUX1_SC_MODE_NAND (1 << 1)
110 # define RADEON_AUX2_SC_EN (1 << 2)
111 # define RADEON_AUX2_SC_MODE_OR (0 << 3)
112 # define RADEON_AUX2_SC_MODE_NAND (1 << 3)
113 # define RADEON_AUX3_SC_EN (1 << 4)
114 # define RADEON_AUX3_SC_MODE_OR (0 << 5)
115 # define RADEON_AUX3_SC_MODE_NAND (1 << 5)
116 #define RADEON_AUX1_SC_BOTTOM 0x1670
117 #define RADEON_AUX1_SC_LEFT 0x1664
118 #define RADEON_AUX1_SC_RIGHT 0x1668
119 #define RADEON_AUX1_SC_TOP 0x166c
120 #define RADEON_AUX2_SC_BOTTOM 0x1680
121 #define RADEON_AUX2_SC_LEFT 0x1674
122 #define RADEON_AUX2_SC_RIGHT 0x1678
123 #define RADEON_AUX2_SC_TOP 0x167c
124 #define RADEON_AUX3_SC_BOTTOM 0x1690
125 #define RADEON_AUX3_SC_LEFT 0x1684
126 #define RADEON_AUX3_SC_RIGHT 0x1688
127 #define RADEON_AUX3_SC_TOP 0x168c
128 #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
129 #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
131 #define RADEON_BASE_CODE 0x0f0b
132 #define RADEON_BIOS_0_SCRATCH 0x0010
133 # define RADEON_FP_PANEL_SCALABLE (1 << 16)
134 # define RADEON_FP_PANEL_SCALE_EN (1 << 17)
135 # define RADEON_FP_CHIP_SCALE_EN (1 << 18)
136 # define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
137 # define RADEON_DISPLAY_ROT_MASK (3 << 28)
138 # define RADEON_DISPLAY_ROT_00 (0 << 28)
139 # define RADEON_DISPLAY_ROT_90 (1 << 28)
140 # define RADEON_DISPLAY_ROT_180 (2 << 28)
141 # define RADEON_DISPLAY_ROT_270 (3 << 28)
142 #define RADEON_BIOS_1_SCRATCH 0x0014
143 #define RADEON_BIOS_2_SCRATCH 0x0018
144 #define RADEON_BIOS_3_SCRATCH 0x001c
145 #define RADEON_BIOS_4_SCRATCH 0x0020
146 # define RADEON_CRT1_ATTACHED_MASK (3 << 0)
147 # define RADEON_CRT1_ATTACHED_MONO (1 << 0)
148 # define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
149 # define RADEON_LCD1_ATTACHED (1 << 2)
150 # define RADEON_DFP1_ATTACHED (1 << 3)
151 # define RADEON_TV1_ATTACHED_MASK (3 << 4)
152 # define RADEON_TV1_ATTACHED_COMP (1 << 4)
153 # define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
154 # define RADEON_CRT2_ATTACHED_MASK (3 << 8)
155 # define RADEON_CRT2_ATTACHED_MONO (1 << 8)
156 # define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
157 # define RADEON_DFP2_ATTACHED (1 << 11)
158 #define RADEON_BIOS_5_SCRATCH 0x0024
159 # define RADEON_LCD1_ON (1 << 0)
160 # define RADEON_CRT1_ON (1 << 1)
161 # define RADEON_TV1_ON (1 << 2)
162 # define RADEON_DFP1_ON (1 << 3)
163 # define RADEON_CRT2_ON (1 << 5)
164 # define RADEON_CV1_ON (1 << 6)
165 # define RADEON_DFP2_ON (1 << 7)
166 # define RADEON_LCD1_CRTC_MASK (1 << 8)
167 # define RADEON_LCD1_CRTC_SHIFT 8
168 # define RADEON_CRT1_CRTC_MASK (1 << 9)
169 # define RADEON_CRT1_CRTC_SHIFT 9
170 # define RADEON_TV1_CRTC_MASK (1 << 10)
171 # define RADEON_TV1_CRTC_SHIFT 10
172 # define RADEON_DFP1_CRTC_MASK (1 << 11)
173 # define RADEON_DFP1_CRTC_SHIFT 11
174 # define RADEON_CRT2_CRTC_MASK (1 << 12)
175 # define RADEON_CRT2_CRTC_SHIFT 12
176 # define RADEON_CV1_CRTC_MASK (1 << 13)
177 # define RADEON_CV1_CRTC_SHIFT 13
178 # define RADEON_DFP2_CRTC_MASK (1 << 14)
179 # define RADEON_DFP2_CRTC_SHIFT 14
180 #define RADEON_BIOS_6_SCRATCH 0x0028
181 # define RADEON_ACC_MODE_CHANGE (1 << 2)
182 # define RADEON_EXT_DESKTOP_MODE (1 << 3)
183 # define RADEON_LCD_DPMS_ON (1 << 20)
184 # define RADEON_CRT_DPMS_ON (1 << 21)
185 # define RADEON_TV_DPMS_ON (1 << 22)
186 # define RADEON_DFP_DPMS_ON (1 << 23)
187 # define RADEON_DPMS_MASK (3 << 24)
188 # define RADEON_DPMS_ON (0 << 24)
189 # define RADEON_DPMS_STANDBY (1 << 24)
190 # define RADEON_DPMS_SUSPEND (2 << 24)
191 # define RADEON_DPMS_OFF (3 << 24)
192 # define RADEON_SCREEN_BLANKING (1 << 26)
193 # define RADEON_DRIVER_CRITICAL (1 << 27)
194 # define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
195 #define RADEON_BIOS_7_SCRATCH 0x002c
196 # define RADEON_SYS_HOTKEY (1 << 10)
197 # define RADEON_DRV_LOADED (1 << 12)
198 #define RADEON_BIOS_ROM 0x0f30 /* PCI */
199 #define RADEON_BIST 0x0f0f /* PCI */
200 #define RADEON_BRUSH_DATA0 0x1480
201 #define RADEON_BRUSH_DATA1 0x1484
202 #define RADEON_BRUSH_DATA10 0x14a8
203 #define RADEON_BRUSH_DATA11 0x14ac
204 #define RADEON_BRUSH_DATA12 0x14b0
205 #define RADEON_BRUSH_DATA13 0x14b4
206 #define RADEON_BRUSH_DATA14 0x14b8
207 #define RADEON_BRUSH_DATA15 0x14bc
208 #define RADEON_BRUSH_DATA16 0x14c0
209 #define RADEON_BRUSH_DATA17 0x14c4
210 #define RADEON_BRUSH_DATA18 0x14c8
211 #define RADEON_BRUSH_DATA19 0x14cc
212 #define RADEON_BRUSH_DATA2 0x1488
213 #define RADEON_BRUSH_DATA20 0x14d0
214 #define RADEON_BRUSH_DATA21 0x14d4
215 #define RADEON_BRUSH_DATA22 0x14d8
216 #define RADEON_BRUSH_DATA23 0x14dc
217 #define RADEON_BRUSH_DATA24 0x14e0
218 #define RADEON_BRUSH_DATA25 0x14e4
219 #define RADEON_BRUSH_DATA26 0x14e8
220 #define RADEON_BRUSH_DATA27 0x14ec
221 #define RADEON_BRUSH_DATA28 0x14f0
222 #define RADEON_BRUSH_DATA29 0x14f4
223 #define RADEON_BRUSH_DATA3 0x148c
224 #define RADEON_BRUSH_DATA30 0x14f8
225 #define RADEON_BRUSH_DATA31 0x14fc
226 #define RADEON_BRUSH_DATA32 0x1500
227 #define RADEON_BRUSH_DATA33 0x1504
228 #define RADEON_BRUSH_DATA34 0x1508
229 #define RADEON_BRUSH_DATA35 0x150c
230 #define RADEON_BRUSH_DATA36 0x1510
231 #define RADEON_BRUSH_DATA37 0x1514
232 #define RADEON_BRUSH_DATA38 0x1518
233 #define RADEON_BRUSH_DATA39 0x151c
234 #define RADEON_BRUSH_DATA4 0x1490
235 #define RADEON_BRUSH_DATA40 0x1520
236 #define RADEON_BRUSH_DATA41 0x1524
237 #define RADEON_BRUSH_DATA42 0x1528
238 #define RADEON_BRUSH_DATA43 0x152c
239 #define RADEON_BRUSH_DATA44 0x1530
240 #define RADEON_BRUSH_DATA45 0x1534
241 #define RADEON_BRUSH_DATA46 0x1538
242 #define RADEON_BRUSH_DATA47 0x153c
243 #define RADEON_BRUSH_DATA48 0x1540
244 #define RADEON_BRUSH_DATA49 0x1544
245 #define RADEON_BRUSH_DATA5 0x1494
246 #define RADEON_BRUSH_DATA50 0x1548
247 #define RADEON_BRUSH_DATA51 0x154c
248 #define RADEON_BRUSH_DATA52 0x1550
249 #define RADEON_BRUSH_DATA53 0x1554
250 #define RADEON_BRUSH_DATA54 0x1558
251 #define RADEON_BRUSH_DATA55 0x155c
252 #define RADEON_BRUSH_DATA56 0x1560
253 #define RADEON_BRUSH_DATA57 0x1564
254 #define RADEON_BRUSH_DATA58 0x1568
255 #define RADEON_BRUSH_DATA59 0x156c
256 #define RADEON_BRUSH_DATA6 0x1498
257 #define RADEON_BRUSH_DATA60 0x1570
258 #define RADEON_BRUSH_DATA61 0x1574
259 #define RADEON_BRUSH_DATA62 0x1578
260 #define RADEON_BRUSH_DATA63 0x157c
261 #define RADEON_BRUSH_DATA7 0x149c
262 #define RADEON_BRUSH_DATA8 0x14a0
263 #define RADEON_BRUSH_DATA9 0x14a4
264 #define RADEON_BRUSH_SCALE 0x1470
265 #define RADEON_BRUSH_Y_X 0x1474
266 #define RADEON_BUS_CNTL 0x0030
267 # define RADEON_BUS_MASTER_DIS (1 << 6)
268 # define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
269 # define RADEON_BUS_RD_DISCARD_EN (1 << 24)
270 # define RADEON_BUS_RD_ABORT_EN (1 << 25)
271 # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
272 # define RADEON_BUS_WRT_BURST (1 << 29)
273 # define RADEON_BUS_READ_BURST (1 << 30)
274 #define RADEON_BUS_CNTL1 0x0034
275 # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
277 #define RADEON_CACHE_CNTL 0x1724
278 #define RADEON_CACHE_LINE 0x0f0c /* PCI */
279 #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
280 #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
281 #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
282 # define RADEON_SCLK_DYN_START_CNTL (1 << 15)
283 #define RADEON_CLOCK_CNTL_DATA 0x000c
284 #define RADEON_CLOCK_CNTL_INDEX 0x0008
285 # define RADEON_PLL_WR_EN (1 << 7)
286 # define RADEON_PLL_DIV_SEL (3 << 8)
287 # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
288 #define RADEON_CLK_PWRMGT_CNTL 0x0014
289 # define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
290 # define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
291 # define RADEON_ACTIVE_HILO_LAT_SHIFT 13
292 # define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
293 # define RADEON_MC_BUSY (1 << 16)
294 # define RADEON_DLL_READY (1 << 19)
295 # define RADEON_CG_NO1_DEBUG_0 (1 << 24)
296 # define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
297 # define RADEON_DYN_STOP_MODE_MASK (7 << 21)
298 # define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
299 # define RADEON_TVCLK_TURNOFF (1 << 31)
300 #define RADEON_PLL_PWRMGT_CNTL 0x0015
301 # define RADEON_TCL_BYPASS_DISABLE (1 << 20)
302 #define RADEON_CLR_CMP_CLR_3D 0x1a24
303 #define RADEON_CLR_CMP_CLR_DST 0x15c8
304 #define RADEON_CLR_CMP_CLR_SRC 0x15c4
305 #define RADEON_CLR_CMP_CNTL 0x15c0
306 # define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
307 # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
308 # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
309 #define RADEON_CLR_CMP_MASK 0x15cc
310 # define RADEON_CLR_CMP_MSK 0xffffffff
311 #define RADEON_CLR_CMP_MASK_3D 0x1A28
312 #define RADEON_COMMAND 0x0f04 /* PCI */
313 #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
314 #define RADEON_CONFIG_APER_0_BASE 0x0100
315 #define RADEON_CONFIG_APER_1_BASE 0x0104
316 #define RADEON_CONFIG_APER_SIZE 0x0108
317 #define RADEON_CONFIG_BONDS 0x00e8
318 #define RADEON_CONFIG_CNTL 0x00e0
319 # define RADEON_CFG_ATI_REV_A11 (0 << 16)
320 # define RADEON_CFG_ATI_REV_A12 (1 << 16)
321 # define RADEON_CFG_ATI_REV_A13 (2 << 16)
322 # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
323 #define RADEON_CONFIG_MEMSIZE 0x00f8
324 #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
325 #define RADEON_CONFIG_REG_1_BASE 0x010c
326 #define RADEON_CONFIG_REG_APER_SIZE 0x0110
327 #define RADEON_CONFIG_XSTRAP 0x00e4
328 #define RADEON_CONSTANT_COLOR_C 0x1d34
329 # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
330 # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
331 # define RADEON_CONSTANT_COLOR_ZERO 0x00000000
332 #define RADEON_CRC_CMDFIFO_ADDR 0x0740
333 #define RADEON_CRC_CMDFIFO_DOUT 0x0744
334 #define RADEON_GRPH_BUFFER_CNTL 0x02f0
335 # define RADEON_GRPH_START_REQ_MASK (0x7f)
336 # define RADEON_GRPH_START_REQ_SHIFT 0
337 # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
338 # define RADEON_GRPH_STOP_REQ_SHIFT 8
339 # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
340 # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
341 # define RADEON_GRPH_CRITICAL_CNTL (1<<28)
342 # define RADEON_GRPH_BUFFER_SIZE (1<<29)
343 # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
344 # define RADEON_GRPH_STOP_CNTL (1<<31)
345 #define RADEON_GRPH2_BUFFER_CNTL 0x03f0
346 # define RADEON_GRPH2_START_REQ_MASK (0x7f)
347 # define RADEON_GRPH2_START_REQ_SHIFT 0
348 # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
349 # define RADEON_GRPH2_STOP_REQ_SHIFT 8
350 # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
351 # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
352 # define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
353 # define RADEON_GRPH2_BUFFER_SIZE (1<<29)
354 # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
355 # define RADEON_GRPH2_STOP_CNTL (1<<31)
356 #define RADEON_CRTC_CRNT_FRAME 0x0214
357 #define RADEON_CRTC_EXT_CNTL 0x0054
358 # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
359 # define RADEON_VGA_ATI_LINEAR (1 << 3)
360 # define RADEON_XCRT_CNT_EN (1 << 6)
361 # define RADEON_CRTC_HSYNC_DIS (1 << 8)
362 # define RADEON_CRTC_VSYNC_DIS (1 << 9)
363 # define RADEON_CRTC_DISPLAY_DIS (1 << 10)
364 # define RADEON_CRTC_SYNC_TRISTAT (1 << 11)
365 # define RADEON_CRTC_CRT_ON (1 << 15)
366 #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
367 # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)
368 # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)
369 # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)
370 #define RADEON_CRTC_GEN_CNTL 0x0050
371 # define RADEON_CRTC_DBL_SCAN_EN (1 << 0)
372 # define RADEON_CRTC_INTERLACE_EN (1 << 1)
373 # define RADEON_CRTC_CSYNC_EN (1 << 4)
374 # define RADEON_CRTC_ICON_EN (1 << 15)
375 # define RADEON_CRTC_CUR_EN (1 << 16)
376 # define RADEON_CRTC_CUR_MODE_MASK (7 << 20)
377 # define RADEON_CRTC_EXT_DISP_EN (1 << 24)
378 # define RADEON_CRTC_EN (1 << 25)
379 # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
380 #define RADEON_CRTC2_GEN_CNTL 0x03f8
381 # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)
382 # define RADEON_CRTC2_INTERLACE_EN (1 << 1)
383 # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)
384 # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
385 # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
386 # define RADEON_CRTC2_CRT2_ON (1 << 7)
387 # define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
388 # define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)
389 # define RADEON_CRTC2_ICON_EN (1 << 15)
390 # define RADEON_CRTC2_CUR_EN (1 << 16)
391 # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
392 # define RADEON_CRTC2_DISP_DIS (1 << 23)
393 # define RADEON_CRTC2_EN (1 << 25)
394 # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)
395 # define RADEON_CRTC2_CSYNC_EN (1 << 27)
396 # define RADEON_CRTC2_HSYNC_DIS (1 << 28)
397 # define RADEON_CRTC2_VSYNC_DIS (1 << 29)
398 #define RADEON_CRTC_MORE_CNTL 0x27c
399 # define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
400 # define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
401 # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
402 # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
403 #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
404 #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
405 # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
406 # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
407 # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
408 # define RADEON_CRTC_H_SYNC_WID (0x3f << 16)
409 # define RADEON_CRTC_H_SYNC_WID_SHIFT 16
410 # define RADEON_CRTC_H_SYNC_POL (1 << 23)
411 #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304
412 # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
413 # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
414 # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
415 # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)
416 # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16
417 # define RADEON_CRTC2_H_SYNC_POL (1 << 23)
418 #define RADEON_CRTC_H_TOTAL_DISP 0x0200
419 # define RADEON_CRTC_H_TOTAL (0x03ff << 0)
420 # define RADEON_CRTC_H_TOTAL_SHIFT 0
421 # define RADEON_CRTC_H_DISP (0x01ff << 16)
422 # define RADEON_CRTC_H_DISP_SHIFT 16
423 #define RADEON_CRTC2_H_TOTAL_DISP 0x0300
424 # define RADEON_CRTC2_H_TOTAL (0x03ff << 0)
425 # define RADEON_CRTC2_H_TOTAL_SHIFT 0
426 # define RADEON_CRTC2_H_DISP (0x01ff << 16)
427 # define RADEON_CRTC2_H_DISP_SHIFT 16
429 #define RADEON_CRTC_OFFSET_RIGHT 0x0220
430 #define RADEON_CRTC_OFFSET 0x0224
431 # define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
432 # define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)
434 #define RADEON_CRTC2_OFFSET 0x0324
435 # define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
436 # define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)
437 #define RADEON_CRTC_OFFSET_CNTL 0x0228
438 # define RADEON_CRTC_TILE_LINE_SHIFT 0
439 # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4
440 # define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)
441 # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)
442 # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)
443 # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
444 # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
445 # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)
446 # define R300_CRTC_X_Y_MODE_EN (1 << 9)
447 # define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)
448 # define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)
449 # define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)
450 # define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)
451 # define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)
452 # define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)
453 # define R300_CRTC_MICRO_TILE_EN (1 << 13)
454 # define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)
455 # define R300_CRTC_MACRO_TILE_EN (1 << 15)
456 # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)
457 # define RADEON_CRTC_TILE_EN (1 << 15)
458 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
459 # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
461 #define R300_CRTC_TILE_X0_Y0 0x0350
462 #define R300_CRTC2_TILE_X0_Y0 0x0358
464 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
465 # define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)
466 # define RADEON_CRTC2_TILE_EN (1 << 15)
467 #define RADEON_CRTC_PITCH 0x022c
468 # define RADEON_CRTC_PITCH__SHIFT 0
469 # define RADEON_CRTC_PITCH__RIGHT_SHIFT 16
471 #define RADEON_CRTC2_PITCH 0x032c
472 #define RADEON_CRTC_STATUS 0x005c
473 # define RADEON_CRTC_VBLANK_SAVE (1 << 1)
474 # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)
475 #define RADEON_CRTC2_STATUS 0x03fc
476 # define RADEON_CRTC2_VBLANK_SAVE (1 << 1)
477 # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)
478 #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c
479 # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)
480 # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0
481 # define RADEON_CRTC_V_SYNC_WID (0x1f << 16)
482 # define RADEON_CRTC_V_SYNC_WID_SHIFT 16
483 # define RADEON_CRTC_V_SYNC_POL (1 << 23)
484 #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c
485 # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)
486 # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
487 # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)
488 # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16
489 # define RADEON_CRTC2_V_SYNC_POL (1 << 23)
490 #define RADEON_CRTC_V_TOTAL_DISP 0x0208
491 # define RADEON_CRTC_V_TOTAL (0x07ff << 0)
492 # define RADEON_CRTC_V_TOTAL_SHIFT 0
493 # define RADEON_CRTC_V_DISP (0x07ff << 16)
494 # define RADEON_CRTC_V_DISP_SHIFT 16
495 #define RADEON_CRTC2_V_TOTAL_DISP 0x0308
496 # define RADEON_CRTC2_V_TOTAL (0x07ff << 0)
497 # define RADEON_CRTC2_V_TOTAL_SHIFT 0
498 # define RADEON_CRTC2_V_DISP (0x07ff << 16)
499 # define RADEON_CRTC2_V_DISP_SHIFT 16
500 #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210
501 # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
502 #define RADEON_CRTC2_CRNT_FRAME 0x0314
503 #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318
504 #define RADEON_CRTC2_STATUS 0x03fc
505 #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310
506 #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
507 #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
508 #define RADEON_CUR_CLR0 0x026c
509 #define RADEON_CUR_CLR1 0x0270
510 #define RADEON_CUR_HORZ_VERT_OFF 0x0268
511 #define RADEON_CUR_HORZ_VERT_POSN 0x0264
512 #define RADEON_CUR_OFFSET 0x0260
513 # define RADEON_CUR_LOCK (1 << 31)
514 #define RADEON_CUR2_CLR0 0x036c
515 #define RADEON_CUR2_CLR1 0x0370
516 #define RADEON_CUR2_HORZ_VERT_OFF 0x0368
517 #define RADEON_CUR2_HORZ_VERT_POSN 0x0364
518 #define RADEON_CUR2_OFFSET 0x0360
519 # define RADEON_CUR2_LOCK (1 << 31)
521 #define RADEON_DAC_CNTL 0x0058
522 # define RADEON_DAC_RANGE_CNTL (3 << 0)
523 # define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)
524 # define RADEON_DAC_RANGE_CNTL_MASK 0x03
525 # define RADEON_DAC_BLANKING (1 << 2)
526 # define RADEON_DAC_CMP_EN (1 << 3)
527 # define RADEON_DAC_CMP_OUTPUT (1 << 7)
528 # define RADEON_DAC_8BIT_EN (1 << 8)
529 # define RADEON_DAC_TVO_EN (1 << 10)
530 # define RADEON_DAC_VGA_ADR_EN (1 << 13)
531 # define RADEON_DAC_PDWN (1 << 15)
532 # define RADEON_DAC_MASK_ALL (0xff << 24)
533 #define RADEON_DAC_CNTL2 0x007c
534 # define RADEON_DAC2_TV_CLK_SEL (0 << 1)
535 # define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
536 # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
537 # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
538 # define RADEON_DAC2_CMP_EN (1 << 7)
539 # define RADEON_DAC2_CMP_OUT_R (1 << 8)
540 # define RADEON_DAC2_CMP_OUT_G (1 << 9)
541 # define RADEON_DAC2_CMP_OUT_B (1 << 10)
542 # define RADEON_DAC2_CMP_OUTPUT (1 << 11)
543 #define RADEON_DAC_EXT_CNTL 0x0280
544 # define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
545 # define RADEON_DAC2_FORCE_DATA_EN (1 << 1)
546 # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
547 # define RADEON_DAC_FORCE_DATA_EN (1 << 5)
548 # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
549 # define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)
550 # define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)
551 # define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)
552 # define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)
553 # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
554 # define RADEON_DAC_FORCE_DATA_SHIFT 8
555 #define RADEON_DAC_MACRO_CNTL 0x0d04
556 # define RADEON_DAC_PDWN_R (1 << 16)
557 # define RADEON_DAC_PDWN_G (1 << 17)
558 # define RADEON_DAC_PDWN_B (1 << 18)
559 #define RADEON_TV_DAC_CNTL 0x088c
560 # define RADEON_TV_DAC_NBLANK (1 << 0)
561 # define RADEON_TV_DAC_NHOLD (1 << 1)
562 # define RADEON_TV_DAC_PEDESTAL (1 << 2)
563 # define RADEON_TV_MONITOR_DETECT_EN (1 << 4)
564 # define RADEON_TV_DAC_CMPOUT (1 << 5)
565 # define RADEON_TV_DAC_STD_MASK (3 << 8)
566 # define RADEON_TV_DAC_STD_PAL (0 << 8)
567 # define RADEON_TV_DAC_STD_NTSC (1 << 8)
568 # define RADEON_TV_DAC_STD_PS2 (2 << 8)
569 # define RADEON_TV_DAC_STD_RS343 (3 << 8)
570 # define RADEON_TV_DAC_BGSLEEP (1 << 6)
571 # define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)
572 # define RADEON_TV_DAC_BGADJ_SHIFT 16
573 # define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)
574 # define RADEON_TV_DAC_DACADJ_SHIFT 20
575 # define RADEON_TV_DAC_RDACPD (1 << 24)
576 # define RADEON_TV_DAC_GDACPD (1 << 25)
577 # define RADEON_TV_DAC_BDACPD (1 << 26)
578 # define RADEON_TV_DAC_RDACDET (1 << 29)
579 # define RADEON_TV_DAC_GDACDET (1 << 30)
580 # define RADEON_TV_DAC_BDACDET (1 << 31)
581 # define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
582 # define R420_TV_DAC_RDACPD (1 << 25)
583 # define R420_TV_DAC_GDACPD (1 << 26)
584 # define R420_TV_DAC_BDACPD (1 << 27)
585 # define R420_TV_DAC_TVENABLE (1 << 28)
586 #define RADEON_DISP_HW_DEBUG 0x0d14
587 # define RADEON_CRT2_DISP1_SEL (1 << 5)
588 #define RADEON_DISP_OUTPUT_CNTL 0x0d64
589 # define RADEON_DISP_DAC_SOURCE_MASK 0x03
590 # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
591 # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
592 # define RADEON_DISP_DAC_SOURCE_RMX 0x02
593 # define RADEON_DISP_DAC_SOURCE_LTU 0x03
594 # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
595 # define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)
596 # define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0
597 # define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
598 # define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)
599 # define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)
600 # define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)
601 # define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
602 # define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)
603 # define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)
604 # define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */
605 # define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */
606 #define RADEON_DISP_TV_OUT_CNTL 0x0d6c
607 # define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
608 # define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
609 #define RADEON_DAC_CRC_SIG 0x02cc
610 #define RADEON_DAC_DATA 0x03c9 /* VGA */
611 #define RADEON_DAC_MASK 0x03c6 /* VGA */
612 #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
613 #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
614 #define RADEON_DDA_CONFIG 0x02e0
615 #define RADEON_DDA_ON_OFF 0x02e4
616 #define RADEON_DEFAULT_OFFSET 0x16e0
617 #define RADEON_DEFAULT_PITCH 0x16e4
618 #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
619 # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
620 # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
621 #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
622 #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
623 #define RADEON_DEVICE_ID 0x0f02 /* PCI */
624 #define RADEON_DISP_MISC_CNTL 0x0d00
625 # define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
626 #define RADEON_DISP_MERGE_CNTL 0x0d60
627 # define RADEON_DISP_ALPHA_MODE_MASK 0x03
628 # define RADEON_DISP_ALPHA_MODE_KEY 0
629 # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
630 # define RADEON_DISP_ALPHA_MODE_GLOBAL 2
631 # define RADEON_DISP_RGB_OFFSET_EN (1 << 8)
632 # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
633 # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
634 # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
635 #define RADEON_DISP2_MERGE_CNTL 0x0d68
636 # define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)
637 #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
638 #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
639 #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
640 #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
641 #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
642 #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
643 #define RADEON_DP_BRUSH_BKGD_CLR 0x1478
644 #define RADEON_DP_BRUSH_FRGD_CLR 0x147c
645 #define RADEON_DP_CNTL 0x16c0
646 # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
647 # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
648 # define RADEON_DP_DST_TILE_LINEAR (0 << 3)
649 # define RADEON_DP_DST_TILE_MACRO (1 << 3)
650 # define RADEON_DP_DST_TILE_MICRO (2 << 3)
651 # define RADEON_DP_DST_TILE_BOTH (3 << 3)
652 #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
653 # define RADEON_DST_Y_MAJOR (1 << 2)
654 # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
655 # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
656 #define RADEON_DP_DATATYPE 0x16c4
657 # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
658 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
659 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
660 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
661 # define RADEON_GMC_SRC_CLIPPING (1 << 2)
662 # define RADEON_GMC_DST_CLIPPING (1 << 3)
663 # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
664 # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
665 # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
666 # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
667 # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
668 # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
669 # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
670 # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
671 # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
672 # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
673 # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
674 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
675 # define RADEON_GMC_BRUSH_NONE (15 << 4)
676 # define RADEON_GMC_DST_8BPP_CI (2 << 8)
677 # define RADEON_GMC_DST_15BPP (3 << 8)
678 # define RADEON_GMC_DST_16BPP (4 << 8)
679 # define RADEON_GMC_DST_24BPP (5 << 8)
680 # define RADEON_GMC_DST_32BPP (6 << 8)
681 # define RADEON_GMC_DST_8BPP_RGB (7 << 8)
682 # define RADEON_GMC_DST_Y8 (8 << 8)
683 # define RADEON_GMC_DST_RGB8 (9 << 8)
684 # define RADEON_GMC_DST_VYUY (11 << 8)
685 # define RADEON_GMC_DST_YVYU (12 << 8)
686 # define RADEON_GMC_DST_AYUV444 (14 << 8)
687 # define RADEON_GMC_DST_ARGB4444 (15 << 8)
688 # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
689 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
690 # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
691 # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
692 # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
693 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
694 # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
695 # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
696 # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
697 # define RADEON_GMC_CONVERSION_TEMP (1 << 15)
698 # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
699 # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
700 # define RADEON_GMC_ROP3_MASK (0xff << 16)
701 # define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
702 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
703 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
704 # define RADEON_GMC_3D_FCN_EN (1 << 27)
705 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
706 # define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
707 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
708 # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
709 # define RADEON_ROP3_ZERO 0x00000000
710 # define RADEON_ROP3_DSa 0x00880000
711 # define RADEON_ROP3_SDna 0x00440000
712 # define RADEON_ROP3_S 0x00cc0000
713 # define RADEON_ROP3_DSna 0x00220000
714 # define RADEON_ROP3_D 0x00aa0000
715 # define RADEON_ROP3_DSx 0x00660000
716 # define RADEON_ROP3_DSo 0x00ee0000
717 # define RADEON_ROP3_DSon 0x00110000
718 # define RADEON_ROP3_DSxn 0x00990000
719 # define RADEON_ROP3_Dn 0x00550000
720 # define RADEON_ROP3_SDno 0x00dd0000
721 # define RADEON_ROP3_Sn 0x00330000
722 # define RADEON_ROP3_DSno 0x00bb0000
723 # define RADEON_ROP3_DSan 0x00770000
724 # define RADEON_ROP3_ONE 0x00ff0000
725 # define RADEON_ROP3_DPa 0x00a00000
726 # define RADEON_ROP3_PDna 0x00500000
727 # define RADEON_ROP3_P 0x00f00000
728 # define RADEON_ROP3_DPna 0x000a0000
729 # define RADEON_ROP3_D 0x00aa0000
730 # define RADEON_ROP3_DPx 0x005a0000
731 # define RADEON_ROP3_DPo 0x00fa0000
732 # define RADEON_ROP3_DPon 0x00050000
733 # define RADEON_ROP3_PDxn 0x00a50000
734 # define RADEON_ROP3_PDno 0x00f50000
735 # define RADEON_ROP3_Pn 0x000f0000
736 # define RADEON_ROP3_DPno 0x00af0000
737 # define RADEON_ROP3_DPan 0x005f0000
738 #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
739 #define RADEON_DP_MIX 0x16c8
740 #define RADEON_DP_SRC_BKGD_CLR 0x15dc
741 #define RADEON_DP_SRC_FRGD_CLR 0x15d8
742 #define RADEON_DP_WRITE_MASK 0x16cc
743 #define RADEON_DST_BRES_DEC 0x1630
744 #define RADEON_DST_BRES_ERR 0x1628
745 #define RADEON_DST_BRES_INC 0x162c
746 #define RADEON_DST_BRES_LNTH 0x1634
747 #define RADEON_DST_BRES_LNTH_SUB 0x1638
748 #define RADEON_DST_HEIGHT 0x1410
749 #define RADEON_DST_HEIGHT_WIDTH 0x143c
750 #define RADEON_DST_HEIGHT_WIDTH_8 0x158c
751 #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
752 #define RADEON_DST_HEIGHT_Y 0x15a0
753 #define RADEON_DST_LINE_START 0x1600
754 #define RADEON_DST_LINE_END 0x1604
755 #define RADEON_DST_LINE_PATCOUNT 0x1608
756 # define RADEON_BRES_CNTL_SHIFT 8
757 #define RADEON_DST_OFFSET 0x1404
758 #define RADEON_DST_PITCH 0x1408
759 #define RADEON_DST_PITCH_OFFSET 0x142c
760 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
761 # define RADEON_PITCH_SHIFT 21
762 # define RADEON_DST_TILE_LINEAR (0 << 30)
763 # define RADEON_DST_TILE_MACRO (1 << 30)
764 # define RADEON_DST_TILE_MICRO (2 << 30)
765 # define RADEON_DST_TILE_BOTH (3 << 30)
766 #define RADEON_DST_WIDTH 0x140c
767 #define RADEON_DST_WIDTH_HEIGHT 0x1598
768 #define RADEON_DST_WIDTH_X 0x1588
769 #define RADEON_DST_WIDTH_X_INCY 0x159c
770 #define RADEON_DST_X 0x141c
771 #define RADEON_DST_X_SUB 0x15a4
772 #define RADEON_DST_X_Y 0x1594
773 #define RADEON_DST_Y 0x1420
774 #define RADEON_DST_Y_SUB 0x15a8
775 #define RADEON_DST_Y_X 0x1438
777 #define RADEON_FCP_CNTL 0x0910
778 # define RADEON_FCP0_SRC_PCICLK 0
779 # define RADEON_FCP0_SRC_PCLK 1
780 # define RADEON_FCP0_SRC_PCLKb 2
781 # define RADEON_FCP0_SRC_HREF 3
782 # define RADEON_FCP0_SRC_GND 4
783 # define RADEON_FCP0_SRC_HREFb 5
784 #define RADEON_FLUSH_1 0x1704
785 #define RADEON_FLUSH_2 0x1708
786 #define RADEON_FLUSH_3 0x170c
787 #define RADEON_FLUSH_4 0x1710
788 #define RADEON_FLUSH_5 0x1714
789 #define RADEON_FLUSH_6 0x1718
790 #define RADEON_FLUSH_7 0x171c
791 #define RADEON_FOG_3D_TABLE_START 0x1810
792 #define RADEON_FOG_3D_TABLE_END 0x1814
793 #define RADEON_FOG_3D_TABLE_DENSITY 0x181c
794 #define RADEON_FOG_TABLE_INDEX 0x1a14
795 #define RADEON_FOG_TABLE_DATA 0x1a18
796 #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
797 #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
798 # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
799 # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
800 # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
801 # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
802 # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
803 # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
804 # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
805 # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
806 # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
807 # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
808 # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
809 # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
810 # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
811 # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
812 # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
813 # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
814 #define RADEON_FP_GEN_CNTL 0x0284
815 # define RADEON_FP_FPON (1 << 0)
816 # define RADEON_FP_BLANK_EN (1 << 1)
817 # define RADEON_FP_TMDS_EN (1 << 2)
818 # define RADEON_FP_PANEL_FORMAT (1 << 3)
819 # define RADEON_FP_EN_TMDS (1 << 7)
820 # define RADEON_FP_DETECT_SENSE (1 << 8)
821 # define R200_FP_SOURCE_SEL_MASK (3 << 10)
822 # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
823 # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
824 # define R200_FP_SOURCE_SEL_RMX (2 << 10)
825 # define R200_FP_SOURCE_SEL_TRANS (3 << 10)
826 # define RADEON_FP_SEL_CRTC1 (0 << 13)
827 # define RADEON_FP_SEL_CRTC2 (1 << 13)
828 # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
829 # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
830 # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
831 # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
832 # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
833 # define RADEON_FP_DFP_SYNC_SEL (1 << 21)
834 # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
835 # define RADEON_FP_CRT_SYNC_SEL (1 << 23)
836 # define RADEON_FP_USE_SHADOW_EN (1 << 24)
837 # define RADEON_FP_CRT_SYNC_ALT (1 << 26)
838 #define RADEON_FP2_GEN_CNTL 0x0288
839 # define RADEON_FP2_BLANK_EN (1 << 1)
840 # define RADEON_FP2_ON (1 << 2)
841 # define RADEON_FP2_PANEL_FORMAT (1 << 3)
842 # define RADEON_FP2_DETECT_SENSE (1 << 8)
843 # define R200_FP2_SOURCE_SEL_MASK (3 << 10)
844 # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
845 # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
846 # define R200_FP2_SOURCE_SEL_RMX (2 << 10)
847 # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)
848 # define RADEON_FP2_SRC_SEL_MASK (3 << 13)
849 # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
850 # define RADEON_FP2_FP_POL (1 << 16)
851 # define RADEON_FP2_LP_POL (1 << 17)
852 # define RADEON_FP2_SCK_POL (1 << 18)
853 # define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
854 # define RADEON_FP2_PAD_FLOP_EN (1 << 22)
855 # define RADEON_FP2_CRC_EN (1 << 23)
856 # define RADEON_FP2_CRC_READ_EN (1 << 24)
857 # define RADEON_FP2_DVO_EN (1 << 25)
858 # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)
859 # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)
860 # define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)
861 # define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)
862 #define RADEON_FP_H_SYNC_STRT_WID 0x02c4
863 #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
864 #define RADEON_FP_HORZ_STRETCH 0x028c
865 #define RADEON_FP_HORZ2_STRETCH 0x038c
866 # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
867 # define RADEON_HORZ_STRETCH_RATIO_MAX 4096
868 # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
869 # define RADEON_HORZ_PANEL_SHIFT 16
870 # define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
871 # define RADEON_HORZ_STRETCH_BLEND (1 << 26)
872 # define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
873 # define RADEON_HORZ_AUTO_RATIO (1 << 27)
874 # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
875 # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
876 #define RADEON_FP_HORZ_VERT_ACTIVE 0x0278
877 #define RADEON_FP_V_SYNC_STRT_WID 0x02c8
878 #define RADEON_FP_VERT_STRETCH 0x0290
879 #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
880 #define RADEON_FP_VERT2_STRETCH 0x0390
881 # define RADEON_VERT_PANEL_SIZE (0xfff << 12)
882 # define RADEON_VERT_PANEL_SHIFT 12
883 # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
884 # define RADEON_VERT_STRETCH_RATIO_SHIFT 0
885 # define RADEON_VERT_STRETCH_RATIO_MAX 4096
886 # define RADEON_VERT_STRETCH_ENABLE (1 << 25)
887 # define RADEON_VERT_STRETCH_LINEREP (0 << 26)
888 # define RADEON_VERT_STRETCH_BLEND (1 << 26)
889 # define RADEON_VERT_AUTO_RATIO_EN (1 << 27)
890 # define RADEON_VERT_AUTO_RATIO_INC (1 << 31)
891 # define RADEON_VERT_STRETCH_RESERVED 0x71000000
892 #define RS400_FP_2ND_GEN_CNTL 0x0384
893 # define RS400_FP_2ND_ON (1 << 0)
894 # define RS400_FP_2ND_BLANK_EN (1 << 1)
895 # define RS400_TMDS_2ND_EN (1 << 2)
896 # define RS400_PANEL_FORMAT_2ND (1 << 3)
897 # define RS400_FP_2ND_EN_TMDS (1 << 7)
898 # define RS400_FP_2ND_DETECT_SENSE (1 << 8)
899 # define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)
900 # define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)
901 # define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)
902 # define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)
903 # define RS400_FP_2ND_DETECT_EN (1 << 12)
904 # define RS400_HPD_2ND_SEL (1 << 13)
905 #define RS400_FP2_2_GEN_CNTL 0x0388
906 # define RS400_FP2_2_BLANK_EN (1 << 1)
907 # define RS400_FP2_2_ON (1 << 2)
908 # define RS400_FP2_2_PANEL_FORMAT (1 << 3)
909 # define RS400_FP2_2_DETECT_SENSE (1 << 8)
910 # define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)
911 # define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)
912 # define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)
913 # define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)
914 # define RS400_FP2_2_DVO2_EN (1 << 25)
915 #define RS400_TMDS2_CNTL 0x0394
916 #define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4
917 # define RS400_TMDS2_PLLEN (1 << 0)
918 # define RS400_TMDS2_PLLRST (1 << 1)
920 #define RADEON_GEN_INT_CNTL 0x0040
921 #define RADEON_GEN_INT_STATUS 0x0044
922 # define RADEON_VSYNC_INT_AK (1 << 2)
923 # define RADEON_VSYNC_INT (1 << 2)
924 # define RADEON_VSYNC2_INT_AK (1 << 6)
925 # define RADEON_VSYNC2_INT (1 << 6)
926 #define RADEON_GENENB 0x03c3 /* VGA */
927 #define RADEON_GENFC_RD 0x03ca /* VGA */
928 #define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */
929 #define RADEON_GENMO_RD 0x03cc /* VGA */
930 #define RADEON_GENMO_WT 0x03c2 /* VGA */
931 #define RADEON_GENS0 0x03c2 /* VGA */
932 #define RADEON_GENS1 0x03da /* VGA, 0x03ba */
933 #define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */
934 #define RADEON_GPIO_MONIDB 0x006c
935 #define RADEON_GPIO_CRT2_DDC 0x006c
936 #define RADEON_GPIO_DVI_DDC 0x0064
937 #define RADEON_GPIO_VGA_DDC 0x0060
938 # define RADEON_GPIO_A_0 (1 << 0)
939 # define RADEON_GPIO_A_1 (1 << 1)
940 # define RADEON_GPIO_Y_0 (1 << 8)
941 # define RADEON_GPIO_Y_1 (1 << 9)
942 # define RADEON_GPIO_Y_SHIFT_0 8
943 # define RADEON_GPIO_Y_SHIFT_1 9
944 # define RADEON_GPIO_EN_0 (1 << 16)
945 # define RADEON_GPIO_EN_1 (1 << 17)
946 # define RADEON_GPIO_MASK_0 (1 << 24) /*??*/
947 # define RADEON_GPIO_MASK_1 (1 << 25) /*??*/
948 #define RADEON_GRPH8_DATA 0x03cf /* VGA */
949 #define RADEON_GRPH8_IDX 0x03ce /* VGA */
950 #define RADEON_GUI_SCRATCH_REG0 0x15e0
951 #define RADEON_GUI_SCRATCH_REG1 0x15e4
952 #define RADEON_GUI_SCRATCH_REG2 0x15e8
953 #define RADEON_GUI_SCRATCH_REG3 0x15ec
954 #define RADEON_GUI_SCRATCH_REG4 0x15f0
955 #define RADEON_GUI_SCRATCH_REG5 0x15f4
957 #define RADEON_HEADER 0x0f0e /* PCI */
958 #define RADEON_HOST_DATA0 0x17c0
959 #define RADEON_HOST_DATA1 0x17c4
960 #define RADEON_HOST_DATA2 0x17c8
961 #define RADEON_HOST_DATA3 0x17cc
962 #define RADEON_HOST_DATA4 0x17d0
963 #define RADEON_HOST_DATA5 0x17d4
964 #define RADEON_HOST_DATA6 0x17d8
965 #define RADEON_HOST_DATA7 0x17dc
966 #define RADEON_HOST_DATA_LAST 0x17e0
967 #define RADEON_HOST_PATH_CNTL 0x0130
968 # define RADEON_HDP_SOFT_RESET (1 << 26)
969 # define RADEON_HDP_APER_CNTL (1 << 23)
970 #define RADEON_HTOTAL_CNTL 0x0009 /* PLL */
971 # define RADEON_HTOT_CNTL_VGA_EN (1 << 28)
972 #define RADEON_HTOTAL2_CNTL 0x002e /* PLL */
974 /* Multimedia I2C bus */
975 #define RADEON_I2C_CNTL_0 0x0090
976 #define RADEON_I2C_DONE (1<<0)
977 #define RADEON_I2C_NACK (1<<1)
978 #define RADEON_I2C_HALT (1<<2)
979 #define RADEON_I2C_SOFT_RST (1<<5)
980 #define RADEON_I2C_DRIVE_EN (1<<6)
981 #define RADEON_I2C_DRIVE_SEL (1<<7)
982 #define RADEON_I2C_START (1<<8)
983 #define RADEON_I2C_STOP (1<<9)
984 #define RADEON_I2C_RECEIVE (1<<10)
985 #define RADEON_I2C_ABORT (1<<11)
986 #define RADEON_I2C_GO (1<<12)
987 #define RADEON_I2C_CNTL_1 0x0094
988 #define RADEON_I2C_SEL (1<<16)
989 #define RADEON_I2C_EN (1<<17)
990 #define RADEON_I2C_DATA 0x0098
992 #define RADEON_DVI_I2C_CNTL_0 0x02e0
993 #define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */
994 #define RADEON_DVI_I2C_DATA 0x02e8
996 #define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */
997 #define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */
998 #define RADEON_IO_BASE 0x0f14 /* PCI */
1000 #define RADEON_LATENCY 0x0f0d /* PCI */
1001 #define RADEON_LEAD_BRES_DEC 0x1608
1002 #define RADEON_LEAD_BRES_LNTH 0x161c
1003 #define RADEON_LEAD_BRES_LNTH_SUB 0x1624
1004 #define RADEON_LVDS_GEN_CNTL 0x02d0
1005 # define RADEON_LVDS_ON (1 << 0)
1006 # define RADEON_LVDS_DISPLAY_DIS (1 << 1)
1007 # define RADEON_LVDS_PANEL_TYPE (1 << 2)
1008 # define RADEON_LVDS_PANEL_FORMAT (1 << 3)
1009 # define RADEON_LVDS_RST_FM (1 << 6)
1010 # define RADEON_LVDS_EN (1 << 7)
1011 # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
1012 # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
1013 # define RADEON_LVDS_BL_MOD_EN (1 << 16)
1014 # define RADEON_LVDS_DIGON (1 << 18)
1015 # define RADEON_LVDS_BLON (1 << 19)
1016 # define RADEON_LVDS_SEL_CRTC2 (1 << 23)
1017 #define RADEON_LVDS_PLL_CNTL 0x02d4
1018 # define RADEON_HSYNC_DELAY_SHIFT 28
1019 # define RADEON_HSYNC_DELAY_MASK (0xf << 28)
1020 # define RADEON_LVDS_PLL_EN (1 << 16)
1021 # define RADEON_LVDS_PLL_RESET (1 << 17)
1022 # define R300_LVDS_SRC_SEL_MASK (3 << 18)
1023 # define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)
1024 # define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)
1025 # define R300_LVDS_SRC_SEL_RMX (2 << 18)
1027 #define RADEON_MAX_LATENCY 0x0f3f /* PCI */
1028 #define RADEON_MC_AGP_LOCATION 0x014c
1029 #define RADEON_MC_FB_LOCATION 0x0148
1030 #define RADEON_DISPLAY_BASE_ADDR 0x23c
1031 #define RADEON_DISPLAY2_BASE_ADDR 0x33c
1032 #define RADEON_OV0_BASE_ADDR 0x43c
1033 #define RADEON_NB_TOM 0x15c
1034 #define R300_MC_INIT_MISC_LAT_TIMER 0x180
1035 #define RADEON_MCLK_CNTL 0x0012 /* PLL */
1036 # define RADEON_FORCEON_MCLKA (1 << 16)
1037 # define RADEON_FORCEON_MCLKB (1 << 17)
1038 # define RADEON_FORCEON_YCLKA (1 << 18)
1039 # define RADEON_FORCEON_YCLKB (1 << 19)
1040 # define RADEON_FORCEON_MC (1 << 20)
1041 # define RADEON_FORCEON_AIC (1 << 21)
1042 # define R300_DISABLE_MC_MCLKA (1 << 21)
1043 # define R300_DISABLE_MC_MCLKB (1 << 21)
1044 #define RADEON_MCLK_MISC 0x001f /* PLL */
1045 # define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)
1046 # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
1047 # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
1048 # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
1049 #define RADEON_LCD_GPIO_MASK 0x01a0
1050 #define RADEON_GPIOPAD_EN 0x01a0
1051 #define RADEON_LCD_GPIO_Y_REG 0x01a4
1052 #define RADEON_MDGPIO_A_REG 0x01ac
1053 #define RADEON_MDGPIO_EN_REG 0x01b0
1054 #define RADEON_MDGPIO_MASK 0x0198
1055 #define RADEON_GPIOPAD_MASK 0x0198
1056 #define RADEON_GPIOPAD_A 0x019c
1057 #define RADEON_MDGPIO_Y_REG 0x01b4
1058 #define RADEON_MEM_ADDR_CONFIG 0x0148
1059 #define RADEON_MEM_BASE 0x0f10 /* PCI */
1060 #define RADEON_MEM_CNTL 0x0140
1061 # define RADEON_MEM_NUM_CHANNELS_MASK 0x01
1062 # define RADEON_MEM_USE_B_CH_ONLY (1 << 1)
1063 # define RV100_HALF_MODE (1 << 3)
1064 # define R300_MEM_NUM_CHANNELS_MASK 0x03
1065 # define R300_MEM_USE_CD_CH_ONLY (1 << 2)
1066 #define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */
1067 #define RADEON_MEM_INIT_LAT_TIMER 0x0154
1068 #define RADEON_MEM_INTF_CNTL 0x014c
1069 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
1070 # define RADEON_SDRAM_MODE_MASK 0xffff0000
1071 # define RADEON_B3MEM_RESET_MASK 0x6fffffff
1072 # define RADEON_MEM_CFG_TYPE_DDR (1 << 30)
1073 #define RADEON_MEM_STR_CNTL 0x0150
1074 # define RADEON_MEM_PWRUP_COMPL_A (1 << 0)
1075 # define RADEON_MEM_PWRUP_COMPL_B (1 << 1)
1076 # define R300_MEM_PWRUP_COMPL_C (1 << 2)
1077 # define R300_MEM_PWRUP_COMPL_D (1 << 3)
1078 # define RADEON_MEM_PWRUP_COMPLETE 0x03
1079 # define R300_MEM_PWRUP_COMPLETE 0x0f
1080 #define RADEON_MC_STATUS 0x0150
1081 # define RADEON_MC_IDLE (1 << 2)
1082 # define R300_MC_IDLE (1 << 4)
1083 #define RADEON_MEM_VGA_RP_SEL 0x003c
1084 #define RADEON_MEM_VGA_WP_SEL 0x0038
1085 #define RADEON_MIN_GRANT 0x0f3e /* PCI */
1086 #define RADEON_MM_DATA 0x0004
1087 #define RADEON_MM_INDEX 0x0000
1088 #define RADEON_MPLL_CNTL 0x000e /* PLL */
1089 #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
1090 #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
1091 #define RADEON_SEPROM_CNTL1 0x01c0
1092 # define RADEON_SCK_PRESCALE_SHIFT 24
1093 # define RADEON_SCK_PRESCALE_MASK (0xff << 24)
1094 #define R300_MC_IND_INDEX 0x01f8
1095 # define R300_MC_IND_ADDR_MASK 0x3f
1096 # define R300_MC_IND_WR_EN (1 << 8)
1097 #define R300_MC_IND_DATA 0x01fc
1098 #define R300_MC_READ_CNTL_AB 0x017c
1099 # define R300_MEM_RBS_POSITION_A_MASK 0x03
1100 #define R300_MC_READ_CNTL_CD_mcind 0x24
1101 # define R300_MEM_RBS_POSITION_C_MASK 0x03
1103 #define RADEON_N_VIF_COUNT 0x0248
1105 #define RADEON_OV0_AUTO_FLIP_CNTL 0x0470
1106 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007
1107 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008
1108 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010
1109 # define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
1110 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040
1111 # define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300
1112 # define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000
1113 # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000
1114 # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000
1115 # define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000
1117 #define RADEON_OV0_COLOUR_CNTL 0x04E0
1118 #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474
1119 #define RADEON_OV0_EXCLUSIVE_HORZ 0x0408
1120 # define RADEON_EXCL_HORZ_START_MASK 0x000000ff
1121 # define RADEON_EXCL_HORZ_END_MASK 0x0000ff00
1122 # define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
1123 # define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
1124 #define RADEON_OV0_EXCLUSIVE_VERT 0x040C
1125 # define RADEON_EXCL_VERT_START_MASK 0x000003ff
1126 # define RADEON_EXCL_VERT_END_MASK 0x03ff0000
1127 #define RADEON_OV0_FILTER_CNTL 0x04A0
1128 # define RADEON_FILTER_PROGRAMMABLE_COEF 0x0
1129 # define RADEON_FILTER_HC_COEF_HORZ_Y 0x1
1130 # define RADEON_FILTER_HC_COEF_HORZ_UV 0x2
1131 # define RADEON_FILTER_HC_COEF_VERT_Y 0x4
1132 # define RADEON_FILTER_HC_COEF_VERT_UV 0x8
1133 # define RADEON_FILTER_HARDCODED_COEF 0xf
1134 # define RADEON_FILTER_COEF_MASK 0xf
1136 #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0
1137 #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4
1138 #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8
1139 #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC
1140 #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0
1141 #define RADEON_OV0_FLAG_CNTL 0x04DC
1142 #define RADEON_OV0_GAMMA_000_00F 0x0d40
1143 #define RADEON_OV0_GAMMA_010_01F 0x0d44
1144 #define RADEON_OV0_GAMMA_020_03F 0x0d48
1145 #define RADEON_OV0_GAMMA_040_07F 0x0d4c
1146 #define RADEON_OV0_GAMMA_080_0BF 0x0e00
1147 #define RADEON_OV0_GAMMA_0C0_0FF 0x0e04
1148 #define RADEON_OV0_GAMMA_100_13F 0x0e08
1149 #define RADEON_OV0_GAMMA_140_17F 0x0e0c
1150 #define RADEON_OV0_GAMMA_180_1BF 0x0e10
1151 #define RADEON_OV0_GAMMA_1C0_1FF 0x0e14
1152 #define RADEON_OV0_GAMMA_200_23F 0x0e18
1153 #define RADEON_OV0_GAMMA_240_27F 0x0e1c
1154 #define RADEON_OV0_GAMMA_280_2BF 0x0e20
1155 #define RADEON_OV0_GAMMA_2C0_2FF 0x0e24
1156 #define RADEON_OV0_GAMMA_300_33F 0x0e28
1157 #define RADEON_OV0_GAMMA_340_37F 0x0e2c
1158 #define RADEON_OV0_GAMMA_380_3BF 0x0d50
1159 #define RADEON_OV0_GAMMA_3C0_3FF 0x0d54
1160 #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC
1161 #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0
1162 #define RADEON_OV0_H_INC 0x0480
1163 #define RADEON_OV0_KEY_CNTL 0x04F4
1164 # define RADEON_VIDEO_KEY_FN_MASK 0x00000003L
1165 # define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L
1166 # define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L
1167 # define RADEON_VIDEO_KEY_FN_EQ 0x00000002L
1168 # define RADEON_VIDEO_KEY_FN_NE 0x00000003L
1169 # define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L
1170 # define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
1171 # define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L
1172 # define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L
1173 # define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L
1174 # define RADEON_CMP_MIX_MASK 0x00000100L
1175 # define RADEON_CMP_MIX_OR 0x00000000L
1176 # define RADEON_CMP_MIX_AND 0x00000100L
1177 #define RADEON_OV0_LIN_TRANS_A 0x0d20
1178 #define RADEON_OV0_LIN_TRANS_B 0x0d24
1179 #define RADEON_OV0_LIN_TRANS_C 0x0d28
1180 #define RADEON_OV0_LIN_TRANS_D 0x0d2c
1181 #define RADEON_OV0_LIN_TRANS_E 0x0d30
1182 #define RADEON_OV0_LIN_TRANS_F 0x0d34
1183 #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430
1184 # define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
1185 # define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L
1186 #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488
1187 #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428
1188 # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
1189 # define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
1190 #define RADEON_OV0_P1_X_START_END 0x0494
1191 #define RADEON_OV0_P2_X_START_END 0x0498
1192 #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434
1193 # define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
1194 # define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L
1195 #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C
1196 #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C
1197 #define RADEON_OV0_P3_X_START_END 0x049C
1198 #define RADEON_OV0_REG_LOAD_CNTL 0x0410
1199 # define RADEON_REG_LD_CTL_LOCK 0x00000001L
1200 # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
1201 # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
1202 # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L
1203 # define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L
1204 #define RADEON_OV0_SCALE_CNTL 0x0420
1205 # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L
1206 # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L
1207 # define RADEON_SCALER_SIGNED_UV 0x00000010L
1208 # define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L
1209 # define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
1210 # define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L
1211 # define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L
1212 # define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L
1213 # define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
1214 # define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L
1215 # define RADEON_SCALER_SOURCE_15BPP 0x00000300L
1216 # define RADEON_SCALER_SOURCE_16BPP 0x00000400L
1217 # define RADEON_SCALER_SOURCE_32BPP 0x00000600L
1218 # define RADEON_SCALER_SOURCE_YUV9 0x00000900L
1219 # define RADEON_SCALER_SOURCE_YUV12 0x00000A00L
1220 # define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L
1221 # define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L
1222 # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
1223 # define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L
1224 # define RADEON_SCALER_CRTC_SEL 0x00004000L
1225 # define RADEON_SCALER_SMART_SWITCH 0x00008000L
1226 # define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L
1227 # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L
1228 # define RADEON_SCALER_DIS_LIMIT 0x08000000L
1229 # define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L
1230 # define RADEON_SCALER_INT_EMU 0x20000000L
1231 # define RADEON_SCALER_ENABLE 0x40000000L
1232 # define RADEON_SCALER_SOFT_RESET 0x80000000L
1233 #define RADEON_OV0_STEP_BY 0x0484
1234 #define RADEON_OV0_TEST 0x04F8
1235 #define RADEON_OV0_V_INC 0x0424
1236 #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460
1237 #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464
1238 #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440
1239 # define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L
1240 # define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L
1241 # define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
1242 # define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
1243 #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444
1244 # define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L
1245 # define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L
1246 # define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
1247 # define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
1248 #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448
1249 # define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L
1250 # define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L
1251 # define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
1252 # define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
1253 #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C
1254 #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450
1255 #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454
1256 #define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8
1257 #define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4
1258 #define RADEON_OV0_Y_X_START 0x0400
1259 #define RADEON_OV0_Y_X_END 0x0404
1260 #define RADEON_OV1_Y_X_START 0x0600
1261 #define RADEON_OV1_Y_X_END 0x0604
1262 #define RADEON_OVR_CLR 0x0230
1263 #define RADEON_OVR_WID_LEFT_RIGHT 0x0234
1264 #define RADEON_OVR_WID_TOP_BOTTOM 0x0238
1266 /* first capture unit */
1268 #define RADEON_CAP0_BUF0_OFFSET 0x0920
1269 #define RADEON_CAP0_BUF1_OFFSET 0x0924
1270 #define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928
1271 #define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C
1273 #define RADEON_CAP0_BUF_PITCH 0x0930
1274 #define RADEON_CAP0_V_WINDOW 0x0934
1275 #define RADEON_CAP0_H_WINDOW 0x0938
1276 #define RADEON_CAP0_VBI0_OFFSET 0x093C
1277 #define RADEON_CAP0_VBI1_OFFSET 0x0940
1278 #define RADEON_CAP0_VBI_V_WINDOW 0x0944
1279 #define RADEON_CAP0_VBI_H_WINDOW 0x0948
1280 #define RADEON_CAP0_PORT_MODE_CNTL 0x094C
1281 #define RADEON_CAP0_TRIG_CNTL 0x0950
1282 #define RADEON_CAP0_DEBUG 0x0954
1283 #define RADEON_CAP0_CONFIG 0x0958
1284 # define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001
1285 # define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002
1286 # define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004
1287 # define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008
1288 # define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010
1289 # define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020
1290 # define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
1291 # define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080
1292 # define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100
1293 # define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200
1294 # define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400
1295 # define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800
1296 # define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000
1297 # define RADEON_CAP0_CONFIG_VBI_EN 0x00002000
1298 # define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000
1299 # define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
1300 # define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000
1301 # define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000
1302 # define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
1303 # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000
1304 # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000
1305 # define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000
1306 # define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000
1307 # define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000
1308 # define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000
1309 # define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000
1310 # define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000
1311 # define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000
1312 # define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000
1313 # define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000
1314 # define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000
1315 # define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000
1316 # define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000
1317 #define RADEON_CAP0_ANC_ODD_OFFSET 0x095C
1318 #define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960
1319 #define RADEON_CAP0_ANC_H_WINDOW 0x0964
1320 #define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968
1321 #define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C
1322 #define RADEON_CAP0_BUF_STATUS 0x0970
1323 /* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */
1324 /* #define RADEON_CAP0_XSHARPNESS 0x097C */
1325 #define RADEON_CAP0_VBI2_OFFSET 0x0980
1326 #define RADEON_CAP0_VBI3_OFFSET 0x0984
1327 #define RADEON_CAP0_ANC2_OFFSET 0x0988
1328 #define RADEON_CAP0_ANC3_OFFSET 0x098C
1329 #define RADEON_VID_BUFFER_CONTROL 0x0900
1331 /* second capture unit */
1333 #define RADEON_CAP1_BUF0_OFFSET 0x0990
1334 #define RADEON_CAP1_BUF1_OFFSET 0x0994
1335 #define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998
1336 #define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C
1338 #define RADEON_CAP1_BUF_PITCH 0x09A0
1339 #define RADEON_CAP1_V_WINDOW 0x09A4
1340 #define RADEON_CAP1_H_WINDOW 0x09A8
1341 #define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC
1342 #define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0
1343 #define RADEON_CAP1_VBI_V_WINDOW 0x09B4
1344 #define RADEON_CAP1_VBI_H_WINDOW 0x09B8
1345 #define RADEON_CAP1_PORT_MODE_CNTL 0x09BC
1346 #define RADEON_CAP1_TRIG_CNTL 0x09C0
1347 #define RADEON_CAP1_DEBUG 0x09C4
1348 #define RADEON_CAP1_CONFIG 0x09C8
1349 #define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC
1350 #define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0
1351 #define RADEON_CAP1_ANC_H_WINDOW 0x09D4
1352 #define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8
1353 #define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC
1354 #define RADEON_CAP1_BUF_STATUS 0x09E0
1355 #define RADEON_CAP1_DWNSC_XRATIO 0x09E8
1356 #define RADEON_CAP1_XSHARPNESS 0x09EC
1358 /* misc multimedia registers */
1360 #define RADEON_IDCT_RUNS 0x1F80
1361 #define RADEON_IDCT_LEVELS 0x1F84
1362 #define RADEON_IDCT_CONTROL 0x1FBC
1363 #define RADEON_IDCT_AUTH_CONTROL 0x1F88
1364 #define RADEON_IDCT_AUTH 0x1F8C
1366 #define RADEON_P2PLL_CNTL 0x002a /* P2PLL */
1367 # define RADEON_P2PLL_RESET (1 << 0)
1368 # define RADEON_P2PLL_SLEEP (1 << 1)
1369 # define RADEON_P2PLL_PVG_MASK (7 << 11)
1370 # define RADEON_P2PLL_PVG_SHIFT 11
1371 # define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
1372 # define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
1373 # define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
1374 #define RADEON_P2PLL_DIV_0 0x002c
1375 # define RADEON_P2PLL_FB0_DIV_MASK 0x07ff
1376 # define RADEON_P2PLL_POST0_DIV_MASK 0x00070000
1377 #define RADEON_P2PLL_REF_DIV 0x002B /* PLL */
1378 # define RADEON_P2PLL_REF_DIV_MASK 0x03ff
1379 # define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
1380 # define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
1381 # define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
1382 # define R300_PPLL_REF_DIV_ACC_SHIFT 18
1383 #define RADEON_PALETTE_DATA 0x00b4
1384 #define RADEON_PALETTE_30_DATA 0x00b8
1385 #define RADEON_PALETTE_INDEX 0x00b0
1386 #define RADEON_PCI_GART_PAGE 0x017c
1387 #define RADEON_PIXCLKS_CNTL 0x002d
1388 # define RADEON_PIX2CLK_SRC_SEL_MASK 0x03
1389 # define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00
1390 # define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
1391 # define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02
1392 # define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
1393 # define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)
1394 # define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)
1395 # define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)
1396 # define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
1397 # define R300_DVOCLK_ALWAYS_ONb (1 << 10)
1398 # define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)
1399 # define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)
1400 # define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)
1401 # define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
1402 # define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
1403 # define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
1404 # define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
1405 # define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
1406 # define R300_P2G2CLK_ALWAYS_ONb (1 << 18)
1407 # define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
1408 # define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
1409 #define RADEON_PLANE_3D_MASK_C 0x1d44
1410 #define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
1411 # define RADEON_PLL_MASK_READ_B (1 << 9)
1412 #define RADEON_PMI_CAP_ID 0x0f5c /* PCI */
1413 #define RADEON_PMI_DATA 0x0f63 /* PCI */
1414 #define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
1415 #define RADEON_PMI_PMC_REG 0x0f5e /* PCI */
1416 #define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */
1417 #define RADEON_PMI_REGISTER 0x0f5c /* PCI */
1418 #define RADEON_PPLL_CNTL 0x0002 /* PLL */
1419 # define RADEON_PPLL_RESET (1 << 0)
1420 # define RADEON_PPLL_SLEEP (1 << 1)
1421 # define RADEON_PPLL_PVG_MASK (7 << 11)
1422 # define RADEON_PPLL_PVG_SHIFT 11
1423 # define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)
1424 # define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
1425 # define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
1426 #define RADEON_PPLL_DIV_0 0x0004 /* PLL */
1427 #define RADEON_PPLL_DIV_1 0x0005 /* PLL */
1428 #define RADEON_PPLL_DIV_2 0x0006 /* PLL */
1429 #define RADEON_PPLL_DIV_3 0x0007 /* PLL */
1430 # define RADEON_PPLL_FB3_DIV_MASK 0x07ff
1431 # define RADEON_PPLL_POST3_DIV_MASK 0x00070000
1432 #define RADEON_PPLL_REF_DIV 0x0003 /* PLL */
1433 # define RADEON_PPLL_REF_DIV_MASK 0x03ff
1434 # define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
1435 # define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
1436 #define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
1438 #define RADEON_RBBM_GUICNTL 0x172c
1439 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
1440 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
1441 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
1442 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
1443 #define RADEON_RBBM_SOFT_RESET 0x00f0
1444 # define RADEON_SOFT_RESET_CP (1 << 0)
1445 # define RADEON_SOFT_RESET_HI (1 << 1)
1446 # define RADEON_SOFT_RESET_SE (1 << 2)
1447 # define RADEON_SOFT_RESET_RE (1 << 3)
1448 # define RADEON_SOFT_RESET_PP (1 << 4)
1449 # define RADEON_SOFT_RESET_E2 (1 << 5)
1450 # define RADEON_SOFT_RESET_RB (1 << 6)
1451 # define RADEON_SOFT_RESET_HDP (1 << 7)
1452 #define RADEON_RBBM_STATUS 0x0e40
1453 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
1454 # define RADEON_RBBM_ACTIVE (1 << 31)
1455 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
1456 # define RADEON_RB2D_DC_FLUSH (3 << 0)
1457 # define RADEON_RB2D_DC_FREE (3 << 2)
1458 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
1459 # define RADEON_RB2D_DC_BUSY (1 << 31)
1460 #define RADEON_RB2D_DSTCACHE_MODE 0x3428
1461 #define RADEON_DSTCACHE_CTLSTAT 0x1714
1463 #define RADEON_RB3D_ZCACHE_MODE 0x3250
1464 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
1465 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
1466 #define RADEON_RB3D_DSTCACHE_MODE 0x3258
1467 # define RADEON_RB3D_DC_CACHE_ENABLE (0)
1468 # define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)
1469 # define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)
1470 # define RADEON_RB3D_DC_CACHE_DISABLE (3)
1471 # define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)
1472 # define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)
1473 # define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)
1474 # define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)
1475 # define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)
1476 # define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)
1477 # define RADEON_RB3D_DC_FORCE_RMW (1 << 16)
1478 # define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)
1479 # define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)
1481 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C
1482 # define RADEON_RB3D_DC_FLUSH (3 << 0)
1483 # define RADEON_RB3D_DC_FREE (3 << 2)
1484 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
1485 # define RADEON_RB3D_DC_BUSY (1 << 31)
1487 #define RADEON_REG_BASE 0x0f18 /* PCI */
1488 #define RADEON_REGPROG_INF 0x0f09 /* PCI */
1489 #define RADEON_REVISION_ID 0x0f08 /* PCI */
1491 #define RADEON_SC_BOTTOM 0x164c
1492 #define RADEON_SC_BOTTOM_RIGHT 0x16f0
1493 #define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c
1494 #define RADEON_SC_LEFT 0x1640
1495 #define RADEON_SC_RIGHT 0x1644
1496 #define RADEON_SC_TOP 0x1648
1497 #define RADEON_SC_TOP_LEFT 0x16ec
1498 #define RADEON_SC_TOP_LEFT_C 0x1c88
1499 # define RADEON_SC_SIGN_MASK_LO 0x8000
1500 # define RADEON_SC_SIGN_MASK_HI 0x80000000
1501 #define RADEON_SCLK_CNTL 0x000d /* PLL */
1502 # define RADEON_SCLK_SRC_SEL_MASK 0x0007
1503 # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
1504 # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
1505 # define RADEON_SCLK_FORCEON_MASK 0xffff8000
1506 # define RADEON_SCLK_FORCE_DISP2 (1<<15)
1507 # define RADEON_SCLK_FORCE_CP (1<<16)
1508 # define RADEON_SCLK_FORCE_HDP (1<<17)
1509 # define RADEON_SCLK_FORCE_DISP1 (1<<18)
1510 # define RADEON_SCLK_FORCE_TOP (1<<19)
1511 # define RADEON_SCLK_FORCE_E2 (1<<20)
1512 # define RADEON_SCLK_FORCE_SE (1<<21)
1513 # define RADEON_SCLK_FORCE_IDCT (1<<22)
1514 # define RADEON_SCLK_FORCE_VIP (1<<23)
1515 # define RADEON_SCLK_FORCE_RE (1<<24)
1516 # define RADEON_SCLK_FORCE_PB (1<<25)
1517 # define RADEON_SCLK_FORCE_TAM (1<<26)
1518 # define RADEON_SCLK_FORCE_TDM (1<<27)
1519 # define RADEON_SCLK_FORCE_RB (1<<28)
1520 # define RADEON_SCLK_FORCE_TV_SCLK (1<<29)
1521 # define RADEON_SCLK_FORCE_SUBPIC (1<<30)
1522 # define RADEON_SCLK_FORCE_OV0 (1<<31)
1523 # define R300_SCLK_FORCE_VAP (1<<21)
1524 # define R300_SCLK_FORCE_SR (1<<25)
1525 # define R300_SCLK_FORCE_PX (1<<26)
1526 # define R300_SCLK_FORCE_TX (1<<27)
1527 # define R300_SCLK_FORCE_US (1<<28)
1528 # define R300_SCLK_FORCE_SU (1<<30)
1529 #define R300_SCLK_CNTL2 0x1e /* PLL */
1530 # define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)
1531 # define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)
1532 # define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)
1533 # define R300_SCLK_FORCE_TCL (1<<13)
1534 # define R300_SCLK_FORCE_CBA (1<<14)
1535 # define R300_SCLK_FORCE_GA (1<<15)
1536 #define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */
1537 # define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
1538 # define RADEON_SCLK_MORE_FORCEON 0x0700
1539 #define RADEON_SDRAM_MODE_REG 0x0158
1540 #define RADEON_SEQ8_DATA 0x03c5 /* VGA */
1541 #define RADEON_SEQ8_IDX 0x03c4 /* VGA */
1542 #define RADEON_SNAPSHOT_F_COUNT 0x0244
1543 #define RADEON_SNAPSHOT_VH_COUNTS 0x0240
1544 #define RADEON_SNAPSHOT_VIF_COUNT 0x024c
1545 #define RADEON_SRC_OFFSET 0x15ac
1546 #define RADEON_SRC_PITCH 0x15b0
1547 #define RADEON_SRC_PITCH_OFFSET 0x1428
1548 #define RADEON_SRC_SC_BOTTOM 0x165c
1549 #define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4
1550 #define RADEON_SRC_SC_RIGHT 0x1654
1551 #define RADEON_SRC_X 0x1414
1552 #define RADEON_SRC_X_Y 0x1590
1553 #define RADEON_SRC_Y 0x1418
1554 #define RADEON_SRC_Y_X 0x1434
1555 #define RADEON_STATUS 0x0f06 /* PCI */
1556 #define RADEON_SUBPIC_CNTL 0x0540 /* ? */
1557 #define RADEON_SUB_CLASS 0x0f0a /* PCI */
1558 #define RADEON_SURFACE_CNTL 0x0b00
1559 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
1560 # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
1561 # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
1562 # define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
1563 # define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
1564 #define RADEON_SURFACE0_INFO 0x0b0c
1565 # define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
1566 # define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)
1567 # define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)
1568 # define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)
1569 # define R200_SURF_TILE_NONE (0 << 16)
1570 # define R200_SURF_TILE_COLOR_MACRO (1 << 16)
1571 # define R200_SURF_TILE_COLOR_MICRO (2 << 16)
1572 # define R200_SURF_TILE_COLOR_BOTH (3 << 16)
1573 # define R200_SURF_TILE_DEPTH_32BPP (4 << 16)
1574 # define R200_SURF_TILE_DEPTH_16BPP (5 << 16)
1575 # define R300_SURF_TILE_NONE (0 << 16)
1576 # define R300_SURF_TILE_COLOR_MACRO (1 << 16)
1577 # define R300_SURF_TILE_DEPTH_32BPP (2 << 16)
1578 # define RADEON_SURF_AP0_SWP_16BPP (1 << 20)
1579 # define RADEON_SURF_AP0_SWP_32BPP (1 << 21)
1580 # define RADEON_SURF_AP1_SWP_16BPP (1 << 22)
1581 # define RADEON_SURF_AP1_SWP_32BPP (1 << 23)
1582 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
1583 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
1584 #define RADEON_SURFACE1_INFO 0x0b1c
1585 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
1586 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
1587 #define RADEON_SURFACE2_INFO 0x0b2c
1588 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
1589 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
1590 #define RADEON_SURFACE3_INFO 0x0b3c
1591 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
1592 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
1593 #define RADEON_SURFACE4_INFO 0x0b4c
1594 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
1595 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
1596 #define RADEON_SURFACE5_INFO 0x0b5c
1597 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
1598 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
1599 #define RADEON_SURFACE6_INFO 0x0b6c
1600 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
1601 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
1602 #define RADEON_SURFACE7_INFO 0x0b7c
1603 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
1604 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
1605 #define RADEON_SW_SEMAPHORE 0x013c
1607 #define RADEON_TEST_DEBUG_CNTL 0x0120
1608 #define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
1610 #define RADEON_TEST_DEBUG_MUX 0x0124
1611 #define RADEON_TEST_DEBUG_OUT 0x012c
1612 #define RADEON_TMDS_PLL_CNTL 0x02a8
1613 #define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4
1614 # define RADEON_TMDS_TRANSMITTER_PLLEN 1
1615 # define RADEON_TMDS_TRANSMITTER_PLLRST 2
1616 #define RADEON_TRAIL_BRES_DEC 0x1614
1617 #define RADEON_TRAIL_BRES_ERR 0x160c
1618 #define RADEON_TRAIL_BRES_INC 0x1610
1619 #define RADEON_TRAIL_X 0x1618
1620 #define RADEON_TRAIL_X_SUB 0x1620
1622 #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */
1623 # define RADEON_VCLK_SRC_SEL_MASK 0x03
1624 # define RADEON_VCLK_SRC_SEL_CPUCLK 0x00
1625 # define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
1626 # define RADEON_VCLK_SRC_SEL_BYTECLK 0x02
1627 # define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03
1628 # define RADEON_PIXCLK_ALWAYS_ONb (1<<6)
1629 # define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
1630 # define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
1632 #define RADEON_VENDOR_ID 0x0f00 /* PCI */
1633 #define RADEON_VGA_DDA_CONFIG 0x02e8
1634 #define RADEON_VGA_DDA_ON_OFF 0x02ec
1635 #define RADEON_VID_BUFFER_CONTROL 0x0900
1636 #define RADEON_VIDEOMUX_CNTL 0x0190
1639 #define RADEON_VIPH_CH0_DATA 0x0c00
1640 #define RADEON_VIPH_CH1_DATA 0x0c04
1641 #define RADEON_VIPH_CH2_DATA 0x0c08
1642 #define RADEON_VIPH_CH3_DATA 0x0c0c
1643 #define RADEON_VIPH_CH0_ADDR 0x0c10
1644 #define RADEON_VIPH_CH1_ADDR 0x0c14
1645 #define RADEON_VIPH_CH2_ADDR 0x0c18
1646 #define RADEON_VIPH_CH3_ADDR 0x0c1c
1647 #define RADEON_VIPH_CH0_SBCNT 0x0c20
1648 #define RADEON_VIPH_CH1_SBCNT 0x0c24
1649 #define RADEON_VIPH_CH2_SBCNT 0x0c28
1650 #define RADEON_VIPH_CH3_SBCNT 0x0c2c
1651 #define RADEON_VIPH_CH0_ABCNT 0x0c30
1652 #define RADEON_VIPH_CH1_ABCNT 0x0c34
1653 #define RADEON_VIPH_CH2_ABCNT 0x0c38
1654 #define RADEON_VIPH_CH3_ABCNT 0x0c3c
1655 #define RADEON_VIPH_CONTROL 0x0c40
1656 # define RADEON_VIP_BUSY 0
1657 # define RADEON_VIP_IDLE 1
1658 # define RADEON_VIP_RESET 2
1659 # define RADEON_VIPH_EN (1 << 21)
1660 #define RADEON_VIPH_DV_LAT 0x0c44
1661 #define RADEON_VIPH_BM_CHUNK 0x0c48
1662 #define RADEON_VIPH_DV_INT 0x0c4c
1663 #define RADEON_VIPH_TIMEOUT_STAT 0x0c50
1664 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
1665 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
1666 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
1668 #define RADEON_VIPH_REG_DATA 0x0084
1669 #define RADEON_VIPH_REG_ADDR 0x0080
1672 #define RADEON_WAIT_UNTIL 0x1720
1673 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
1674 # define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)
1675 # define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)
1676 # define RADEON_WAIT_CRTC_VLINE (1 << 3)
1677 # define RADEON_WAIT_DMA_VID_IDLE (1 << 8)
1678 # define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)
1679 # define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */
1680 # define RADEON_WAIT_OV0_FLIP (1 << 11)
1681 # define RADEON_WAIT_AGP_FLUSH (1 << 13)
1682 # define RADEON_WAIT_2D_IDLE (1 << 14)
1683 # define RADEON_WAIT_3D_IDLE (1 << 15)
1684 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1685 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1686 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1687 # define RADEON_CMDFIFO_ENTRIES_SHIFT 10
1688 # define RADEON_CMDFIFO_ENTRIES_MASK 0x7f
1689 # define RADEON_WAIT_VAP_IDLE (1 << 28)
1690 # define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)
1691 # define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)
1692 # define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)
1694 #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
1695 #define RADEON_XCLK_CNTL 0x000d /* PLL */
1696 #define RADEON_XDLL_CNTL 0x000c /* PLL */
1697 #define RADEON_XPLL_CNTL 0x000b /* PLL */
1701 /* Registers for 3D/TCL */
1702 #define RADEON_PP_BORDER_COLOR_0 0x1d40
1703 #define RADEON_PP_BORDER_COLOR_1 0x1d44
1704 #define RADEON_PP_BORDER_COLOR_2 0x1d48
1705 #define RADEON_PP_CNTL 0x1c38
1706 # define RADEON_STIPPLE_ENABLE (1 << 0)
1707 # define RADEON_SCISSOR_ENABLE (1 << 1)
1708 # define RADEON_PATTERN_ENABLE (1 << 2)
1709 # define RADEON_SHADOW_ENABLE (1 << 3)
1710 # define RADEON_TEX_ENABLE_MASK (0xf << 4)
1711 # define RADEON_TEX_0_ENABLE (1 << 4)
1712 # define RADEON_TEX_1_ENABLE (1 << 5)
1713 # define RADEON_TEX_2_ENABLE (1 << 6)
1714 # define RADEON_TEX_3_ENABLE (1 << 7)
1715 # define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
1716 # define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
1717 # define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
1718 # define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
1719 # define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
1720 # define RADEON_PLANAR_YUV_ENABLE (1 << 20)
1721 # define RADEON_SPECULAR_ENABLE (1 << 21)
1722 # define RADEON_FOG_ENABLE (1 << 22)
1723 # define RADEON_ALPHA_TEST_ENABLE (1 << 23)
1724 # define RADEON_ANTI_ALIAS_NONE (0 << 24)
1725 # define RADEON_ANTI_ALIAS_LINE (1 << 24)
1726 # define RADEON_ANTI_ALIAS_POLY (2 << 24)
1727 # define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
1728 # define RADEON_BUMP_MAP_ENABLE (1 << 26)
1729 # define RADEON_BUMPED_MAP_T0 (0 << 27)
1730 # define RADEON_BUMPED_MAP_T1 (1 << 27)
1731 # define RADEON_BUMPED_MAP_T2 (2 << 27)
1732 # define RADEON_TEX_3D_ENABLE_0 (1 << 29)
1733 # define RADEON_TEX_3D_ENABLE_1 (1 << 30)
1734 # define RADEON_MC_ENABLE (1 << 31)
1735 #define RADEON_PP_FOG_COLOR 0x1c18
1736 # define RADEON_FOG_COLOR_MASK 0x00ffffff
1737 # define RADEON_FOG_VERTEX (0 << 24)
1738 # define RADEON_FOG_TABLE (1 << 24)
1739 # define RADEON_FOG_USE_DEPTH (0 << 25)
1740 # define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)
1741 # define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)
1742 #define RADEON_PP_LUM_MATRIX 0x1d00
1743 #define RADEON_PP_MISC 0x1c14
1744 # define RADEON_REF_ALPHA_MASK 0x000000ff
1745 # define RADEON_ALPHA_TEST_FAIL (0 << 8)
1746 # define RADEON_ALPHA_TEST_LESS (1 << 8)
1747 # define RADEON_ALPHA_TEST_LEQUAL (2 << 8)
1748 # define RADEON_ALPHA_TEST_EQUAL (3 << 8)
1749 # define RADEON_ALPHA_TEST_GEQUAL (4 << 8)
1750 # define RADEON_ALPHA_TEST_GREATER (5 << 8)
1751 # define RADEON_ALPHA_TEST_NEQUAL (6 << 8)
1752 # define RADEON_ALPHA_TEST_PASS (7 << 8)
1753 # define RADEON_ALPHA_TEST_OP_MASK (7 << 8)
1754 # define RADEON_CHROMA_FUNC_FAIL (0 << 16)
1755 # define RADEON_CHROMA_FUNC_PASS (1 << 16)
1756 # define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)
1757 # define RADEON_CHROMA_FUNC_EQUAL (3 << 16)
1758 # define RADEON_CHROMA_KEY_NEAREST (0 << 18)
1759 # define RADEON_CHROMA_KEY_ZERO (1 << 18)
1760 # define RADEON_SHADOW_ID_AUTO_INC (1 << 20)
1761 # define RADEON_SHADOW_FUNC_EQUAL (0 << 21)
1762 # define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)
1763 # define RADEON_SHADOW_PASS_1 (0 << 22)
1764 # define RADEON_SHADOW_PASS_2 (1 << 22)
1765 # define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)
1766 # define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)
1767 #define RADEON_PP_ROT_MATRIX_0 0x1d58
1768 #define RADEON_PP_ROT_MATRIX_1 0x1d5c
1769 #define RADEON_PP_TXFILTER_0 0x1c54
1770 #define RADEON_PP_TXFILTER_1 0x1c6c
1771 #define RADEON_PP_TXFILTER_2 0x1c84
1772 # define RADEON_MAG_FILTER_NEAREST (0 << 0)
1773 # define RADEON_MAG_FILTER_LINEAR (1 << 0)
1774 # define RADEON_MAG_FILTER_MASK (1 << 0)
1775 # define RADEON_MIN_FILTER_NEAREST (0 << 1)
1776 # define RADEON_MIN_FILTER_LINEAR (1 << 1)
1777 # define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
1778 # define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
1779 # define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
1780 # define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
1781 # define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)
1782 # define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)
1783 # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
1784 # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
1785 # define RADEON_MIN_FILTER_MASK (15 << 1)
1786 # define RADEON_MAX_ANISO_1_TO_1 (0 << 5)
1787 # define RADEON_MAX_ANISO_2_TO_1 (1 << 5)
1788 # define RADEON_MAX_ANISO_4_TO_1 (2 << 5)
1789 # define RADEON_MAX_ANISO_8_TO_1 (3 << 5)
1790 # define RADEON_MAX_ANISO_16_TO_1 (4 << 5)
1791 # define RADEON_MAX_ANISO_MASK (7 << 5)
1792 # define RADEON_LOD_BIAS_MASK (0xff << 8)
1793 # define RADEON_LOD_BIAS_SHIFT 8
1794 # define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)
1795 # define RADEON_MAX_MIP_LEVEL_SHIFT 16
1796 # define RADEON_YUV_TO_RGB (1 << 20)
1797 # define RADEON_YUV_TEMPERATURE_COOL (0 << 21)
1798 # define RADEON_YUV_TEMPERATURE_HOT (1 << 21)
1799 # define RADEON_YUV_TEMPERATURE_MASK (1 << 21)
1800 # define RADEON_WRAPEN_S (1 << 22)
1801 # define RADEON_CLAMP_S_WRAP (0 << 23)
1802 # define RADEON_CLAMP_S_MIRROR (1 << 23)
1803 # define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)
1804 # define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
1805 # define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)
1806 # define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
1807 # define RADEON_CLAMP_S_CLAMP_GL (6 << 23)
1808 # define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
1809 # define RADEON_CLAMP_S_MASK (7 << 23)
1810 # define RADEON_WRAPEN_T (1 << 26)
1811 # define RADEON_CLAMP_T_WRAP (0 << 27)
1812 # define RADEON_CLAMP_T_MIRROR (1 << 27)
1813 # define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)
1814 # define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
1815 # define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)
1816 # define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
1817 # define RADEON_CLAMP_T_CLAMP_GL (6 << 27)
1818 # define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
1819 # define RADEON_CLAMP_T_MASK (7 << 27)
1820 # define RADEON_BORDER_MODE_OGL (0 << 31)
1821 # define RADEON_BORDER_MODE_D3D (1 << 31)
1822 #define RADEON_PP_TXFORMAT_0 0x1c58
1823 #define RADEON_PP_TXFORMAT_1 0x1c70
1824 #define RADEON_PP_TXFORMAT_2 0x1c88
1825 # define RADEON_TXFORMAT_I8 (0 << 0)
1826 # define RADEON_TXFORMAT_AI88 (1 << 0)
1827 # define RADEON_TXFORMAT_RGB332 (2 << 0)
1828 # define RADEON_TXFORMAT_ARGB1555 (3 << 0)
1829 # define RADEON_TXFORMAT_RGB565 (4 << 0)
1830 # define RADEON_TXFORMAT_ARGB4444 (5 << 0)
1831 # define RADEON_TXFORMAT_ARGB8888 (6 << 0)
1832 # define RADEON_TXFORMAT_RGBA8888 (7 << 0)
1833 # define RADEON_TXFORMAT_Y8 (8 << 0)
1834 # define RADEON_TXFORMAT_VYUY422 (10 << 0)
1835 # define RADEON_TXFORMAT_YVYU422 (11 << 0)
1836 # define RADEON_TXFORMAT_DXT1 (12 << 0)
1837 # define RADEON_TXFORMAT_DXT23 (14 << 0)
1838 # define RADEON_TXFORMAT_DXT45 (15 << 0)
1839 # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
1840 # define RADEON_TXFORMAT_FORMAT_SHIFT 0
1841 # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
1842 # define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
1843 # define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
1844 # define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
1845 # define RADEON_TXFORMAT_WIDTH_SHIFT 8
1846 # define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
1847 # define RADEON_TXFORMAT_HEIGHT_SHIFT 12
1848 # define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
1849 # define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
1850 # define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
1851 # define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
1852 # define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
1853 # define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
1854 # define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
1855 # define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
1856 # define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
1857 # define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
1858 # define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
1859 # define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
1860 # define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
1861 # define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
1862 # define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
1863 # define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
1864 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1865 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1866 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1867 # define RADEON_FACE_WIDTH_1_SHIFT 0
1868 # define RADEON_FACE_HEIGHT_1_SHIFT 4
1869 # define RADEON_FACE_WIDTH_1_MASK (0xf << 0)
1870 # define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)
1871 # define RADEON_FACE_WIDTH_2_SHIFT 8
1872 # define RADEON_FACE_HEIGHT_2_SHIFT 12
1873 # define RADEON_FACE_WIDTH_2_MASK (0xf << 8)
1874 # define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)
1875 # define RADEON_FACE_WIDTH_3_SHIFT 16
1876 # define RADEON_FACE_HEIGHT_3_SHIFT 20
1877 # define RADEON_FACE_WIDTH_3_MASK (0xf << 16)
1878 # define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)
1879 # define RADEON_FACE_WIDTH_4_SHIFT 24
1880 # define RADEON_FACE_HEIGHT_4_SHIFT 28
1881 # define RADEON_FACE_WIDTH_4_MASK (0xf << 24)
1882 # define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)
1884 #define RADEON_PP_TXOFFSET_0 0x1c5c
1885 #define RADEON_PP_TXOFFSET_1 0x1c74
1886 #define RADEON_PP_TXOFFSET_2 0x1c8c
1887 # define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
1888 # define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
1889 # define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
1890 # define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
1891 # define RADEON_TXO_MACRO_LINEAR (0 << 2)
1892 # define RADEON_TXO_MACRO_TILE (1 << 2)
1893 # define RADEON_TXO_MICRO_LINEAR (0 << 3)
1894 # define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
1895 # define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
1896 # define RADEON_TXO_OFFSET_MASK 0xffffffe0
1897 # define RADEON_TXO_OFFSET_SHIFT 5
1899 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1900 #define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4
1901 #define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8
1902 #define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc
1903 #define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0
1904 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1905 #define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04
1906 #define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08
1907 #define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c
1908 #define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10
1909 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1910 #define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18
1911 #define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c
1912 #define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20
1913 #define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24
1915 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1916 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1917 #define RADEON_PP_TEX_SIZE_2 0x1d14
1918 # define RADEON_TEX_USIZE_MASK (0x7ff << 0)
1919 # define RADEON_TEX_USIZE_SHIFT 0
1920 # define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
1921 # define RADEON_TEX_VSIZE_SHIFT 16
1922 # define RADEON_SIGNED_RGB_MASK (1 << 30)
1923 # define RADEON_SIGNED_RGB_SHIFT 30
1924 # define RADEON_SIGNED_ALPHA_MASK (1 << 31)
1925 # define RADEON_SIGNED_ALPHA_SHIFT 31
1926 #define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
1927 #define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
1928 #define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */
1929 /* note: bits 13-5: 32 byte aligned stride of texture map */
1931 #define RADEON_PP_TXCBLEND_0 0x1c60
1932 #define RADEON_PP_TXCBLEND_1 0x1c78
1933 #define RADEON_PP_TXCBLEND_2 0x1c90
1934 # define RADEON_COLOR_ARG_A_SHIFT 0
1935 # define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
1936 # define RADEON_COLOR_ARG_A_ZERO (0 << 0)
1937 # define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)
1938 # define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)
1939 # define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)
1940 # define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)
1941 # define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)
1942 # define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)
1943 # define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)
1944 # define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)
1945 # define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)
1946 # define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)
1947 # define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)
1948 # define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)
1949 # define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)
1950 # define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)
1951 # define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)
1952 # define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)
1953 # define RADEON_COLOR_ARG_B_SHIFT 5
1954 # define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
1955 # define RADEON_COLOR_ARG_B_ZERO (0 << 5)
1956 # define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)
1957 # define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)
1958 # define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)
1959 # define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)
1960 # define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)
1961 # define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)
1962 # define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)
1963 # define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)
1964 # define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)
1965 # define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)
1966 # define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)
1967 # define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)
1968 # define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)
1969 # define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)
1970 # define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)
1971 # define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)
1972 # define RADEON_COLOR_ARG_C_SHIFT 10
1973 # define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
1974 # define RADEON_COLOR_ARG_C_ZERO (0 << 10)
1975 # define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)
1976 # define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)
1977 # define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)
1978 # define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)
1979 # define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)
1980 # define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)
1981 # define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)
1982 # define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)
1983 # define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)
1984 # define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)
1985 # define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)
1986 # define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)
1987 # define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)
1988 # define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)
1989 # define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)
1990 # define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)
1991 # define RADEON_COMP_ARG_A (1 << 15)
1992 # define RADEON_COMP_ARG_A_SHIFT 15
1993 # define RADEON_COMP_ARG_B (1 << 16)
1994 # define RADEON_COMP_ARG_B_SHIFT 16
1995 # define RADEON_COMP_ARG_C (1 << 17)
1996 # define RADEON_COMP_ARG_C_SHIFT 17
1997 # define RADEON_BLEND_CTL_MASK (7 << 18)
1998 # define RADEON_BLEND_CTL_ADD (0 << 18)
1999 # define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
2000 # define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
2001 # define RADEON_BLEND_CTL_BLEND (3 << 18)
2002 # define RADEON_BLEND_CTL_DOT3 (4 << 18)
2003 # define RADEON_SCALE_SHIFT 21
2004 # define RADEON_SCALE_MASK (3 << 21)
2005 # define RADEON_SCALE_1X (0 << 21)
2006 # define RADEON_SCALE_2X (1 << 21)
2007 # define RADEON_SCALE_4X (2 << 21)
2008 # define RADEON_CLAMP_TX (1 << 23)
2009 # define RADEON_T0_EQ_TCUR (1 << 24)
2010 # define RADEON_T1_EQ_TCUR (1 << 25)
2011 # define RADEON_T2_EQ_TCUR (1 << 26)
2012 # define RADEON_T3_EQ_TCUR (1 << 27)
2013 # define RADEON_COLOR_ARG_MASK 0x1f
2014 # define RADEON_COMP_ARG_SHIFT 15
2015 #define RADEON_PP_TXABLEND_0 0x1c64
2016 #define RADEON_PP_TXABLEND_1 0x1c7c
2017 #define RADEON_PP_TXABLEND_2 0x1c94
2018 # define RADEON_ALPHA_ARG_A_SHIFT 0
2019 # define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
2020 # define RADEON_ALPHA_ARG_A_ZERO (0 << 0)
2021 # define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)
2022 # define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)
2023 # define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)
2024 # define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)
2025 # define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)
2026 # define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)
2027 # define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)
2028 # define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)
2029 # define RADEON_ALPHA_ARG_B_SHIFT 4
2030 # define RADEON_ALPHA_ARG_B_MASK (0xf << 4)
2031 # define RADEON_ALPHA_ARG_B_ZERO (0 << 4)
2032 # define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)
2033 # define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)
2034 # define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)
2035 # define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)
2036 # define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)
2037 # define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)
2038 # define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)
2039 # define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)
2040 # define RADEON_ALPHA_ARG_C_SHIFT 8
2041 # define RADEON_ALPHA_ARG_C_MASK (0xf << 8)
2042 # define RADEON_ALPHA_ARG_C_ZERO (0 << 8)
2043 # define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)
2044 # define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)
2045 # define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)
2046 # define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)
2047 # define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)
2048 # define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)
2049 # define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)
2050 # define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)
2051 # define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)
2052 # define RADEON_ALPHA_ARG_MASK 0xf
2054 #define RADEON_PP_TFACTOR_0 0x1c68
2055 #define RADEON_PP_TFACTOR_1 0x1c80
2056 #define RADEON_PP_TFACTOR_2 0x1c98
2058 #define RADEON_RB3D_BLENDCNTL 0x1c20
2059 # define RADEON_COMB_FCN_MASK (3 << 12)
2060 # define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)
2061 # define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)
2062 # define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)
2063 # define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)
2064 # define RADEON_SRC_BLEND_GL_ZERO (32 << 16)
2065 # define RADEON_SRC_BLEND_GL_ONE (33 << 16)
2066 # define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)
2067 # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
2068 # define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)
2069 # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
2070 # define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
2071 # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
2072 # define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)
2073 # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
2074 # define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
2075 # define RADEON_SRC_BLEND_MASK (63 << 16)
2076 # define RADEON_DST_BLEND_GL_ZERO (32 << 24)
2077 # define RADEON_DST_BLEND_GL_ONE (33 << 24)
2078 # define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)
2079 # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
2080 # define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)
2081 # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
2082 # define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)
2083 # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
2084 # define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)
2085 # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
2086 # define RADEON_DST_BLEND_MASK (63 << 24)
2087 #define RADEON_RB3D_CNTL 0x1c3c
2088 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
2089 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
2090 # define RADEON_DITHER_ENABLE (1 << 2)
2091 # define RADEON_ROUND_ENABLE (1 << 3)
2092 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
2093 # define RADEON_DITHER_INIT (1 << 5)
2094 # define RADEON_ROP_ENABLE (1 << 6)
2095 # define RADEON_STENCIL_ENABLE (1 << 7)
2096 # define RADEON_Z_ENABLE (1 << 8)
2097 # define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
2098 # define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10)
2099 # define RADEON_COLOR_FORMAT_RGB565 (4 << 10)
2100 # define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10)
2101 # define RADEON_COLOR_FORMAT_RGB332 (7 << 10)
2102 # define RADEON_COLOR_FORMAT_Y8 (8 << 10)
2103 # define RADEON_COLOR_FORMAT_RGB8 (9 << 10)
2104 # define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10)
2105 # define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10)
2106 # define RADEON_COLOR_FORMAT_aYUV444 (14 << 10)
2107 # define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10)
2108 # define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
2109 #define RADEON_RB3D_COLOROFFSET 0x1c40
2110 # define RADEON_COLOROFFSET_MASK 0xfffffff0
2111 #define RADEON_RB3D_COLORPITCH 0x1c48
2112 # define RADEON_COLORPITCH_MASK 0x000001ff8
2113 # define RADEON_COLOR_TILE_ENABLE (1 << 16)
2114 # define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)
2115 # define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)
2116 # define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)
2117 # define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
2118 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
2119 #define RADEON_RB3D_DEPTHPITCH 0x1c28
2120 # define RADEON_DEPTHPITCH_MASK 0x00001ff8
2121 # define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)
2122 # define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)
2123 # define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
2124 #define RADEON_RB3D_PLANEMASK 0x1d84
2125 #define RADEON_RB3D_ROPCNTL 0x1d80
2126 # define RADEON_ROP_MASK (15 << 8)
2127 # define RADEON_ROP_CLEAR (0 << 8)
2128 # define RADEON_ROP_NOR (1 << 8)
2129 # define RADEON_ROP_AND_INVERTED (2 << 8)
2130 # define RADEON_ROP_COPY_INVERTED (3 << 8)
2131 # define RADEON_ROP_AND_REVERSE (4 << 8)
2132 # define RADEON_ROP_INVERT (5 << 8)
2133 # define RADEON_ROP_XOR (6 << 8)
2134 # define RADEON_ROP_NAND (7 << 8)
2135 # define RADEON_ROP_AND (8 << 8)
2136 # define RADEON_ROP_EQUIV (9 << 8)
2137 # define RADEON_ROP_NOOP (10 << 8)
2138 # define RADEON_ROP_OR_INVERTED (11 << 8)
2139 # define RADEON_ROP_COPY (12 << 8)
2140 # define RADEON_ROP_OR_REVERSE (13 << 8)
2141 # define RADEON_ROP_OR (14 << 8)
2142 # define RADEON_ROP_SET (15 << 8)
2143 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
2144 # define RADEON_STENCIL_REF_SHIFT 0
2145 # define RADEON_STENCIL_REF_MASK (0xff << 0)
2146 # define RADEON_STENCIL_MASK_SHIFT 16
2147 # define RADEON_STENCIL_VALUE_MASK (0xff << 16)
2148 # define RADEON_STENCIL_WRITEMASK_SHIFT 24
2149 # define RADEON_STENCIL_WRITE_MASK (0xff << 24)
2150 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
2151 # define RADEON_DEPTH_FORMAT_MASK (0xf << 0)
2152 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
2153 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
2154 # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)
2155 # define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)
2156 # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)
2157 # define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)
2158 # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)
2159 # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)
2160 # define RADEON_Z_TEST_NEVER (0 << 4)
2161 # define RADEON_Z_TEST_LESS (1 << 4)
2162 # define RADEON_Z_TEST_LEQUAL (2 << 4)
2163 # define RADEON_Z_TEST_EQUAL (3 << 4)
2164 # define RADEON_Z_TEST_GEQUAL (4 << 4)
2165 # define RADEON_Z_TEST_GREATER (5 << 4)
2166 # define RADEON_Z_TEST_NEQUAL (6 << 4)
2167 # define RADEON_Z_TEST_ALWAYS (7 << 4)
2168 # define RADEON_Z_TEST_MASK (7 << 4)
2169 # define RADEON_STENCIL_TEST_NEVER (0 << 12)
2170 # define RADEON_STENCIL_TEST_LESS (1 << 12)
2171 # define RADEON_STENCIL_TEST_LEQUAL (2 << 12)
2172 # define RADEON_STENCIL_TEST_EQUAL (3 << 12)
2173 # define RADEON_STENCIL_TEST_GEQUAL (4 << 12)
2174 # define RADEON_STENCIL_TEST_GREATER (5 << 12)
2175 # define RADEON_STENCIL_TEST_NEQUAL (6 << 12)
2176 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
2177 # define RADEON_STENCIL_TEST_MASK (0x7 << 12)
2178 # define RADEON_STENCIL_FAIL_KEEP (0 << 16)
2179 # define RADEON_STENCIL_FAIL_ZERO (1 << 16)
2180 # define RADEON_STENCIL_FAIL_REPLACE (2 << 16)
2181 # define RADEON_STENCIL_FAIL_INC (3 << 16)
2182 # define RADEON_STENCIL_FAIL_DEC (4 << 16)
2183 # define RADEON_STENCIL_FAIL_INVERT (5 << 16)
2184 # define RADEON_STENCIL_FAIL_MASK (0x7 << 16)
2185 # define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
2186 # define RADEON_STENCIL_ZPASS_ZERO (1 << 20)
2187 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
2188 # define RADEON_STENCIL_ZPASS_INC (3 << 20)
2189 # define RADEON_STENCIL_ZPASS_DEC (4 << 20)
2190 # define RADEON_STENCIL_ZPASS_INVERT (5 << 20)
2191 # define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)
2192 # define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)
2193 # define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)
2194 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
2195 # define RADEON_STENCIL_ZFAIL_INC (3 << 24)
2196 # define RADEON_STENCIL_ZFAIL_DEC (4 << 24)
2197 # define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)
2198 # define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)
2199 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
2200 # define RADEON_FORCE_Z_DIRTY (1 << 29)
2201 # define RADEON_Z_WRITE_ENABLE (1 << 30)
2202 #define RADEON_RE_LINE_PATTERN 0x1cd0
2203 # define RADEON_LINE_PATTERN_MASK 0x0000ffff
2204 # define RADEON_LINE_REPEAT_COUNT_SHIFT 16
2205 # define RADEON_LINE_PATTERN_START_SHIFT 24
2206 # define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)
2207 # define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)
2208 # define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)
2209 #define RADEON_RE_LINE_STATE 0x1cd4
2210 # define RADEON_LINE_CURRENT_PTR_SHIFT 0
2211 # define RADEON_LINE_CURRENT_COUNT_SHIFT 8
2212 #define RADEON_RE_MISC 0x26c4
2213 # define RADEON_STIPPLE_COORD_MASK 0x1f
2214 # define RADEON_STIPPLE_X_OFFSET_SHIFT 0
2215 # define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)
2216 # define RADEON_STIPPLE_Y_OFFSET_SHIFT 8
2217 # define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)
2218 # define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)
2219 # define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)
2220 #define RADEON_RE_SOLID_COLOR 0x1c1c
2221 #define RADEON_RE_TOP_LEFT 0x26c0
2222 # define RADEON_RE_LEFT_SHIFT 0
2223 # define RADEON_RE_TOP_SHIFT 16
2224 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
2225 # define RADEON_RE_WIDTH_SHIFT 0
2226 # define RADEON_RE_HEIGHT_SHIFT 16
2228 #define RADEON_SE_CNTL 0x1c4c
2229 # define RADEON_FFACE_CULL_CW (0 << 0)
2230 # define RADEON_FFACE_CULL_CCW (1 << 0)
2231 # define RADEON_FFACE_CULL_DIR_MASK (1 << 0)
2232 # define RADEON_BFACE_CULL (0 << 1)
2233 # define RADEON_BFACE_SOLID (3 << 1)
2234 # define RADEON_FFACE_CULL (0 << 3)
2235 # define RADEON_FFACE_SOLID (3 << 3)
2236 # define RADEON_FFACE_CULL_MASK (3 << 3)
2237 # define RADEON_BADVTX_CULL_DISABLE (1 << 5)
2238 # define RADEON_FLAT_SHADE_VTX_0 (0 << 6)
2239 # define RADEON_FLAT_SHADE_VTX_1 (1 << 6)
2240 # define RADEON_FLAT_SHADE_VTX_2 (2 << 6)
2241 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
2242 # define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)
2243 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
2244 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
2245 # define RADEON_DIFFUSE_SHADE_MASK (3 << 8)
2246 # define RADEON_ALPHA_SHADE_SOLID (0 << 10)
2247 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
2248 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
2249 # define RADEON_ALPHA_SHADE_MASK (3 << 10)
2250 # define RADEON_SPECULAR_SHADE_SOLID (0 << 12)
2251 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
2252 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
2253 # define RADEON_SPECULAR_SHADE_MASK (3 << 12)
2254 # define RADEON_FOG_SHADE_SOLID (0 << 14)
2255 # define RADEON_FOG_SHADE_FLAT (1 << 14)
2256 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
2257 # define RADEON_FOG_SHADE_MASK (3 << 14)
2258 # define RADEON_ZBIAS_ENABLE_POINT (1 << 16)
2259 # define RADEON_ZBIAS_ENABLE_LINE (1 << 17)
2260 # define RADEON_ZBIAS_ENABLE_TRI (1 << 18)
2261 # define RADEON_WIDELINE_ENABLE (1 << 20)
2262 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
2263 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
2264 # define RADEON_VTX_PIX_CENTER_D3D (0 << 27)
2265 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
2266 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
2267 # define RADEON_ROUND_MODE_ROUND (1 << 28)
2268 # define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)
2269 # define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)
2270 # define RADEON_ROUND_PREC_16TH_PIX (0 << 30)
2271 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
2272 # define RADEON_ROUND_PREC_4TH_PIX (2 << 30)
2273 # define RADEON_ROUND_PREC_HALF_PIX (3 << 30)
2274 #define R200_RE_CNTL 0x1c50
2275 # define R200_STIPPLE_ENABLE 0x1
2276 # define R200_SCISSOR_ENABLE 0x2
2277 # define R200_PATTERN_ENABLE 0x4
2278 # define R200_PERSPECTIVE_ENABLE 0x8
2279 # define R200_POINT_SMOOTH 0x20
2280 # define R200_VTX_STQ0_D3D 0x00010000
2281 # define R200_VTX_STQ1_D3D 0x00040000
2282 # define R200_VTX_STQ2_D3D 0x00100000
2283 # define R200_VTX_STQ3_D3D 0x00400000
2284 # define R200_VTX_STQ4_D3D 0x01000000
2285 # define R200_VTX_STQ5_D3D 0x04000000
2286 #define RADEON_SE_CNTL_STATUS 0x2140
2287 # define RADEON_VC_NO_SWAP (0 << 0)
2288 # define RADEON_VC_16BIT_SWAP (1 << 0)
2289 # define RADEON_VC_32BIT_SWAP (2 << 0)
2290 # define RADEON_VC_HALF_DWORD_SWAP (3 << 0)
2291 # define RADEON_TCL_BYPASS (1 << 8)
2292 #define RADEON_SE_COORD_FMT 0x1c50
2293 # define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)
2294 # define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)
2295 # define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)
2296 # define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)
2297 # define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)
2298 # define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)
2299 # define RADEON_VTX_W0_NORMALIZE (1 << 12)
2300 # define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)
2301 # define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
2302 # define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
2303 # define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
2304 # define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
2305 # define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)
2306 # define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)
2307 #define RADEON_SE_LINE_WIDTH 0x1db8
2308 #define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c
2309 # define RADEON_LIGHTING_ENABLE (1 << 0)
2310 # define RADEON_LIGHT_IN_MODELSPACE (1 << 1)
2311 # define RADEON_LOCAL_VIEWER (1 << 2)
2312 # define RADEON_NORMALIZE_NORMALS (1 << 3)
2313 # define RADEON_RESCALE_NORMALS (1 << 4)
2314 # define RADEON_SPECULAR_LIGHTS (1 << 5)
2315 # define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)
2316 # define RADEON_LIGHT_ALPHA (1 << 7)
2317 # define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)
2318 # define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)
2319 # define RADEON_LM_SOURCE_STATE_PREMULT 0
2320 # define RADEON_LM_SOURCE_STATE_MULT 1
2321 # define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2
2322 # define RADEON_LM_SOURCE_VERTEX_SPECULAR 3
2323 # define RADEON_EMISSIVE_SOURCE_SHIFT 16
2324 # define RADEON_AMBIENT_SOURCE_SHIFT 18
2325 # define RADEON_DIFFUSE_SOURCE_SHIFT 20
2326 # define RADEON_SPECULAR_SOURCE_SHIFT 22
2327 #define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220
2328 #define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224
2329 #define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228
2330 #define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c
2331 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230
2332 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234
2333 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238
2334 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c
2335 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
2336 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214
2337 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218
2338 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c
2339 #define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240
2340 #define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244
2341 #define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248
2342 #define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c
2343 #define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c
2344 # define RADEON_MODELVIEW_0_SHIFT 0
2345 # define RADEON_MODELVIEW_1_SHIFT 4
2346 # define RADEON_MODELVIEW_2_SHIFT 8
2347 # define RADEON_MODELVIEW_3_SHIFT 12
2348 # define RADEON_IT_MODELVIEW_0_SHIFT 16
2349 # define RADEON_IT_MODELVIEW_1_SHIFT 20
2350 # define RADEON_IT_MODELVIEW_2_SHIFT 24
2351 # define RADEON_IT_MODELVIEW_3_SHIFT 28
2352 #define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260
2353 # define RADEON_MODELPROJECT_0_SHIFT 0
2354 # define RADEON_MODELPROJECT_1_SHIFT 4
2355 # define RADEON_MODELPROJECT_2_SHIFT 8
2356 # define RADEON_MODELPROJECT_3_SHIFT 12
2357 # define RADEON_TEXMAT_0_SHIFT 16
2358 # define RADEON_TEXMAT_1_SHIFT 20
2359 # define RADEON_TEXMAT_2_SHIFT 24
2360 # define RADEON_TEXMAT_3_SHIFT 28
2363 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
2364 # define RADEON_TCL_VTX_W0 (1 << 0)
2365 # define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)
2366 # define RADEON_TCL_VTX_FP_ALPHA (1 << 2)
2367 # define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)
2368 # define RADEON_TCL_VTX_FP_SPEC (1 << 4)
2369 # define RADEON_TCL_VTX_FP_FOG (1 << 5)
2370 # define RADEON_TCL_VTX_PK_SPEC (1 << 6)
2371 # define RADEON_TCL_VTX_ST0 (1 << 7)
2372 # define RADEON_TCL_VTX_ST1 (1 << 8)
2373 # define RADEON_TCL_VTX_Q1 (1 << 9)
2374 # define RADEON_TCL_VTX_ST2 (1 << 10)
2375 # define RADEON_TCL_VTX_Q2 (1 << 11)
2376 # define RADEON_TCL_VTX_ST3 (1 << 12)
2377 # define RADEON_TCL_VTX_Q3 (1 << 13)
2378 # define RADEON_TCL_VTX_Q0 (1 << 14)
2379 # define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15
2380 # define RADEON_TCL_VTX_NORM0 (1 << 18)
2381 # define RADEON_TCL_VTX_XY1 (1 << 27)
2382 # define RADEON_TCL_VTX_Z1 (1 << 28)
2383 # define RADEON_TCL_VTX_W1 (1 << 29)
2384 # define RADEON_TCL_VTX_NORM1 (1 << 30)
2385 # define RADEON_TCL_VTX_Z0 (1 << 31)
2387 #define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258
2388 # define RADEON_TCL_COMPUTE_XYZW (1 << 0)
2389 # define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)
2390 # define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)
2391 # define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)
2392 # define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)
2393 # define RADEON_TCL_TEX_INPUT_TEX_0 0
2394 # define RADEON_TCL_TEX_INPUT_TEX_1 1
2395 # define RADEON_TCL_TEX_INPUT_TEX_2 2
2396 # define RADEON_TCL_TEX_INPUT_TEX_3 3
2397 # define RADEON_TCL_TEX_COMPUTED_TEX_0 8
2398 # define RADEON_TCL_TEX_COMPUTED_TEX_1 9
2399 # define RADEON_TCL_TEX_COMPUTED_TEX_2 10
2400 # define RADEON_TCL_TEX_COMPUTED_TEX_3 11
2401 # define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16
2402 # define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20
2403 # define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24
2404 # define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28
2406 #define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270
2407 # define RADEON_LIGHT_0_ENABLE (1 << 0)
2408 # define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)
2409 # define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)
2410 # define RADEON_LIGHT_0_IS_LOCAL (1 << 3)
2411 # define RADEON_LIGHT_0_IS_SPOT (1 << 4)
2412 # define RADEON_LIGHT_0_DUAL_CONE (1 << 5)
2413 # define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)
2414 # define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)
2415 # define RADEON_LIGHT_0_SHIFT 0
2416 # define RADEON_LIGHT_1_ENABLE (1 << 16)
2417 # define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)
2418 # define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)
2419 # define RADEON_LIGHT_1_IS_LOCAL (1 << 19)
2420 # define RADEON_LIGHT_1_IS_SPOT (1 << 20)
2421 # define RADEON_LIGHT_1_DUAL_CONE (1 << 21)
2422 # define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)
2423 # define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)
2424 # define RADEON_LIGHT_1_SHIFT 16
2425 #define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274
2426 # define RADEON_LIGHT_2_SHIFT 0
2427 # define RADEON_LIGHT_3_SHIFT 16
2428 #define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278
2429 # define RADEON_LIGHT_4_SHIFT 0
2430 # define RADEON_LIGHT_5_SHIFT 16
2431 #define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c
2432 # define RADEON_LIGHT_6_SHIFT 0
2433 # define RADEON_LIGHT_7_SHIFT 16
2435 #define RADEON_SE_TCL_SHININESS 0x2250
2437 #define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268
2438 # define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)
2439 # define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)
2440 # define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)
2441 # define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)
2442 # define RADEON_TEXMAT_0_ENABLE (1 << 4)
2443 # define RADEON_TEXMAT_1_ENABLE (1 << 5)
2444 # define RADEON_TEXMAT_2_ENABLE (1 << 6)
2445 # define RADEON_TEXMAT_3_ENABLE (1 << 7)
2446 # define RADEON_TEXGEN_INPUT_MASK 0xf
2447 # define RADEON_TEXGEN_INPUT_TEXCOORD_0 0
2448 # define RADEON_TEXGEN_INPUT_TEXCOORD_1 1
2449 # define RADEON_TEXGEN_INPUT_TEXCOORD_2 2
2450 # define RADEON_TEXGEN_INPUT_TEXCOORD_3 3
2451 # define RADEON_TEXGEN_INPUT_OBJ 4
2452 # define RADEON_TEXGEN_INPUT_EYE 5
2453 # define RADEON_TEXGEN_INPUT_EYE_NORMAL 6
2454 # define RADEON_TEXGEN_INPUT_EYE_REFLECT 7
2455 # define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8
2456 # define RADEON_TEXGEN_0_INPUT_SHIFT 16
2457 # define RADEON_TEXGEN_1_INPUT_SHIFT 20
2458 # define RADEON_TEXGEN_2_INPUT_SHIFT 24
2459 # define RADEON_TEXGEN_3_INPUT_SHIFT 28
2461 #define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264
2462 # define RADEON_UCP_IN_CLIP_SPACE (1 << 0)
2463 # define RADEON_UCP_IN_MODEL_SPACE (1 << 1)
2464 # define RADEON_UCP_ENABLE_0 (1 << 2)
2465 # define RADEON_UCP_ENABLE_1 (1 << 3)
2466 # define RADEON_UCP_ENABLE_2 (1 << 4)
2467 # define RADEON_UCP_ENABLE_3 (1 << 5)
2468 # define RADEON_UCP_ENABLE_4 (1 << 6)
2469 # define RADEON_UCP_ENABLE_5 (1 << 7)
2470 # define RADEON_TCL_FOG_MASK (3 << 8)
2471 # define RADEON_TCL_FOG_DISABLE (0 << 8)
2472 # define RADEON_TCL_FOG_EXP (1 << 8)
2473 # define RADEON_TCL_FOG_EXP2 (2 << 8)
2474 # define RADEON_TCL_FOG_LINEAR (3 << 8)
2475 # define RADEON_RNG_BASED_FOG (1 << 10)
2476 # define RADEON_LIGHT_TWOSIDE (1 << 11)
2477 # define RADEON_BLEND_OP_COUNT_MASK (7 << 12)
2478 # define RADEON_BLEND_OP_COUNT_SHIFT 12
2479 # define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)
2480 # define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)
2481 # define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)
2482 # define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)
2483 # define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)
2484 # define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)
2485 # define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)
2486 # define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)
2487 # define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)
2488 # define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)
2489 # define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)
2490 # define RADEON_CULL_FRONT_IS_CW (0 << 28)
2491 # define RADEON_CULL_FRONT_IS_CCW (1 << 28)
2492 # define RADEON_CULL_FRONT (1 << 29)
2493 # define RADEON_CULL_BACK (1 << 30)
2494 # define RADEON_FORCE_W_TO_ONE (1 << 31)
2496 #define RADEON_SE_VPORT_XSCALE 0x1d98
2497 #define RADEON_SE_VPORT_XOFFSET 0x1d9c
2498 #define RADEON_SE_VPORT_YSCALE 0x1da0
2499 #define RADEON_SE_VPORT_YOFFSET 0x1da4
2500 #define RADEON_SE_VPORT_ZSCALE 0x1da8
2501 #define RADEON_SE_VPORT_ZOFFSET 0x1dac
2502 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
2503 #define RADEON_SE_ZBIAS_CONSTANT 0x1db4
2505 #define RADEON_SE_VTX_FMT 0x2080
2506 # define RADEON_SE_VTX_FMT_XY 0x00000000
2507 # define RADEON_SE_VTX_FMT_W0 0x00000001
2508 # define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002
2509 # define RADEON_SE_VTX_FMT_FPALPHA 0x00000004
2510 # define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008
2511 # define RADEON_SE_VTX_FMT_FPSPEC 0x00000010
2512 # define RADEON_SE_VTX_FMT_FPFOG 0x00000020
2513 # define RADEON_SE_VTX_FMT_PKSPEC 0x00000040
2514 # define RADEON_SE_VTX_FMT_ST0 0x00000080
2515 # define RADEON_SE_VTX_FMT_ST1 0x00000100
2516 # define RADEON_SE_VTX_FMT_Q1 0x00000200
2517 # define RADEON_SE_VTX_FMT_ST2 0x00000400
2518 # define RADEON_SE_VTX_FMT_Q2 0x00000800
2519 # define RADEON_SE_VTX_FMT_ST3 0x00001000
2520 # define RADEON_SE_VTX_FMT_Q3 0x00002000
2521 # define RADEON_SE_VTX_FMT_Q0 0x00004000
2522 # define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000
2523 # define RADEON_SE_VTX_FMT_N0 0x00040000
2524 # define RADEON_SE_VTX_FMT_XY1 0x08000000
2525 # define RADEON_SE_VTX_FMT_Z1 0x10000000
2526 # define RADEON_SE_VTX_FMT_W1 0x20000000
2527 # define RADEON_SE_VTX_FMT_N1 0x40000000
2528 # define RADEON_SE_VTX_FMT_Z 0x80000000
2530 #define RADEON_SE_VF_CNTL 0x2084
2531 # define RADEON_VF_PRIM_TYPE_POINT_LIST 1
2532 # define RADEON_VF_PRIM_TYPE_LINE_LIST 2
2533 # define RADEON_VF_PRIM_TYPE_LINE_STRIP 3
2534 # define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4
2535 # define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5
2536 # define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6
2537 # define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7
2538 # define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8
2539 # define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9
2540 # define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10
2541 # define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11
2542 # define RADEON_VF_PRIM_TYPE_LINE_LOOP 12
2543 # define RADEON_VF_PRIM_TYPE_QUAD_LIST 13
2544 # define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14
2545 # define RADEON_VF_PRIM_TYPE_POLYGON 15
2546 # define RADEON_VF_PRIM_WALK_STATE (0<<4)
2547 # define RADEON_VF_PRIM_WALK_INDEX (1<<4)
2548 # define RADEON_VF_PRIM_WALK_LIST (2<<4)
2549 # define RADEON_VF_PRIM_WALK_DATA (3<<4)
2550 # define RADEON_VF_COLOR_ORDER_RGBA (1<<6)
2551 # define RADEON_VF_RADEON_MODE (1<<8)
2552 # define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)
2553 # define RADEON_VF_PROG_STREAM_ENA (1<<10)
2554 # define RADEON_VF_INDEX_SIZE_SHIFT 11
2555 # define RADEON_VF_NUM_VERTICES_SHIFT 16
2557 #define RADEON_SE_PORT_DATA0 0x2000
2559 #define R200_SE_VAP_CNTL 0x2080
2560 # define R200_VAP_TCL_ENABLE 0x00000001
2561 # define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010
2562 # define R200_VAP_FORCE_W_TO_ONE 0x00010000
2563 # define R200_VAP_D3D_TEX_DEFAULT 0x00020000
2564 # define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18
2565 # define R200_VAP_VF_MAX_VTX_NUM (9 << 18)
2566 # define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000
2567 #define R200_VF_MAX_VTX_INDX 0x210c
2568 #define R200_VF_MIN_VTX_INDX 0x2110
2569 #define R200_SE_VTE_CNTL 0x20b0
2570 # define R200_VPORT_X_SCALE_ENA 0x00000001
2571 # define R200_VPORT_X_OFFSET_ENA 0x00000002
2572 # define R200_VPORT_Y_SCALE_ENA 0x00000004
2573 # define R200_VPORT_Y_OFFSET_ENA 0x00000008
2574 # define R200_VPORT_Z_SCALE_ENA 0x00000010
2575 # define R200_VPORT_Z_OFFSET_ENA 0x00000020
2576 # define R200_VTX_XY_FMT 0x00000100
2577 # define R200_VTX_Z_FMT 0x00000200
2578 # define R200_VTX_W0_FMT 0x00000400
2579 # define R200_VTX_W0_NORMALIZE 0x00000800
2580 # define R200_VTX_ST_DENORMALIZED 0x00001000
2581 #define R200_SE_VAP_CNTL_STATUS 0x2140
2582 # define R200_VC_NO_SWAP (0 << 0)
2583 # define R200_VC_16BIT_SWAP (1 << 0)
2584 # define R200_VC_32BIT_SWAP (2 << 0)
2585 #define R200_PP_TXFILTER_0 0x2c00
2586 #define R200_PP_TXFILTER_1 0x2c20
2587 #define R200_PP_TXFILTER_2 0x2c40
2588 #define R200_PP_TXFILTER_3 0x2c60
2589 #define R200_PP_TXFILTER_4 0x2c80
2590 #define R200_PP_TXFILTER_5 0x2ca0
2591 # define R200_MAG_FILTER_NEAREST (0 << 0)
2592 # define R200_MAG_FILTER_LINEAR (1 << 0)
2593 # define R200_MAG_FILTER_MASK (1 << 0)
2594 # define R200_MIN_FILTER_NEAREST (0 << 1)
2595 # define R200_MIN_FILTER_LINEAR (1 << 1)
2596 # define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
2597 # define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
2598 # define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
2599 # define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
2600 # define R200_MIN_FILTER_ANISO_NEAREST (8 << 1)
2601 # define R200_MIN_FILTER_ANISO_LINEAR (9 << 1)
2602 # define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
2603 # define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
2604 # define R200_MIN_FILTER_MASK (15 << 1)
2605 # define R200_MAX_ANISO_1_TO_1 (0 << 5)
2606 # define R200_MAX_ANISO_2_TO_1 (1 << 5)
2607 # define R200_MAX_ANISO_4_TO_1 (2 << 5)
2608 # define R200_MAX_ANISO_8_TO_1 (3 << 5)
2609 # define R200_MAX_ANISO_16_TO_1 (4 << 5)
2610 # define R200_MAX_ANISO_MASK (7 << 5)
2611 # define R200_MAX_MIP_LEVEL_MASK (0x0f << 16)
2612 # define R200_MAX_MIP_LEVEL_SHIFT 16
2613 # define R200_YUV_TO_RGB (1 << 20)
2614 # define R200_YUV_TEMPERATURE_COOL (0 << 21)
2615 # define R200_YUV_TEMPERATURE_HOT (1 << 21)
2616 # define R200_YUV_TEMPERATURE_MASK (1 << 21)
2617 # define R200_WRAPEN_S (1 << 22)
2618 # define R200_CLAMP_S_WRAP (0 << 23)
2619 # define R200_CLAMP_S_MIRROR (1 << 23)
2620 # define R200_CLAMP_S_CLAMP_LAST (2 << 23)
2621 # define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
2622 # define R200_CLAMP_S_CLAMP_BORDER (4 << 23)
2623 # define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
2624 # define R200_CLAMP_S_CLAMP_GL (6 << 23)
2625 # define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
2626 # define R200_CLAMP_S_MASK (7 << 23)
2627 # define R200_WRAPEN_T (1 << 26)
2628 # define R200_CLAMP_T_WRAP (0 << 27)
2629 # define R200_CLAMP_T_MIRROR (1 << 27)
2630 # define R200_CLAMP_T_CLAMP_LAST (2 << 27)
2631 # define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
2632 # define R200_CLAMP_T_CLAMP_BORDER (4 << 27)
2633 # define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
2634 # define R200_CLAMP_T_CLAMP_GL (6 << 27)
2635 # define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
2636 # define R200_CLAMP_T_MASK (7 << 27)
2637 # define R200_KILL_LT_ZERO (1 << 30)
2638 # define R200_BORDER_MODE_OGL (0 << 31)
2639 # define R200_BORDER_MODE_D3D (1 << 31)
2640 #define R200_PP_TXFORMAT_0 0x2c04
2641 #define R200_PP_TXFORMAT_1 0x2c24
2642 #define R200_PP_TXFORMAT_2 0x2c44
2643 #define R200_PP_TXFORMAT_3 0x2c64
2644 #define R200_PP_TXFORMAT_4 0x2c84
2645 #define R200_PP_TXFORMAT_5 0x2ca4
2646 # define R200_TXFORMAT_I8 (0 << 0)
2647 # define R200_TXFORMAT_AI88 (1 << 0)
2648 # define R200_TXFORMAT_RGB332 (2 << 0)
2649 # define R200_TXFORMAT_ARGB1555 (3 << 0)
2650 # define R200_TXFORMAT_RGB565 (4 << 0)
2651 # define R200_TXFORMAT_ARGB4444 (5 << 0)
2652 # define R200_TXFORMAT_ARGB8888 (6 << 0)
2653 # define R200_TXFORMAT_RGBA8888 (7 << 0)
2654 # define R200_TXFORMAT_Y8 (8 << 0)
2655 # define R200_TXFORMAT_AVYU4444 (9 << 0)
2656 # define R200_TXFORMAT_VYUY422 (10 << 0)
2657 # define R200_TXFORMAT_YVYU422 (11 << 0)
2658 # define R200_TXFORMAT_DXT1 (12 << 0)
2659 # define R200_TXFORMAT_DXT23 (14 << 0)
2660 # define R200_TXFORMAT_DXT45 (15 << 0)
2661 # define R200_TXFORMAT_ABGR8888 (22 << 0)
2662 # define R200_TXFORMAT_FORMAT_MASK (31 << 0)
2663 # define R200_TXFORMAT_FORMAT_SHIFT 0
2664 # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)
2665 # define R200_TXFORMAT_NON_POWER2 (1 << 7)
2666 # define R200_TXFORMAT_WIDTH_MASK (15 << 8)
2667 # define R200_TXFORMAT_WIDTH_SHIFT 8
2668 # define R200_TXFORMAT_HEIGHT_MASK (15 << 12)
2669 # define R200_TXFORMAT_HEIGHT_SHIFT 12
2670 # define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */
2671 # define R200_TXFORMAT_F5_WIDTH_SHIFT 16
2672 # define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
2673 # define R200_TXFORMAT_F5_HEIGHT_SHIFT 20
2674 # define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
2675 # define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
2676 # define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
2677 # define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24)
2678 # define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24)
2679 # define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24)
2680 # define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24)
2681 # define R200_TXFORMAT_ST_ROUTE_SHIFT 24
2682 # define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
2683 # define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
2684 # define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
2685 #define R200_PP_TXFORMAT_X_0 0x2c08
2686 #define R200_PP_TXFORMAT_X_1 0x2c28
2687 #define R200_PP_TXFORMAT_X_2 0x2c48
2688 #define R200_PP_TXFORMAT_X_3 0x2c68
2689 #define R200_PP_TXFORMAT_X_4 0x2c88
2690 #define R200_PP_TXFORMAT_X_5 0x2ca8
2692 #define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */
2693 #define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */
2694 #define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */
2695 #define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */
2696 #define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */
2697 #define R200_PP_TXSIZE_5 0x2cac /* NPOT only */
2699 #define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */
2700 #define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */
2701 #define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */
2702 #define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */
2703 #define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */
2704 #define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */
2706 #define R200_PP_TXOFFSET_0 0x2d00
2707 # define R200_TXO_ENDIAN_NO_SWAP (0 << 0)
2708 # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)
2709 # define R200_TXO_ENDIAN_WORD_SWAP (2 << 0)
2710 # define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
2711 # define R200_TXO_MACRO_LINEAR (0 << 2)
2712 # define R200_TXO_MACRO_TILE (1 << 2)
2713 # define R200_TXO_MICRO_LINEAR (0 << 3)
2714 # define R200_TXO_MICRO_TILE (1 << 3)
2715 # define R200_TXO_OFFSET_MASK 0xffffffe0
2716 # define R200_TXO_OFFSET_SHIFT 5
2717 #define R200_PP_TXOFFSET_1 0x2d18
2718 #define R200_PP_TXOFFSET_2 0x2d30
2719 #define R200_PP_TXOFFSET_3 0x2d48
2720 #define R200_PP_TXOFFSET_4 0x2d60
2721 #define R200_PP_TXOFFSET_5 0x2d78
2723 #define R200_PP_TFACTOR_0 0x2ee0
2724 #define R200_PP_TFACTOR_1 0x2ee4
2725 #define R200_PP_TFACTOR_2 0x2ee8
2726 #define R200_PP_TFACTOR_3 0x2eec
2727 #define R200_PP_TFACTOR_4 0x2ef0
2728 #define R200_PP_TFACTOR_5 0x2ef4
2730 #define R200_PP_TXCBLEND_0 0x2f00
2731 # define R200_TXC_ARG_A_ZERO (0)
2732 # define R200_TXC_ARG_A_CURRENT_COLOR (2)
2733 # define R200_TXC_ARG_A_CURRENT_ALPHA (3)
2734 # define R200_TXC_ARG_A_DIFFUSE_COLOR (4)
2735 # define R200_TXC_ARG_A_DIFFUSE_ALPHA (5)
2736 # define R200_TXC_ARG_A_SPECULAR_COLOR (6)
2737 # define R200_TXC_ARG_A_SPECULAR_ALPHA (7)
2738 # define R200_TXC_ARG_A_TFACTOR_COLOR (8)
2739 # define R200_TXC_ARG_A_TFACTOR_ALPHA (9)
2740 # define R200_TXC_ARG_A_R0_COLOR (10)
2741 # define R200_TXC_ARG_A_R0_ALPHA (11)
2742 # define R200_TXC_ARG_A_R1_COLOR (12)
2743 # define R200_TXC_ARG_A_R1_ALPHA (13)
2744 # define R200_TXC_ARG_A_R2_COLOR (14)
2745 # define R200_TXC_ARG_A_R2_ALPHA (15)
2746 # define R200_TXC_ARG_A_R3_COLOR (16)
2747 # define R200_TXC_ARG_A_R3_ALPHA (17)
2748 # define R200_TXC_ARG_A_R4_COLOR (18)
2749 # define R200_TXC_ARG_A_R4_ALPHA (19)
2750 # define R200_TXC_ARG_A_R5_COLOR (20)
2751 # define R200_TXC_ARG_A_R5_ALPHA (21)
2752 # define R200_TXC_ARG_A_TFACTOR1_COLOR (26)
2753 # define R200_TXC_ARG_A_TFACTOR1_ALPHA (27)
2754 # define R200_TXC_ARG_A_MASK (31 << 0)
2755 # define R200_TXC_ARG_A_SHIFT 0
2756 # define R200_TXC_ARG_B_ZERO (0 << 5)
2757 # define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5)
2758 # define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5)
2759 # define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5)
2760 # define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5)
2761 # define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5)
2762 # define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5)
2763 # define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5)
2764 # define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5)
2765 # define R200_TXC_ARG_B_R0_COLOR (10 << 5)
2766 # define R200_TXC_ARG_B_R0_ALPHA (11 << 5)
2767 # define R200_TXC_ARG_B_R1_COLOR (12 << 5)
2768 # define R200_TXC_ARG_B_R1_ALPHA (13 << 5)
2769 # define R200_TXC_ARG_B_R2_COLOR (14 << 5)
2770 # define R200_TXC_ARG_B_R2_ALPHA (15 << 5)
2771 # define R200_TXC_ARG_B_R3_COLOR (16 << 5)
2772 # define R200_TXC_ARG_B_R3_ALPHA (17 << 5)
2773 # define R200_TXC_ARG_B_R4_COLOR (18 << 5)
2774 # define R200_TXC_ARG_B_R4_ALPHA (19 << 5)
2775 # define R200_TXC_ARG_B_R5_COLOR (20 << 5)
2776 # define R200_TXC_ARG_B_R5_ALPHA (21 << 5)
2777 # define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5)
2778 # define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5)
2779 # define R200_TXC_ARG_B_MASK (31 << 5)
2780 # define R200_TXC_ARG_B_SHIFT 5
2781 # define R200_TXC_ARG_C_ZERO (0 << 10)
2782 # define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10)
2783 # define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10)
2784 # define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10)
2785 # define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10)
2786 # define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10)
2787 # define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10)
2788 # define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10)
2789 # define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10)
2790 # define R200_TXC_ARG_C_R0_COLOR (10 << 10)
2791 # define R200_TXC_ARG_C_R0_ALPHA (11 << 10)
2792 # define R200_TXC_ARG_C_R1_COLOR (12 << 10)
2793 # define R200_TXC_ARG_C_R1_ALPHA (13 << 10)
2794 # define R200_TXC_ARG_C_R2_COLOR (14 << 10)
2795 # define R200_TXC_ARG_C_R2_ALPHA (15 << 10)
2796 # define R200_TXC_ARG_C_R3_COLOR (16 << 10)
2797 # define R200_TXC_ARG_C_R3_ALPHA (17 << 10)
2798 # define R200_TXC_ARG_C_R4_COLOR (18 << 10)
2799 # define R200_TXC_ARG_C_R4_ALPHA (19 << 10)
2800 # define R200_TXC_ARG_C_R5_COLOR (20 << 10)
2801 # define R200_TXC_ARG_C_R5_ALPHA (21 << 10)
2802 # define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10)
2803 # define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10)
2804 # define R200_TXC_ARG_C_MASK (31 << 10)
2805 # define R200_TXC_ARG_C_SHIFT 10
2806 # define R200_TXC_COMP_ARG_A (1 << 16)
2807 # define R200_TXC_COMP_ARG_A_SHIFT (16)
2808 # define R200_TXC_BIAS_ARG_A (1 << 17)
2809 # define R200_TXC_SCALE_ARG_A (1 << 18)
2810 # define R200_TXC_NEG_ARG_A (1 << 19)
2811 # define R200_TXC_COMP_ARG_B (1 << 20)
2812 # define R200_TXC_COMP_ARG_B_SHIFT (20)
2813 # define R200_TXC_BIAS_ARG_B (1 << 21)
2814 # define R200_TXC_SCALE_ARG_B (1 << 22)
2815 # define R200_TXC_NEG_ARG_B (1 << 23)
2816 # define R200_TXC_COMP_ARG_C (1 << 24)
2817 # define R200_TXC_COMP_ARG_C_SHIFT (24)
2818 # define R200_TXC_BIAS_ARG_C (1 << 25)
2819 # define R200_TXC_SCALE_ARG_C (1 << 26)
2820 # define R200_TXC_NEG_ARG_C (1 << 27)
2821 # define R200_TXC_OP_MADD (0 << 28)
2822 # define R200_TXC_OP_CND0 (2 << 28)
2823 # define R200_TXC_OP_LERP (3 << 28)
2824 # define R200_TXC_OP_DOT3 (4 << 28)
2825 # define R200_TXC_OP_DOT4 (5 << 28)
2826 # define R200_TXC_OP_CONDITIONAL (6 << 28)
2827 # define R200_TXC_OP_DOT2_ADD (7 << 28)
2828 # define R200_TXC_OP_MASK (7 << 28)
2829 #define R200_PP_TXCBLEND2_0 0x2f04
2830 # define R200_TXC_TFACTOR_SEL_SHIFT 0
2831 # define R200_TXC_TFACTOR_SEL_MASK 0x7
2832 # define R200_TXC_TFACTOR1_SEL_SHIFT 4
2833 # define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4)
2834 # define R200_TXC_SCALE_SHIFT 8
2835 # define R200_TXC_SCALE_MASK (7 << 8)
2836 # define R200_TXC_SCALE_1X (0 << 8)
2837 # define R200_TXC_SCALE_2X (1 << 8)
2838 # define R200_TXC_SCALE_4X (2 << 8)
2839 # define R200_TXC_SCALE_8X (3 << 8)
2840 # define R200_TXC_SCALE_INV2 (5 << 8)
2841 # define R200_TXC_SCALE_INV4 (6 << 8)
2842 # define R200_TXC_SCALE_INV8 (7 << 8)
2843 # define R200_TXC_CLAMP_SHIFT 12
2844 # define R200_TXC_CLAMP_MASK (3 << 12)
2845 # define R200_TXC_CLAMP_WRAP (0 << 12)
2846 # define R200_TXC_CLAMP_0_1 (1 << 12)
2847 # define R200_TXC_CLAMP_8_8 (2 << 12)
2848 # define R200_TXC_OUTPUT_REG_MASK (7 << 16)
2849 # define R200_TXC_OUTPUT_REG_NONE (0 << 16)
2850 # define R200_TXC_OUTPUT_REG_R0 (1 << 16)
2851 # define R200_TXC_OUTPUT_REG_R1 (2 << 16)
2852 # define R200_TXC_OUTPUT_REG_R2 (3 << 16)
2853 # define R200_TXC_OUTPUT_REG_R3 (4 << 16)
2854 # define R200_TXC_OUTPUT_REG_R4 (5 << 16)
2855 # define R200_TXC_OUTPUT_REG_R5 (6 << 16)
2856 # define R200_TXC_OUTPUT_MASK_MASK (7 << 20)
2857 # define R200_TXC_OUTPUT_MASK_RGB (0 << 20)
2858 # define R200_TXC_OUTPUT_MASK_RG (1 << 20)
2859 # define R200_TXC_OUTPUT_MASK_RB (2 << 20)
2860 # define R200_TXC_OUTPUT_MASK_R (3 << 20)
2861 # define R200_TXC_OUTPUT_MASK_GB (4 << 20)
2862 # define R200_TXC_OUTPUT_MASK_G (5 << 20)
2863 # define R200_TXC_OUTPUT_MASK_B (6 << 20)
2864 # define R200_TXC_OUTPUT_MASK_NONE (7 << 20)
2865 # define R200_TXC_REPL_NORMAL 0
2866 # define R200_TXC_REPL_RED 1
2867 # define R200_TXC_REPL_GREEN 2
2868 # define R200_TXC_REPL_BLUE 3
2869 # define R200_TXC_REPL_ARG_A_SHIFT 26
2870 # define R200_TXC_REPL_ARG_A_MASK (3 << 26)
2871 # define R200_TXC_REPL_ARG_B_SHIFT 28
2872 # define R200_TXC_REPL_ARG_B_MASK (3 << 28)
2873 # define R200_TXC_REPL_ARG_C_SHIFT 30
2874 # define R200_TXC_REPL_ARG_C_MASK (3 << 30)
2875 #define R200_PP_TXABLEND_0 0x2f08
2876 # define R200_TXA_ARG_A_ZERO (0)
2877 # define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */
2878 # define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */
2879 # define R200_TXA_ARG_A_DIFFUSE_ALPHA (4)
2880 # define R200_TXA_ARG_A_DIFFUSE_BLUE (5)
2881 # define R200_TXA_ARG_A_SPECULAR_ALPHA (6)
2882 # define R200_TXA_ARG_A_SPECULAR_BLUE (7)
2883 # define R200_TXA_ARG_A_TFACTOR_ALPHA (8)
2884 # define R200_TXA_ARG_A_TFACTOR_BLUE (9)
2885 # define R200_TXA_ARG_A_R0_ALPHA (10)
2886 # define R200_TXA_ARG_A_R0_BLUE (11)
2887 # define R200_TXA_ARG_A_R1_ALPHA (12)
2888 # define R200_TXA_ARG_A_R1_BLUE (13)
2889 # define R200_TXA_ARG_A_R2_ALPHA (14)
2890 # define R200_TXA_ARG_A_R2_BLUE (15)
2891 # define R200_TXA_ARG_A_R3_ALPHA (16)
2892 # define R200_TXA_ARG_A_R3_BLUE (17)
2893 # define R200_TXA_ARG_A_R4_ALPHA (18)
2894 # define R200_TXA_ARG_A_R4_BLUE (19)
2895 # define R200_TXA_ARG_A_R5_ALPHA (20)
2896 # define R200_TXA_ARG_A_R5_BLUE (21)
2897 # define R200_TXA_ARG_A_TFACTOR1_ALPHA (26)
2898 # define R200_TXA_ARG_A_TFACTOR1_BLUE (27)
2899 # define R200_TXA_ARG_A_MASK (31 << 0)
2900 # define R200_TXA_ARG_A_SHIFT 0
2901 # define R200_TXA_ARG_B_ZERO (0 << 5)
2902 # define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */
2903 # define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */
2904 # define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5)
2905 # define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5)
2906 # define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5)
2907 # define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5)
2908 # define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5)
2909 # define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5)
2910 # define R200_TXA_ARG_B_R0_ALPHA (10 << 5)
2911 # define R200_TXA_ARG_B_R0_BLUE (11 << 5)
2912 # define R200_TXA_ARG_B_R1_ALPHA (12 << 5)
2913 # define R200_TXA_ARG_B_R1_BLUE (13 << 5)
2914 # define R200_TXA_ARG_B_R2_ALPHA (14 << 5)
2915 # define R200_TXA_ARG_B_R2_BLUE (15 << 5)
2916 # define R200_TXA_ARG_B_R3_ALPHA (16 << 5)
2917 # define R200_TXA_ARG_B_R3_BLUE (17 << 5)
2918 # define R200_TXA_ARG_B_R4_ALPHA (18 << 5)
2919 # define R200_TXA_ARG_B_R4_BLUE (19 << 5)
2920 # define R200_TXA_ARG_B_R5_ALPHA (20 << 5)
2921 # define R200_TXA_ARG_B_R5_BLUE (21 << 5)
2922 # define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5)
2923 # define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5)
2924 # define R200_TXA_ARG_B_MASK (31 << 5)
2925 # define R200_TXA_ARG_B_SHIFT 5
2926 # define R200_TXA_ARG_C_ZERO (0 << 10)
2927 # define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */
2928 # define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */
2929 # define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10)
2930 # define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10)
2931 # define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10)
2932 # define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10)
2933 # define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10)
2934 # define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10)
2935 # define R200_TXA_ARG_C_R0_ALPHA (10 << 10)
2936 # define R200_TXA_ARG_C_R0_BLUE (11 << 10)
2937 # define R200_TXA_ARG_C_R1_ALPHA (12 << 10)
2938 # define R200_TXA_ARG_C_R1_BLUE (13 << 10)
2939 # define R200_TXA_ARG_C_R2_ALPHA (14 << 10)
2940 # define R200_TXA_ARG_C_R2_BLUE (15 << 10)
2941 # define R200_TXA_ARG_C_R3_ALPHA (16 << 10)
2942 # define R200_TXA_ARG_C_R3_BLUE (17 << 10)
2943 # define R200_TXA_ARG_C_R4_ALPHA (18 << 10)
2944 # define R200_TXA_ARG_C_R4_BLUE (19 << 10)
2945 # define R200_TXA_ARG_C_R5_ALPHA (20 << 10)
2946 # define R200_TXA_ARG_C_R5_BLUE (21 << 10)
2947 # define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10)
2948 # define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10)
2949 # define R200_TXA_ARG_C_MASK (31 << 10)
2950 # define R200_TXA_ARG_C_SHIFT 10
2951 # define R200_TXA_COMP_ARG_A (1 << 16)
2952 # define R200_TXA_COMP_ARG_A_SHIFT (16)
2953 # define R200_TXA_BIAS_ARG_A (1 << 17)
2954 # define R200_TXA_SCALE_ARG_A (1 << 18)
2955 # define R200_TXA_NEG_ARG_A (1 << 19)
2956 # define R200_TXA_COMP_ARG_B (1 << 20)
2957 # define R200_TXA_COMP_ARG_B_SHIFT (20)
2958 # define R200_TXA_BIAS_ARG_B (1 << 21)
2959 # define R200_TXA_SCALE_ARG_B (1 << 22)
2960 # define R200_TXA_NEG_ARG_B (1 << 23)
2961 # define R200_TXA_COMP_ARG_C (1 << 24)
2962 # define R200_TXA_COMP_ARG_C_SHIFT (24)
2963 # define R200_TXA_BIAS_ARG_C (1 << 25)
2964 # define R200_TXA_SCALE_ARG_C (1 << 26)
2965 # define R200_TXA_NEG_ARG_C (1 << 27)
2966 # define R200_TXA_OP_MADD (0 << 28)
2967 # define R200_TXA_OP_CND0 (2 << 28)
2968 # define R200_TXA_OP_LERP (3 << 28)
2969 # define R200_TXA_OP_CONDITIONAL (6 << 28)
2970 # define R200_TXA_OP_MASK (7 << 28)
2971 #define R200_PP_TXABLEND2_0 0x2f0c
2972 # define R200_TXA_TFACTOR_SEL_SHIFT 0
2973 # define R200_TXA_TFACTOR_SEL_MASK 0x7
2974 # define R200_TXA_TFACTOR1_SEL_SHIFT 4
2975 # define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4)
2976 # define R200_TXA_SCALE_SHIFT 8
2977 # define R200_TXA_SCALE_MASK (7 << 8)
2978 # define R200_TXA_SCALE_1X (0 << 8)
2979 # define R200_TXA_SCALE_2X (1 << 8)
2980 # define R200_TXA_SCALE_4X (2 << 8)
2981 # define R200_TXA_SCALE_8X (3 << 8)
2982 # define R200_TXA_SCALE_INV2 (5 << 8)
2983 # define R200_TXA_SCALE_INV4 (6 << 8)
2984 # define R200_TXA_SCALE_INV8 (7 << 8)
2985 # define R200_TXA_CLAMP_SHIFT 12
2986 # define R200_TXA_CLAMP_MASK (3 << 12)
2987 # define R200_TXA_CLAMP_WRAP (0 << 12)
2988 # define R200_TXA_CLAMP_0_1 (1 << 12)
2989 # define R200_TXA_CLAMP_8_8 (2 << 12)
2990 # define R200_TXA_OUTPUT_REG_MASK (7 << 16)
2991 # define R200_TXA_OUTPUT_REG_NONE (0 << 16)
2992 # define R200_TXA_OUTPUT_REG_R0 (1 << 16)
2993 # define R200_TXA_OUTPUT_REG_R1 (2 << 16)
2994 # define R200_TXA_OUTPUT_REG_R2 (3 << 16)
2995 # define R200_TXA_OUTPUT_REG_R3 (4 << 16)
2996 # define R200_TXA_OUTPUT_REG_R4 (5 << 16)
2997 # define R200_TXA_OUTPUT_REG_R5 (6 << 16)
2998 # define R200_TXA_DOT_ALPHA (1 << 20)
2999 # define R200_TXA_REPL_NORMAL 0
3000 # define R200_TXA_REPL_RED 1
3001 # define R200_TXA_REPL_GREEN 2
3002 # define R200_TXA_REPL_ARG_A_SHIFT 26
3003 # define R200_TXA_REPL_ARG_A_MASK (3 << 26)
3004 # define R200_TXA_REPL_ARG_B_SHIFT 28
3005 # define R200_TXA_REPL_ARG_B_MASK (3 << 28)
3006 # define R200_TXA_REPL_ARG_C_SHIFT 30
3007 # define R200_TXA_REPL_ARG_C_MASK (3 << 30)
3009 #define R200_SE_VTX_FMT_0 0x2088
3010 # define R200_VTX_XY 0 /* always have xy */
3011 # define R200_VTX_Z0 (1<<0)
3012 # define R200_VTX_W0 (1<<1)
3013 # define R200_VTX_WEIGHT_COUNT_SHIFT (2)
3014 # define R200_VTX_PV_MATRIX_SEL (1<<5)
3015 # define R200_VTX_N0 (1<<6)
3016 # define R200_VTX_POINT_SIZE (1<<7)
3017 # define R200_VTX_DISCRETE_FOG (1<<8)
3018 # define R200_VTX_SHININESS_0 (1<<9)
3019 # define R200_VTX_SHININESS_1 (1<<10)
3020 # define R200_VTX_COLOR_NOT_PRESENT 0
3021 # define R200_VTX_PK_RGBA 1
3022 # define R200_VTX_FP_RGB 2
3023 # define R200_VTX_FP_RGBA 3
3024 # define R200_VTX_COLOR_MASK 3
3025 # define R200_VTX_COLOR_0_SHIFT 11
3026 # define R200_VTX_COLOR_1_SHIFT 13
3027 # define R200_VTX_COLOR_2_SHIFT 15
3028 # define R200_VTX_COLOR_3_SHIFT 17
3029 # define R200_VTX_COLOR_4_SHIFT 19
3030 # define R200_VTX_COLOR_5_SHIFT 21
3031 # define R200_VTX_COLOR_6_SHIFT 23
3032 # define R200_VTX_COLOR_7_SHIFT 25
3033 # define R200_VTX_XY1 (1<<28)
3034 # define R200_VTX_Z1 (1<<29)
3035 # define R200_VTX_W1 (1<<30)
3036 # define R200_VTX_N1 (1<<31)
3037 #define R200_SE_VTX_FMT_1 0x208c
3038 # define R200_VTX_TEX0_COMP_CNT_SHIFT 0
3039 # define R200_VTX_TEX1_COMP_CNT_SHIFT 3
3040 # define R200_VTX_TEX2_COMP_CNT_SHIFT 6
3041 # define R200_VTX_TEX3_COMP_CNT_SHIFT 9
3042 # define R200_VTX_TEX4_COMP_CNT_SHIFT 12
3043 # define R200_VTX_TEX5_COMP_CNT_SHIFT 15
3045 #define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090
3046 #define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094
3047 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
3048 # define R200_OUTPUT_XYZW (1<<0)
3049 # define R200_OUTPUT_COLOR_0 (1<<8)
3050 # define R200_OUTPUT_COLOR_1 (1<<9)
3051 # define R200_OUTPUT_TEX_0 (1<<16)
3052 # define R200_OUTPUT_TEX_1 (1<<17)
3053 # define R200_OUTPUT_TEX_2 (1<<18)
3054 # define R200_OUTPUT_TEX_3 (1<<19)
3055 # define R200_OUTPUT_TEX_4 (1<<20)
3056 # define R200_OUTPUT_TEX_5 (1<<21)
3057 # define R200_OUTPUT_TEX_MASK (0x3f<<16)
3058 # define R200_OUTPUT_DISCRETE_FOG (1<<24)
3059 # define R200_OUTPUT_PT_SIZE (1<<25)
3060 # define R200_FORCE_INORDER_PROC (1<<31)
3061 #define R200_PP_CNTL_X 0x2cc4
3062 #define R200_PP_TXMULTI_CTL_0 0x2c1c
3063 #define R200_SE_VTX_STATE_CNTL 0x2180
3064 # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
3066 /* Registers for CP and Microcode Engine */
3067 #define RADEON_CP_ME_RAM_ADDR 0x07d4
3068 #define RADEON_CP_ME_RAM_RADDR 0x07d8
3069 #define RADEON_CP_ME_RAM_DATAH 0x07dc
3070 #define RADEON_CP_ME_RAM_DATAL 0x07e0
3072 #define RADEON_CP_RB_BASE 0x0700
3073 #define RADEON_CP_RB_CNTL 0x0704
3074 #define RADEON_CP_RB_RPTR_ADDR 0x070c
3075 #define RADEON_CP_RB_RPTR 0x0710
3076 #define RADEON_CP_RB_WPTR 0x0714
3078 #define RADEON_CP_IB_BASE 0x0738
3079 #define RADEON_CP_IB_BUFSZ 0x073c
3081 #define RADEON_CP_CSQ_CNTL 0x0740
3082 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
3083 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
3084 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
3085 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
3086 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
3087 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
3088 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
3089 #define RADEON_CP_CSQ_STAT 0x07f8
3090 # define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)
3091 # define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)
3092 # define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)
3093 # define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)
3094 #define RADEON_CP_CSQ_ADDR 0x07f0
3095 #define RADEON_CP_CSQ_DATA 0x07f4
3096 #define RADEON_CP_CSQ_APER_PRIMARY 0x1000
3097 #define RADEON_CP_CSQ_APER_INDIRECT 0x1300
3099 #define RADEON_CP_RB_WPTR_DELAY 0x0718
3100 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
3101 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
3103 #define RADEON_AIC_CNTL 0x01d0
3104 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
3105 #define RADEON_AIC_LO_ADDR 0x01dc
3110 //#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0
3111 //efine RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2
3115 /* CP packet types */
3116 #define RADEON_CP_PACKET0 0x00000000
3117 #define RADEON_CP_PACKET1 0x40000000
3118 #define RADEON_CP_PACKET2 0x80000000
3119 #define RADEON_CP_PACKET3 0xC0000000
3120 # define RADEON_CP_PACKET_MASK 0xC0000000
3121 # define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
3122 # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)
3123 # define RADEON_CP_PACKET0_REG_MASK 0x000007ff
3124 # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
3125 # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
3127 #define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000
3129 #define RADEON_CP_PACKET3_NOP 0xC0001000
3130 #define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
3131 #define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
3132 #define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
3133 #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
3134 #define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
3135 #define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
3136 #define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
3137 #define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
3138 #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
3139 #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
3140 #define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500
3141 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
3142 #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
3143 #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
3144 #define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
3145 #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
3146 #define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
3147 #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
3148 #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
3149 #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
3150 #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
3153 #define RADEON_CP_VC_FRMT_XY 0x00000000
3154 #define RADEON_CP_VC_FRMT_W0 0x00000001
3155 #define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002
3156 #define RADEON_CP_VC_FRMT_FPALPHA 0x00000004
3157 #define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008
3158 #define RADEON_CP_VC_FRMT_FPSPEC 0x00000010
3159 #define RADEON_CP_VC_FRMT_FPFOG 0x00000020
3160 #define RADEON_CP_VC_FRMT_PKSPEC 0x00000040
3161 #define RADEON_CP_VC_FRMT_ST0 0x00000080
3162 #define RADEON_CP_VC_FRMT_ST1 0x00000100
3163 #define RADEON_CP_VC_FRMT_Q1 0x00000200
3164 #define RADEON_CP_VC_FRMT_ST2 0x00000400
3165 #define RADEON_CP_VC_FRMT_Q2 0x00000800
3166 #define RADEON_CP_VC_FRMT_ST3 0x00001000
3167 #define RADEON_CP_VC_FRMT_Q3 0x00002000
3168 #define RADEON_CP_VC_FRMT_Q0 0x00004000
3169 #define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000
3170 #define RADEON_CP_VC_FRMT_N0 0x00040000
3171 #define RADEON_CP_VC_FRMT_XY1 0x08000000
3172 #define RADEON_CP_VC_FRMT_Z1 0x10000000
3173 #define RADEON_CP_VC_FRMT_W1 0x20000000
3174 #define RADEON_CP_VC_FRMT_N1 0x40000000
3175 #define RADEON_CP_VC_FRMT_Z 0x80000000
3177 #define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
3178 #define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
3179 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
3180 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
3181 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
3182 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
3183 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
3184 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
3185 #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
3186 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
3187 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
3188 #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
3189 #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
3190 #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
3191 #define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000
3192 #define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040
3193 #define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080
3194 #define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000
3195 #define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
3196 #define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000
3197 #define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200
3198 #define RADEON_CP_VC_CNTL_NUM_SHIFT 16
3200 #define RADEON_VS_MATRIX_0_ADDR 0
3201 #define RADEON_VS_MATRIX_1_ADDR 4
3202 #define RADEON_VS_MATRIX_2_ADDR 8
3203 #define RADEON_VS_MATRIX_3_ADDR 12
3204 #define RADEON_VS_MATRIX_4_ADDR 16
3205 #define RADEON_VS_MATRIX_5_ADDR 20
3206 #define RADEON_VS_MATRIX_6_ADDR 24
3207 #define RADEON_VS_MATRIX_7_ADDR 28
3208 #define RADEON_VS_MATRIX_8_ADDR 32
3209 #define RADEON_VS_MATRIX_9_ADDR 36
3210 #define RADEON_VS_MATRIX_10_ADDR 40
3211 #define RADEON_VS_MATRIX_11_ADDR 44
3212 #define RADEON_VS_MATRIX_12_ADDR 48
3213 #define RADEON_VS_MATRIX_13_ADDR 52
3214 #define RADEON_VS_MATRIX_14_ADDR 56
3215 #define RADEON_VS_MATRIX_15_ADDR 60
3216 #define RADEON_VS_LIGHT_AMBIENT_ADDR 64
3217 #define RADEON_VS_LIGHT_DIFFUSE_ADDR 72
3218 #define RADEON_VS_LIGHT_SPECULAR_ADDR 80
3219 #define RADEON_VS_LIGHT_DIRPOS_ADDR 88
3220 #define RADEON_VS_LIGHT_HWVSPOT_ADDR 96
3221 #define RADEON_VS_LIGHT_ATTENUATION_ADDR 104
3222 #define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112
3223 #define RADEON_VS_UCP_ADDR 116
3224 #define RADEON_VS_GLOBAL_AMBIENT_ADDR 122
3225 #define RADEON_VS_FOG_PARAM_ADDR 123
3226 #define RADEON_VS_EYE_VECTOR_ADDR 124
3228 #define RADEON_SS_LIGHT_DCD_ADDR 0
3229 #define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8
3230 #define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16
3231 #define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24
3232 #define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32
3233 #define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48
3234 #define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49
3235 #define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50
3236 #define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51
3237 #define RADEON_SS_SHININESS 60
3239 #define RADEON_TV_MASTER_CNTL 0x0800
3240 # define RADEON_TV_ASYNC_RST (1 << 0)
3241 # define RADEON_CRT_ASYNC_RST (1 << 1)
3242 # define RADEON_RESTART_PHASE_FIX (1 << 3)
3243 # define RADEON_TV_FIFO_ASYNC_RST (1 << 4)
3244 # define RADEON_VIN_ASYNC_RST (1 << 5)
3245 # define RADEON_AUD_ASYNC_RST (1 << 6)
3246 # define RADEON_DVS_ASYNC_RST (1 << 7)
3247 # define RADEON_CRT_FIFO_CE_EN (1 << 9)
3248 # define RADEON_TV_FIFO_CE_EN (1 << 10)
3249 # define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)
3250 # define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
3251 # define RADEON_TV_ON (1 << 31)
3252 #define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
3253 # define RADEON_Y_RED_EN (1 << 0)
3254 # define RADEON_C_GRN_EN (1 << 1)
3255 # define RADEON_CMP_BLU_EN (1 << 2)
3256 # define RADEON_DAC_DITHER_EN (1 << 3)
3257 # define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)
3258 # define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)
3259 # define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)
3260 # define RADEON_TV_FORCE_DAC_DATA_SHIFT 16
3261 #define RADEON_TV_RGB_CNTL 0x0804
3262 # define RADEON_SWITCH_TO_BLUE (1 << 4)
3263 # define RADEON_RGB_DITHER_EN (1 << 5)
3264 # define RADEON_RGB_SRC_SEL_MASK (3 << 8)
3265 # define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)
3266 # define RADEON_RGB_SRC_SEL_RMX (1 << 8)
3267 # define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)
3268 # define RADEON_RGB_CONVERT_BY_PASS (1 << 10)
3269 # define RADEON_UVRAM_READ_MARGIN_SHIFT 16
3270 # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20
3271 # define RADEON_TVOUT_SCALE_EN (1 << 26)
3272 #define RADEON_TV_SYNC_CNTL 0x0808
3273 # define RADEON_SYNC_OE (1 << 0)
3274 # define RADEON_SYNC_OUT (1 << 1)
3275 # define RADEON_SYNC_IN (1 << 2)
3276 # define RADEON_SYNC_PUB (1 << 3)
3277 # define RADEON_SYNC_PD (1 << 4)
3278 # define RADEON_TV_SYNC_IO_DRIVE (1 << 5)
3279 #define RADEON_TV_HTOTAL 0x080c
3280 #define RADEON_TV_HDISP 0x0810
3281 #define RADEON_TV_HSTART 0x0818
3282 #define RADEON_TV_HCOUNT 0x081C
3283 #define RADEON_TV_VTOTAL 0x0820
3284 #define RADEON_TV_VDISP 0x0824
3285 #define RADEON_TV_VCOUNT 0x0828
3286 #define RADEON_TV_FTOTAL 0x082c
3287 #define RADEON_TV_FCOUNT 0x0830
3288 #define RADEON_TV_FRESTART 0x0834
3289 #define RADEON_TV_HRESTART 0x0838
3290 #define RADEON_TV_VRESTART 0x083c
3291 #define RADEON_TV_HOST_READ_DATA 0x0840
3292 #define RADEON_TV_HOST_WRITE_DATA 0x0844
3293 #define RADEON_TV_HOST_RD_WT_CNTL 0x0848
3294 # define RADEON_HOST_FIFO_RD (1 << 12)
3295 # define RADEON_HOST_FIFO_RD_ACK (1 << 13)
3296 # define RADEON_HOST_FIFO_WT (1 << 14)
3297 # define RADEON_HOST_FIFO_WT_ACK (1 << 15)
3298 #define RADEON_TV_VSCALER_CNTL1 0x084c
3299 # define RADEON_UV_INC_MASK 0xffff
3300 # define RADEON_UV_INC_SHIFT 0
3301 # define RADEON_Y_W_EN (1 << 24)
3302 # define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */
3303 # define RADEON_Y_DEL_W_SIG_SHIFT 26
3304 #define RADEON_TV_TIMING_CNTL 0x0850
3305 # define RADEON_H_INC_MASK 0xfff
3306 # define RADEON_H_INC_SHIFT 0
3307 # define RADEON_REQ_Y_FIRST (1 << 19)
3308 # define RADEON_FORCE_BURST_ALWAYS (1 << 21)
3309 # define RADEON_UV_POST_SCALE_BYPASS (1 << 23)
3310 # define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24
3311 #define RADEON_TV_VSCALER_CNTL2 0x0854
3312 # define RADEON_DITHER_MODE (1 << 0)
3313 # define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)
3314 # define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)
3315 # define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)
3316 #define RADEON_TV_Y_FALL_CNTL 0x0858
3317 # define RADEON_Y_FALL_PING_PONG (1 << 16)
3318 # define RADEON_Y_COEF_EN (1 << 17)
3319 #define RADEON_TV_Y_RISE_CNTL 0x085c
3320 # define RADEON_Y_RISE_PING_PONG (1 << 16)
3321 #define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860
3322 #define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864
3323 # define RADEON_YUPSAMP_EN (1 << 0)
3324 # define RADEON_UVUPSAMP_EN (1 << 2)
3325 #define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868
3326 # define RADEON_Y_GAIN_LIMIT_SHIFT 0
3327 # define RADEON_UV_GAIN_LIMIT_SHIFT 16
3328 #define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c
3329 # define RADEON_Y_GAIN_SHIFT 0
3330 # define RADEON_UV_GAIN_SHIFT 16
3331 #define RADEON_TV_MODULATOR_CNTL1 0x0870
3332 # define RADEON_YFLT_EN (1 << 2)
3333 # define RADEON_UVFLT_EN (1 << 3)
3334 # define RADEON_ALT_PHASE_EN (1 << 6)
3335 # define RADEON_SYNC_TIP_LEVEL (1 << 7)
3336 # define RADEON_BLANK_LEVEL_SHIFT 8
3337 # define RADEON_SET_UP_LEVEL_SHIFT 16
3338 # define RADEON_SLEW_RATE_LIMIT (1 << 23)
3339 # define RADEON_CY_FILT_BLEND_SHIFT 28
3340 #define RADEON_TV_MODULATOR_CNTL2 0x0874
3341 # define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff
3342 # define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff
3343 # define RADEON_TV_V_BURST_LEVEL_SHIFT 16
3344 #define RADEON_TV_CRC_CNTL 0x0890
3345 #define RADEON_TV_UV_ADR 0x08ac
3346 # define RADEON_MAX_UV_ADR_MASK 0x000000ff
3347 # define RADEON_MAX_UV_ADR_SHIFT 0
3348 # define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00
3349 # define RADEON_TABLE1_BOT_ADR_SHIFT 8
3350 # define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000
3351 # define RADEON_TABLE3_TOP_ADR_SHIFT 16
3352 # define RADEON_HCODE_TABLE_SEL_MASK 0x06000000
3353 # define RADEON_HCODE_TABLE_SEL_SHIFT 25
3354 # define RADEON_VCODE_TABLE_SEL_MASK 0x18000000
3355 # define RADEON_VCODE_TABLE_SEL_SHIFT 27
3356 # define RADEON_TV_MAX_FIFO_ADDR 0x1a7
3357 # define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff
3358 #define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */
3359 #define RADEON_TV_PLL_CNTL 0x0021 /* PLL */
3360 # define RADEON_TV_M0LO_MASK 0xff
3361 # define RADEON_TV_M0HI_MASK 0x7
3362 # define RADEON_TV_M0HI_SHIFT 18
3363 # define RADEON_TV_N0LO_MASK 0x1ff
3364 # define RADEON_TV_N0LO_SHIFT 8
3365 # define RADEON_TV_N0HI_MASK 0x3
3366 # define RADEON_TV_N0HI_SHIFT 21
3367 # define RADEON_TV_P_MASK 0xf
3368 # define RADEON_TV_P_SHIFT 24
3369 # define RADEON_TV_SLIP_EN (1 << 23)
3370 # define RADEON_TV_DTO_EN (1 << 28)
3371 #define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */
3372 # define RADEON_TVPLL_RESET (1 << 1)
3373 # define RADEON_TVPLL_SLEEP (1 << 3)
3374 # define RADEON_TVPLL_REFCLK_SEL (1 << 4)
3375 # define RADEON_TVPCP_SHIFT 8
3376 # define RADEON_TVPCP_MASK (7 << 8)
3377 # define RADEON_TVPVG_SHIFT 11
3378 # define RADEON_TVPVG_MASK (7 << 11)
3379 # define RADEON_TVPDC_SHIFT 14
3380 # define RADEON_TVPDC_MASK (3 << 14)
3381 # define RADEON_TVPLL_TEST_DIS (1 << 31)
3382 # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)
3384 #define RS400_DISP2_REQ_CNTL1 0xe30
3385 # define RS400_DISP2_START_REQ_LEVEL_SHIFT 0
3386 # define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff
3387 # define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12
3388 # define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff
3389 # define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22
3390 # define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff
3391 #define RS400_DISP2_REQ_CNTL2 0xe34
3392 # define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12
3393 # define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff
3394 # define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22
3395 # define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff
3396 #define RS400_DMIF_MEM_CNTL1 0xe38
3397 # define RS400_DISP2_START_ADR_SHIFT 0
3398 # define RS400_DISP2_START_ADR_MASK 0x3ff
3399 # define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12
3400 # define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff
3401 # define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22
3402 # define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff
3403 #define RS400_DISP1_REQ_CNTL1 0xe3c
3404 # define RS400_DISP1_START_REQ_LEVEL_SHIFT 0
3405 # define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff
3406 # define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12
3407 # define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff
3408 # define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22
3409 # define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff
3411 #define RS690_MC_INDEX 0x78
3412 # define RS690_MC_INDEX_MASK 0x1ff
3413 # define RS690_MC_INDEX_WR_EN (1 << 9)
3414 # define RS690_MC_INDEX_WR_ACK 0x7f
3415 #define RS690_MC_DATA 0x7c
3417 #define RS690_MC_FB_LOCATION 0x100
3418 #define RS690_MC_AGP_LOCATION 0x101
3419 #define RS690_MC_AGP_BASE 0x102
3420 #define RS690_MC_AGP_BASE_2 0x103
3421 #define RS690_MC_STATUS 0x90
3422 #define RS690_MC_STATUS_IDLE (1 << 0)
3424 #define RS600_MC_INDEX 0x78
3425 # define RS600_MC_INDEX_MASK 0xff
3426 # define RS600_MC_INDEX_WR_EN (1 << 8)
3427 # define RS600_MC_INDEX_WR_ACK 0xff
3428 #define RS600_MC_DATA 0x7c
3430 #define RS600_MC_FB_LOCATION 0xA
3431 #define RS600_MC_STATUS 0x0
3432 #define RS600_MC_STATUS_IDLE (1 << 0)
3434 #define AVIVO_MC_INDEX 0x0070
3435 #define R520_MC_STATUS 0x00
3436 #define R520_MC_STATUS_IDLE (1<<1)
3437 #define RV515_MC_STATUS 0x08
3438 #define RV515_MC_STATUS_IDLE (1<<4)
3439 #define AVIVO_MC_DATA 0x0074
3441 #define RV515_MC_FB_LOCATION 0x1
3442 #define RV515_MC_AGP_LOCATION 0x2
3443 #define RV515_MC_AGP_BASE 0x3
3444 #define RV515_MC_AGP_BASE_2 0x4
3445 #define RV515_MC_CNTL 0x5
3446 # define RV515_MEM_NUM_CHANNELS_MASK 0x3
3447 #define R520_MC_FB_LOCATION 0x4
3448 #define R520_MC_AGP_LOCATION 0x5
3449 #define R520_MC_AGP_BASE 0x6
3450 #define R520_MC_AGP_BASE_2 0x7
3451 #define R520_MC_CNTL0 0x8
3452 # define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24)
3453 # define R520_MEM_NUM_CHANNELS_SHIFT 24
3454 # define R520_MC_CHANNEL_SIZE (1 << 23)
3456 #define R600_RAMCFG 0x2408
3457 # define R600_CHANSIZE (1 << 7)
3458 # define R600_CHANSIZE_OVERRIDE (1 << 10)
3460 #define AVIVO_HDP_FB_LOCATION 0x134
3462 #define AVIVO_VGA_RENDER_CONTROL 0x0300
3463 # define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16)
3464 #define AVIVO_D1VGA_CONTROL 0x0330
3465 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
3466 # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)
3467 # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)
3468 # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
3469 # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)
3470 # define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
3471 #define AVIVO_D2VGA_CONTROL 0x0338
3473 #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
3474 #define AVIVO_EXT1_PPLL_REF_DIV 0x404
3475 #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
3476 #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
3478 #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
3479 #define AVIVO_EXT2_PPLL_REF_DIV 0x414
3480 #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
3481 #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
3483 #define AVIVO_EXT1_PPLL_FB_DIV 0x430
3484 #define AVIVO_EXT2_PPLL_FB_DIV 0x434
3486 #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
3487 #define AVIVO_EXT1_PPLL_POST_DIV 0x43c
3489 #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
3490 #define AVIVO_EXT2_PPLL_POST_DIV 0x444
3492 #define AVIVO_EXT1_PPLL_CNTL 0x448
3493 #define AVIVO_EXT2_PPLL_CNTL 0x44c
3495 #define AVIVO_P1PLL_CNTL 0x450
3496 #define AVIVO_P2PLL_CNTL 0x454
3497 #define AVIVO_P1PLL_INT_SS_CNTL 0x458
3498 #define AVIVO_P2PLL_INT_SS_CNTL 0x45c
3499 #define AVIVO_P1PLL_TMDSA_CNTL 0x460
3500 #define AVIVO_P2PLL_LVTMA_CNTL 0x464
3502 #define AVIVO_PCLK_CRTC1_CNTL 0x480
3503 #define AVIVO_PCLK_CRTC2_CNTL 0x484
3505 #define AVIVO_D1CRTC_H_TOTAL 0x6000
3506 #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
3507 #define AVIVO_D1CRTC_H_SYNC_A 0x6008
3508 #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c
3509 #define AVIVO_D1CRTC_H_SYNC_B 0x6010
3510 #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
3512 #define AVIVO_D1CRTC_V_TOTAL 0x6020
3513 #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
3514 #define AVIVO_D1CRTC_V_SYNC_A 0x6028
3515 #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c
3516 #define AVIVO_D1CRTC_V_SYNC_B 0x6030
3517 #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
3519 #define AVIVO_D1CRTC_CONTROL 0x6080
3520 # define AVIVO_CRTC_EN (1<<0)
3521 #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
3522 #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
3523 #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
3524 #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
3526 /* master controls */
3527 #define AVIVO_DC_CRTC_MASTER_EN 0x60f8
3528 #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
3530 #define AVIVO_D1GRPH_ENABLE 0x6100
3531 #define AVIVO_D1GRPH_CONTROL 0x6104
3532 # define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0)
3533 # define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0)
3534 # define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0)
3535 # define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0)
3537 # define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8)
3539 # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8)
3540 # define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8)
3541 # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8)
3542 # define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8)
3543 # define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8)
3545 # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8)
3546 # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8)
3547 # define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8)
3548 # define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8)
3551 # define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8)
3553 # define AVIVO_D1GRPH_SWAP_RB (1<<16)
3554 # define AVIVO_D1GRPH_TILED (1<<20)
3555 # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21)
3557 #define AVIVO_D1GRPH_LUT_SEL 0x6108
3558 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
3559 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
3560 #define AVIVO_D1GRPH_PITCH 0x6120
3561 #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
3562 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
3563 #define AVIVO_D1GRPH_X_START 0x612c
3564 #define AVIVO_D1GRPH_Y_START 0x6130
3565 #define AVIVO_D1GRPH_X_END 0x6134
3566 #define AVIVO_D1GRPH_Y_END 0x6138
3567 #define AVIVO_D1GRPH_UPDATE 0x6144
3568 # define AVIVO_D1GRPH_UPDATE_LOCK (1<<16)
3569 #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
3571 #define AVIVO_D1CUR_CONTROL 0x6400
3572 # define AVIVO_D1CURSOR_EN (1<<0)
3573 # define AVIVO_D1CURSOR_MODE_SHIFT 8
3574 # define AVIVO_D1CURSOR_MODE_MASK (0x3<<8)
3575 # define AVIVO_D1CURSOR_MODE_24BPP (0x2)
3576 #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
3577 #define AVIVO_D1CUR_SIZE 0x6410
3578 #define AVIVO_D1CUR_POSITION 0x6414
3579 #define AVIVO_D1CUR_HOT_SPOT 0x6418
3580 #define AVIVO_D1CUR_UPDATE 0x6424
3581 # define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)
3583 #define AVIVO_DC_LUT_RW_SELECT 0x6480
3584 #define AVIVO_DC_LUT_RW_MODE 0x6484
3585 #define AVIVO_DC_LUT_RW_INDEX 0x6488
3586 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c
3587 #define AVIVO_DC_LUT_PWL_DATA 0x6490
3588 #define AVIVO_DC_LUT_30_COLOR 0x6494
3589 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
3590 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
3591 #define AVIVO_DC_LUT_AUTOFILL 0x64a0
3593 #define AVIVO_DC_LUTA_CONTROL 0x64c0
3594 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
3595 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
3596 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
3597 #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
3598 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
3599 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
3602 #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
3603 #define AVIVO_D1MODE_VIEWPORT_START 0x6580
3604 #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
3605 #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
3606 #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
3608 #define AVIVO_D1SCL_SCALER_ENABLE 0x6590
3609 #define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
3610 #define AVIVO_D1SCL_UPDATE 0x65cc
3611 # define AVIVO_D1SCL_UPDATE_LOCK (1<<16)
3614 #define AVIVO_D2CRTC_H_TOTAL 0x6800
3615 #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
3616 #define AVIVO_D2CRTC_H_SYNC_A 0x6808
3617 #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
3618 #define AVIVO_D2CRTC_H_SYNC_B 0x6810
3619 #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
3621 #define AVIVO_D2CRTC_V_TOTAL 0x6820
3622 #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
3623 #define AVIVO_D2CRTC_V_SYNC_A 0x6828
3624 #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
3625 #define AVIVO_D2CRTC_V_SYNC_B 0x6830
3626 #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
3628 #define AVIVO_D2CRTC_CONTROL 0x6880
3629 #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
3630 #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
3631 #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
3632 #define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
3634 #define AVIVO_D2GRPH_ENABLE 0x6900
3635 #define AVIVO_D2GRPH_CONTROL 0x6904
3636 #define AVIVO_D2GRPH_LUT_SEL 0x6908
3637 #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
3638 #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
3639 #define AVIVO_D2GRPH_PITCH 0x6920
3640 #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
3641 #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
3642 #define AVIVO_D2GRPH_X_START 0x692c
3643 #define AVIVO_D2GRPH_Y_START 0x6930
3644 #define AVIVO_D2GRPH_X_END 0x6934
3645 #define AVIVO_D2GRPH_Y_END 0x6938
3646 #define AVIVO_D2GRPH_UPDATE 0x6944
3647 #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
3649 #define AVIVO_D2CUR_CONTROL 0x6c00
3650 #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
3651 #define AVIVO_D2CUR_SIZE 0x6c10
3652 #define AVIVO_D2CUR_POSITION 0x6c14
3654 #define AVIVO_D2MODE_VIEWPORT_START 0x6d80
3655 #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
3656 #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
3657 #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
3659 #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
3660 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
3662 #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214
3664 #define AVIVO_DACA_ENABLE 0x7800
3665 # define AVIVO_DAC_ENABLE (1 << 0)
3666 #define AVIVO_DACA_SOURCE_SELECT 0x7804
3667 # define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
3668 # define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
3669 # define AVIVO_DAC_SOURCE_TV (2 << 0)
3671 #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c
3672 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
3673 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
3674 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
3675 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
3676 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
3677 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
3678 #define AVIVO_DACA_POWERDOWN 0x7850
3679 # define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
3680 # define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
3681 # define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
3682 # define AVIVO_DACA_POWERDOWN_RED (1 << 24)
3684 #define AVIVO_DACB_ENABLE 0x7a00
3685 #define AVIVO_DACB_SOURCE_SELECT 0x7a04
3686 #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c
3687 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
3688 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
3689 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
3690 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
3691 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
3692 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
3693 #define AVIVO_DACB_POWERDOWN 0x7a50
3694 # define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
3695 # define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
3696 # define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
3697 # define AVIVO_DACB_POWERDOWN_RED
3699 #define AVIVO_TMDSA_CNTL 0x7880
3700 # define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
3701 # define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
3702 # define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
3703 # define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
3704 # define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
3705 # define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
3706 # define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
3707 #define AVIVO_TMDSA_SOURCE_SELECT 0x7884
3708 /* 78a8 appears to be some kind of (reasonably tolerant) clock?
3709 * 78d0 definitely hits the transmitter, definitely clock. */
3710 /* MYSTERY1 This appears to control dithering? */
3711 #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
3712 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
3713 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
3714 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
3715 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
3716 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
3717 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
3718 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
3719 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
3720 #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
3721 # define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
3722 # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
3723 # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
3724 # define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
3725 #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
3726 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
3727 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
3728 #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
3729 #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
3730 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
3731 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
3732 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
3733 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
3734 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
3735 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
3736 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
3737 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
3738 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
3739 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
3740 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
3741 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
3743 #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
3744 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
3745 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
3746 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
3747 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
3748 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
3749 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
3750 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
3751 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
3752 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
3753 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
3754 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
3755 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
3756 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
3757 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
3759 #define AVIVO_LVTMA_CNTL 0x7a80
3760 # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
3761 # define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
3762 # define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
3763 # define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
3764 # define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
3765 # define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
3766 # define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
3767 #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
3768 #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
3769 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
3770 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
3771 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
3772 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
3773 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
3774 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
3775 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
3776 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
3777 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
3781 #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
3782 # define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
3783 # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
3784 # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
3785 # define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
3787 #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
3788 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
3789 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
3790 #define R500_LVTMA_CLOCK_ENABLE 0x7b00
3791 #define R600_LVTMA_CLOCK_ENABLE 0x7b04
3793 #define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
3794 #define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
3795 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
3796 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
3797 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
3798 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
3799 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
3800 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
3801 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
3802 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
3803 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
3804 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
3805 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
3807 #define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
3808 #define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
3809 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
3810 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
3811 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
3812 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
3813 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
3814 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
3815 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
3816 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
3817 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
3818 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
3819 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
3820 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
3821 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
3822 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
3824 #define R500_LVTMA_PWRSEQ_CNTL 0x7af0
3825 #define R600_LVTMA_PWRSEQ_CNTL 0x7af4
3826 # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
3827 # define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
3828 # define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
3829 # define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
3830 # define AVIVO_LVTMA_SYNCEN (1 << 8)
3831 # define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
3832 # define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
3833 # define AVIVO_LVTMA_DIGON (1 << 16)
3834 # define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
3835 # define AVIVO_LVTMA_DIGON_POL (1 << 18)
3836 # define AVIVO_LVTMA_BLON (1 << 24)
3837 # define AVIVO_LVTMA_BLON_OVRD (1 << 25)
3838 # define AVIVO_LVTMA_BLON_POL (1 << 26)
3840 #define R500_LVTMA_PWRSEQ_STATE 0x7af4
3841 #define R600_LVTMA_PWRSEQ_STATE 0x7af8
3842 # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
3843 # define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
3844 # define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
3845 # define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
3846 # define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
3847 # define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
3849 #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
3850 # define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
3851 # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
3852 # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8
3854 #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988
3856 #define AVIVO_GPIO_0 0x7e30
3857 #define AVIVO_GPIO_1 0x7e40
3858 #define AVIVO_GPIO_2 0x7e50
3859 #define AVIVO_GPIO_3 0x7e60
3861 #define AVIVO_DC_GPIO_HPD_Y 0x7e9c
3863 #define AVIVO_I2C_STATUS 0x7d30
3864 # define AVIVO_I2C_STATUS_DONE (1 << 0)
3865 # define AVIVO_I2C_STATUS_NACK (1 << 1)
3866 # define AVIVO_I2C_STATUS_HALT (1 << 2)
3867 # define AVIVO_I2C_STATUS_GO (1 << 3)
3868 # define AVIVO_I2C_STATUS_MASK 0x7
3869 /* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
3871 # define AVIVO_I2C_STATUS_CMD_RESET 0x7
3872 # define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3)
3873 #define AVIVO_I2C_STOP 0x7d34
3874 #define AVIVO_I2C_START_CNTL 0x7d38
3875 # define AVIVO_I2C_START (1 << 8)
3876 # define AVIVO_I2C_CONNECTOR0 (0 << 16)
3877 # define AVIVO_I2C_CONNECTOR1 (1 << 16)
3878 #define R520_I2C_START (1<<0)
3879 #define R520_I2C_STOP (1<<1)
3880 #define R520_I2C_RX (1<<2)
3881 #define R520_I2C_EN (1<<8)
3882 #define R520_I2C_DDC1 (0<<16)
3883 #define R520_I2C_DDC2 (1<<16)
3884 #define R520_I2C_DDC3 (2<<16)
3885 #define R520_I2C_DDC_MASK (3<<16)
3886 #define AVIVO_I2C_CONTROL2 0x7d3c
3887 # define AVIVO_I2C_7D3C_SIZE_SHIFT 8
3888 # define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8)
3889 #define AVIVO_I2C_CONTROL3 0x7d40
3890 /* Reading is done 4 bytes at a time: read the bottom 8 bits from
3891 * 7d44, four times in a row.
3892 * Writing is a little more complex. First write DATA with
3893 * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
3894 * magic number, zz is, I think, the slave address, and yy is the byte
3895 * you want to write. */
3896 #define AVIVO_I2C_DATA 0x7d44
3897 #define R520_I2C_ADDR_COUNT_MASK (0x7)
3898 #define R520_I2C_DATA_COUNT_SHIFT (8)
3899 #define R520_I2C_DATA_COUNT_MASK (0xF00)
3900 #define AVIVO_I2C_CNTL 0x7d50
3901 # define AVIVO_I2C_EN (1 << 0)
3902 # define AVIVO_I2C_RESET (1 << 8)
3904 #define R600_GENERAL_PWRMGT 0x618
3905 # define R600_OPEN_DRAIN_PADS (1 << 11)
3907 #define R600_LOWER_GPIO_ENABLE 0x710
3908 #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
3909 #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
3910 #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
3911 #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
3913 #define R600_MC_VM_FB_LOCATION 0x2180
3914 #define R600_MC_VM_AGP_TOP 0x2184
3915 #define R600_MC_VM_AGP_BOT 0x2188
3916 #define R600_MC_VM_AGP_BASE 0x218c
3917 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
3918 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
3919 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
3921 #define R700_MC_VM_FB_LOCATION 0x2024
3923 #define R600_HDP_NONSURFACE_BASE 0x2c04
3925 #define R600_BUS_CNTL 0x5420
3926 #define R600_CONFIG_CNTL 0x5424
3927 #define R600_CONFIG_MEMSIZE 0x5428
3928 #define R600_CONFIG_F0_BASE 0x542C
3929 #define R600_CONFIG_APER_SIZE 0x5430
3931 #define R600_ROM_CNTL 0x1600
3932 # define R600_SCK_OVERWRITE (1 << 1)
3933 # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
3934 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
3936 #define R600_BIOS_0_SCRATCH 0x1724
3937 #define R600_BIOS_1_SCRATCH 0x1728
3938 #define R600_BIOS_2_SCRATCH 0x172c
3939 #define R600_BIOS_3_SCRATCH 0x1730
3940 #define R600_BIOS_4_SCRATCH 0x1734
3941 #define R600_BIOS_5_SCRATCH 0x1738
3942 #define R600_BIOS_6_SCRATCH 0x173c
3943 #define R600_BIOS_7_SCRATCH 0x1740
3945 #define R300_GB_TILE_CONFIG 0x4018
3946 # define R300_ENABLE_TILING (1 << 0)
3947 # define R300_PIPE_COUNT_RV350 (0 << 1)
3948 # define R300_PIPE_COUNT_R300 (3 << 1)
3949 # define R300_PIPE_COUNT_R420_3P (6 << 1)
3950 # define R300_PIPE_COUNT_R420 (7 << 1)
3951 # define R300_TILE_SIZE_8 (0 << 4)
3952 # define R300_TILE_SIZE_16 (1 << 4)
3953 # define R300_TILE_SIZE_32 (2 << 4)
3954 # define R300_SUBPIXEL_1_12 (0 << 16)
3955 # define R300_SUBPIXEL_1_16 (1 << 16)
3956 #define R300_GB_SELECT 0x401c
3957 #define R300_GB_ENABLE 0x4008
3958 #define R300_GB_AA_CONFIG 0x4020
3959 #define R400_GB_PIPE_SELECT 0x402c
3960 #define R300_GB_MSPOS0 0x4010
3961 # define R300_MS_X0_SHIFT 0
3962 # define R300_MS_Y0_SHIFT 4
3963 # define R300_MS_X1_SHIFT 8
3964 # define R300_MS_Y1_SHIFT 12
3965 # define R300_MS_X2_SHIFT 16
3966 # define R300_MS_Y2_SHIFT 20
3967 # define R300_MSBD0_Y_SHIFT 24
3968 # define R300_MSBD0_X_SHIFT 28
3969 #define R300_GB_MSPOS1 0x4014
3970 # define R300_MS_X3_SHIFT 0
3971 # define R300_MS_Y3_SHIFT 4
3972 # define R300_MS_X4_SHIFT 8
3973 # define R300_MS_Y4_SHIFT 12
3974 # define R300_MS_X5_SHIFT 16
3975 # define R300_MS_Y5_SHIFT 20
3976 # define R300_MSBD1_SHIFT 24
3978 #define R300_GA_ENHANCE 0x4274
3979 # define R300_GA_DEADLOCK_CNTL (1 << 0)
3980 # define R300_GA_FASTSYNC_CNTL (1 << 1)
3982 #define R300_GA_POLY_MODE 0x4288
3983 # define R300_FRONT_PTYPE_POINT (0 << 4)
3984 # define R300_FRONT_PTYPE_LINE (1 << 4)
3985 # define R300_FRONT_PTYPE_TRIANGE (2 << 4)
3986 # define R300_BACK_PTYPE_POINT (0 << 7)
3987 # define R300_BACK_PTYPE_LINE (1 << 7)
3988 # define R300_BACK_PTYPE_TRIANGE (2 << 7)
3989 #define R300_GA_ROUND_MODE 0x428c
3990 # define R300_GEOMETRY_ROUND_TRUNC (0 << 0)
3991 # define R300_GEOMETRY_ROUND_NEAREST (1 << 0)
3992 # define R300_COLOR_ROUND_TRUNC (0 << 2)
3993 # define R300_COLOR_ROUND_NEAREST (1 << 2)
3994 #define R300_GA_COLOR_CONTROL 0x4278
3995 # define R300_RGB0_SHADING_SOLID (0 << 0)
3996 # define R300_RGB0_SHADING_FLAT (1 << 0)
3997 # define R300_RGB0_SHADING_GOURAUD (2 << 0)
3998 # define R300_ALPHA0_SHADING_SOLID (0 << 2)
3999 # define R300_ALPHA0_SHADING_FLAT (1 << 2)
4000 # define R300_ALPHA0_SHADING_GOURAUD (2 << 2)
4001 # define R300_RGB1_SHADING_SOLID (0 << 4)
4002 # define R300_RGB1_SHADING_FLAT (1 << 4)
4003 # define R300_RGB1_SHADING_GOURAUD (2 << 4)
4004 # define R300_ALPHA1_SHADING_SOLID (0 << 6)
4005 # define R300_ALPHA1_SHADING_FLAT (1 << 6)
4006 # define R300_ALPHA1_SHADING_GOURAUD (2 << 6)
4007 # define R300_RGB2_SHADING_SOLID (0 << 8)
4008 # define R300_RGB2_SHADING_FLAT (1 << 8)
4009 # define R300_RGB2_SHADING_GOURAUD (2 << 8)
4010 # define R300_ALPHA2_SHADING_SOLID (0 << 10)
4011 # define R300_ALPHA2_SHADING_FLAT (1 << 10)
4012 # define R300_ALPHA2_SHADING_GOURAUD (2 << 10)
4013 # define R300_RGB3_SHADING_SOLID (0 << 12)
4014 # define R300_RGB3_SHADING_FLAT (1 << 12)
4015 # define R300_RGB3_SHADING_GOURAUD (2 << 12)
4016 # define R300_ALPHA3_SHADING_SOLID (0 << 14)
4017 # define R300_ALPHA3_SHADING_FLAT (1 << 14)
4018 # define R300_ALPHA3_SHADING_GOURAUD (2 << 14)
4019 #define R300_GA_OFFSET 0x4290
4021 #define R500_SU_REG_DEST 0x42c8
4023 #define R300_VAP_CNTL_STATUS 0x2140
4024 # define R300_PVS_BYPASS (1 << 8)
4025 #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
4026 #define R300_VAP_CNTL 0x2080
4027 # define R300_PVS_NUM_SLOTS_SHIFT 0
4028 # define R300_PVS_NUM_CNTLRS_SHIFT 4
4029 # define R300_PVS_NUM_FPUS_SHIFT 8
4030 # define R300_VF_MAX_VTX_NUM_SHIFT 18
4031 # define R300_GL_CLIP_SPACE_DEF (0 << 22)
4032 # define R300_DX_CLIP_SPACE_DEF (1 << 22)
4033 # define R500_TCL_STATE_OPTIMIZATION (1 << 23)
4034 #define R300_VAP_VTE_CNTL 0x20B0
4035 # define R300_VPORT_X_SCALE_ENA (1 << 0)
4036 # define R300_VPORT_X_OFFSET_ENA (1 << 1)
4037 # define R300_VPORT_Y_SCALE_ENA (1 << 2)
4038 # define R300_VPORT_Y_OFFSET_ENA (1 << 3)
4039 # define R300_VPORT_Z_SCALE_ENA (1 << 4)
4040 # define R300_VPORT_Z_OFFSET_ENA (1 << 5)
4041 # define R300_VTX_XY_FMT (1 << 8)
4042 # define R300_VTX_Z_FMT (1 << 9)
4043 # define R300_VTX_W0_FMT (1 << 10)
4044 #define R300_VAP_VTX_STATE_CNTL 0x2180
4045 #define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC
4046 #define R300_VAP_PROG_STREAM_CNTL_0 0x2150
4047 # define R300_DATA_TYPE_0_SHIFT 0
4048 # define R300_DATA_TYPE_FLOAT_1 0
4049 # define R300_DATA_TYPE_FLOAT_2 1
4050 # define R300_DATA_TYPE_FLOAT_3 2
4051 # define R300_DATA_TYPE_FLOAT_4 3
4052 # define R300_DATA_TYPE_BYTE 4
4053 # define R300_DATA_TYPE_D3DCOLOR 5
4054 # define R300_DATA_TYPE_SHORT_2 6
4055 # define R300_DATA_TYPE_SHORT_4 7
4056 # define R300_DATA_TYPE_VECTOR_3_TTT 8
4057 # define R300_DATA_TYPE_VECTOR_3_EET 9
4058 # define R300_SKIP_DWORDS_0_SHIFT 4
4059 # define R300_DST_VEC_LOC_0_SHIFT 8
4060 # define R300_LAST_VEC_0 (1 << 13)
4061 # define R300_SIGNED_0 (1 << 14)
4062 # define R300_NORMALIZE_0 (1 << 15)
4063 # define R300_DATA_TYPE_1_SHIFT 16
4064 # define R300_SKIP_DWORDS_1_SHIFT 20
4065 # define R300_DST_VEC_LOC_1_SHIFT 24
4066 # define R300_LAST_VEC_1 (1 << 29)
4067 # define R300_SIGNED_1 (1 << 30)
4068 # define R300_NORMALIZE_1 (1 << 31)
4069 #define R300_VAP_PROG_STREAM_CNTL_1 0x2154
4070 # define R300_DATA_TYPE_2_SHIFT 0
4071 # define R300_SKIP_DWORDS_2_SHIFT 4
4072 # define R300_DST_VEC_LOC_2_SHIFT 8
4073 # define R300_LAST_VEC_2 (1 << 13)
4074 # define R300_SIGNED_2 (1 << 14)
4075 # define R300_NORMALIZE_2 (1 << 15)
4076 # define R300_DATA_TYPE_3_SHIFT 16
4077 # define R300_SKIP_DWORDS_3_SHIFT 20
4078 # define R300_DST_VEC_LOC_3_SHIFT 24
4079 # define R300_LAST_VEC_3 (1 << 29)
4080 # define R300_SIGNED_3 (1 << 30)
4081 # define R300_NORMALIZE_3 (1 << 31)
4082 #define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0
4083 # define R300_SWIZZLE_SELECT_X_0_SHIFT 0
4084 # define R300_SWIZZLE_SELECT_Y_0_SHIFT 3
4085 # define R300_SWIZZLE_SELECT_Z_0_SHIFT 6
4086 # define R300_SWIZZLE_SELECT_W_0_SHIFT 9
4087 # define R300_SWIZZLE_SELECT_X 0
4088 # define R300_SWIZZLE_SELECT_Y 1
4089 # define R300_SWIZZLE_SELECT_Z 2
4090 # define R300_SWIZZLE_SELECT_W 3
4091 # define R300_SWIZZLE_SELECT_FP_ZERO 4
4092 # define R300_SWIZZLE_SELECT_FP_ONE 5
4093 # define R300_WRITE_ENA_0_SHIFT 12
4094 # define R300_WRITE_ENA_X 1
4095 # define R300_WRITE_ENA_Y 2
4096 # define R300_WRITE_ENA_Z 4
4097 # define R300_WRITE_ENA_W 8
4098 # define R300_SWIZZLE_SELECT_X_1_SHIFT 16
4099 # define R300_SWIZZLE_SELECT_Y_1_SHIFT 19
4100 # define R300_SWIZZLE_SELECT_Z_1_SHIFT 22
4101 # define R300_SWIZZLE_SELECT_W_1_SHIFT 25
4102 # define R300_WRITE_ENA_1_SHIFT 28
4103 #define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4
4104 # define R300_SWIZZLE_SELECT_X_2_SHIFT 0
4105 # define R300_SWIZZLE_SELECT_Y_2_SHIFT 3
4106 # define R300_SWIZZLE_SELECT_Z_2_SHIFT 6
4107 # define R300_SWIZZLE_SELECT_W_2_SHIFT 9
4108 # define R300_WRITE_ENA_2_SHIFT 12
4109 # define R300_SWIZZLE_SELECT_X_3_SHIFT 16
4110 # define R300_SWIZZLE_SELECT_Y_3_SHIFT 19
4111 # define R300_SWIZZLE_SELECT_Z_3_SHIFT 22
4112 # define R300_SWIZZLE_SELECT_W_3_SHIFT 25
4113 # define R300_WRITE_ENA_3_SHIFT 28
4114 #define R300_VAP_PVS_CODE_CNTL_0 0x22D0
4115 # define R300_PVS_FIRST_INST_SHIFT 0
4116 # define R300_PVS_XYZW_VALID_INST_SHIFT 10
4117 # define R300_PVS_LAST_INST_SHIFT 20
4118 #define R300_VAP_PVS_CODE_CNTL_1 0x22D8
4119 # define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0
4120 #define R300_VAP_PVS_VECTOR_INDX_REG 0x2200
4121 #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204
4122 /* PVS instructions */
4123 /* Opcode and dst instruction */
4124 #define R300_PVS_DST_OPCODE(x) (x << 0)
4126 # define R300_VECTOR_NO_OP 0
4127 # define R300_VE_DOT_PRODUCT 1
4128 # define R300_VE_MULTIPLY 2
4129 # define R300_VE_ADD 3
4130 # define R300_VE_MULTIPLY_ADD 4
4131 # define R300_VE_DISTANCE_VECTOR 5
4132 # define R300_VE_FRACTION 6
4133 # define R300_VE_MAXIMUM 7
4134 # define R300_VE_MINIMUM 8
4135 # define R300_VE_SET_GREATER_THAN_EQUAL 9
4136 # define R300_VE_SET_LESS_THAN 10
4137 # define R300_VE_MULTIPLYX2_ADD 11
4138 # define R300_VE_MULTIPLY_CLAMP 12
4139 # define R300_VE_FLT2FIX_DX 13
4140 # define R300_VE_FLT2FIX_DX_RND 14
4141 /* R500 additions */
4142 # define R500_VE_PRED_SET_EQ_PUSH 15
4143 # define R500_VE_PRED_SET_GT_PUSH 16
4144 # define R500_VE_PRED_SET_GTE_PUSH 17
4145 # define R500_VE_PRED_SET_NEQ_PUSH 18
4146 # define R500_VE_COND_WRITE_EQ 19
4147 # define R500_VE_COND_WRITE_GT 20
4148 # define R500_VE_COND_WRITE_GTE 21
4149 # define R500_VE_COND_WRITE_NEQ 22
4150 # define R500_VE_COND_MUX_EQ 23
4151 # define R500_VE_COND_MUX_GT 24
4152 # define R500_VE_COND_MUX_GTE 25
4153 # define R500_VE_SET_GREATER_THAN 26
4154 # define R500_VE_SET_EQUAL 27
4155 # define R500_VE_SET_NOT_EQUAL 28
4157 # define R300_MATH_NO_OP 0
4158 # define R300_ME_EXP_BASE2_DX 1
4159 # define R300_ME_LOG_BASE2_DX 2
4160 # define R300_ME_EXP_BASEE_FF 3
4161 # define R300_ME_LIGHT_COEFF_DX 4
4162 # define R300_ME_POWER_FUNC_FF 5
4163 # define R300_ME_RECIP_DX 6
4164 # define R300_ME_RECIP_FF 7
4165 # define R300_ME_RECIP_SQRT_DX 8
4166 # define R300_ME_RECIP_SQRT_FF 9
4167 # define R300_ME_MULTIPLY 10
4168 # define R300_ME_EXP_BASE2_FULL_DX 11
4169 # define R300_ME_LOG_BASE2_FULL_DX 12
4170 # define R300_ME_POWER_FUNC_FF_CLAMP_B 13
4171 # define R300_ME_POWER_FUNC_FF_CLAMP_B1 14
4172 # define R300_ME_POWER_FUNC_FF_CLAMP_01 15
4173 # define R300_ME_SIN 16
4174 # define R300_ME_COS 17
4175 /* R500 additions */
4176 # define R500_ME_LOG_BASE2_IEEE 18
4177 # define R500_ME_RECIP_IEEE 19
4178 # define R500_ME_RECIP_SQRT_IEEE 20
4179 # define R500_ME_PRED_SET_EQ 21
4180 # define R500_ME_PRED_SET_GT 22
4181 # define R500_ME_PRED_SET_GTE 23
4182 # define R500_ME_PRED_SET_NEQ 24
4183 # define R500_ME_PRED_SET_CLR 25
4184 # define R500_ME_PRED_SET_INV 26
4185 # define R500_ME_PRED_SET_POP 27
4186 # define R500_ME_PRED_SET_RESTORE 28
4188 # define R300_PVS_MACRO_OP_2CLK_MADD 0
4189 # define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1
4190 #define R300_PVS_DST_MATH_INST (1 << 6)
4191 #define R300_PVS_DST_MACRO_INST (1 << 7)
4192 #define R300_PVS_DST_REG_TYPE(x) (x << 8)
4193 # define R300_PVS_DST_REG_TEMPORARY 0
4194 # define R300_PVS_DST_REG_A0 1
4195 # define R300_PVS_DST_REG_OUT 2
4196 # define R500_PVS_DST_REG_OUT_REPL_X 3
4197 # define R300_PVS_DST_REG_ALT_TEMPORARY 4
4198 # define R300_PVS_DST_REG_INPUT 5
4199 #define R300_PVS_DST_ADDR_MODE_1 (1 << 12)
4200 #define R300_PVS_DST_OFFSET(x) (x << 13)
4201 #define R300_PVS_DST_WE_X (1 << 20)
4202 #define R300_PVS_DST_WE_Y (1 << 21)
4203 #define R300_PVS_DST_WE_Z (1 << 22)
4204 #define R300_PVS_DST_WE_W (1 << 23)
4205 #define R300_PVS_DST_VE_SAT (1 << 24)
4206 #define R300_PVS_DST_ME_SAT (1 << 25)
4207 #define R300_PVS_DST_PRED_ENABLE (1 << 26)
4208 #define R300_PVS_DST_PRED_SENSE (1 << 27)
4209 #define R300_PVS_DST_DUAL_MATH_OP (1 << 28)
4210 #define R300_PVS_DST_ADDR_SEL(x) (x << 29)
4211 #define R300_PVS_DST_ADDR_MODE_0 (1 << 31)
4212 /* src operand instruction */
4213 #define R300_PVS_SRC_REG_TYPE(x) (x << 0)
4214 # define R300_PVS_SRC_REG_TEMPORARY 0
4215 # define R300_PVS_SRC_REG_INPUT 1
4216 # define R300_PVS_SRC_REG_CONSTANT 2
4217 # define R300_PVS_SRC_REG_ALT_TEMPORARY 3
4218 #define R300_SPARE_0 (1 << 2)
4219 #define R300_PVS_SRC_ABS_XYZW (1 << 3)
4220 #define R300_PVS_SRC_ADDR_MODE_0 (1 << 4)
4221 #define R300_PVS_SRC_OFFSET(x) (x << 5)
4222 #define R300_PVS_SRC_SWIZZLE_X(x) (x << 13)
4223 #define R300_PVS_SRC_SWIZZLE_Y(x) (x << 16)
4224 #define R300_PVS_SRC_SWIZZLE_Z(x) (x << 19)
4225 #define R300_PVS_SRC_SWIZZLE_W(x) (x << 22)
4226 # define R300_PVS_SRC_SELECT_X 0
4227 # define R300_PVS_SRC_SELECT_Y 1
4228 # define R300_PVS_SRC_SELECT_Z 2
4229 # define R300_PVS_SRC_SELECT_W 3
4230 # define R300_PVS_SRC_SELECT_FORCE_0 4
4231 # define R300_PVS_SRC_SELECT_FORCE_1 5
4232 #define R300_PVS_SRC_NEG_X (1 << 25)
4233 #define R300_PVS_SRC_NEG_Y (1 << 26)
4234 #define R300_PVS_SRC_NEG_Z (1 << 27)
4235 #define R300_PVS_SRC_NEG_W (1 << 28)
4236 #define R300_PVS_SRC_ADDR_SEL(x) (x << 29)
4237 #define R300_PVS_SRC_ADDR_MODE_1 (1 << 31)
4239 #define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC
4240 #define R300_VAP_OUT_VTX_FMT_0 0x2090
4241 # define R300_VTX_POS_PRESENT (1 << 0)
4242 # define R300_VTX_COLOR_0_PRESENT (1 << 1)
4243 # define R300_VTX_COLOR_1_PRESENT (1 << 2)
4244 # define R300_VTX_COLOR_2_PRESENT (1 << 3)
4245 # define R300_VTX_COLOR_3_PRESENT (1 << 4)
4246 # define R300_VTX_PT_SIZE_PRESENT (1 << 16)
4247 #define R300_VAP_OUT_VTX_FMT_1 0x2094
4248 # define R300_TEX_0_COMP_CNT_SHIFT 0
4249 # define R300_TEX_1_COMP_CNT_SHIFT 3
4250 # define R300_TEX_2_COMP_CNT_SHIFT 6
4251 # define R300_TEX_3_COMP_CNT_SHIFT 9
4252 # define R300_TEX_4_COMP_CNT_SHIFT 12
4253 # define R300_TEX_5_COMP_CNT_SHIFT 15
4254 # define R300_TEX_6_COMP_CNT_SHIFT 18
4255 # define R300_TEX_7_COMP_CNT_SHIFT 21
4256 #define R300_VAP_VTX_SIZE 0x20b4
4257 #define R300_VAP_GB_VERT_CLIP_ADJ 0x2220
4258 #define R300_VAP_GB_VERT_DISC_ADJ 0x2224
4259 #define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228
4260 #define R300_VAP_GB_HORZ_DISC_ADJ 0x222c
4261 #define R300_VAP_CLIP_CNTL 0x221c
4262 # define R300_UCP_ENA_0 (1 << 0)
4263 # define R300_UCP_ENA_1 (1 << 1)
4264 # define R300_UCP_ENA_2 (1 << 2)
4265 # define R300_UCP_ENA_3 (1 << 3)
4266 # define R300_UCP_ENA_4 (1 << 4)
4267 # define R300_UCP_ENA_5 (1 << 5)
4268 # define R300_PS_UCP_MODE_SHIFT 14
4269 # define R300_CLIP_DISABLE (1 << 16)
4270 # define R300_UCP_CULL_ONLY_ENA (1 << 17)
4271 # define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18)
4272 #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
4274 #define R500_VAP_INDEX_OFFSET 0x208c
4276 #define R300_SU_TEX_WRAP 0x42a0
4277 #define R300_SU_POLY_OFFSET_ENABLE 0x42b4
4278 #define R300_SU_CULL_MODE 0x42b8
4279 # define R300_CULL_FRONT (1 << 0)
4280 # define R300_CULL_BACK (1 << 1)
4281 # define R300_FACE_POS (0 << 2)
4282 # define R300_FACE_NEG (1 << 2)
4283 #define R300_SU_DEPTH_SCALE 0x42c0
4284 #define R300_SU_DEPTH_OFFSET 0x42c4
4286 #define R300_RS_COUNT 0x4300
4287 # define R300_RS_COUNT_IT_COUNT_SHIFT 0
4288 # define R300_RS_COUNT_IC_COUNT_SHIFT 7
4289 # define R300_RS_COUNT_HIRES_EN (1 << 18)
4291 #define R300_RS_IP_0 0x4310
4292 #define R300_RS_IP_1 0x4314
4293 # define R300_RS_TEX_PTR(x) (x << 0)
4294 # define R300_RS_COL_PTR(x) (x << 6)
4295 # define R300_RS_COL_FMT(x) (x << 9)
4296 # define R300_RS_COL_FMT_RGBA 0
4297 # define R300_RS_COL_FMT_RGB0 2
4298 # define R300_RS_COL_FMT_RGB1 3
4299 # define R300_RS_COL_FMT_000A 4
4300 # define R300_RS_COL_FMT_0000 5
4301 # define R300_RS_COL_FMT_0001 6
4302 # define R300_RS_COL_FMT_111A 8
4303 # define R300_RS_COL_FMT_1110 9
4304 # define R300_RS_COL_FMT_1111 10
4305 # define R300_RS_SEL_S(x) (x << 13)
4306 # define R300_RS_SEL_T(x) (x << 16)
4307 # define R300_RS_SEL_R(x) (x << 19)
4308 # define R300_RS_SEL_Q(x) (x << 22)
4309 # define R300_RS_SEL_C0 0
4310 # define R300_RS_SEL_C1 1
4311 # define R300_RS_SEL_C2 2
4312 # define R300_RS_SEL_C3 3
4313 # define R300_RS_SEL_K0 4
4314 # define R300_RS_SEL_K1 5
4315 #define R300_RS_INST_COUNT 0x4304
4316 # define R300_INST_COUNT_RS(x) (x << 0)
4317 # define R300_RS_W_EN (1 << 4)
4318 # define R300_TX_OFFSET_RS(x) (x << 5)
4319 #define R300_RS_INST_0 0x4330
4320 #define R300_RS_INST_1 0x4334
4321 # define R300_INST_TEX_ID(x) (x << 0)
4322 # define R300_RS_INST_TEX_CN_WRITE (1 << 3)
4323 # define R300_INST_TEX_ADDR(x) (x << 6)
4325 #define R300_TX_INVALTAGS 0x4100
4326 #define R300_TX_FILTER0_0 0x4400
4327 # define R300_TX_CLAMP_S(x) (x << 0)
4328 # define R300_TX_CLAMP_T(x) (x << 3)
4329 # define R300_TX_CLAMP_R(x) (x << 6)
4330 # define R300_TX_CLAMP_WRAP 0
4331 # define R300_TX_CLAMP_MIRROR 1
4332 # define R300_TX_CLAMP_CLAMP_LAST 2
4333 # define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3
4334 # define R300_TX_CLAMP_CLAMP_BORDER 4
4335 # define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5
4336 # define R300_TX_CLAMP_CLAMP_GL 6
4337 # define R300_TX_CLAMP_MIRROR_CLAMP_GL 7
4338 # define R300_TX_MAG_FILTER_NEAREST (1 << 9)
4339 # define R300_TX_MIN_FILTER_NEAREST (1 << 11)
4340 # define R300_TX_MAG_FILTER_LINEAR (2 << 9)
4341 # define R300_TX_MIN_FILTER_LINEAR (2 << 11)
4342 # define R300_TX_ID_SHIFT 28
4343 #define R300_TX_FILTER1_0 0x4440
4344 #define R300_TX_FORMAT0_0 0x4480
4345 # define R300_TXWIDTH_SHIFT 0
4346 # define R300_TXHEIGHT_SHIFT 11
4347 # define R300_NUM_LEVELS_SHIFT 26
4348 # define R300_NUM_LEVELS_MASK 0x
4349 # define R300_TXPROJECTED (1 << 30)
4350 # define R300_TXPITCH_EN (1 << 31)
4351 #define R300_TX_FORMAT1_0 0x44c0
4352 # define R300_TX_FORMAT_X8 0x0
4353 # define R300_TX_FORMAT_X16 0x1
4354 # define R300_TX_FORMAT_Y4X4 0x2
4355 # define R300_TX_FORMAT_Y8X8 0x3
4356 # define R300_TX_FORMAT_Y16X16 0x4
4357 # define R300_TX_FORMAT_Z3Y3X2 0x5
4358 # define R300_TX_FORMAT_Z5Y6X5 0x6
4359 # define R300_TX_FORMAT_Z6Y5X5 0x7
4360 # define R300_TX_FORMAT_Z11Y11X10 0x8
4361 # define R300_TX_FORMAT_Z10Y11X11 0x9
4362 # define R300_TX_FORMAT_W4Z4Y4X4 0xA
4363 # define R300_TX_FORMAT_W1Z5Y5X5 0xB
4364 # define R300_TX_FORMAT_W8Z8Y8X8 0xC
4365 # define R300_TX_FORMAT_W2Z10Y10X10 0xD
4366 # define R300_TX_FORMAT_W16Z16Y16X16 0xE
4367 # define R300_TX_FORMAT_DXT1 0xF
4368 # define R300_TX_FORMAT_DXT3 0x10
4369 # define R300_TX_FORMAT_DXT5 0x11
4370 # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
4371 # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
4372 # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
4373 # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
4374 # define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */
4375 # define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */
4376 # define R300_TX_FORMAT_X24_Y8 0x1e
4377 # define R300_TX_FORMAT_X32 0x1e
4378 /* Floating point formats */
4379 /* Note - hardware supports both 16 and 32 bit floating point */
4380 # define R300_TX_FORMAT_FL_I16 0x18
4381 # define R300_TX_FORMAT_FL_I16A16 0x19
4382 # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
4383 # define R300_TX_FORMAT_FL_I32 0x1B
4384 # define R300_TX_FORMAT_FL_I32A32 0x1C
4385 # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
4386 /* alpha modes, convenience mostly */
4387 /* if you have alpha, pick constant appropriate to the
4388 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
4389 # define R300_TX_FORMAT_ALPHA_1CH 0x000
4390 # define R300_TX_FORMAT_ALPHA_2CH 0x200
4391 # define R300_TX_FORMAT_ALPHA_4CH 0x600
4392 # define R300_TX_FORMAT_ALPHA_NONE 0xA00
4395 # define R300_TX_FORMAT_X 0
4396 # define R300_TX_FORMAT_Y 1
4397 # define R300_TX_FORMAT_Z 2
4398 # define R300_TX_FORMAT_W 3
4399 # define R300_TX_FORMAT_ZERO 4
4400 # define R300_TX_FORMAT_ONE 5
4401 /* 2.0*Z, everything above 1.0 is set to 0.0 */
4402 # define R300_TX_FORMAT_CUT_Z 6
4403 /* 2.0*W, everything above 1.0 is set to 0.0 */
4404 # define R300_TX_FORMAT_CUT_W 7
4406 # define R300_TX_FORMAT_B_SHIFT 18
4407 # define R300_TX_FORMAT_G_SHIFT 15
4408 # define R300_TX_FORMAT_R_SHIFT 12
4409 # define R300_TX_FORMAT_A_SHIFT 9
4411 /* Convenience macro to take care of layout and swizzling */
4412 # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
4413 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
4414 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
4415 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
4416 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
4417 | (R300_TX_FORMAT_##FMT) \
4420 # define R300_TX_FORMAT_YUV_TO_RGB_CLAMP (1 << 22)
4421 # define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP (2 << 22)
4422 # define R300_TX_FORMAT_SWAP_YUV (1 << 24)
4424 #define R300_TX_FORMAT2_0 0x4500
4425 # define R500_TXWIDTH_11 (1 << 15)
4426 # define R500_TXHEIGHT_11 (1 << 16)
4428 #define R300_TX_OFFSET_0 0x4540
4429 # define R300_ENDIAN_SWAP_16_BIT (1 << 0)
4430 # define R300_ENDIAN_SWAP_32_BIT (2 << 0)
4431 # define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0)
4432 # define R300_MACRO_TILE (1 << 2)
4434 #define R300_TX_BORDER_COLOR_0 0x45c0
4436 #define R300_TX_ENABLE 0x4104
4437 # define R300_TEX_0_ENABLE (1 << 0)
4438 # define R300_TEX_1_ENABLE (1 << 1)
4440 #define R300_US_W_FMT 0x46b4
4441 #define R300_US_OUT_FMT_1 0x46a8
4442 #define R300_US_OUT_FMT_2 0x46ac
4443 #define R300_US_OUT_FMT_3 0x46b0
4444 #define R300_US_OUT_FMT_0 0x46a4
4445 # define R300_OUT_FMT_C4_8 (0 << 0)
4446 # define R300_OUT_FMT_C4_10 (1 << 0)
4447 # define R300_OUT_FMT_C4_10_GAMMA (2 << 0)
4448 # define R300_OUT_FMT_C_16 (3 << 0)
4449 # define R300_OUT_FMT_C2_16 (4 << 0)
4450 # define R300_OUT_FMT_C4_16 (5 << 0)
4451 # define R300_OUT_FMT_C_16_MPEG (6 << 0)
4452 # define R300_OUT_FMT_C2_16_MPEG (7 << 0)
4453 # define R300_OUT_FMT_C2_4 (8 << 0)
4454 # define R300_OUT_FMT_C_3_3_2 (9 << 0)
4455 # define R300_OUT_FMT_C_5_6_5 (10 << 0)
4456 # define R300_OUT_FMT_C_11_11_10 (11 << 0)
4457 # define R300_OUT_FMT_C_10_11_11 (12 << 0)
4458 # define R300_OUT_FMT_C_2_10_10_10 (13 << 0)
4459 # define R300_OUT_FMT_UNUSED (15 << 0)
4460 # define R300_OUT_FMT_C_16_FP (16 << 0)
4461 # define R300_OUT_FMT_C2_16_FP (17 << 0)
4462 # define R300_OUT_FMT_C4_16_FP (18 << 0)
4463 # define R300_OUT_FMT_C_32_FP (19 << 0)
4464 # define R300_OUT_FMT_C2_32_FP (20 << 0)
4465 # define R300_OUT_FMT_C4_32_FP (21 << 0)
4466 # define R300_OUT_FMT_C0_SEL_ALPHA (0 << 8)
4467 # define R300_OUT_FMT_C0_SEL_RED (1 << 8)
4468 # define R300_OUT_FMT_C0_SEL_GREEN (2 << 8)
4469 # define R300_OUT_FMT_C0_SEL_BLUE (3 << 8)
4470 # define R300_OUT_FMT_C1_SEL_ALPHA (0 << 10)
4471 # define R300_OUT_FMT_C1_SEL_RED (1 << 10)
4472 # define R300_OUT_FMT_C1_SEL_GREEN (2 << 10)
4473 # define R300_OUT_FMT_C1_SEL_BLUE (3 << 10)
4474 # define R300_OUT_FMT_C2_SEL_ALPHA (0 << 12)
4475 # define R300_OUT_FMT_C2_SEL_RED (1 << 12)
4476 # define R300_OUT_FMT_C2_SEL_GREEN (2 << 12)
4477 # define R300_OUT_FMT_C2_SEL_BLUE (3 << 12)
4478 # define R300_OUT_FMT_C3_SEL_ALPHA (0 << 14)
4479 # define R300_OUT_FMT_C3_SEL_RED (1 << 14)
4480 # define R300_OUT_FMT_C3_SEL_GREEN (2 << 14)
4481 # define R300_OUT_FMT_C3_SEL_BLUE (3 << 14)
4482 #define R300_US_CONFIG 0x4600
4483 # define R300_NLEVEL_SHIFT 0
4484 # define R300_FIRST_TEX (1 << 3)
4485 # define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
4486 #define R300_US_PIXSIZE 0x4604
4487 #define R300_US_CODE_OFFSET 0x4608
4488 # define R300_ALU_CODE_OFFSET(x) (x << 0)
4489 # define R300_ALU_CODE_SIZE(x) (x << 6)
4490 # define R300_TEX_CODE_OFFSET(x) (x << 13)
4491 # define R300_TEX_CODE_SIZE(x) (x << 18)
4492 #define R300_US_CODE_ADDR_0 0x4610
4493 # define R300_ALU_START(x) (x << 0)
4494 # define R300_ALU_SIZE(x) (x << 6)
4495 # define R300_TEX_START(x) (x << 12)
4496 # define R300_TEX_SIZE(x) (x << 17)
4497 # define R300_RGBA_OUT (1 << 22)
4498 # define R300_W_OUT (1 << 23)
4499 #define R300_US_CODE_ADDR_1 0x4614
4500 #define R300_US_CODE_ADDR_2 0x4618
4501 #define R300_US_CODE_ADDR_3 0x461c
4502 #define R300_US_TEX_INST_0 0x4620
4503 #define R300_US_TEX_INST_1 0x4624
4504 #define R300_US_TEX_INST_2 0x4628
4505 # define R300_TEX_SRC_ADDR(x) (x << 0)
4506 # define R300_TEX_DST_ADDR(x) (x << 6)
4507 # define R300_TEX_ID(x) (x << 11)
4508 # define R300_TEX_INST(x) (x << 15)
4509 # define R300_TEX_INST_NOP 0
4510 # define R300_TEX_INST_LD 1
4511 # define R300_TEX_INST_TEXKILL 2
4512 # define R300_TEX_INST_PROJ 3
4513 # define R300_TEX_INST_LODBIAS 4
4514 #define R300_US_ALU_RGB_ADDR_0 0x46c0
4515 #define R300_US_ALU_RGB_ADDR_1 0x46c4
4516 #define R300_US_ALU_RGB_ADDR_2 0x46c8
4517 /* for ADDR0-2, values 0-31 specify a location in the pixel stack,
4518 values 32-63 specify a constant */
4519 # define R300_ALU_RGB_ADDR0(x) (x << 0)
4520 # define R300_ALU_RGB_ADDR1(x) (x << 6)
4521 # define R300_ALU_RGB_ADDR2(x) (x << 12)
4522 /* ADDRD - where on the pixel stack the result of this instruction
4524 # define R300_ALU_RGB_ADDRD(x) (x << 18)
4525 # define R300_ALU_RGB_WMASK(x) (x << 23)
4526 # define R300_ALU_RGB_OMASK(x) (x << 26)
4527 # define R300_ALU_RGB_MASK_NONE 0
4528 # define R300_ALU_RGB_MASK_R 1
4529 # define R300_ALU_RGB_MASK_G 2
4530 # define R300_ALU_RGB_MASK_B 4
4531 # define R300_ALU_RGB_TARGET_A (0 << 29)
4532 # define R300_ALU_RGB_TARGET_B (1 << 29)
4533 # define R300_ALU_RGB_TARGET_C (2 << 29)
4534 # define R300_ALU_RGB_TARGET_D (3 << 29)
4535 #define R300_US_ALU_RGB_INST_0 0x48c0
4536 #define R300_US_ALU_RGB_INST_1 0x48c4
4537 #define R300_US_ALU_RGB_INST_2 0x48c8
4538 # define R300_ALU_RGB_SEL_A(x) (x << 0)
4539 # define R300_ALU_RGB_SRC0_RGB 0
4540 # define R300_ALU_RGB_SRC0_RRR 1
4541 # define R300_ALU_RGB_SRC0_GGG 2
4542 # define R300_ALU_RGB_SRC0_BBB 3
4543 # define R300_ALU_RGB_SRC1_RGB 4
4544 # define R300_ALU_RGB_SRC1_RRR 5
4545 # define R300_ALU_RGB_SRC1_GGG 6
4546 # define R300_ALU_RGB_SRC1_BBB 7
4547 # define R300_ALU_RGB_SRC2_RGB 8
4548 # define R300_ALU_RGB_SRC2_RRR 9
4549 # define R300_ALU_RGB_SRC2_GGG 10
4550 # define R300_ALU_RGB_SRC2_BBB 11
4551 # define R300_ALU_RGB_SRC0_AAA 12
4552 # define R300_ALU_RGB_SRC1_AAA 13
4553 # define R300_ALU_RGB_SRC2_AAA 14
4554 # define R300_ALU_RGB_SRCP_RGB 15
4555 # define R300_ALU_RGB_SRCP_RRR 16
4556 # define R300_ALU_RGB_SRCP_GGG 17
4557 # define R300_ALU_RGB_SRCP_BBB 18
4558 # define R300_ALU_RGB_SRCP_AAA 19
4559 # define R300_ALU_RGB_0_0 20
4560 # define R300_ALU_RGB_1_0 21
4561 # define R300_ALU_RGB_0_5 22
4562 # define R300_ALU_RGB_SRC0_GBR 23
4563 # define R300_ALU_RGB_SRC1_GBR 24
4564 # define R300_ALU_RGB_SRC2_GBR 25
4565 # define R300_ALU_RGB_SRC0_BRG 26
4566 # define R300_ALU_RGB_SRC1_BRG 27
4567 # define R300_ALU_RGB_SRC2_BRG 28
4568 # define R300_ALU_RGB_SRC0_ABG 29
4569 # define R300_ALU_RGB_SRC1_ABG 30
4570 # define R300_ALU_RGB_SRC2_ABG 31
4571 # define R300_ALU_RGB_MOD_A(x) (x << 5)
4572 # define R300_ALU_RGB_MOD_NOP 0
4573 # define R300_ALU_RGB_MOD_NEG 1
4574 # define R300_ALU_RGB_MOD_ABS 2
4575 # define R300_ALU_RGB_MOD_NAB 3
4576 # define R300_ALU_RGB_SEL_B(x) (x << 7)
4577 # define R300_ALU_RGB_MOD_B(x) (x << 12)
4578 # define R300_ALU_RGB_SEL_C(x) (x << 14)
4579 # define R300_ALU_RGB_MOD_C(x) (x << 19)
4580 # define R300_ALU_RGB_SRCP_OP(x) (x << 21)
4581 # define R300_ALU_RGB_SRCP_OP_1_MINUS_2RGB0 0
4582 # define R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0 1
4583 # define R300_ALU_RGB_SRCP_OP_RGB1_PLUS_RGB0 2
4584 # define R300_ALU_RGB_SRCP_OP_1_MINUS_RGB0 3
4585 # define R300_ALU_RGB_OP(x) (x << 23)
4586 # define R300_ALU_RGB_OP_MAD 0
4587 # define R300_ALU_RGB_OP_DP3 1
4588 # define R300_ALU_RGB_OP_DP4 2
4589 # define R300_ALU_RGB_OP_D2A 3
4590 # define R300_ALU_RGB_OP_MIN 4
4591 # define R300_ALU_RGB_OP_MAX 5
4592 # define R300_ALU_RGB_OP_CND 7
4593 # define R300_ALU_RGB_OP_CMP 8
4594 # define R300_ALU_RGB_OP_FRC 9
4595 # define R300_ALU_RGB_OP_SOP 10
4596 # define R300_ALU_RGB_OMOD(x) (x << 27)
4597 # define R300_ALU_RGB_OMOD_NONE 0
4598 # define R300_ALU_RGB_OMOD_MUL_2 1
4599 # define R300_ALU_RGB_OMOD_MUL_4 2
4600 # define R300_ALU_RGB_OMOD_MUL_8 3
4601 # define R300_ALU_RGB_OMOD_DIV_2 4
4602 # define R300_ALU_RGB_OMOD_DIV_4 5
4603 # define R300_ALU_RGB_OMOD_DIV_8 6
4604 # define R300_ALU_RGB_CLAMP (1 << 30)
4605 # define R300_ALU_RGB_INSERT_NOP (1 << 31)
4606 #define R300_US_ALU_ALPHA_ADDR_0 0x47c0
4607 #define R300_US_ALU_ALPHA_ADDR_1 0x47c4
4608 #define R300_US_ALU_ALPHA_ADDR_2 0x47c8
4609 /* for ADDR0-2, values 0-31 specify a location in the pixel stack,
4610 values 32-63 specify a constant */
4611 # define R300_ALU_ALPHA_ADDR0(x) (x << 0)
4612 # define R300_ALU_ALPHA_ADDR1(x) (x << 6)
4613 # define R300_ALU_ALPHA_ADDR2(x) (x << 12)
4614 /* ADDRD - where on the pixel stack the result of this instruction
4616 # define R300_ALU_ALPHA_ADDRD(x) (x << 18)
4617 # define R300_ALU_ALPHA_WMASK(x) (x << 23)
4618 # define R300_ALU_ALPHA_OMASK(x) (x << 24)
4619 # define R300_ALU_ALPHA_OMASK_W(x) (x << 27)
4620 # define R300_ALU_ALPHA_MASK_NONE 0
4621 # define R300_ALU_ALPHA_MASK_A 1
4622 # define R300_ALU_ALPHA_TARGET_A (0 << 25)
4623 # define R300_ALU_ALPHA_TARGET_B (1 << 25)
4624 # define R300_ALU_ALPHA_TARGET_C (2 << 25)
4625 # define R300_ALU_ALPHA_TARGET_D (3 << 25)
4626 #define R300_US_ALU_ALPHA_INST_0 0x49c0
4627 #define R300_US_ALU_ALPHA_INST_1 0x49c4
4628 #define R300_US_ALU_ALPHA_INST_2 0x49c8
4629 # define R300_ALU_ALPHA_SEL_A(x) (x << 0)
4630 # define R300_ALU_ALPHA_SRC0_R 0
4631 # define R300_ALU_ALPHA_SRC0_G 1
4632 # define R300_ALU_ALPHA_SRC0_B 2
4633 # define R300_ALU_ALPHA_SRC1_R 3
4634 # define R300_ALU_ALPHA_SRC1_G 4
4635 # define R300_ALU_ALPHA_SRC1_B 5
4636 # define R300_ALU_ALPHA_SRC2_R 6
4637 # define R300_ALU_ALPHA_SRC2_G 7
4638 # define R300_ALU_ALPHA_SRC2_B 8
4639 # define R300_ALU_ALPHA_SRC0_A 9
4640 # define R300_ALU_ALPHA_SRC1_A 10
4641 # define R300_ALU_ALPHA_SRC2_A 11
4642 # define R300_ALU_ALPHA_SRCP_R 12
4643 # define R300_ALU_ALPHA_SRCP_G 13
4644 # define R300_ALU_ALPHA_SRCP_B 14
4645 # define R300_ALU_ALPHA_SRCP_A 15
4646 # define R300_ALU_ALPHA_0_0 16
4647 # define R300_ALU_ALPHA_1_0 17
4648 # define R300_ALU_ALPHA_0_5 18
4649 # define R300_ALU_ALPHA_MOD_A(x) (x << 5)
4650 # define R300_ALU_ALPHA_MOD_NOP 0
4651 # define R300_ALU_ALPHA_MOD_NEG 1
4652 # define R300_ALU_ALPHA_MOD_ABS 2
4653 # define R300_ALU_ALPHA_MOD_NAB 3
4654 # define R300_ALU_ALPHA_SEL_B(x) (x << 7)
4655 # define R300_ALU_ALPHA_MOD_B(x) (x << 12)
4656 # define R300_ALU_ALPHA_SEL_C(x) (x << 14)
4657 # define R300_ALU_ALPHA_MOD_C(x) (x << 19)
4658 # define R300_ALU_ALPHA_SRCP_OP(x) (x << 21)
4659 # define R300_ALU_ALPHA_SRCP_OP_1_MINUS_2RGB0 0
4660 # define R300_ALU_ALPHA_SRCP_OP_RGB1_MINUS_RGB0 1
4661 # define R300_ALU_ALPHA_SRCP_OP_RGB1_PLUS_RGB0 2
4662 # define R300_ALU_ALPHA_SRCP_OP_1_MINUS_RGB0 3
4663 # define R300_ALU_ALPHA_OP(x) (x << 23)
4664 # define R300_ALU_ALPHA_OP_MAD 0
4665 # define R300_ALU_ALPHA_OP_DP 1
4666 # define R300_ALU_ALPHA_OP_MIN 2
4667 # define R300_ALU_ALPHA_OP_MAX 3
4668 # define R300_ALU_ALPHA_OP_CND 5
4669 # define R300_ALU_ALPHA_OP_CMP 6
4670 # define R300_ALU_ALPHA_OP_FRC 7
4671 # define R300_ALU_ALPHA_OP_EX2 8
4672 # define R300_ALU_ALPHA_OP_LN2 9
4673 # define R300_ALU_ALPHA_OP_RCP 10
4674 # define R300_ALU_ALPHA_OP_RSQ 11
4675 # define R300_ALU_ALPHA_OMOD(x) (x << 27)
4676 # define R300_ALU_ALPHA_OMOD_NONE 0
4677 # define R300_ALU_ALPHA_OMOD_MUL_2 1
4678 # define R300_ALU_ALPHA_OMOD_MUL_4 2
4679 # define R300_ALU_ALPHA_OMOD_MUL_8 3
4680 # define R300_ALU_ALPHA_OMOD_DIV_2 4
4681 # define R300_ALU_ALPHA_OMOD_DIV_4 5
4682 # define R300_ALU_ALPHA_OMOD_DIV_8 6
4683 # define R300_ALU_ALPHA_CLAMP (1 << 30)
4685 #define R300_FG_DEPTH_SRC 0x4bd8
4686 #define R300_FG_FOG_BLEND 0x4bc0
4687 #define R300_FG_ALPHA_FUNC 0x4bd4
4689 #define R300_DST_PIPE_CONFIG 0x170c
4690 # define R300_PIPE_AUTO_CONFIG (1 << 31)
4691 #define R300_RB2D_DSTCACHE_MODE 0x3428
4692 #define R300_RB2D_DSTCACHE_MODE 0x3428
4693 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
4694 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
4695 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use DSTCACHE_CTLSTAT instead */
4696 #define R300_DSTCACHE_CTLSTAT 0x1714
4697 # define R300_DC_FLUSH_2D (1 << 0)
4698 # define R300_DC_FREE_2D (1 << 2)
4699 # define R300_RB2D_DC_FLUSH_ALL (R300_DC_FLUSH_2D | R300_DC_FREE_2D)
4700 # define R300_RB2D_DC_BUSY (1 << 31)
4701 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
4702 # define R300_DC_FLUSH_3D (2 << 0)
4703 # define R300_DC_FREE_3D (2 << 2)
4704 # define R300_RB3D_DC_FLUSH_ALL (R300_DC_FLUSH_3D | R300_DC_FREE_3D)
4705 # define R300_DC_FINISH_3D (1 << 4)
4706 #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18
4707 # define R300_ZC_FLUSH (1 << 0)
4708 # define R300_ZC_FREE (1 << 1)
4709 # define R300_ZC_FLUSH_ALL 0x3
4710 #define R300_RB3D_ZSTENCILCNTL 0x4f04
4711 #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18
4712 #define R300_RB3D_BW_CNTL 0x4f1c
4713 #define R300_RB3D_ZCNTL 0x4f00
4714 #define R300_RB3D_ZTOP 0x4f14
4715 #define R300_RB3D_ROPCNTL 0x4e18
4716 #define R300_RB3D_BLENDCNTL 0x4e04
4717 # define R300_ALPHA_BLEND_ENABLE (1 << 0)
4718 # define R300_SEPARATE_ALPHA_ENABLE (1 << 1)
4719 # define R300_READ_ENABLE (1 << 2)
4720 #define R300_RB3D_ABLENDCNTL 0x4e08
4721 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
4722 #define R300_RB3D_COLOROFFSET0 0x4e28
4723 #define R300_RB3D_COLORPITCH0 0x4e38
4724 # define R300_COLORTILE (1 << 16)
4725 # define R300_COLORENDIAN_WORD (1 << 19)
4726 # define R300_COLORENDIAN_DWORD (2 << 19)
4727 # define R300_COLORENDIAN_HALF_DWORD (3 << 19)
4728 # define R300_COLORFORMAT_ARGB1555 (3 << 21)
4729 # define R300_COLORFORMAT_RGB565 (4 << 21)
4730 # define R300_COLORFORMAT_ARGB8888 (6 << 21)
4731 # define R300_COLORFORMAT_ARGB32323232 (7 << 21)
4732 # define R300_COLORFORMAT_I8 (9 << 21)
4733 # define R300_COLORFORMAT_ARGB16161616 (10 << 21)
4734 # define R300_COLORFORMAT_VYUY (11 << 21)
4735 # define R300_COLORFORMAT_YVYU (12 << 21)
4736 # define R300_COLORFORMAT_UV88 (13 << 21)
4737 # define R300_COLORFORMAT_ARGB4444 (15 << 21)
4739 #define R300_RB3D_AARESOLVE_CTL 0x4e88
4740 #define R300_RB3D_COLOR_CHANNEL_MASK 0x4e0c
4741 # define R300_BLUE_MASK_EN (1 << 0)
4742 # define R300_GREEN_MASK_EN (1 << 1)
4743 # define R300_RED_MASK_EN (1 << 2)
4744 # define R300_ALPHA_MASK_EN (1 << 3)
4745 #define R300_RB3D_COLOR_CLEAR_VALUE 0x4e14
4746 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
4747 #define R300_RB3D_CCTL 0x4e00
4748 #define R300_RB3D_DITHER_CTL 0x4e50
4750 #define R300_SC_EDGERULE 0x43a8
4751 #define R300_SC_SCISSOR0 0x43e0
4752 #define R300_SC_SCISSOR1 0x43e4
4753 # define R300_SCISSOR_X_SHIFT 0
4754 # define R300_SCISSOR_Y_SHIFT 13
4755 #define R300_SC_CLIP_0_A 0x43b0
4756 #define R300_SC_CLIP_0_B 0x43b4
4757 # define R300_CLIP_X_SHIFT 0
4758 # define R300_CLIP_Y_SHIFT 13
4759 #define R300_SC_CLIP_RULE 0x43d0
4760 #define R300_SC_SCREENDOOR 0x43e8
4762 /* R500 US has to be loaded through an index/data pair */
4763 #define R500_GA_US_VECTOR_INDEX 0x4250
4764 # define R500_US_VECTOR_INDEX(x) (x << 0)
4765 # define R500_US_VECTOR_TYPE_INST (0 << 16)
4766 # define R500_US_VECTOR_TYPE_CONST (1 << 16)
4767 # define R500_US_VECTOR_CLAMP (1 << 17)
4768 #define R500_GA_US_VECTOR_DATA 0x4254
4771 * The R500 unified shader (US) registers come in banks of 512 each, one
4772 * for each instruction slot in the shader. You can't touch them directly.
4773 * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive
4774 * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the
4775 * instruction is fully specified.
4777 #define R500_US_ALU_ALPHA_INST_0 0xa800
4778 # define R500_ALPHA_OP_MAD 0
4779 # define R500_ALPHA_OP_DP 1
4780 # define R500_ALPHA_OP_MIN 2
4781 # define R500_ALPHA_OP_MAX 3
4782 /* #define R500_ALPHA_OP_RESERVED 4 */
4783 # define R500_ALPHA_OP_CND 5
4784 # define R500_ALPHA_OP_CMP 6
4785 # define R500_ALPHA_OP_FRC 7
4786 # define R500_ALPHA_OP_EX2 8
4787 # define R500_ALPHA_OP_LN2 9
4788 # define R500_ALPHA_OP_RCP 10
4789 # define R500_ALPHA_OP_RSQ 11
4790 # define R500_ALPHA_OP_SIN 12
4791 # define R500_ALPHA_OP_COS 13
4792 # define R500_ALPHA_OP_MDH 14
4793 # define R500_ALPHA_OP_MDV 15
4794 # define R500_ALPHA_ADDRD(x) (x << 4)
4795 # define R500_ALPHA_ADDRD_REL (1 << 11)
4796 # define R500_ALPHA_SEL_A_SRC0 (0 << 12)
4797 # define R500_ALPHA_SEL_A_SRC1 (1 << 12)
4798 # define R500_ALPHA_SEL_A_SRC2 (2 << 12)
4799 # define R500_ALPHA_SEL_A_SRCP (3 << 12)
4800 # define R500_ALPHA_SWIZ_A_R (0 << 14)
4801 # define R500_ALPHA_SWIZ_A_G (1 << 14)
4802 # define R500_ALPHA_SWIZ_A_B (2 << 14)
4803 # define R500_ALPHA_SWIZ_A_A (3 << 14)
4804 # define R500_ALPHA_SWIZ_A_0 (4 << 14)
4805 # define R500_ALPHA_SWIZ_A_HALF (5 << 14)
4806 # define R500_ALPHA_SWIZ_A_1 (6 << 14)
4807 /* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */
4808 # define R500_ALPHA_MOD_A_NOP (0 << 17)
4809 # define R500_ALPHA_MOD_A_NEG (1 << 17)
4810 # define R500_ALPHA_MOD_A_ABS (2 << 17)
4811 # define R500_ALPHA_MOD_A_NAB (3 << 17)
4812 # define R500_ALPHA_SEL_B_SRC0 (0 << 19)
4813 # define R500_ALPHA_SEL_B_SRC1 (1 << 19)
4814 # define R500_ALPHA_SEL_B_SRC2 (2 << 19)
4815 # define R500_ALPHA_SEL_B_SRCP (3 << 19)
4816 # define R500_ALPHA_SWIZ_B_R (0 << 21)
4817 # define R500_ALPHA_SWIZ_B_G (1 << 21)
4818 # define R500_ALPHA_SWIZ_B_B (2 << 21)
4819 # define R500_ALPHA_SWIZ_B_A (3 << 21)
4820 # define R500_ALPHA_SWIZ_B_0 (4 << 21)
4821 # define R500_ALPHA_SWIZ_B_HALF (5 << 21)
4822 # define R500_ALPHA_SWIZ_B_1 (6 << 21)
4823 /* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */
4824 # define R500_ALPHA_MOD_B_NOP (0 << 24)
4825 # define R500_ALPHA_MOD_B_NEG (1 << 24)
4826 # define R500_ALPHA_MOD_B_ABS (2 << 24)
4827 # define R500_ALPHA_MOD_B_NAB (3 << 24)
4828 # define R500_ALPHA_OMOD_IDENTITY (0 << 26)
4829 # define R500_ALPHA_OMOD_MUL_2 (1 << 26)
4830 # define R500_ALPHA_OMOD_MUL_4 (2 << 26)
4831 # define R500_ALPHA_OMOD_MUL_8 (3 << 26)
4832 # define R500_ALPHA_OMOD_DIV_2 (4 << 26)
4833 # define R500_ALPHA_OMOD_DIV_4 (5 << 26)
4834 # define R500_ALPHA_OMOD_DIV_8 (6 << 26)
4835 # define R500_ALPHA_OMOD_DISABLE (7 << 26)
4836 # define R500_ALPHA_TARGET(x) (x << 29)
4837 # define R500_ALPHA_W_OMASK (1 << 31)
4838 #define R500_US_ALU_ALPHA_ADDR_0 0x9800
4839 # define R500_ALPHA_ADDR0(x) (x << 0)
4840 # define R500_ALPHA_ADDR0_CONST (1 << 8)
4841 # define R500_ALPHA_ADDR0_REL (1 << 9)
4842 # define R500_ALPHA_ADDR1(x) (x << 10)
4843 # define R500_ALPHA_ADDR1_CONST (1 << 18)
4844 # define R500_ALPHA_ADDR1_REL (1 << 19)
4845 # define R500_ALPHA_ADDR2(x) (x << 20)
4846 # define R500_ALPHA_ADDR2_CONST (1 << 28)
4847 # define R500_ALPHA_ADDR2_REL (1 << 29)
4848 # define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30)
4849 # define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30)
4850 # define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30)
4851 # define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30)
4852 #define R500_US_ALU_RGBA_INST_0 0xb000
4853 # define R500_ALU_RGBA_OP_MAD (0 << 0)
4854 # define R500_ALU_RGBA_OP_DP3 (1 << 0)
4855 # define R500_ALU_RGBA_OP_DP4 (2 << 0)
4856 # define R500_ALU_RGBA_OP_D2A (3 << 0)
4857 # define R500_ALU_RGBA_OP_MIN (4 << 0)
4858 # define R500_ALU_RGBA_OP_MAX (5 << 0)
4859 /* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */
4860 # define R500_ALU_RGBA_OP_CND (7 << 0)
4861 # define R500_ALU_RGBA_OP_CMP (8 << 0)
4862 # define R500_ALU_RGBA_OP_FRC (9 << 0)
4863 # define R500_ALU_RGBA_OP_SOP (10 << 0)
4864 # define R500_ALU_RGBA_OP_MDH (11 << 0)
4865 # define R500_ALU_RGBA_OP_MDV (12 << 0)
4866 # define R500_ALU_RGBA_ADDRD(x) (x << 4)
4867 # define R500_ALU_RGBA_ADDRD_REL (1 << 11)
4868 # define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12)
4869 # define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12)
4870 # define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12)
4871 # define R500_ALU_RGBA_SEL_C_SRCP (3 << 12)
4872 # define R500_ALU_RGBA_R_SWIZ_R (0 << 14)
4873 # define R500_ALU_RGBA_R_SWIZ_G (1 << 14)
4874 # define R500_ALU_RGBA_R_SWIZ_B (2 << 14)
4875 # define R500_ALU_RGBA_R_SWIZ_A (3 << 14)
4876 # define R500_ALU_RGBA_R_SWIZ_0 (4 << 14)
4877 # define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14)
4878 # define R500_ALU_RGBA_R_SWIZ_1 (6 << 14)
4879 /* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */
4880 # define R500_ALU_RGBA_G_SWIZ_R (0 << 17)
4881 # define R500_ALU_RGBA_G_SWIZ_G (1 << 17)
4882 # define R500_ALU_RGBA_G_SWIZ_B (2 << 17)
4883 # define R500_ALU_RGBA_G_SWIZ_A (3 << 17)
4884 # define R500_ALU_RGBA_G_SWIZ_0 (4 << 17)
4885 # define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17)
4886 # define R500_ALU_RGBA_G_SWIZ_1 (6 << 17)
4887 /* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */
4888 # define R500_ALU_RGBA_B_SWIZ_R (0 << 20)
4889 # define R500_ALU_RGBA_B_SWIZ_G (1 << 20)
4890 # define R500_ALU_RGBA_B_SWIZ_B (2 << 20)
4891 # define R500_ALU_RGBA_B_SWIZ_A (3 << 20)
4892 # define R500_ALU_RGBA_B_SWIZ_0 (4 << 20)
4893 # define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20)
4894 # define R500_ALU_RGBA_B_SWIZ_1 (6 << 20)
4895 /* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */
4896 # define R500_ALU_RGBA_MOD_C_NOP (0 << 23)
4897 # define R500_ALU_RGBA_MOD_C_NEG (1 << 23)
4898 # define R500_ALU_RGBA_MOD_C_ABS (2 << 23)
4899 # define R500_ALU_RGBA_MOD_C_NAB (3 << 23)
4900 # define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25)
4901 # define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25)
4902 # define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25)
4903 # define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25)
4904 # define R500_ALU_RGBA_A_SWIZ_R (0 << 27)
4905 # define R500_ALU_RGBA_A_SWIZ_G (1 << 27)
4906 # define R500_ALU_RGBA_A_SWIZ_B (2 << 27)
4907 # define R500_ALU_RGBA_A_SWIZ_A (3 << 27)
4908 # define R500_ALU_RGBA_A_SWIZ_0 (4 << 27)
4909 # define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27)
4910 # define R500_ALU_RGBA_A_SWIZ_1 (6 << 27)
4911 /* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */
4912 # define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30)
4913 # define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30)
4914 # define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30)
4915 # define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30)
4916 #define R500_US_ALU_RGB_INST_0 0xa000
4917 # define R500_ALU_RGB_SEL_A_SRC0 (0 << 0)
4918 # define R500_ALU_RGB_SEL_A_SRC1 (1 << 0)
4919 # define R500_ALU_RGB_SEL_A_SRC2 (2 << 0)
4920 # define R500_ALU_RGB_SEL_A_SRCP (3 << 0)
4921 # define R500_ALU_RGB_R_SWIZ_A_R (0 << 2)
4922 # define R500_ALU_RGB_R_SWIZ_A_G (1 << 2)
4923 # define R500_ALU_RGB_R_SWIZ_A_B (2 << 2)
4924 # define R500_ALU_RGB_R_SWIZ_A_A (3 << 2)
4925 # define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2)
4926 # define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2)
4927 # define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2)
4928 /* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */
4929 # define R500_ALU_RGB_G_SWIZ_A_R (0 << 5)
4930 # define R500_ALU_RGB_G_SWIZ_A_G (1 << 5)
4931 # define R500_ALU_RGB_G_SWIZ_A_B (2 << 5)
4932 # define R500_ALU_RGB_G_SWIZ_A_A (3 << 5)
4933 # define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5)
4934 # define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5)
4935 # define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5)
4936 /* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */
4937 # define R500_ALU_RGB_B_SWIZ_A_R (0 << 8)
4938 # define R500_ALU_RGB_B_SWIZ_A_G (1 << 8)
4939 # define R500_ALU_RGB_B_SWIZ_A_B (2 << 8)
4940 # define R500_ALU_RGB_B_SWIZ_A_A (3 << 8)
4941 # define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8)
4942 # define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8)
4943 # define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8)
4944 /* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */
4945 # define R500_ALU_RGB_MOD_A_NOP (0 << 11)
4946 # define R500_ALU_RGB_MOD_A_NEG (1 << 11)
4947 # define R500_ALU_RGB_MOD_A_ABS (2 << 11)
4948 # define R500_ALU_RGB_MOD_A_NAB (3 << 11)
4949 # define R500_ALU_RGB_SEL_B_SRC0 (0 << 13)
4950 # define R500_ALU_RGB_SEL_B_SRC1 (1 << 13)
4951 # define R500_ALU_RGB_SEL_B_SRC2 (2 << 13)
4952 # define R500_ALU_RGB_SEL_B_SRCP (3 << 13)
4953 # define R500_ALU_RGB_R_SWIZ_B_R (0 << 15)
4954 # define R500_ALU_RGB_R_SWIZ_B_G (1 << 15)
4955 # define R500_ALU_RGB_R_SWIZ_B_B (2 << 15)
4956 # define R500_ALU_RGB_R_SWIZ_B_A (3 << 15)
4957 # define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15)
4958 # define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15)
4959 # define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15)
4960 /* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */
4961 # define R500_ALU_RGB_G_SWIZ_B_R (0 << 18)
4962 # define R500_ALU_RGB_G_SWIZ_B_G (1 << 18)
4963 # define R500_ALU_RGB_G_SWIZ_B_B (2 << 18)
4964 # define R500_ALU_RGB_G_SWIZ_B_A (3 << 18)
4965 # define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18)
4966 # define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18)
4967 # define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18)
4968 /* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */
4969 # define R500_ALU_RGB_B_SWIZ_B_R (0 << 21)
4970 # define R500_ALU_RGB_B_SWIZ_B_G (1 << 21)
4971 # define R500_ALU_RGB_B_SWIZ_B_B (2 << 21)
4972 # define R500_ALU_RGB_B_SWIZ_B_A (3 << 21)
4973 # define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21)
4974 # define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21)
4975 # define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21)
4976 /* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */
4977 # define R500_ALU_RGB_MOD_B_NOP (0 << 24)
4978 # define R500_ALU_RGB_MOD_B_NEG (1 << 24)
4979 # define R500_ALU_RGB_MOD_B_ABS (2 << 24)
4980 # define R500_ALU_RGB_MOD_B_NAB (3 << 24)
4981 # define R500_ALU_RGB_OMOD_IDENTITY (0 << 26)
4982 # define R500_ALU_RGB_OMOD_MUL_2 (1 << 26)
4983 # define R500_ALU_RGB_OMOD_MUL_4 (2 << 26)
4984 # define R500_ALU_RGB_OMOD_MUL_8 (3 << 26)
4985 # define R500_ALU_RGB_OMOD_DIV_2 (4 << 26)
4986 # define R500_ALU_RGB_OMOD_DIV_4 (5 << 26)
4987 # define R500_ALU_RGB_OMOD_DIV_8 (6 << 26)
4988 # define R500_ALU_RGB_OMOD_DISABLE (7 << 26)
4989 # define R500_ALU_RGB_TARGET(x) (x << 29)
4990 # define R500_ALU_RGB_WMASK (1 << 31)
4991 #define R500_US_ALU_RGB_ADDR_0 0x9000
4992 # define R500_RGB_ADDR0(x) (x << 0)
4993 # define R500_RGB_ADDR0_CONST (1 << 8)
4994 # define R500_RGB_ADDR0_REL (1 << 9)
4995 # define R500_RGB_ADDR1(x) (x << 10)
4996 # define R500_RGB_ADDR1_CONST (1 << 18)
4997 # define R500_RGB_ADDR1_REL (1 << 19)
4998 # define R500_RGB_ADDR2(x) (x << 20)
4999 # define R500_RGB_ADDR2_CONST (1 << 28)
5000 # define R500_RGB_ADDR2_REL (1 << 29)
5001 # define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30)
5002 # define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30)
5003 # define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30)
5004 # define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30)
5005 #define R500_US_CMN_INST_0 0xb800
5006 # define R500_INST_TYPE_ALU (0 << 0)
5007 # define R500_INST_TYPE_OUT (1 << 0)
5008 # define R500_INST_TYPE_FC (2 << 0)
5009 # define R500_INST_TYPE_TEX (3 << 0)
5010 # define R500_INST_TEX_SEM_WAIT (1 << 2)
5011 # define R500_INST_RGB_PRED_SEL_NONE (0 << 3)
5012 # define R500_INST_RGB_PRED_SEL_RGBA (1 << 3)
5013 # define R500_INST_RGB_PRED_SEL_RRRR (2 << 3)
5014 # define R500_INST_RGB_PRED_SEL_GGGG (3 << 3)
5015 # define R500_INST_RGB_PRED_SEL_BBBB (4 << 3)
5016 # define R500_INST_RGB_PRED_SEL_AAAA (5 << 3)
5017 # define R500_INST_RGB_PRED_INV (1 << 6)
5018 # define R500_INST_WRITE_INACTIVE (1 << 7)
5019 # define R500_INST_LAST (1 << 8)
5020 # define R500_INST_NOP (1 << 9)
5021 # define R500_INST_ALU_WAIT (1 << 10)
5022 # define R500_INST_RGB_WMASK_R (1 << 11)
5023 # define R500_INST_RGB_WMASK_G (1 << 12)
5024 # define R500_INST_RGB_WMASK_B (1 << 13)
5025 # define R500_INST_ALPHA_WMASK (1 << 14)
5026 # define R500_INST_RGB_OMASK_R (1 << 15)
5027 # define R500_INST_RGB_OMASK_G (1 << 16)
5028 # define R500_INST_RGB_OMASK_B (1 << 17)
5029 # define R500_INST_ALPHA_OMASK (1 << 18)
5030 # define R500_INST_RGB_CLAMP (1 << 19)
5031 # define R500_INST_ALPHA_CLAMP (1 << 20)
5032 # define R500_INST_ALU_RESULT_SEL (1 << 21)
5033 # define R500_INST_ALPHA_PRED_INV (1 << 22)
5034 # define R500_INST_ALU_RESULT_OP_EQ (0 << 23)
5035 # define R500_INST_ALU_RESULT_OP_LT (1 << 23)
5036 # define R500_INST_ALU_RESULT_OP_GE (2 << 23)
5037 # define R500_INST_ALU_RESULT_OP_NE (3 << 23)
5038 # define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25)
5039 # define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25)
5040 # define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25)
5041 # define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25)
5042 # define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25)
5043 # define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25)
5044 /* XXX next four are kind of guessed */
5045 # define R500_INST_STAT_WE_R (1 << 28)
5046 # define R500_INST_STAT_WE_G (1 << 29)
5047 # define R500_INST_STAT_WE_B (1 << 30)
5048 # define R500_INST_STAT_WE_A (1 << 31)
5049 /* note that these are 8 bit lengths, despite the offsets, at least for R500 */
5050 #define R500_US_CODE_ADDR 0x4630
5051 # define R500_US_CODE_START_ADDR(x) (x << 0)
5052 # define R500_US_CODE_END_ADDR(x) (x << 16)
5053 #define R500_US_CODE_OFFSET 0x4638
5054 # define R500_US_CODE_OFFSET_ADDR(x) (x << 0)
5055 #define R500_US_CODE_RANGE 0x4634
5056 # define R500_US_CODE_RANGE_ADDR(x) (x << 0)
5057 # define R500_US_CODE_RANGE_SIZE(x) (x << 16)
5058 #define R500_US_CONFIG 0x4600
5059 # define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
5060 #define R500_US_FC_ADDR_0 0xa000
5061 # define R500_FC_BOOL_ADDR(x) (x << 0)
5062 # define R500_FC_INT_ADDR(x) (x << 8)
5063 # define R500_FC_JUMP_ADDR(x) (x << 16)
5064 # define R500_FC_JUMP_GLOBAL (1 << 31)
5065 #define R500_US_FC_BOOL_CONST 0x4620
5066 # define R500_FC_KBOOL(x) (x)
5067 #define R500_US_FC_CTRL 0x4624
5068 # define R500_FC_TEST_EN (1 << 30)
5069 # define R500_FC_FULL_FC_EN (1 << 31)
5070 #define R500_US_FC_INST_0 0x9800
5071 # define R500_FC_OP_JUMP (0 << 0)
5072 # define R500_FC_OP_LOOP (1 << 0)
5073 # define R500_FC_OP_ENDLOOP (2 << 0)
5074 # define R500_FC_OP_REP (3 << 0)
5075 # define R500_FC_OP_ENDREP (4 << 0)
5076 # define R500_FC_OP_BREAKLOOP (5 << 0)
5077 # define R500_FC_OP_BREAKREP (6 << 0)
5078 # define R500_FC_OP_CONTINUE (7 << 0)
5079 # define R500_FC_B_ELSE (1 << 4)
5080 # define R500_FC_JUMP_ANY (1 << 5)
5081 # define R500_FC_A_OP_NONE (0 << 6)
5082 # define R500_FC_A_OP_POP (1 << 6)
5083 # define R500_FC_A_OP_PUSH (2 << 6)
5084 # define R500_FC_JUMP_FUNC(x) (x << 8)
5085 # define R500_FC_B_POP_CNT(x) (x << 16)
5086 # define R500_FC_B_OP0_NONE (0 << 24)
5087 # define R500_FC_B_OP0_DECR (1 << 24)
5088 # define R500_FC_B_OP0_INCR (2 << 24)
5089 # define R500_FC_B_OP1_DECR (0 << 26)
5090 # define R500_FC_B_OP1_NONE (1 << 26)
5091 # define R500_FC_B_OP1_INCR (2 << 26)
5092 # define R500_FC_IGNORE_UNCOVERED (1 << 28)
5093 #define R500_US_FC_INT_CONST_0 0x4c00
5094 # define R500_FC_INT_CONST_KR(x) (x << 0)
5095 # define R500_FC_INT_CONST_KG(x) (x << 8)
5096 # define R500_FC_INT_CONST_KB(x) (x << 16)
5097 /* _0 through _15 */
5098 #define R500_US_FORMAT0_0 0x4640
5099 # define R500_FORMAT_TXWIDTH(x) (x << 0)
5100 # define R500_FORMAT_TXHEIGHT(x) (x << 11)
5101 # define R500_FORMAT_TXDEPTH(x) (x << 22)
5103 #define R500_US_OUT_FMT_0 0x46a4
5104 # define R500_OUT_FMT_C4_8 (0 << 0)
5105 # define R500_OUT_FMT_C4_10 (1 << 0)
5106 # define R500_OUT_FMT_C4_10_GAMMA (2 << 0)
5107 # define R500_OUT_FMT_C_16 (3 << 0)
5108 # define R500_OUT_FMT_C2_16 (4 << 0)
5109 # define R500_OUT_FMT_C4_16 (5 << 0)
5110 # define R500_OUT_FMT_C_16_MPEG (6 << 0)
5111 # define R500_OUT_FMT_C2_16_MPEG (7 << 0)
5112 # define R500_OUT_FMT_C2_4 (8 << 0)
5113 # define R500_OUT_FMT_C_3_3_2 (9 << 0)
5114 # define R500_OUT_FMT_C_6_5_6 (10 << 0)
5115 # define R500_OUT_FMT_C_11_11_10 (11 << 0)
5116 # define R500_OUT_FMT_C_10_11_11 (12 << 0)
5117 # define R500_OUT_FMT_C_2_10_10_10 (13 << 0)
5118 /* #define R500_OUT_FMT_RESERVED (14 << 0) */
5119 # define R500_OUT_FMT_UNUSED (15 << 0)
5120 # define R500_OUT_FMT_C_16_FP (16 << 0)
5121 # define R500_OUT_FMT_C2_16_FP (17 << 0)
5122 # define R500_OUT_FMT_C4_16_FP (18 << 0)
5123 # define R500_OUT_FMT_C_32_FP (19 << 0)
5124 # define R500_OUT_FMT_C2_32_FP (20 << 0)
5125 # define R500_OUT_FMT_C4_32_FP (21 << 0)
5126 # define R500_C0_SEL_A (0 << 8)
5127 # define R500_C0_SEL_R (1 << 8)
5128 # define R500_C0_SEL_G (2 << 8)
5129 # define R500_C0_SEL_B (3 << 8)
5130 # define R500_C1_SEL_A (0 << 10)
5131 # define R500_C1_SEL_R (1 << 10)
5132 # define R500_C1_SEL_G (2 << 10)
5133 # define R500_C1_SEL_B (3 << 10)
5134 # define R500_C2_SEL_A (0 << 12)
5135 # define R500_C2_SEL_R (1 << 12)
5136 # define R500_C2_SEL_G (2 << 12)
5137 # define R500_C2_SEL_B (3 << 12)
5138 # define R500_C3_SEL_A (0 << 14)
5139 # define R500_C3_SEL_R (1 << 14)
5140 # define R500_C3_SEL_G (2 << 14)
5141 # define R500_C3_SEL_B (3 << 14)
5142 # define R500_OUT_SIGN(x) (x << 16)
5143 # define R500_ROUND_ADJ (1 << 20)
5144 #define R500_US_PIXSIZE 0x4604
5145 # define R500_PIX_SIZE(x) (x)
5146 #define R500_US_TEX_ADDR_0 0x9800
5147 # define R500_TEX_SRC_ADDR(x) (x << 0)
5148 # define R500_TEX_SRC_ADDR_REL (1 << 7)
5149 # define R500_TEX_SRC_S_SWIZ_R (0 << 8)
5150 # define R500_TEX_SRC_S_SWIZ_G (1 << 8)
5151 # define R500_TEX_SRC_S_SWIZ_B (2 << 8)
5152 # define R500_TEX_SRC_S_SWIZ_A (3 << 8)
5153 # define R500_TEX_SRC_T_SWIZ_R (0 << 10)
5154 # define R500_TEX_SRC_T_SWIZ_G (1 << 10)
5155 # define R500_TEX_SRC_T_SWIZ_B (2 << 10)
5156 # define R500_TEX_SRC_T_SWIZ_A (3 << 10)
5157 # define R500_TEX_SRC_R_SWIZ_R (0 << 12)
5158 # define R500_TEX_SRC_R_SWIZ_G (1 << 12)
5159 # define R500_TEX_SRC_R_SWIZ_B (2 << 12)
5160 # define R500_TEX_SRC_R_SWIZ_A (3 << 12)
5161 # define R500_TEX_SRC_Q_SWIZ_R (0 << 14)
5162 # define R500_TEX_SRC_Q_SWIZ_G (1 << 14)
5163 # define R500_TEX_SRC_Q_SWIZ_B (2 << 14)
5164 # define R500_TEX_SRC_Q_SWIZ_A (3 << 14)
5165 # define R500_TEX_DST_ADDR(x) (x << 16)
5166 # define R500_TEX_DST_ADDR_REL (1 << 23)
5167 # define R500_TEX_DST_R_SWIZ_R (0 << 24)
5168 # define R500_TEX_DST_R_SWIZ_G (1 << 24)
5169 # define R500_TEX_DST_R_SWIZ_B (2 << 24)
5170 # define R500_TEX_DST_R_SWIZ_A (3 << 24)
5171 # define R500_TEX_DST_G_SWIZ_R (0 << 26)
5172 # define R500_TEX_DST_G_SWIZ_G (1 << 26)
5173 # define R500_TEX_DST_G_SWIZ_B (2 << 26)
5174 # define R500_TEX_DST_G_SWIZ_A (3 << 26)
5175 # define R500_TEX_DST_B_SWIZ_R (0 << 28)
5176 # define R500_TEX_DST_B_SWIZ_G (1 << 28)
5177 # define R500_TEX_DST_B_SWIZ_B (2 << 28)
5178 # define R500_TEX_DST_B_SWIZ_A (3 << 28)
5179 # define R500_TEX_DST_A_SWIZ_R (0 << 30)
5180 # define R500_TEX_DST_A_SWIZ_G (1 << 30)
5181 # define R500_TEX_DST_A_SWIZ_B (2 << 30)
5182 # define R500_TEX_DST_A_SWIZ_A (3 << 30)
5183 #define R500_US_TEX_ADDR_DXDY_0 0xa000
5184 # define R500_DX_ADDR(x) (x << 0)
5185 # define R500_DX_ADDR_REL (1 << 7)
5186 # define R500_DX_S_SWIZ_R (0 << 8)
5187 # define R500_DX_S_SWIZ_G (1 << 8)
5188 # define R500_DX_S_SWIZ_B (2 << 8)
5189 # define R500_DX_S_SWIZ_A (3 << 8)
5190 # define R500_DX_T_SWIZ_R (0 << 10)
5191 # define R500_DX_T_SWIZ_G (1 << 10)
5192 # define R500_DX_T_SWIZ_B (2 << 10)
5193 # define R500_DX_T_SWIZ_A (3 << 10)
5194 # define R500_DX_R_SWIZ_R (0 << 12)
5195 # define R500_DX_R_SWIZ_G (1 << 12)
5196 # define R500_DX_R_SWIZ_B (2 << 12)
5197 # define R500_DX_R_SWIZ_A (3 << 12)
5198 # define R500_DX_Q_SWIZ_R (0 << 14)
5199 # define R500_DX_Q_SWIZ_G (1 << 14)
5200 # define R500_DX_Q_SWIZ_B (2 << 14)
5201 # define R500_DX_Q_SWIZ_A (3 << 14)
5202 # define R500_DY_ADDR(x) (x << 16)
5203 # define R500_DY_ADDR_REL (1 << 17)
5204 # define R500_DY_S_SWIZ_R (0 << 24)
5205 # define R500_DY_S_SWIZ_G (1 << 24)
5206 # define R500_DY_S_SWIZ_B (2 << 24)
5207 # define R500_DY_S_SWIZ_A (3 << 24)
5208 # define R500_DY_T_SWIZ_R (0 << 26)
5209 # define R500_DY_T_SWIZ_G (1 << 26)
5210 # define R500_DY_T_SWIZ_B (2 << 26)
5211 # define R500_DY_T_SWIZ_A (3 << 26)
5212 # define R500_DY_R_SWIZ_R (0 << 28)
5213 # define R500_DY_R_SWIZ_G (1 << 28)
5214 # define R500_DY_R_SWIZ_B (2 << 28)
5215 # define R500_DY_R_SWIZ_A (3 << 28)
5216 # define R500_DY_Q_SWIZ_R (0 << 30)
5217 # define R500_DY_Q_SWIZ_G (1 << 30)
5218 # define R500_DY_Q_SWIZ_B (2 << 30)
5219 # define R500_DY_Q_SWIZ_A (3 << 30)
5220 #define R500_US_TEX_INST_0 0x9000
5221 # define R500_TEX_ID(x) (x << 16)
5222 # define R500_TEX_INST_NOP (0 << 22)
5223 # define R500_TEX_INST_LD (1 << 22)
5224 # define R500_TEX_INST_TEXKILL (2 << 22)
5225 # define R500_TEX_INST_PROJ (3 << 22)
5226 # define R500_TEX_INST_LODBIAS (4 << 22)
5227 # define R500_TEX_INST_LOD (5 << 22)
5228 # define R500_TEX_INST_DXDY (6 << 22)
5229 # define R500_TEX_SEM_ACQUIRE (1 << 25)
5230 # define R500_TEX_IGNORE_UNCOVERED (1 << 26)
5231 # define R500_TEX_UNSCALED (1 << 27)
5232 #define R500_US_W_FMT 0x46b4
5233 # define R500_W_FMT_W0 (0 << 0)
5234 # define R500_W_FMT_W24 (1 << 0)
5235 # define R500_W_FMT_W24FP (2 << 0)
5236 # define R500_W_SRC_US (0 << 2)
5237 # define R500_W_SRC_RAS (1 << 2)
5239 #define R500_GA_US_VECTOR_INDEX 0x4250
5240 #define R500_GA_US_VECTOR_DATA 0x4254
5242 #define R500_RS_INST_0 0x4320
5243 #define R500_RS_INST_1 0x4324
5244 # define R500_RS_INST_TEX_ID_SHIFT 0
5245 # define R500_RS_INST_TEX_CN_WRITE (1 << 4)
5246 # define R500_RS_INST_TEX_ADDR_SHIFT 5
5247 # define R500_RS_INST_COL_ID_SHIFT 12
5248 # define R500_RS_INST_COL_CN_NO_WRITE (0 << 16)
5249 # define R500_RS_INST_COL_CN_WRITE (1 << 16)
5250 # define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16)
5251 # define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16)
5252 # define R500_RS_INST_COL_COL_ADDR_SHIFT 18
5253 # define R500_RS_INST_TEX_ADJ (1 << 25)
5254 # define R500_RS_INST_W_CN (1 << 26)
5256 #define R500_US_FC_CTRL 0x4624
5257 #define R500_US_CODE_ADDR 0x4630
5258 #define R500_US_CODE_RANGE 0x4634
5259 #define R500_US_CODE_OFFSET 0x4638
5261 #define R500_RS_IP_0 0x4074
5262 #define R500_RS_IP_1 0x4078
5263 # define R500_RS_IP_PTR_K0 62
5264 # define R500_RS_IP_PTR_K1 63
5265 # define R500_RS_IP_TEX_PTR_S_SHIFT 0
5266 # define R500_RS_IP_TEX_PTR_T_SHIFT 6
5267 # define R500_RS_IP_TEX_PTR_R_SHIFT 12
5268 # define R500_RS_IP_TEX_PTR_Q_SHIFT 18
5269 # define R500_RS_IP_COL_PTR_SHIFT 24
5270 # define R500_RS_IP_COL_FMT_SHIFT 27
5271 # define R500_RS_IP_COL_FMT_RGBA (0 << 27)
5272 # define R500_RS_IP_OFFSET_EN (1 << 31)
5274 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */