2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
31 * Kevin E. Martin <martin@xfree86.org>
32 * Rickard E. Faith <faith@valinux.com>
33 * Alan Hourihane <alanh@fairlite.demon.co.uk>
38 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
39 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
43 * RAGE 128 Software Development Manual (Technical Reference Manual P/N
44 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
48 /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
49 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
50 * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
52 #ifndef _RADEON_REG_H_
53 #define _RADEON_REG_H_
55 #define ATI_DATATYPE_VQ 0
56 #define ATI_DATATYPE_CI4 1
57 #define ATI_DATATYPE_CI8 2
58 #define ATI_DATATYPE_ARGB1555 3
59 #define ATI_DATATYPE_RGB565 4
60 #define ATI_DATATYPE_RGB888 5
61 #define ATI_DATATYPE_ARGB8888 6
62 #define ATI_DATATYPE_RGB332 7
63 #define ATI_DATATYPE_Y8 8
64 #define ATI_DATATYPE_RGB8 9
65 #define ATI_DATATYPE_CI16 10
66 #define ATI_DATATYPE_VYUY_422 11
67 #define ATI_DATATYPE_YVYU_422 12
68 #define ATI_DATATYPE_AYUV_444 14
69 #define ATI_DATATYPE_ARGB4444 15
71 /* Registers for 2D/Video/Overlay */
72 #define RADEON_ADAPTER_ID 0x0f2c /* PCI */
73 #define RADEON_AGP_BASE 0x0170
74 #define RADEON_AGP_CNTL 0x0174
75 # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
76 # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
77 # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
78 # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
79 # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
80 # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
81 # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
82 # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
83 #define RADEON_STATUS_PCI_CONFIG 0x06
84 # define RADEON_CAP_LIST 0x100000
85 #define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
86 # define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
87 # define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
88 # define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
89 # define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
90 #define RADEON_AGP_COMMAND 0x0f60 /* PCI */
91 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
92 # define RADEON_AGP_ENABLE (1<<8)
93 #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
94 #define RADEON_AGP_STATUS 0x0f5c /* PCI */
95 # define RADEON_AGP_1X_MODE 0x01
96 # define RADEON_AGP_2X_MODE 0x02
97 # define RADEON_AGP_4X_MODE 0x04
98 # define RADEON_AGP_FW_MODE 0x10
99 # define RADEON_AGP_MODE_MASK 0x17
100 # define RADEON_AGPv3_MODE 0x08
101 # define RADEON_AGPv3_4X_MODE 0x01
102 # define RADEON_AGPv3_8X_MODE 0x02
103 #define RADEON_ATTRDR 0x03c1 /* VGA */
104 #define RADEON_ATTRDW 0x03c0 /* VGA */
105 #define RADEON_ATTRX 0x03c0 /* VGA */
106 #define RADEON_AUX_SC_CNTL 0x1660
107 # define RADEON_AUX1_SC_EN (1 << 0)
108 # define RADEON_AUX1_SC_MODE_OR (0 << 1)
109 # define RADEON_AUX1_SC_MODE_NAND (1 << 1)
110 # define RADEON_AUX2_SC_EN (1 << 2)
111 # define RADEON_AUX2_SC_MODE_OR (0 << 3)
112 # define RADEON_AUX2_SC_MODE_NAND (1 << 3)
113 # define RADEON_AUX3_SC_EN (1 << 4)
114 # define RADEON_AUX3_SC_MODE_OR (0 << 5)
115 # define RADEON_AUX3_SC_MODE_NAND (1 << 5)
116 #define RADEON_AUX1_SC_BOTTOM 0x1670
117 #define RADEON_AUX1_SC_LEFT 0x1664
118 #define RADEON_AUX1_SC_RIGHT 0x1668
119 #define RADEON_AUX1_SC_TOP 0x166c
120 #define RADEON_AUX2_SC_BOTTOM 0x1680
121 #define RADEON_AUX2_SC_LEFT 0x1674
122 #define RADEON_AUX2_SC_RIGHT 0x1678
123 #define RADEON_AUX2_SC_TOP 0x167c
124 #define RADEON_AUX3_SC_BOTTOM 0x1690
125 #define RADEON_AUX3_SC_LEFT 0x1684
126 #define RADEON_AUX3_SC_RIGHT 0x1688
127 #define RADEON_AUX3_SC_TOP 0x168c
128 #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
129 #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
131 #define RADEON_BASE_CODE 0x0f0b
132 #define RADEON_BIOS_0_SCRATCH 0x0010
133 # define RADEON_FP_PANEL_SCALABLE (1 << 16)
134 # define RADEON_FP_PANEL_SCALE_EN (1 << 17)
135 # define RADEON_FP_CHIP_SCALE_EN (1 << 18)
136 # define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
137 # define RADEON_DISPLAY_ROT_MASK (3 << 28)
138 # define RADEON_DISPLAY_ROT_00 (0 << 28)
139 # define RADEON_DISPLAY_ROT_90 (1 << 28)
140 # define RADEON_DISPLAY_ROT_180 (2 << 28)
141 # define RADEON_DISPLAY_ROT_270 (3 << 28)
142 #define RADEON_BIOS_1_SCRATCH 0x0014
143 #define RADEON_BIOS_2_SCRATCH 0x0018
144 #define RADEON_BIOS_3_SCRATCH 0x001c
145 #define RADEON_BIOS_4_SCRATCH 0x0020
146 # define RADEON_CRT1_ATTACHED_MASK (3 << 0)
147 # define RADEON_CRT1_ATTACHED_MONO (1 << 0)
148 # define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
149 # define RADEON_LCD1_ATTACHED (1 << 2)
150 # define RADEON_DFP1_ATTACHED (1 << 3)
151 # define RADEON_TV1_ATTACHED_MASK (3 << 4)
152 # define RADEON_TV1_ATTACHED_COMP (1 << 4)
153 # define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
154 # define RADEON_CRT2_ATTACHED_MASK (3 << 8)
155 # define RADEON_CRT2_ATTACHED_MONO (1 << 8)
156 # define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
157 # define RADEON_DFP2_ATTACHED (1 << 11)
158 #define RADEON_BIOS_5_SCRATCH 0x0024
159 # define RADEON_LCD1_ON (1 << 0)
160 # define RADEON_CRT1_ON (1 << 1)
161 # define RADEON_TV1_ON (1 << 2)
162 # define RADEON_DFP1_ON (1 << 3)
163 # define RADEON_CRT2_ON (1 << 5)
164 # define RADEON_CV1_ON (1 << 6)
165 # define RADEON_DFP2_ON (1 << 7)
166 # define RADEON_LCD1_CRTC_MASK (1 << 8)
167 # define RADEON_LCD1_CRTC_SHIFT 8
168 # define RADEON_CRT1_CRTC_MASK (1 << 9)
169 # define RADEON_CRT1_CRTC_SHIFT 9
170 # define RADEON_TV1_CRTC_MASK (1 << 10)
171 # define RADEON_TV1_CRTC_SHIFT 10
172 # define RADEON_DFP1_CRTC_MASK (1 << 11)
173 # define RADEON_DFP1_CRTC_SHIFT 11
174 # define RADEON_CRT2_CRTC_MASK (1 << 12)
175 # define RADEON_CRT2_CRTC_SHIFT 12
176 # define RADEON_CV1_CRTC_MASK (1 << 13)
177 # define RADEON_CV1_CRTC_SHIFT 13
178 # define RADEON_DFP2_CRTC_MASK (1 << 14)
179 # define RADEON_DFP2_CRTC_SHIFT 14
180 #define RADEON_BIOS_6_SCRATCH 0x0028
181 # define RADEON_ACC_MODE_CHANGE (1 << 2)
182 # define RADEON_EXT_DESKTOP_MODE (1 << 3)
183 # define RADEON_LCD_DPMS_ON (1 << 20)
184 # define RADEON_CRT_DPMS_ON (1 << 21)
185 # define RADEON_TV_DPMS_ON (1 << 22)
186 # define RADEON_DFP_DPMS_ON (1 << 23)
187 # define RADEON_DPMS_MASK (3 << 24)
188 # define RADEON_DPMS_ON (0 << 24)
189 # define RADEON_DPMS_STANDBY (1 << 24)
190 # define RADEON_DPMS_SUSPEND (2 << 24)
191 # define RADEON_DPMS_OFF (3 << 24)
192 # define RADEON_SCREEN_BLANKING (1 << 26)
193 # define RADEON_DRIVER_CRITICAL (1 << 27)
194 # define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
195 #define RADEON_BIOS_7_SCRATCH 0x002c
196 # define RADEON_SYS_HOTKEY (1 << 10)
197 # define RADEON_DRV_LOADED (1 << 12)
198 #define RADEON_BIOS_ROM 0x0f30 /* PCI */
199 #define RADEON_BIST 0x0f0f /* PCI */
200 #define RADEON_BRUSH_DATA0 0x1480
201 #define RADEON_BRUSH_DATA1 0x1484
202 #define RADEON_BRUSH_DATA10 0x14a8
203 #define RADEON_BRUSH_DATA11 0x14ac
204 #define RADEON_BRUSH_DATA12 0x14b0
205 #define RADEON_BRUSH_DATA13 0x14b4
206 #define RADEON_BRUSH_DATA14 0x14b8
207 #define RADEON_BRUSH_DATA15 0x14bc
208 #define RADEON_BRUSH_DATA16 0x14c0
209 #define RADEON_BRUSH_DATA17 0x14c4
210 #define RADEON_BRUSH_DATA18 0x14c8
211 #define RADEON_BRUSH_DATA19 0x14cc
212 #define RADEON_BRUSH_DATA2 0x1488
213 #define RADEON_BRUSH_DATA20 0x14d0
214 #define RADEON_BRUSH_DATA21 0x14d4
215 #define RADEON_BRUSH_DATA22 0x14d8
216 #define RADEON_BRUSH_DATA23 0x14dc
217 #define RADEON_BRUSH_DATA24 0x14e0
218 #define RADEON_BRUSH_DATA25 0x14e4
219 #define RADEON_BRUSH_DATA26 0x14e8
220 #define RADEON_BRUSH_DATA27 0x14ec
221 #define RADEON_BRUSH_DATA28 0x14f0
222 #define RADEON_BRUSH_DATA29 0x14f4
223 #define RADEON_BRUSH_DATA3 0x148c
224 #define RADEON_BRUSH_DATA30 0x14f8
225 #define RADEON_BRUSH_DATA31 0x14fc
226 #define RADEON_BRUSH_DATA32 0x1500
227 #define RADEON_BRUSH_DATA33 0x1504
228 #define RADEON_BRUSH_DATA34 0x1508
229 #define RADEON_BRUSH_DATA35 0x150c
230 #define RADEON_BRUSH_DATA36 0x1510
231 #define RADEON_BRUSH_DATA37 0x1514
232 #define RADEON_BRUSH_DATA38 0x1518
233 #define RADEON_BRUSH_DATA39 0x151c
234 #define RADEON_BRUSH_DATA4 0x1490
235 #define RADEON_BRUSH_DATA40 0x1520
236 #define RADEON_BRUSH_DATA41 0x1524
237 #define RADEON_BRUSH_DATA42 0x1528
238 #define RADEON_BRUSH_DATA43 0x152c
239 #define RADEON_BRUSH_DATA44 0x1530
240 #define RADEON_BRUSH_DATA45 0x1534
241 #define RADEON_BRUSH_DATA46 0x1538
242 #define RADEON_BRUSH_DATA47 0x153c
243 #define RADEON_BRUSH_DATA48 0x1540
244 #define RADEON_BRUSH_DATA49 0x1544
245 #define RADEON_BRUSH_DATA5 0x1494
246 #define RADEON_BRUSH_DATA50 0x1548
247 #define RADEON_BRUSH_DATA51 0x154c
248 #define RADEON_BRUSH_DATA52 0x1550
249 #define RADEON_BRUSH_DATA53 0x1554
250 #define RADEON_BRUSH_DATA54 0x1558
251 #define RADEON_BRUSH_DATA55 0x155c
252 #define RADEON_BRUSH_DATA56 0x1560
253 #define RADEON_BRUSH_DATA57 0x1564
254 #define RADEON_BRUSH_DATA58 0x1568
255 #define RADEON_BRUSH_DATA59 0x156c
256 #define RADEON_BRUSH_DATA6 0x1498
257 #define RADEON_BRUSH_DATA60 0x1570
258 #define RADEON_BRUSH_DATA61 0x1574
259 #define RADEON_BRUSH_DATA62 0x1578
260 #define RADEON_BRUSH_DATA63 0x157c
261 #define RADEON_BRUSH_DATA7 0x149c
262 #define RADEON_BRUSH_DATA8 0x14a0
263 #define RADEON_BRUSH_DATA9 0x14a4
264 #define RADEON_BRUSH_SCALE 0x1470
265 #define RADEON_BRUSH_Y_X 0x1474
266 #define RADEON_BUS_CNTL 0x0030
267 # define RADEON_BUS_MASTER_DIS (1 << 6)
268 # define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
269 # define RADEON_BUS_RD_DISCARD_EN (1 << 24)
270 # define RADEON_BUS_RD_ABORT_EN (1 << 25)
271 # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
272 # define RADEON_BUS_WRT_BURST (1 << 29)
273 # define RADEON_BUS_READ_BURST (1 << 30)
274 #define RADEON_BUS_CNTL1 0x0034
275 # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
277 //#define RADEON_PCIE_INDEX 0x0030
278 //#define RADEON_PCIE_DATA 0x0034
279 #define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */
280 # define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0
281 # define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7
282 # define RADEON_PCIE_LC_LINK_WIDTH_X0 0
283 # define RADEON_PCIE_LC_LINK_WIDTH_X1 1
284 # define RADEON_PCIE_LC_LINK_WIDTH_X2 2
285 # define RADEON_PCIE_LC_LINK_WIDTH_X4 3
286 # define RADEON_PCIE_LC_LINK_WIDTH_X8 4
287 # define RADEON_PCIE_LC_LINK_WIDTH_X12 5
288 # define RADEON_PCIE_LC_LINK_WIDTH_X16 6
289 # define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4
290 # define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70
291 # define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
292 # define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
293 # define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
295 #define RADEON_CACHE_CNTL 0x1724
296 #define RADEON_CACHE_LINE 0x0f0c /* PCI */
297 #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
298 #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
299 #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
300 # define RADEON_SCLK_DYN_START_CNTL (1 << 15)
301 #define RADEON_CLOCK_CNTL_DATA 0x000c
302 #define RADEON_CLOCK_CNTL_INDEX 0x0008
303 # define RADEON_PLL_WR_EN (1 << 7)
304 # define RADEON_PLL_DIV_SEL (3 << 8)
305 # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
306 #define RADEON_CLK_PWRMGT_CNTL 0x0014
307 # define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
308 # define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
309 # define RADEON_ACTIVE_HILO_LAT_SHIFT 13
310 # define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
311 # define RADEON_MC_BUSY (1 << 16)
312 # define RADEON_DLL_READY (1 << 19)
313 # define RADEON_CG_NO1_DEBUG_0 (1 << 24)
314 # define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
315 # define RADEON_DYN_STOP_MODE_MASK (7 << 21)
316 # define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
317 # define RADEON_TVCLK_TURNOFF (1 << 31)
318 #define RADEON_PLL_PWRMGT_CNTL 0x0015
319 # define RADEON_TCL_BYPASS_DISABLE (1 << 20)
320 #define RADEON_CLR_CMP_CLR_3D 0x1a24
321 #define RADEON_CLR_CMP_CLR_DST 0x15c8
322 #define RADEON_CLR_CMP_CLR_SRC 0x15c4
323 #define RADEON_CLR_CMP_CNTL 0x15c0
324 # define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
325 # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
326 # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
327 #define RADEON_CLR_CMP_MASK 0x15cc
328 # define RADEON_CLR_CMP_MSK 0xffffffff
329 #define RADEON_CLR_CMP_MASK_3D 0x1A28
330 #define RADEON_COMMAND 0x0f04 /* PCI */
331 #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
332 #define RADEON_CONFIG_APER_0_BASE 0x0100
333 #define RADEON_CONFIG_APER_1_BASE 0x0104
334 #define RADEON_CONFIG_APER_SIZE 0x0108
335 #define RADEON_CONFIG_BONDS 0x00e8
336 #define RADEON_CONFIG_CNTL 0x00e0
337 # define RADEON_CFG_ATI_REV_A11 (0 << 16)
338 # define RADEON_CFG_ATI_REV_A12 (1 << 16)
339 # define RADEON_CFG_ATI_REV_A13 (2 << 16)
340 # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
341 #define RADEON_CONFIG_MEMSIZE 0x00f8
342 #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
343 #define RADEON_CONFIG_REG_1_BASE 0x010c
344 #define RADEON_CONFIG_REG_APER_SIZE 0x0110
345 #define RADEON_CONFIG_XSTRAP 0x00e4
346 #define RADEON_CONSTANT_COLOR_C 0x1d34
347 # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
348 # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
349 # define RADEON_CONSTANT_COLOR_ZERO 0x00000000
350 #define RADEON_CRC_CMDFIFO_ADDR 0x0740
351 #define RADEON_CRC_CMDFIFO_DOUT 0x0744
352 #define RADEON_GRPH_BUFFER_CNTL 0x02f0
353 # define RADEON_GRPH_START_REQ_MASK (0x7f)
354 # define RADEON_GRPH_START_REQ_SHIFT 0
355 # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
356 # define RADEON_GRPH_STOP_REQ_SHIFT 8
357 # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
358 # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
359 # define RADEON_GRPH_CRITICAL_CNTL (1<<28)
360 # define RADEON_GRPH_BUFFER_SIZE (1<<29)
361 # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
362 # define RADEON_GRPH_STOP_CNTL (1<<31)
363 #define RADEON_GRPH2_BUFFER_CNTL 0x03f0
364 # define RADEON_GRPH2_START_REQ_MASK (0x7f)
365 # define RADEON_GRPH2_START_REQ_SHIFT 0
366 # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
367 # define RADEON_GRPH2_STOP_REQ_SHIFT 8
368 # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
369 # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
370 # define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
371 # define RADEON_GRPH2_BUFFER_SIZE (1<<29)
372 # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
373 # define RADEON_GRPH2_STOP_CNTL (1<<31)
374 #define RADEON_CRTC_CRNT_FRAME 0x0214
375 #define RADEON_CRTC_EXT_CNTL 0x0054
376 # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
377 # define RADEON_VGA_ATI_LINEAR (1 << 3)
378 # define RADEON_XCRT_CNT_EN (1 << 6)
379 # define RADEON_CRTC_HSYNC_DIS (1 << 8)
380 # define RADEON_CRTC_VSYNC_DIS (1 << 9)
381 # define RADEON_CRTC_DISPLAY_DIS (1 << 10)
382 # define RADEON_CRTC_SYNC_TRISTAT (1 << 11)
383 # define RADEON_CRTC_CRT_ON (1 << 15)
384 #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
385 # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)
386 # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)
387 # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)
388 #define RADEON_CRTC_GEN_CNTL 0x0050
389 # define RADEON_CRTC_DBL_SCAN_EN (1 << 0)
390 # define RADEON_CRTC_INTERLACE_EN (1 << 1)
391 # define RADEON_CRTC_CSYNC_EN (1 << 4)
392 # define RADEON_CRTC_ICON_EN (1 << 15)
393 # define RADEON_CRTC_CUR_EN (1 << 16)
394 # define RADEON_CRTC_CUR_MODE_MASK (7 << 20)
395 # define RADEON_CRTC_CUR_MODE_SHIFT 20
396 # define RADEON_CRTC_CUR_MODE_MONO 0
397 # define RADEON_CRTC_CUR_MODE_24BPP 2
398 # define RADEON_CRTC_EXT_DISP_EN (1 << 24)
399 # define RADEON_CRTC_EN (1 << 25)
400 # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
401 #define RADEON_CRTC2_GEN_CNTL 0x03f8
402 # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)
403 # define RADEON_CRTC2_INTERLACE_EN (1 << 1)
404 # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)
405 # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
406 # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
407 # define RADEON_CRTC2_CRT2_ON (1 << 7)
408 # define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
409 # define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)
410 # define RADEON_CRTC2_ICON_EN (1 << 15)
411 # define RADEON_CRTC2_CUR_EN (1 << 16)
412 # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
413 # define RADEON_CRTC2_DISP_DIS (1 << 23)
414 # define RADEON_CRTC2_EN (1 << 25)
415 # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)
416 # define RADEON_CRTC2_CSYNC_EN (1 << 27)
417 # define RADEON_CRTC2_HSYNC_DIS (1 << 28)
418 # define RADEON_CRTC2_VSYNC_DIS (1 << 29)
419 #define RADEON_CRTC_MORE_CNTL 0x27c
420 # define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
421 # define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
422 # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
423 # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
424 #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
425 #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
426 # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
427 # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
428 # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
429 # define RADEON_CRTC_H_SYNC_WID (0x3f << 16)
430 # define RADEON_CRTC_H_SYNC_WID_SHIFT 16
431 # define RADEON_CRTC_H_SYNC_POL (1 << 23)
432 #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304
433 # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
434 # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
435 # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
436 # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)
437 # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16
438 # define RADEON_CRTC2_H_SYNC_POL (1 << 23)
439 #define RADEON_CRTC_H_TOTAL_DISP 0x0200
440 # define RADEON_CRTC_H_TOTAL (0x03ff << 0)
441 # define RADEON_CRTC_H_TOTAL_SHIFT 0
442 # define RADEON_CRTC_H_DISP (0x01ff << 16)
443 # define RADEON_CRTC_H_DISP_SHIFT 16
444 #define RADEON_CRTC2_H_TOTAL_DISP 0x0300
445 # define RADEON_CRTC2_H_TOTAL (0x03ff << 0)
446 # define RADEON_CRTC2_H_TOTAL_SHIFT 0
447 # define RADEON_CRTC2_H_DISP (0x01ff << 16)
448 # define RADEON_CRTC2_H_DISP_SHIFT 16
450 #define RADEON_CRTC_OFFSET_RIGHT 0x0220
451 #define RADEON_CRTC_OFFSET 0x0224
452 # define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
453 # define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)
455 #define RADEON_CRTC2_OFFSET 0x0324
456 # define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
457 # define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)
458 #define RADEON_CRTC_OFFSET_CNTL 0x0228
459 # define RADEON_CRTC_TILE_LINE_SHIFT 0
460 # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4
461 # define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)
462 # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)
463 # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)
464 # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
465 # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
466 # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)
467 # define R300_CRTC_X_Y_MODE_EN (1 << 9)
468 # define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)
469 # define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)
470 # define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)
471 # define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)
472 # define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)
473 # define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)
474 # define R300_CRTC_MICRO_TILE_EN (1 << 13)
475 # define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)
476 # define R300_CRTC_MACRO_TILE_EN (1 << 15)
477 # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)
478 # define RADEON_CRTC_TILE_EN (1 << 15)
479 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
480 # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
482 #define R300_CRTC_TILE_X0_Y0 0x0350
483 #define R300_CRTC2_TILE_X0_Y0 0x0358
485 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
486 # define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)
487 # define RADEON_CRTC2_TILE_EN (1 << 15)
488 #define RADEON_CRTC_PITCH 0x022c
489 # define RADEON_CRTC_PITCH__SHIFT 0
490 # define RADEON_CRTC_PITCH__RIGHT_SHIFT 16
492 #define RADEON_CRTC2_PITCH 0x032c
493 #define RADEON_CRTC_STATUS 0x005c
494 # define RADEON_CRTC_VBLANK_SAVE (1 << 1)
495 # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)
496 #define RADEON_CRTC2_STATUS 0x03fc
497 # define RADEON_CRTC2_VBLANK_SAVE (1 << 1)
498 # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)
499 #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c
500 # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)
501 # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0
502 # define RADEON_CRTC_V_SYNC_WID (0x1f << 16)
503 # define RADEON_CRTC_V_SYNC_WID_SHIFT 16
504 # define RADEON_CRTC_V_SYNC_POL (1 << 23)
505 #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c
506 # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)
507 # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
508 # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)
509 # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16
510 # define RADEON_CRTC2_V_SYNC_POL (1 << 23)
511 #define RADEON_CRTC_V_TOTAL_DISP 0x0208
512 # define RADEON_CRTC_V_TOTAL (0x07ff << 0)
513 # define RADEON_CRTC_V_TOTAL_SHIFT 0
514 # define RADEON_CRTC_V_DISP (0x07ff << 16)
515 # define RADEON_CRTC_V_DISP_SHIFT 16
516 #define RADEON_CRTC2_V_TOTAL_DISP 0x0308
517 # define RADEON_CRTC2_V_TOTAL (0x07ff << 0)
518 # define RADEON_CRTC2_V_TOTAL_SHIFT 0
519 # define RADEON_CRTC2_V_DISP (0x07ff << 16)
520 # define RADEON_CRTC2_V_DISP_SHIFT 16
521 #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210
522 # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
523 #define RADEON_CRTC2_CRNT_FRAME 0x0314
524 #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318
525 #define RADEON_CRTC2_STATUS 0x03fc
526 #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310
527 #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
528 #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
529 #define RADEON_CUR_CLR0 0x026c
530 #define RADEON_CUR_CLR1 0x0270
531 #define RADEON_CUR_HORZ_VERT_OFF 0x0268
532 #define RADEON_CUR_HORZ_VERT_POSN 0x0264
533 #define RADEON_CUR_OFFSET 0x0260
534 # define RADEON_CUR_LOCK (1 << 31)
535 #define RADEON_CUR2_CLR0 0x036c
536 #define RADEON_CUR2_CLR1 0x0370
537 #define RADEON_CUR2_HORZ_VERT_OFF 0x0368
538 #define RADEON_CUR2_HORZ_VERT_POSN 0x0364
539 #define RADEON_CUR2_OFFSET 0x0360
540 # define RADEON_CUR2_LOCK (1 << 31)
542 #define RADEON_DAC_CNTL 0x0058
543 # define RADEON_DAC_RANGE_CNTL (3 << 0)
544 # define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)
545 # define RADEON_DAC_RANGE_CNTL_MASK 0x03
546 # define RADEON_DAC_BLANKING (1 << 2)
547 # define RADEON_DAC_CMP_EN (1 << 3)
548 # define RADEON_DAC_CMP_OUTPUT (1 << 7)
549 # define RADEON_DAC_8BIT_EN (1 << 8)
550 # define RADEON_DAC_TVO_EN (1 << 10)
551 # define RADEON_DAC_VGA_ADR_EN (1 << 13)
552 # define RADEON_DAC_PDWN (1 << 15)
553 # define RADEON_DAC_MASK_ALL (0xff << 24)
554 #define RADEON_DAC_CNTL2 0x007c
555 # define RADEON_DAC2_TV_CLK_SEL (0 << 1)
556 # define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
557 # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
558 # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
559 # define RADEON_DAC2_CMP_EN (1 << 7)
560 # define RADEON_DAC2_CMP_OUT_R (1 << 8)
561 # define RADEON_DAC2_CMP_OUT_G (1 << 9)
562 # define RADEON_DAC2_CMP_OUT_B (1 << 10)
563 # define RADEON_DAC2_CMP_OUTPUT (1 << 11)
564 #define RADEON_DAC_EXT_CNTL 0x0280
565 # define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
566 # define RADEON_DAC2_FORCE_DATA_EN (1 << 1)
567 # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
568 # define RADEON_DAC_FORCE_DATA_EN (1 << 5)
569 # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
570 # define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)
571 # define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)
572 # define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)
573 # define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)
574 # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
575 # define RADEON_DAC_FORCE_DATA_SHIFT 8
576 #define RADEON_DAC_MACRO_CNTL 0x0d04
577 # define RADEON_DAC_PDWN_R (1 << 16)
578 # define RADEON_DAC_PDWN_G (1 << 17)
579 # define RADEON_DAC_PDWN_B (1 << 18)
580 #define RADEON_DISP_PWR_MAN 0x0d08
581 # define RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
582 # define RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4)
583 # define RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8)
584 # define RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8)
585 # define RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8)
586 # define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8)
587 # define RADEON_DISP_D3_RST (1 << 16)
588 # define RADEON_DISP_D3_REG_RST (1 << 17)
589 # define RADEON_DISP_D3_GRPH_RST (1 << 18)
590 # define RADEON_DISP_D3_SUBPIC_RST (1 << 19)
591 # define RADEON_DISP_D3_OV0_RST (1 << 20)
592 # define RADEON_DISP_D1D2_GRPH_RST (1 << 21)
593 # define RADEON_DISP_D1D2_SUBPIC_RST (1 << 22)
594 # define RADEON_DISP_D1D2_OV0_RST (1 << 23)
595 # define RADEON_DIG_TMDS_ENABLE_RST (1 << 24)
596 # define RADEON_TV_ENABLE_RST (1 << 25)
597 # define RADEON_AUTO_PWRUP_EN (1 << 26)
598 #define RADEON_TV_DAC_CNTL 0x088c
599 # define RADEON_TV_DAC_NBLANK (1 << 0)
600 # define RADEON_TV_DAC_NHOLD (1 << 1)
601 # define RADEON_TV_DAC_PEDESTAL (1 << 2)
602 # define RADEON_TV_MONITOR_DETECT_EN (1 << 4)
603 # define RADEON_TV_DAC_CMPOUT (1 << 5)
604 # define RADEON_TV_DAC_STD_MASK (3 << 8)
605 # define RADEON_TV_DAC_STD_PAL (0 << 8)
606 # define RADEON_TV_DAC_STD_NTSC (1 << 8)
607 # define RADEON_TV_DAC_STD_PS2 (2 << 8)
608 # define RADEON_TV_DAC_STD_RS343 (3 << 8)
609 # define RADEON_TV_DAC_BGSLEEP (1 << 6)
610 # define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)
611 # define RADEON_TV_DAC_BGADJ_SHIFT 16
612 # define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)
613 # define RADEON_TV_DAC_DACADJ_SHIFT 20
614 # define RADEON_TV_DAC_RDACPD (1 << 24)
615 # define RADEON_TV_DAC_GDACPD (1 << 25)
616 # define RADEON_TV_DAC_BDACPD (1 << 26)
617 # define RADEON_TV_DAC_RDACDET (1 << 29)
618 # define RADEON_TV_DAC_GDACDET (1 << 30)
619 # define RADEON_TV_DAC_BDACDET (1 << 31)
620 # define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
621 # define R420_TV_DAC_RDACPD (1 << 25)
622 # define R420_TV_DAC_GDACPD (1 << 26)
623 # define R420_TV_DAC_BDACPD (1 << 27)
624 # define R420_TV_DAC_TVENABLE (1 << 28)
625 #define RADEON_DISP_HW_DEBUG 0x0d14
626 # define RADEON_CRT2_DISP1_SEL (1 << 5)
627 #define RADEON_DISP_OUTPUT_CNTL 0x0d64
628 # define RADEON_DISP_DAC_SOURCE_MASK 0x03
629 # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
630 # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
631 # define RADEON_DISP_DAC_SOURCE_RMX 0x02
632 # define RADEON_DISP_DAC_SOURCE_LTU 0x03
633 # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
634 # define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)
635 # define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0
636 # define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
637 # define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)
638 # define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)
639 # define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)
640 # define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
641 # define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)
642 # define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)
643 # define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */
644 # define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */
645 #define RADEON_DISP_TV_OUT_CNTL 0x0d6c
646 # define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
647 # define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
648 #define RADEON_DAC_CRC_SIG 0x02cc
649 #define RADEON_DAC_DATA 0x03c9 /* VGA */
650 #define RADEON_DAC_MASK 0x03c6 /* VGA */
651 #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
652 #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
653 #define RADEON_DDA_CONFIG 0x02e0
654 #define RADEON_DDA_ON_OFF 0x02e4
655 #define RADEON_DEFAULT_OFFSET 0x16e0
656 #define RADEON_DEFAULT_PITCH 0x16e4
657 #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
658 # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
659 # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
660 #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
661 #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
662 #define RADEON_DEVICE_ID 0x0f02 /* PCI */
663 #define RADEON_DISP_MISC_CNTL 0x0d00
664 # define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
665 #define RADEON_DISP_MERGE_CNTL 0x0d60
666 # define RADEON_DISP_ALPHA_MODE_MASK 0x03
667 # define RADEON_DISP_ALPHA_MODE_KEY 0
668 # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
669 # define RADEON_DISP_ALPHA_MODE_GLOBAL 2
670 # define RADEON_DISP_RGB_OFFSET_EN (1 << 8)
671 # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
672 # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
673 # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
674 #define RADEON_DISP2_MERGE_CNTL 0x0d68
675 # define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)
676 #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
677 #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
678 #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
679 #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
680 #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
681 #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
682 #define RADEON_DP_BRUSH_BKGD_CLR 0x1478
683 #define RADEON_DP_BRUSH_FRGD_CLR 0x147c
684 #define RADEON_DP_CNTL 0x16c0
685 # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
686 # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
687 # define RADEON_DP_DST_TILE_LINEAR (0 << 3)
688 # define RADEON_DP_DST_TILE_MACRO (1 << 3)
689 # define RADEON_DP_DST_TILE_MICRO (2 << 3)
690 # define RADEON_DP_DST_TILE_BOTH (3 << 3)
691 #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
692 # define RADEON_DST_Y_MAJOR (1 << 2)
693 # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
694 # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
695 #define RADEON_DP_DATATYPE 0x16c4
696 # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
697 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
698 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
699 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
700 # define RADEON_GMC_SRC_CLIPPING (1 << 2)
701 # define RADEON_GMC_DST_CLIPPING (1 << 3)
702 # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
703 # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
704 # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
705 # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
706 # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
707 # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
708 # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
709 # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
710 # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
711 # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
712 # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
713 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
714 # define RADEON_GMC_BRUSH_NONE (15 << 4)
715 # define RADEON_GMC_DST_8BPP_CI (2 << 8)
716 # define RADEON_GMC_DST_15BPP (3 << 8)
717 # define RADEON_GMC_DST_16BPP (4 << 8)
718 # define RADEON_GMC_DST_24BPP (5 << 8)
719 # define RADEON_GMC_DST_32BPP (6 << 8)
720 # define RADEON_GMC_DST_8BPP_RGB (7 << 8)
721 # define RADEON_GMC_DST_Y8 (8 << 8)
722 # define RADEON_GMC_DST_RGB8 (9 << 8)
723 # define RADEON_GMC_DST_VYUY (11 << 8)
724 # define RADEON_GMC_DST_YVYU (12 << 8)
725 # define RADEON_GMC_DST_AYUV444 (14 << 8)
726 # define RADEON_GMC_DST_ARGB4444 (15 << 8)
727 # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
728 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
729 # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
730 # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
731 # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
732 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
733 # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
734 # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
735 # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
736 # define RADEON_GMC_CONVERSION_TEMP (1 << 15)
737 # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
738 # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
739 # define RADEON_GMC_ROP3_MASK (0xff << 16)
740 # define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
741 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
742 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
743 # define RADEON_GMC_3D_FCN_EN (1 << 27)
744 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
745 # define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
746 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
747 # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
748 # define RADEON_ROP3_ZERO 0x00000000
749 # define RADEON_ROP3_DSa 0x00880000
750 # define RADEON_ROP3_SDna 0x00440000
751 # define RADEON_ROP3_S 0x00cc0000
752 # define RADEON_ROP3_DSna 0x00220000
753 # define RADEON_ROP3_D 0x00aa0000
754 # define RADEON_ROP3_DSx 0x00660000
755 # define RADEON_ROP3_DSo 0x00ee0000
756 # define RADEON_ROP3_DSon 0x00110000
757 # define RADEON_ROP3_DSxn 0x00990000
758 # define RADEON_ROP3_Dn 0x00550000
759 # define RADEON_ROP3_SDno 0x00dd0000
760 # define RADEON_ROP3_Sn 0x00330000
761 # define RADEON_ROP3_DSno 0x00bb0000
762 # define RADEON_ROP3_DSan 0x00770000
763 # define RADEON_ROP3_ONE 0x00ff0000
764 # define RADEON_ROP3_DPa 0x00a00000
765 # define RADEON_ROP3_PDna 0x00500000
766 # define RADEON_ROP3_P 0x00f00000
767 # define RADEON_ROP3_DPna 0x000a0000
768 # define RADEON_ROP3_D 0x00aa0000
769 # define RADEON_ROP3_DPx 0x005a0000
770 # define RADEON_ROP3_DPo 0x00fa0000
771 # define RADEON_ROP3_DPon 0x00050000
772 # define RADEON_ROP3_PDxn 0x00a50000
773 # define RADEON_ROP3_PDno 0x00f50000
774 # define RADEON_ROP3_Pn 0x000f0000
775 # define RADEON_ROP3_DPno 0x00af0000
776 # define RADEON_ROP3_DPan 0x005f0000
777 #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
778 #define RADEON_DP_MIX 0x16c8
779 #define RADEON_DP_SRC_BKGD_CLR 0x15dc
780 #define RADEON_DP_SRC_FRGD_CLR 0x15d8
781 #define RADEON_DP_WRITE_MASK 0x16cc
782 #define RADEON_DST_BRES_DEC 0x1630
783 #define RADEON_DST_BRES_ERR 0x1628
784 #define RADEON_DST_BRES_INC 0x162c
785 #define RADEON_DST_BRES_LNTH 0x1634
786 #define RADEON_DST_BRES_LNTH_SUB 0x1638
787 #define RADEON_DST_HEIGHT 0x1410
788 #define RADEON_DST_HEIGHT_WIDTH 0x143c
789 #define RADEON_DST_HEIGHT_WIDTH_8 0x158c
790 #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
791 #define RADEON_DST_HEIGHT_Y 0x15a0
792 #define RADEON_DST_LINE_START 0x1600
793 #define RADEON_DST_LINE_END 0x1604
794 #define RADEON_DST_LINE_PATCOUNT 0x1608
795 # define RADEON_BRES_CNTL_SHIFT 8
796 #define RADEON_DST_OFFSET 0x1404
797 #define RADEON_DST_PITCH 0x1408
798 #define RADEON_DST_PITCH_OFFSET 0x142c
799 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
800 # define RADEON_PITCH_SHIFT 21
801 # define RADEON_DST_TILE_LINEAR (0 << 30)
802 # define RADEON_DST_TILE_MACRO (1 << 30)
803 # define RADEON_DST_TILE_MICRO (2 << 30)
804 # define RADEON_DST_TILE_BOTH (3 << 30)
805 #define RADEON_DST_WIDTH 0x140c
806 #define RADEON_DST_WIDTH_HEIGHT 0x1598
807 #define RADEON_DST_WIDTH_X 0x1588
808 #define RADEON_DST_WIDTH_X_INCY 0x159c
809 #define RADEON_DST_X 0x141c
810 #define RADEON_DST_X_SUB 0x15a4
811 #define RADEON_DST_X_Y 0x1594
812 #define RADEON_DST_Y 0x1420
813 #define RADEON_DST_Y_SUB 0x15a8
814 #define RADEON_DST_Y_X 0x1438
816 #define RADEON_FCP_CNTL 0x0910
817 # define RADEON_FCP0_SRC_PCICLK 0
818 # define RADEON_FCP0_SRC_PCLK 1
819 # define RADEON_FCP0_SRC_PCLKb 2
820 # define RADEON_FCP0_SRC_HREF 3
821 # define RADEON_FCP0_SRC_GND 4
822 # define RADEON_FCP0_SRC_HREFb 5
823 #define RADEON_FLUSH_1 0x1704
824 #define RADEON_FLUSH_2 0x1708
825 #define RADEON_FLUSH_3 0x170c
826 #define RADEON_FLUSH_4 0x1710
827 #define RADEON_FLUSH_5 0x1714
828 #define RADEON_FLUSH_6 0x1718
829 #define RADEON_FLUSH_7 0x171c
830 #define RADEON_FOG_3D_TABLE_START 0x1810
831 #define RADEON_FOG_3D_TABLE_END 0x1814
832 #define RADEON_FOG_3D_TABLE_DENSITY 0x181c
833 #define RADEON_FOG_TABLE_INDEX 0x1a14
834 #define RADEON_FOG_TABLE_DATA 0x1a18
835 #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
836 #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
837 # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
838 # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
839 # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
840 # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
841 # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
842 # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
843 # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
844 # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
845 # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
846 # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
847 # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
848 # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
849 # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
850 # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
851 # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
852 # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
853 #define RADEON_FP_GEN_CNTL 0x0284
854 # define RADEON_FP_FPON (1 << 0)
855 # define RADEON_FP_BLANK_EN (1 << 1)
856 # define RADEON_FP_TMDS_EN (1 << 2)
857 # define RADEON_FP_PANEL_FORMAT (1 << 3)
858 # define RADEON_FP_EN_TMDS (1 << 7)
859 # define RADEON_FP_DETECT_SENSE (1 << 8)
860 # define R200_FP_SOURCE_SEL_MASK (3 << 10)
861 # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
862 # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
863 # define R200_FP_SOURCE_SEL_RMX (2 << 10)
864 # define R200_FP_SOURCE_SEL_TRANS (3 << 10)
865 # define RADEON_FP_SEL_CRTC1 (0 << 13)
866 # define RADEON_FP_SEL_CRTC2 (1 << 13)
867 # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
868 # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
869 # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
870 # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
871 # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
872 # define RADEON_FP_DFP_SYNC_SEL (1 << 21)
873 # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
874 # define RADEON_FP_CRT_SYNC_SEL (1 << 23)
875 # define RADEON_FP_USE_SHADOW_EN (1 << 24)
876 # define RADEON_FP_CRT_SYNC_ALT (1 << 26)
877 #define RADEON_FP2_GEN_CNTL 0x0288
878 # define RADEON_FP2_BLANK_EN (1 << 1)
879 # define RADEON_FP2_ON (1 << 2)
880 # define RADEON_FP2_PANEL_FORMAT (1 << 3)
881 # define RADEON_FP2_DETECT_SENSE (1 << 8)
882 # define R200_FP2_SOURCE_SEL_MASK (3 << 10)
883 # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
884 # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
885 # define R200_FP2_SOURCE_SEL_RMX (2 << 10)
886 # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)
887 # define RADEON_FP2_SRC_SEL_MASK (3 << 13)
888 # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
889 # define RADEON_FP2_FP_POL (1 << 16)
890 # define RADEON_FP2_LP_POL (1 << 17)
891 # define RADEON_FP2_SCK_POL (1 << 18)
892 # define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
893 # define RADEON_FP2_PAD_FLOP_EN (1 << 22)
894 # define RADEON_FP2_CRC_EN (1 << 23)
895 # define RADEON_FP2_CRC_READ_EN (1 << 24)
896 # define RADEON_FP2_DVO_EN (1 << 25)
897 # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)
898 # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)
899 # define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)
900 # define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)
901 #define RADEON_FP_H_SYNC_STRT_WID 0x02c4
902 #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
903 #define RADEON_FP_HORZ_STRETCH 0x028c
904 #define RADEON_FP_HORZ2_STRETCH 0x038c
905 # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
906 # define RADEON_HORZ_STRETCH_RATIO_MAX 4096
907 # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
908 # define RADEON_HORZ_PANEL_SHIFT 16
909 # define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
910 # define RADEON_HORZ_STRETCH_BLEND (1 << 26)
911 # define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
912 # define RADEON_HORZ_AUTO_RATIO (1 << 27)
913 # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
914 # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
915 #define RADEON_FP_HORZ_VERT_ACTIVE 0x0278
916 #define RADEON_FP_V_SYNC_STRT_WID 0x02c8
917 #define RADEON_FP_VERT_STRETCH 0x0290
918 #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
919 #define RADEON_FP_VERT2_STRETCH 0x0390
920 # define RADEON_VERT_PANEL_SIZE (0xfff << 12)
921 # define RADEON_VERT_PANEL_SHIFT 12
922 # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
923 # define RADEON_VERT_STRETCH_RATIO_SHIFT 0
924 # define RADEON_VERT_STRETCH_RATIO_MAX 4096
925 # define RADEON_VERT_STRETCH_ENABLE (1 << 25)
926 # define RADEON_VERT_STRETCH_LINEREP (0 << 26)
927 # define RADEON_VERT_STRETCH_BLEND (1 << 26)
928 # define RADEON_VERT_AUTO_RATIO_EN (1 << 27)
929 # define RADEON_VERT_AUTO_RATIO_INC (1 << 31)
930 # define RADEON_VERT_STRETCH_RESERVED 0x71000000
931 #define RS400_FP_2ND_GEN_CNTL 0x0384
932 # define RS400_FP_2ND_ON (1 << 0)
933 # define RS400_FP_2ND_BLANK_EN (1 << 1)
934 # define RS400_TMDS_2ND_EN (1 << 2)
935 # define RS400_PANEL_FORMAT_2ND (1 << 3)
936 # define RS400_FP_2ND_EN_TMDS (1 << 7)
937 # define RS400_FP_2ND_DETECT_SENSE (1 << 8)
938 # define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)
939 # define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)
940 # define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)
941 # define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)
942 # define RS400_FP_2ND_DETECT_EN (1 << 12)
943 # define RS400_HPD_2ND_SEL (1 << 13)
944 #define RS400_FP2_2_GEN_CNTL 0x0388
945 # define RS400_FP2_2_BLANK_EN (1 << 1)
946 # define RS400_FP2_2_ON (1 << 2)
947 # define RS400_FP2_2_PANEL_FORMAT (1 << 3)
948 # define RS400_FP2_2_DETECT_SENSE (1 << 8)
949 # define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)
950 # define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)
951 # define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)
952 # define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)
953 # define RS400_FP2_2_DVO2_EN (1 << 25)
954 #define RS400_TMDS2_CNTL 0x0394
955 #define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4
956 # define RS400_TMDS2_PLLEN (1 << 0)
957 # define RS400_TMDS2_PLLRST (1 << 1)
959 #define RADEON_GEN_INT_CNTL 0x0040
960 #define RADEON_GEN_INT_STATUS 0x0044
961 # define RADEON_VSYNC_INT_AK (1 << 2)
962 # define RADEON_VSYNC_INT (1 << 2)
963 # define RADEON_VSYNC2_INT_AK (1 << 6)
964 # define RADEON_VSYNC2_INT (1 << 6)
965 #define RADEON_GENENB 0x03c3 /* VGA */
966 #define RADEON_GENFC_RD 0x03ca /* VGA */
967 #define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */
968 #define RADEON_GENMO_RD 0x03cc /* VGA */
969 #define RADEON_GENMO_WT 0x03c2 /* VGA */
970 #define RADEON_GENS0 0x03c2 /* VGA */
971 #define RADEON_GENS1 0x03da /* VGA, 0x03ba */
972 #define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */
973 #define RADEON_GPIO_MONIDB 0x006c
974 #define RADEON_GPIO_CRT2_DDC 0x006c
975 #define RADEON_GPIO_DVI_DDC 0x0064
976 #define RADEON_GPIO_VGA_DDC 0x0060
977 # define RADEON_GPIO_A_0 (1 << 0)
978 # define RADEON_GPIO_A_1 (1 << 1)
979 # define RADEON_GPIO_Y_0 (1 << 8)
980 # define RADEON_GPIO_Y_1 (1 << 9)
981 # define RADEON_GPIO_Y_SHIFT_0 8
982 # define RADEON_GPIO_Y_SHIFT_1 9
983 # define RADEON_GPIO_EN_0 (1 << 16)
984 # define RADEON_GPIO_EN_1 (1 << 17)
985 # define RADEON_GPIO_MASK_0 (1 << 24) /*??*/
986 # define RADEON_GPIO_MASK_1 (1 << 25) /*??*/
987 #define RADEON_GRPH8_DATA 0x03cf /* VGA */
988 #define RADEON_GRPH8_IDX 0x03ce /* VGA */
989 #define RADEON_GUI_SCRATCH_REG0 0x15e0
990 #define RADEON_GUI_SCRATCH_REG1 0x15e4
991 #define RADEON_GUI_SCRATCH_REG2 0x15e8
992 #define RADEON_GUI_SCRATCH_REG3 0x15ec
993 #define RADEON_GUI_SCRATCH_REG4 0x15f0
994 #define RADEON_GUI_SCRATCH_REG5 0x15f4
996 #define RADEON_HEADER 0x0f0e /* PCI */
997 #define RADEON_HOST_DATA0 0x17c0
998 #define RADEON_HOST_DATA1 0x17c4
999 #define RADEON_HOST_DATA2 0x17c8
1000 #define RADEON_HOST_DATA3 0x17cc
1001 #define RADEON_HOST_DATA4 0x17d0
1002 #define RADEON_HOST_DATA5 0x17d4
1003 #define RADEON_HOST_DATA6 0x17d8
1004 #define RADEON_HOST_DATA7 0x17dc
1005 #define RADEON_HOST_DATA_LAST 0x17e0
1006 #define RADEON_HOST_PATH_CNTL 0x0130
1007 # define RADEON_HDP_SOFT_RESET (1 << 26)
1008 # define RADEON_HDP_APER_CNTL (1 << 23)
1009 #define RADEON_HTOTAL_CNTL 0x0009 /* PLL */
1010 # define RADEON_HTOT_CNTL_VGA_EN (1 << 28)
1011 #define RADEON_HTOTAL2_CNTL 0x002e /* PLL */
1013 /* Multimedia I2C bus */
1014 #define RADEON_I2C_CNTL_0 0x0090
1015 #define RADEON_I2C_DONE (1<<0)
1016 #define RADEON_I2C_NACK (1<<1)
1017 #define RADEON_I2C_HALT (1<<2)
1018 #define RADEON_I2C_SOFT_RST (1<<5)
1019 #define RADEON_I2C_DRIVE_EN (1<<6)
1020 #define RADEON_I2C_DRIVE_SEL (1<<7)
1021 #define RADEON_I2C_START (1<<8)
1022 #define RADEON_I2C_STOP (1<<9)
1023 #define RADEON_I2C_RECEIVE (1<<10)
1024 #define RADEON_I2C_ABORT (1<<11)
1025 #define RADEON_I2C_GO (1<<12)
1026 #define RADEON_I2C_CNTL_1 0x0094
1027 #define RADEON_I2C_SEL (1<<16)
1028 #define RADEON_I2C_EN (1<<17)
1029 #define RADEON_I2C_DATA 0x0098
1031 #define RADEON_DVI_I2C_CNTL_0 0x02e0
1032 #define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */
1033 #define RADEON_DVI_I2C_DATA 0x02e8
1035 #define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */
1036 #define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */
1037 #define RADEON_IO_BASE 0x0f14 /* PCI */
1039 #define RADEON_LATENCY 0x0f0d /* PCI */
1040 #define RADEON_LEAD_BRES_DEC 0x1608
1041 #define RADEON_LEAD_BRES_LNTH 0x161c
1042 #define RADEON_LEAD_BRES_LNTH_SUB 0x1624
1043 #define RADEON_LVDS_GEN_CNTL 0x02d0
1044 # define RADEON_LVDS_ON (1 << 0)
1045 # define RADEON_LVDS_DISPLAY_DIS (1 << 1)
1046 # define RADEON_LVDS_PANEL_TYPE (1 << 2)
1047 # define RADEON_LVDS_PANEL_FORMAT (1 << 3)
1048 # define RADEON_LVDS_NO_FM (0 << 4)
1049 # define RADEON_LVDS_2_GREY (1 << 4)
1050 # define RADEON_LVDS_4_GREY (2 << 4)
1051 # define RADEON_LVDS_RST_FM (1 << 6)
1052 # define RADEON_LVDS_EN (1 << 7)
1053 # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
1054 # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
1055 # define RADEON_LVDS_BL_MOD_EN (1 << 16)
1056 # define RADEON_LVDS_BL_CLK_SEL (1 << 17)
1057 # define RADEON_LVDS_DIGON (1 << 18)
1058 # define RADEON_LVDS_BLON (1 << 19)
1059 # define RADEON_LVDS_FP_POL_LOW (1 << 20)
1060 # define RADEON_LVDS_LP_POL_LOW (1 << 21)
1061 # define RADEON_LVDS_DTM_POL_LOW (1 << 22)
1062 # define RADEON_LVDS_SEL_CRTC2 (1 << 23)
1063 # define RADEON_LVDS_FPDI_EN (1 << 27)
1064 # define RADEON_LVDS_HSYNC_DELAY_SHIFT 28
1065 #define RADEON_LVDS_PLL_CNTL 0x02d4
1066 # define RADEON_HSYNC_DELAY_SHIFT 28
1067 # define RADEON_HSYNC_DELAY_MASK (0xf << 28)
1068 # define RADEON_LVDS_PLL_EN (1 << 16)
1069 # define RADEON_LVDS_PLL_RESET (1 << 17)
1070 # define R300_LVDS_SRC_SEL_MASK (3 << 18)
1071 # define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)
1072 # define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)
1073 # define R300_LVDS_SRC_SEL_RMX (2 << 18)
1074 #define RADEON_LVDS_SS_GEN_CNTL 0x02ec
1075 # define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 16
1076 # define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 20
1078 #define RADEON_MAX_LATENCY 0x0f3f /* PCI */
1079 #define RADEON_MC_AGP_LOCATION 0x014c
1080 #define RADEON_MC_FB_LOCATION 0x0148
1081 #define RADEON_DISPLAY_BASE_ADDR 0x23c
1082 #define RADEON_DISPLAY2_BASE_ADDR 0x33c
1083 #define RADEON_OV0_BASE_ADDR 0x43c
1084 #define RADEON_NB_TOM 0x15c
1085 #define R300_MC_INIT_MISC_LAT_TIMER 0x180
1086 #define RADEON_MCLK_CNTL 0x0012 /* PLL */
1087 # define RADEON_FORCEON_MCLKA (1 << 16)
1088 # define RADEON_FORCEON_MCLKB (1 << 17)
1089 # define RADEON_FORCEON_YCLKA (1 << 18)
1090 # define RADEON_FORCEON_YCLKB (1 << 19)
1091 # define RADEON_FORCEON_MC (1 << 20)
1092 # define RADEON_FORCEON_AIC (1 << 21)
1093 # define R300_DISABLE_MC_MCLKA (1 << 21)
1094 # define R300_DISABLE_MC_MCLKB (1 << 21)
1095 #define RADEON_MCLK_MISC 0x001f /* PLL */
1096 # define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)
1097 # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
1098 # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
1099 # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
1100 #define RADEON_LCD_GPIO_MASK 0x01a0
1101 #define RADEON_GPIOPAD_EN 0x01a0
1102 #define RADEON_LCD_GPIO_Y_REG 0x01a4
1103 #define RADEON_MDGPIO_A_REG 0x01ac
1104 #define RADEON_MDGPIO_EN_REG 0x01b0
1105 #define RADEON_MDGPIO_MASK 0x0198
1106 #define RADEON_GPIOPAD_MASK 0x0198
1107 #define RADEON_GPIOPAD_A 0x019c
1108 #define RADEON_MDGPIO_Y_REG 0x01b4
1109 #define RADEON_MEM_ADDR_CONFIG 0x0148
1110 #define RADEON_MEM_BASE 0x0f10 /* PCI */
1111 #define RADEON_MEM_CNTL 0x0140
1112 # define RADEON_MEM_NUM_CHANNELS_MASK 0x01
1113 # define RADEON_MEM_USE_B_CH_ONLY (1 << 1)
1114 # define RV100_HALF_MODE (1 << 3)
1115 # define R300_MEM_NUM_CHANNELS_MASK 0x03
1116 # define R300_MEM_USE_CD_CH_ONLY (1 << 2)
1117 #define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */
1118 #define RADEON_MEM_INIT_LAT_TIMER 0x0154
1119 #define RADEON_MEM_INTF_CNTL 0x014c
1120 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
1121 # define RADEON_SDRAM_MODE_MASK 0xffff0000
1122 # define RADEON_B3MEM_RESET_MASK 0x6fffffff
1123 # define RADEON_MEM_CFG_TYPE_DDR (1 << 30)
1124 #define RADEON_MEM_STR_CNTL 0x0150
1125 # define RADEON_MEM_PWRUP_COMPL_A (1 << 0)
1126 # define RADEON_MEM_PWRUP_COMPL_B (1 << 1)
1127 # define R300_MEM_PWRUP_COMPL_C (1 << 2)
1128 # define R300_MEM_PWRUP_COMPL_D (1 << 3)
1129 # define RADEON_MEM_PWRUP_COMPLETE 0x03
1130 # define R300_MEM_PWRUP_COMPLETE 0x0f
1131 #define RADEON_MC_STATUS 0x0150
1132 # define RADEON_MC_IDLE (1 << 2)
1133 # define R300_MC_IDLE (1 << 4)
1134 #define RADEON_MEM_VGA_RP_SEL 0x003c
1135 #define RADEON_MEM_VGA_WP_SEL 0x0038
1136 #define RADEON_MIN_GRANT 0x0f3e /* PCI */
1137 #define RADEON_MM_DATA 0x0004
1138 #define RADEON_MM_INDEX 0x0000
1139 #define RADEON_MPLL_CNTL 0x000e /* PLL */
1140 #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
1141 #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
1142 #define RADEON_SEPROM_CNTL1 0x01c0
1143 # define RADEON_SCK_PRESCALE_SHIFT 24
1144 # define RADEON_SCK_PRESCALE_MASK (0xff << 24)
1145 #define R300_MC_IND_INDEX 0x01f8
1146 # define R300_MC_IND_ADDR_MASK 0x3f
1147 # define R300_MC_IND_WR_EN (1 << 8)
1148 #define R300_MC_IND_DATA 0x01fc
1149 #define R300_MC_READ_CNTL_AB 0x017c
1150 # define R300_MEM_RBS_POSITION_A_MASK 0x03
1151 #define R300_MC_READ_CNTL_CD_mcind 0x24
1152 # define R300_MEM_RBS_POSITION_C_MASK 0x03
1154 #define RADEON_N_VIF_COUNT 0x0248
1156 #define RADEON_OV0_AUTO_FLIP_CNTL 0x0470
1157 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007
1158 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008
1159 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010
1160 # define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
1161 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040
1162 # define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300
1163 # define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000
1164 # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000
1165 # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000
1166 # define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000
1168 #define RADEON_OV0_COLOUR_CNTL 0x04E0
1169 #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474
1170 #define RADEON_OV0_EXCLUSIVE_HORZ 0x0408
1171 # define RADEON_EXCL_HORZ_START_MASK 0x000000ff
1172 # define RADEON_EXCL_HORZ_END_MASK 0x0000ff00
1173 # define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
1174 # define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
1175 #define RADEON_OV0_EXCLUSIVE_VERT 0x040C
1176 # define RADEON_EXCL_VERT_START_MASK 0x000003ff
1177 # define RADEON_EXCL_VERT_END_MASK 0x03ff0000
1178 #define RADEON_OV0_FILTER_CNTL 0x04A0
1179 # define RADEON_FILTER_PROGRAMMABLE_COEF 0x0
1180 # define RADEON_FILTER_HC_COEF_HORZ_Y 0x1
1181 # define RADEON_FILTER_HC_COEF_HORZ_UV 0x2
1182 # define RADEON_FILTER_HC_COEF_VERT_Y 0x4
1183 # define RADEON_FILTER_HC_COEF_VERT_UV 0x8
1184 # define RADEON_FILTER_HARDCODED_COEF 0xf
1185 # define RADEON_FILTER_COEF_MASK 0xf
1187 #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0
1188 #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4
1189 #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8
1190 #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC
1191 #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0
1192 #define RADEON_OV0_FLAG_CNTL 0x04DC
1193 #define RADEON_OV0_GAMMA_000_00F 0x0d40
1194 #define RADEON_OV0_GAMMA_010_01F 0x0d44
1195 #define RADEON_OV0_GAMMA_020_03F 0x0d48
1196 #define RADEON_OV0_GAMMA_040_07F 0x0d4c
1197 #define RADEON_OV0_GAMMA_080_0BF 0x0e00
1198 #define RADEON_OV0_GAMMA_0C0_0FF 0x0e04
1199 #define RADEON_OV0_GAMMA_100_13F 0x0e08
1200 #define RADEON_OV0_GAMMA_140_17F 0x0e0c
1201 #define RADEON_OV0_GAMMA_180_1BF 0x0e10
1202 #define RADEON_OV0_GAMMA_1C0_1FF 0x0e14
1203 #define RADEON_OV0_GAMMA_200_23F 0x0e18
1204 #define RADEON_OV0_GAMMA_240_27F 0x0e1c
1205 #define RADEON_OV0_GAMMA_280_2BF 0x0e20
1206 #define RADEON_OV0_GAMMA_2C0_2FF 0x0e24
1207 #define RADEON_OV0_GAMMA_300_33F 0x0e28
1208 #define RADEON_OV0_GAMMA_340_37F 0x0e2c
1209 #define RADEON_OV0_GAMMA_380_3BF 0x0d50
1210 #define RADEON_OV0_GAMMA_3C0_3FF 0x0d54
1211 #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC
1212 #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0
1213 #define RADEON_OV0_H_INC 0x0480
1214 #define RADEON_OV0_KEY_CNTL 0x04F4
1215 # define RADEON_VIDEO_KEY_FN_MASK 0x00000003L
1216 # define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L
1217 # define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L
1218 # define RADEON_VIDEO_KEY_FN_EQ 0x00000002L
1219 # define RADEON_VIDEO_KEY_FN_NE 0x00000003L
1220 # define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L
1221 # define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
1222 # define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L
1223 # define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L
1224 # define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L
1225 # define RADEON_CMP_MIX_MASK 0x00000100L
1226 # define RADEON_CMP_MIX_OR 0x00000000L
1227 # define RADEON_CMP_MIX_AND 0x00000100L
1228 #define RADEON_OV0_LIN_TRANS_A 0x0d20
1229 #define RADEON_OV0_LIN_TRANS_B 0x0d24
1230 #define RADEON_OV0_LIN_TRANS_C 0x0d28
1231 #define RADEON_OV0_LIN_TRANS_D 0x0d2c
1232 #define RADEON_OV0_LIN_TRANS_E 0x0d30
1233 #define RADEON_OV0_LIN_TRANS_F 0x0d34
1234 #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430
1235 # define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
1236 # define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L
1237 #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488
1238 #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428
1239 # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
1240 # define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
1241 #define RADEON_OV0_P1_X_START_END 0x0494
1242 #define RADEON_OV0_P2_X_START_END 0x0498
1243 #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434
1244 # define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
1245 # define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L
1246 #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C
1247 #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C
1248 #define RADEON_OV0_P3_X_START_END 0x049C
1249 #define RADEON_OV0_REG_LOAD_CNTL 0x0410
1250 # define RADEON_REG_LD_CTL_LOCK 0x00000001L
1251 # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
1252 # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
1253 # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L
1254 # define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L
1255 #define RADEON_OV0_SCALE_CNTL 0x0420
1256 # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L
1257 # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L
1258 # define RADEON_SCALER_SIGNED_UV 0x00000010L
1259 # define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L
1260 # define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
1261 # define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L
1262 # define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L
1263 # define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L
1264 # define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
1265 # define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L
1266 # define RADEON_SCALER_SOURCE_15BPP 0x00000300L
1267 # define RADEON_SCALER_SOURCE_16BPP 0x00000400L
1268 # define RADEON_SCALER_SOURCE_32BPP 0x00000600L
1269 # define RADEON_SCALER_SOURCE_YUV9 0x00000900L
1270 # define RADEON_SCALER_SOURCE_YUV12 0x00000A00L
1271 # define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L
1272 # define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L
1273 # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
1274 # define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L
1275 # define RADEON_SCALER_CRTC_SEL 0x00004000L
1276 # define RADEON_SCALER_SMART_SWITCH 0x00008000L
1277 # define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L
1278 # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L
1279 # define RADEON_SCALER_DIS_LIMIT 0x08000000L
1280 # define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L
1281 # define RADEON_SCALER_INT_EMU 0x20000000L
1282 # define RADEON_SCALER_ENABLE 0x40000000L
1283 # define RADEON_SCALER_SOFT_RESET 0x80000000L
1284 #define RADEON_OV0_STEP_BY 0x0484
1285 #define RADEON_OV0_TEST 0x04F8
1286 #define RADEON_OV0_V_INC 0x0424
1287 #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460
1288 #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464
1289 #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440
1290 # define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L
1291 # define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L
1292 # define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
1293 # define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
1294 #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444
1295 # define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L
1296 # define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L
1297 # define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
1298 # define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
1299 #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448
1300 # define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L
1301 # define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L
1302 # define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
1303 # define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
1304 #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C
1305 #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450
1306 #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454
1307 #define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8
1308 #define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4
1309 #define RADEON_OV0_Y_X_START 0x0400
1310 #define RADEON_OV0_Y_X_END 0x0404
1311 #define RADEON_OV1_Y_X_START 0x0600
1312 #define RADEON_OV1_Y_X_END 0x0604
1313 #define RADEON_OVR_CLR 0x0230
1314 #define RADEON_OVR_WID_LEFT_RIGHT 0x0234
1315 #define RADEON_OVR_WID_TOP_BOTTOM 0x0238
1317 /* first capture unit */
1319 #define RADEON_CAP0_BUF0_OFFSET 0x0920
1320 #define RADEON_CAP0_BUF1_OFFSET 0x0924
1321 #define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928
1322 #define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C
1324 #define RADEON_CAP0_BUF_PITCH 0x0930
1325 #define RADEON_CAP0_V_WINDOW 0x0934
1326 #define RADEON_CAP0_H_WINDOW 0x0938
1327 #define RADEON_CAP0_VBI0_OFFSET 0x093C
1328 #define RADEON_CAP0_VBI1_OFFSET 0x0940
1329 #define RADEON_CAP0_VBI_V_WINDOW 0x0944
1330 #define RADEON_CAP0_VBI_H_WINDOW 0x0948
1331 #define RADEON_CAP0_PORT_MODE_CNTL 0x094C
1332 #define RADEON_CAP0_TRIG_CNTL 0x0950
1333 #define RADEON_CAP0_DEBUG 0x0954
1334 #define RADEON_CAP0_CONFIG 0x0958
1335 # define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001
1336 # define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002
1337 # define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004
1338 # define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008
1339 # define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010
1340 # define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020
1341 # define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
1342 # define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080
1343 # define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100
1344 # define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200
1345 # define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400
1346 # define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800
1347 # define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000
1348 # define RADEON_CAP0_CONFIG_VBI_EN 0x00002000
1349 # define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000
1350 # define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
1351 # define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000
1352 # define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000
1353 # define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
1354 # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000
1355 # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000
1356 # define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000
1357 # define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000
1358 # define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000
1359 # define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000
1360 # define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000
1361 # define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000
1362 # define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000
1363 # define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000
1364 # define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000
1365 # define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000
1366 # define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000
1367 # define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000
1368 #define RADEON_CAP0_ANC_ODD_OFFSET 0x095C
1369 #define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960
1370 #define RADEON_CAP0_ANC_H_WINDOW 0x0964
1371 #define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968
1372 #define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C
1373 #define RADEON_CAP0_BUF_STATUS 0x0970
1374 /* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */
1375 /* #define RADEON_CAP0_XSHARPNESS 0x097C */
1376 #define RADEON_CAP0_VBI2_OFFSET 0x0980
1377 #define RADEON_CAP0_VBI3_OFFSET 0x0984
1378 #define RADEON_CAP0_ANC2_OFFSET 0x0988
1379 #define RADEON_CAP0_ANC3_OFFSET 0x098C
1380 #define RADEON_VID_BUFFER_CONTROL 0x0900
1382 /* second capture unit */
1384 #define RADEON_CAP1_BUF0_OFFSET 0x0990
1385 #define RADEON_CAP1_BUF1_OFFSET 0x0994
1386 #define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998
1387 #define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C
1389 #define RADEON_CAP1_BUF_PITCH 0x09A0
1390 #define RADEON_CAP1_V_WINDOW 0x09A4
1391 #define RADEON_CAP1_H_WINDOW 0x09A8
1392 #define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC
1393 #define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0
1394 #define RADEON_CAP1_VBI_V_WINDOW 0x09B4
1395 #define RADEON_CAP1_VBI_H_WINDOW 0x09B8
1396 #define RADEON_CAP1_PORT_MODE_CNTL 0x09BC
1397 #define RADEON_CAP1_TRIG_CNTL 0x09C0
1398 #define RADEON_CAP1_DEBUG 0x09C4
1399 #define RADEON_CAP1_CONFIG 0x09C8
1400 #define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC
1401 #define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0
1402 #define RADEON_CAP1_ANC_H_WINDOW 0x09D4
1403 #define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8
1404 #define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC
1405 #define RADEON_CAP1_BUF_STATUS 0x09E0
1406 #define RADEON_CAP1_DWNSC_XRATIO 0x09E8
1407 #define RADEON_CAP1_XSHARPNESS 0x09EC
1409 /* misc multimedia registers */
1411 #define RADEON_IDCT_RUNS 0x1F80
1412 #define RADEON_IDCT_LEVELS 0x1F84
1413 #define RADEON_IDCT_CONTROL 0x1FBC
1414 #define RADEON_IDCT_AUTH_CONTROL 0x1F88
1415 #define RADEON_IDCT_AUTH 0x1F8C
1417 #define RADEON_P2PLL_CNTL 0x002a /* P2PLL */
1418 # define RADEON_P2PLL_RESET (1 << 0)
1419 # define RADEON_P2PLL_SLEEP (1 << 1)
1420 # define RADEON_P2PLL_PVG_MASK (7 << 11)
1421 # define RADEON_P2PLL_PVG_SHIFT 11
1422 # define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
1423 # define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
1424 # define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
1425 #define RADEON_P2PLL_DIV_0 0x002c
1426 # define RADEON_P2PLL_FB0_DIV_MASK 0x07ff
1427 # define RADEON_P2PLL_POST0_DIV_MASK 0x00070000
1428 #define RADEON_P2PLL_REF_DIV 0x002B /* PLL */
1429 # define RADEON_P2PLL_REF_DIV_MASK 0x03ff
1430 # define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
1431 # define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
1432 # define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
1433 # define R300_PPLL_REF_DIV_ACC_SHIFT 18
1434 #define RADEON_PALETTE_DATA 0x00b4
1435 #define RADEON_PALETTE_30_DATA 0x00b8
1436 #define RADEON_PALETTE_INDEX 0x00b0
1437 #define RADEON_PCI_GART_PAGE 0x017c
1438 #define RADEON_PIXCLKS_CNTL 0x002d
1439 # define RADEON_PIX2CLK_SRC_SEL_MASK 0x03
1440 # define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00
1441 # define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
1442 # define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02
1443 # define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
1444 # define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)
1445 # define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)
1446 # define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)
1447 # define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
1448 # define R300_DVOCLK_ALWAYS_ONb (1 << 10)
1449 # define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)
1450 # define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)
1451 # define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)
1452 # define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
1453 # define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
1454 # define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
1455 # define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
1456 # define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
1457 # define R300_P2G2CLK_ALWAYS_ONb (1 << 18)
1458 # define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
1459 # define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
1460 #define RADEON_PLANE_3D_MASK_C 0x1d44
1461 #define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
1462 # define RADEON_PLL_MASK_READ_B (1 << 9)
1463 #define RADEON_PMI_CAP_ID 0x0f5c /* PCI */
1464 #define RADEON_PMI_DATA 0x0f63 /* PCI */
1465 #define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
1466 #define RADEON_PMI_PMC_REG 0x0f5e /* PCI */
1467 #define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */
1468 #define RADEON_PMI_REGISTER 0x0f5c /* PCI */
1469 #define RADEON_PPLL_CNTL 0x0002 /* PLL */
1470 # define RADEON_PPLL_RESET (1 << 0)
1471 # define RADEON_PPLL_SLEEP (1 << 1)
1472 # define RADEON_PPLL_PVG_MASK (7 << 11)
1473 # define RADEON_PPLL_PVG_SHIFT 11
1474 # define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)
1475 # define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
1476 # define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
1477 #define RADEON_PPLL_DIV_0 0x0004 /* PLL */
1478 #define RADEON_PPLL_DIV_1 0x0005 /* PLL */
1479 #define RADEON_PPLL_DIV_2 0x0006 /* PLL */
1480 #define RADEON_PPLL_DIV_3 0x0007 /* PLL */
1481 # define RADEON_PPLL_FB3_DIV_MASK 0x07ff
1482 # define RADEON_PPLL_POST3_DIV_MASK 0x00070000
1483 #define RADEON_PPLL_REF_DIV 0x0003 /* PLL */
1484 # define RADEON_PPLL_REF_DIV_MASK 0x03ff
1485 # define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
1486 # define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
1487 #define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
1489 #define RADEON_RBBM_GUICNTL 0x172c
1490 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
1491 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
1492 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
1493 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
1494 #define RADEON_RBBM_SOFT_RESET 0x00f0
1495 # define RADEON_SOFT_RESET_CP (1 << 0)
1496 # define RADEON_SOFT_RESET_HI (1 << 1)
1497 # define RADEON_SOFT_RESET_SE (1 << 2)
1498 # define RADEON_SOFT_RESET_RE (1 << 3)
1499 # define RADEON_SOFT_RESET_PP (1 << 4)
1500 # define RADEON_SOFT_RESET_E2 (1 << 5)
1501 # define RADEON_SOFT_RESET_RB (1 << 6)
1502 # define RADEON_SOFT_RESET_HDP (1 << 7)
1503 #define RADEON_RBBM_STATUS 0x0e40
1504 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
1505 # define RADEON_RBBM_ACTIVE (1 << 31)
1506 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
1507 # define RADEON_RB2D_DC_FLUSH (3 << 0)
1508 # define RADEON_RB2D_DC_FREE (3 << 2)
1509 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
1510 # define RADEON_RB2D_DC_BUSY (1 << 31)
1511 #define RADEON_RB2D_DSTCACHE_MODE 0x3428
1512 #define RADEON_DSTCACHE_CTLSTAT 0x1714
1514 #define RADEON_RB3D_ZCACHE_MODE 0x3250
1515 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
1516 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
1517 #define RADEON_RB3D_DSTCACHE_MODE 0x3258
1518 # define RADEON_RB3D_DC_CACHE_ENABLE (0)
1519 # define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)
1520 # define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)
1521 # define RADEON_RB3D_DC_CACHE_DISABLE (3)
1522 # define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)
1523 # define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)
1524 # define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)
1525 # define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)
1526 # define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)
1527 # define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)
1528 # define RADEON_RB3D_DC_FORCE_RMW (1 << 16)
1529 # define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)
1530 # define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)
1532 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C
1533 # define RADEON_RB3D_DC_FLUSH (3 << 0)
1534 # define RADEON_RB3D_DC_FREE (3 << 2)
1535 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
1536 # define RADEON_RB3D_DC_BUSY (1 << 31)
1538 #define RADEON_REG_BASE 0x0f18 /* PCI */
1539 #define RADEON_REGPROG_INF 0x0f09 /* PCI */
1540 #define RADEON_REVISION_ID 0x0f08 /* PCI */
1542 #define RADEON_SC_BOTTOM 0x164c
1543 #define RADEON_SC_BOTTOM_RIGHT 0x16f0
1544 #define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c
1545 #define RADEON_SC_LEFT 0x1640
1546 #define RADEON_SC_RIGHT 0x1644
1547 #define RADEON_SC_TOP 0x1648
1548 #define RADEON_SC_TOP_LEFT 0x16ec
1549 #define RADEON_SC_TOP_LEFT_C 0x1c88
1550 # define RADEON_SC_SIGN_MASK_LO 0x8000
1551 # define RADEON_SC_SIGN_MASK_HI 0x80000000
1552 #define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */
1553 # define RADEON_M_SPLL_REF_DIV_SHIFT 0
1554 # define RADEON_M_SPLL_REF_DIV_MASK 0xff
1555 # define RADEON_MPLL_FB_DIV_SHIFT 8
1556 # define RADEON_MPLL_FB_DIV_MASK 0xff
1557 # define RADEON_SPLL_FB_DIV_SHIFT 16
1558 # define RADEON_SPLL_FB_DIV_MASK 0xff
1559 #define RADEON_SCLK_CNTL 0x000d /* PLL */
1560 # define RADEON_SCLK_SRC_SEL_MASK 0x0007
1561 # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
1562 # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
1563 # define RADEON_SCLK_FORCEON_MASK 0xffff8000
1564 # define RADEON_SCLK_FORCE_DISP2 (1<<15)
1565 # define RADEON_SCLK_FORCE_CP (1<<16)
1566 # define RADEON_SCLK_FORCE_HDP (1<<17)
1567 # define RADEON_SCLK_FORCE_DISP1 (1<<18)
1568 # define RADEON_SCLK_FORCE_TOP (1<<19)
1569 # define RADEON_SCLK_FORCE_E2 (1<<20)
1570 # define RADEON_SCLK_FORCE_SE (1<<21)
1571 # define RADEON_SCLK_FORCE_IDCT (1<<22)
1572 # define RADEON_SCLK_FORCE_VIP (1<<23)
1573 # define RADEON_SCLK_FORCE_RE (1<<24)
1574 # define RADEON_SCLK_FORCE_PB (1<<25)
1575 # define RADEON_SCLK_FORCE_TAM (1<<26)
1576 # define RADEON_SCLK_FORCE_TDM (1<<27)
1577 # define RADEON_SCLK_FORCE_RB (1<<28)
1578 # define RADEON_SCLK_FORCE_TV_SCLK (1<<29)
1579 # define RADEON_SCLK_FORCE_SUBPIC (1<<30)
1580 # define RADEON_SCLK_FORCE_OV0 (1<<31)
1581 # define R300_SCLK_FORCE_VAP (1<<21)
1582 # define R300_SCLK_FORCE_SR (1<<25)
1583 # define R300_SCLK_FORCE_PX (1<<26)
1584 # define R300_SCLK_FORCE_TX (1<<27)
1585 # define R300_SCLK_FORCE_US (1<<28)
1586 # define R300_SCLK_FORCE_SU (1<<30)
1587 #define R300_SCLK_CNTL2 0x1e /* PLL */
1588 # define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)
1589 # define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)
1590 # define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)
1591 # define R300_SCLK_FORCE_TCL (1<<13)
1592 # define R300_SCLK_FORCE_CBA (1<<14)
1593 # define R300_SCLK_FORCE_GA (1<<15)
1594 #define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */
1595 # define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
1596 # define RADEON_SCLK_MORE_FORCEON 0x0700
1597 #define RADEON_SDRAM_MODE_REG 0x0158
1598 #define RADEON_SEQ8_DATA 0x03c5 /* VGA */
1599 #define RADEON_SEQ8_IDX 0x03c4 /* VGA */
1600 #define RADEON_SNAPSHOT_F_COUNT 0x0244
1601 #define RADEON_SNAPSHOT_VH_COUNTS 0x0240
1602 #define RADEON_SNAPSHOT_VIF_COUNT 0x024c
1603 #define RADEON_SRC_OFFSET 0x15ac
1604 #define RADEON_SRC_PITCH 0x15b0
1605 #define RADEON_SRC_PITCH_OFFSET 0x1428
1606 #define RADEON_SRC_SC_BOTTOM 0x165c
1607 #define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4
1608 #define RADEON_SRC_SC_RIGHT 0x1654
1609 #define RADEON_SRC_X 0x1414
1610 #define RADEON_SRC_X_Y 0x1590
1611 #define RADEON_SRC_Y 0x1418
1612 #define RADEON_SRC_Y_X 0x1434
1613 #define RADEON_STATUS 0x0f06 /* PCI */
1614 #define RADEON_SUBPIC_CNTL 0x0540 /* ? */
1615 #define RADEON_SUB_CLASS 0x0f0a /* PCI */
1616 #define RADEON_SURFACE_CNTL 0x0b00
1617 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
1618 # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
1619 # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
1620 # define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
1621 # define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
1622 #define RADEON_SURFACE0_INFO 0x0b0c
1623 # define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
1624 # define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)
1625 # define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)
1626 # define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)
1627 # define R200_SURF_TILE_NONE (0 << 16)
1628 # define R200_SURF_TILE_COLOR_MACRO (1 << 16)
1629 # define R200_SURF_TILE_COLOR_MICRO (2 << 16)
1630 # define R200_SURF_TILE_COLOR_BOTH (3 << 16)
1631 # define R200_SURF_TILE_DEPTH_32BPP (4 << 16)
1632 # define R200_SURF_TILE_DEPTH_16BPP (5 << 16)
1633 # define R300_SURF_TILE_NONE (0 << 16)
1634 # define R300_SURF_TILE_COLOR_MACRO (1 << 16)
1635 # define R300_SURF_TILE_DEPTH_32BPP (2 << 16)
1636 # define RADEON_SURF_AP0_SWP_16BPP (1 << 20)
1637 # define RADEON_SURF_AP0_SWP_32BPP (1 << 21)
1638 # define RADEON_SURF_AP1_SWP_16BPP (1 << 22)
1639 # define RADEON_SURF_AP1_SWP_32BPP (1 << 23)
1640 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
1641 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
1642 #define RADEON_SURFACE1_INFO 0x0b1c
1643 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
1644 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
1645 #define RADEON_SURFACE2_INFO 0x0b2c
1646 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
1647 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
1648 #define RADEON_SURFACE3_INFO 0x0b3c
1649 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
1650 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
1651 #define RADEON_SURFACE4_INFO 0x0b4c
1652 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
1653 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
1654 #define RADEON_SURFACE5_INFO 0x0b5c
1655 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
1656 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
1657 #define RADEON_SURFACE6_INFO 0x0b6c
1658 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
1659 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
1660 #define RADEON_SURFACE7_INFO 0x0b7c
1661 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
1662 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
1663 #define RADEON_SW_SEMAPHORE 0x013c
1665 #define RADEON_TEST_DEBUG_CNTL 0x0120
1666 #define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
1668 #define RADEON_TEST_DEBUG_MUX 0x0124
1669 #define RADEON_TEST_DEBUG_OUT 0x012c
1670 #define RADEON_TMDS_PLL_CNTL 0x02a8
1671 #define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4
1672 # define RADEON_TMDS_TRANSMITTER_PLLEN 1
1673 # define RADEON_TMDS_TRANSMITTER_PLLRST 2
1674 #define RADEON_TRAIL_BRES_DEC 0x1614
1675 #define RADEON_TRAIL_BRES_ERR 0x160c
1676 #define RADEON_TRAIL_BRES_INC 0x1610
1677 #define RADEON_TRAIL_X 0x1618
1678 #define RADEON_TRAIL_X_SUB 0x1620
1680 #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */
1681 # define RADEON_VCLK_SRC_SEL_MASK 0x03
1682 # define RADEON_VCLK_SRC_SEL_CPUCLK 0x00
1683 # define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
1684 # define RADEON_VCLK_SRC_SEL_BYTECLK 0x02
1685 # define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03
1686 # define RADEON_PIXCLK_ALWAYS_ONb (1<<6)
1687 # define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
1688 # define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
1690 #define RADEON_VENDOR_ID 0x0f00 /* PCI */
1691 #define RADEON_VGA_DDA_CONFIG 0x02e8
1692 #define RADEON_VGA_DDA_ON_OFF 0x02ec
1693 #define RADEON_VID_BUFFER_CONTROL 0x0900
1694 #define RADEON_VIDEOMUX_CNTL 0x0190
1697 #define RADEON_VIPH_CH0_DATA 0x0c00
1698 #define RADEON_VIPH_CH1_DATA 0x0c04
1699 #define RADEON_VIPH_CH2_DATA 0x0c08
1700 #define RADEON_VIPH_CH3_DATA 0x0c0c
1701 #define RADEON_VIPH_CH0_ADDR 0x0c10
1702 #define RADEON_VIPH_CH1_ADDR 0x0c14
1703 #define RADEON_VIPH_CH2_ADDR 0x0c18
1704 #define RADEON_VIPH_CH3_ADDR 0x0c1c
1705 #define RADEON_VIPH_CH0_SBCNT 0x0c20
1706 #define RADEON_VIPH_CH1_SBCNT 0x0c24
1707 #define RADEON_VIPH_CH2_SBCNT 0x0c28
1708 #define RADEON_VIPH_CH3_SBCNT 0x0c2c
1709 #define RADEON_VIPH_CH0_ABCNT 0x0c30
1710 #define RADEON_VIPH_CH1_ABCNT 0x0c34
1711 #define RADEON_VIPH_CH2_ABCNT 0x0c38
1712 #define RADEON_VIPH_CH3_ABCNT 0x0c3c
1713 #define RADEON_VIPH_CONTROL 0x0c40
1714 # define RADEON_VIP_BUSY 0
1715 # define RADEON_VIP_IDLE 1
1716 # define RADEON_VIP_RESET 2
1717 # define RADEON_VIPH_EN (1 << 21)
1718 #define RADEON_VIPH_DV_LAT 0x0c44
1719 #define RADEON_VIPH_BM_CHUNK 0x0c48
1720 #define RADEON_VIPH_DV_INT 0x0c4c
1721 #define RADEON_VIPH_TIMEOUT_STAT 0x0c50
1722 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
1723 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
1724 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
1726 #define RADEON_VIPH_REG_DATA 0x0084
1727 #define RADEON_VIPH_REG_ADDR 0x0080
1730 #define RADEON_WAIT_UNTIL 0x1720
1731 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
1732 # define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)
1733 # define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)
1734 # define RADEON_WAIT_CRTC_VLINE (1 << 3)
1735 # define RADEON_WAIT_DMA_VID_IDLE (1 << 8)
1736 # define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)
1737 # define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */
1738 # define RADEON_WAIT_OV0_FLIP (1 << 11)
1739 # define RADEON_WAIT_AGP_FLUSH (1 << 13)
1740 # define RADEON_WAIT_2D_IDLE (1 << 14)
1741 # define RADEON_WAIT_3D_IDLE (1 << 15)
1742 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1743 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1744 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1745 # define RADEON_CMDFIFO_ENTRIES_SHIFT 10
1746 # define RADEON_CMDFIFO_ENTRIES_MASK 0x7f
1747 # define RADEON_WAIT_VAP_IDLE (1 << 28)
1748 # define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)
1749 # define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)
1750 # define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)
1752 #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
1753 #define RADEON_XCLK_CNTL 0x000d /* PLL */
1754 #define RADEON_XDLL_CNTL 0x000c /* PLL */
1755 #define RADEON_XPLL_CNTL 0x000b /* PLL */
1759 /* Registers for 3D/TCL */
1760 #define RADEON_PP_BORDER_COLOR_0 0x1d40
1761 #define RADEON_PP_BORDER_COLOR_1 0x1d44
1762 #define RADEON_PP_BORDER_COLOR_2 0x1d48
1763 #define RADEON_PP_CNTL 0x1c38
1764 # define RADEON_STIPPLE_ENABLE (1 << 0)
1765 # define RADEON_SCISSOR_ENABLE (1 << 1)
1766 # define RADEON_PATTERN_ENABLE (1 << 2)
1767 # define RADEON_SHADOW_ENABLE (1 << 3)
1768 # define RADEON_TEX_ENABLE_MASK (0xf << 4)
1769 # define RADEON_TEX_0_ENABLE (1 << 4)
1770 # define RADEON_TEX_1_ENABLE (1 << 5)
1771 # define RADEON_TEX_2_ENABLE (1 << 6)
1772 # define RADEON_TEX_3_ENABLE (1 << 7)
1773 # define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
1774 # define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
1775 # define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
1776 # define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
1777 # define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
1778 # define RADEON_PLANAR_YUV_ENABLE (1 << 20)
1779 # define RADEON_SPECULAR_ENABLE (1 << 21)
1780 # define RADEON_FOG_ENABLE (1 << 22)
1781 # define RADEON_ALPHA_TEST_ENABLE (1 << 23)
1782 # define RADEON_ANTI_ALIAS_NONE (0 << 24)
1783 # define RADEON_ANTI_ALIAS_LINE (1 << 24)
1784 # define RADEON_ANTI_ALIAS_POLY (2 << 24)
1785 # define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
1786 # define RADEON_BUMP_MAP_ENABLE (1 << 26)
1787 # define RADEON_BUMPED_MAP_T0 (0 << 27)
1788 # define RADEON_BUMPED_MAP_T1 (1 << 27)
1789 # define RADEON_BUMPED_MAP_T2 (2 << 27)
1790 # define RADEON_TEX_3D_ENABLE_0 (1 << 29)
1791 # define RADEON_TEX_3D_ENABLE_1 (1 << 30)
1792 # define RADEON_MC_ENABLE (1 << 31)
1793 #define RADEON_PP_FOG_COLOR 0x1c18
1794 # define RADEON_FOG_COLOR_MASK 0x00ffffff
1795 # define RADEON_FOG_VERTEX (0 << 24)
1796 # define RADEON_FOG_TABLE (1 << 24)
1797 # define RADEON_FOG_USE_DEPTH (0 << 25)
1798 # define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)
1799 # define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)
1800 #define RADEON_PP_LUM_MATRIX 0x1d00
1801 #define RADEON_PP_MISC 0x1c14
1802 # define RADEON_REF_ALPHA_MASK 0x000000ff
1803 # define RADEON_ALPHA_TEST_FAIL (0 << 8)
1804 # define RADEON_ALPHA_TEST_LESS (1 << 8)
1805 # define RADEON_ALPHA_TEST_LEQUAL (2 << 8)
1806 # define RADEON_ALPHA_TEST_EQUAL (3 << 8)
1807 # define RADEON_ALPHA_TEST_GEQUAL (4 << 8)
1808 # define RADEON_ALPHA_TEST_GREATER (5 << 8)
1809 # define RADEON_ALPHA_TEST_NEQUAL (6 << 8)
1810 # define RADEON_ALPHA_TEST_PASS (7 << 8)
1811 # define RADEON_ALPHA_TEST_OP_MASK (7 << 8)
1812 # define RADEON_CHROMA_FUNC_FAIL (0 << 16)
1813 # define RADEON_CHROMA_FUNC_PASS (1 << 16)
1814 # define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)
1815 # define RADEON_CHROMA_FUNC_EQUAL (3 << 16)
1816 # define RADEON_CHROMA_KEY_NEAREST (0 << 18)
1817 # define RADEON_CHROMA_KEY_ZERO (1 << 18)
1818 # define RADEON_SHADOW_ID_AUTO_INC (1 << 20)
1819 # define RADEON_SHADOW_FUNC_EQUAL (0 << 21)
1820 # define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)
1821 # define RADEON_SHADOW_PASS_1 (0 << 22)
1822 # define RADEON_SHADOW_PASS_2 (1 << 22)
1823 # define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)
1824 # define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)
1825 #define RADEON_PP_ROT_MATRIX_0 0x1d58
1826 #define RADEON_PP_ROT_MATRIX_1 0x1d5c
1827 #define RADEON_PP_TXFILTER_0 0x1c54
1828 #define RADEON_PP_TXFILTER_1 0x1c6c
1829 #define RADEON_PP_TXFILTER_2 0x1c84
1830 # define RADEON_MAG_FILTER_NEAREST (0 << 0)
1831 # define RADEON_MAG_FILTER_LINEAR (1 << 0)
1832 # define RADEON_MAG_FILTER_MASK (1 << 0)
1833 # define RADEON_MIN_FILTER_NEAREST (0 << 1)
1834 # define RADEON_MIN_FILTER_LINEAR (1 << 1)
1835 # define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
1836 # define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
1837 # define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
1838 # define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
1839 # define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)
1840 # define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)
1841 # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
1842 # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
1843 # define RADEON_MIN_FILTER_MASK (15 << 1)
1844 # define RADEON_MAX_ANISO_1_TO_1 (0 << 5)
1845 # define RADEON_MAX_ANISO_2_TO_1 (1 << 5)
1846 # define RADEON_MAX_ANISO_4_TO_1 (2 << 5)
1847 # define RADEON_MAX_ANISO_8_TO_1 (3 << 5)
1848 # define RADEON_MAX_ANISO_16_TO_1 (4 << 5)
1849 # define RADEON_MAX_ANISO_MASK (7 << 5)
1850 # define RADEON_LOD_BIAS_MASK (0xff << 8)
1851 # define RADEON_LOD_BIAS_SHIFT 8
1852 # define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)
1853 # define RADEON_MAX_MIP_LEVEL_SHIFT 16
1854 # define RADEON_YUV_TO_RGB (1 << 20)
1855 # define RADEON_YUV_TEMPERATURE_COOL (0 << 21)
1856 # define RADEON_YUV_TEMPERATURE_HOT (1 << 21)
1857 # define RADEON_YUV_TEMPERATURE_MASK (1 << 21)
1858 # define RADEON_WRAPEN_S (1 << 22)
1859 # define RADEON_CLAMP_S_WRAP (0 << 23)
1860 # define RADEON_CLAMP_S_MIRROR (1 << 23)
1861 # define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)
1862 # define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
1863 # define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)
1864 # define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
1865 # define RADEON_CLAMP_S_CLAMP_GL (6 << 23)
1866 # define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
1867 # define RADEON_CLAMP_S_MASK (7 << 23)
1868 # define RADEON_WRAPEN_T (1 << 26)
1869 # define RADEON_CLAMP_T_WRAP (0 << 27)
1870 # define RADEON_CLAMP_T_MIRROR (1 << 27)
1871 # define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)
1872 # define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
1873 # define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)
1874 # define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
1875 # define RADEON_CLAMP_T_CLAMP_GL (6 << 27)
1876 # define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
1877 # define RADEON_CLAMP_T_MASK (7 << 27)
1878 # define RADEON_BORDER_MODE_OGL (0 << 31)
1879 # define RADEON_BORDER_MODE_D3D (1 << 31)
1880 #define RADEON_PP_TXFORMAT_0 0x1c58
1881 #define RADEON_PP_TXFORMAT_1 0x1c70
1882 #define RADEON_PP_TXFORMAT_2 0x1c88
1883 # define RADEON_TXFORMAT_I8 (0 << 0)
1884 # define RADEON_TXFORMAT_AI88 (1 << 0)
1885 # define RADEON_TXFORMAT_RGB332 (2 << 0)
1886 # define RADEON_TXFORMAT_ARGB1555 (3 << 0)
1887 # define RADEON_TXFORMAT_RGB565 (4 << 0)
1888 # define RADEON_TXFORMAT_ARGB4444 (5 << 0)
1889 # define RADEON_TXFORMAT_ARGB8888 (6 << 0)
1890 # define RADEON_TXFORMAT_RGBA8888 (7 << 0)
1891 # define RADEON_TXFORMAT_Y8 (8 << 0)
1892 # define RADEON_TXFORMAT_VYUY422 (10 << 0)
1893 # define RADEON_TXFORMAT_YVYU422 (11 << 0)
1894 # define RADEON_TXFORMAT_DXT1 (12 << 0)
1895 # define RADEON_TXFORMAT_DXT23 (14 << 0)
1896 # define RADEON_TXFORMAT_DXT45 (15 << 0)
1897 # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
1898 # define RADEON_TXFORMAT_FORMAT_SHIFT 0
1899 # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
1900 # define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
1901 # define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
1902 # define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
1903 # define RADEON_TXFORMAT_WIDTH_SHIFT 8
1904 # define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
1905 # define RADEON_TXFORMAT_HEIGHT_SHIFT 12
1906 # define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
1907 # define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
1908 # define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
1909 # define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
1910 # define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
1911 # define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
1912 # define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
1913 # define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
1914 # define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
1915 # define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
1916 # define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
1917 # define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
1918 # define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
1919 # define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
1920 # define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
1921 # define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
1922 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1923 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1924 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1925 # define RADEON_FACE_WIDTH_1_SHIFT 0
1926 # define RADEON_FACE_HEIGHT_1_SHIFT 4
1927 # define RADEON_FACE_WIDTH_1_MASK (0xf << 0)
1928 # define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)
1929 # define RADEON_FACE_WIDTH_2_SHIFT 8
1930 # define RADEON_FACE_HEIGHT_2_SHIFT 12
1931 # define RADEON_FACE_WIDTH_2_MASK (0xf << 8)
1932 # define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)
1933 # define RADEON_FACE_WIDTH_3_SHIFT 16
1934 # define RADEON_FACE_HEIGHT_3_SHIFT 20
1935 # define RADEON_FACE_WIDTH_3_MASK (0xf << 16)
1936 # define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)
1937 # define RADEON_FACE_WIDTH_4_SHIFT 24
1938 # define RADEON_FACE_HEIGHT_4_SHIFT 28
1939 # define RADEON_FACE_WIDTH_4_MASK (0xf << 24)
1940 # define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)
1942 #define RADEON_PP_TXOFFSET_0 0x1c5c
1943 #define RADEON_PP_TXOFFSET_1 0x1c74
1944 #define RADEON_PP_TXOFFSET_2 0x1c8c
1945 # define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
1946 # define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
1947 # define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
1948 # define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
1949 # define RADEON_TXO_MACRO_LINEAR (0 << 2)
1950 # define RADEON_TXO_MACRO_TILE (1 << 2)
1951 # define RADEON_TXO_MICRO_LINEAR (0 << 3)
1952 # define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
1953 # define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
1954 # define RADEON_TXO_OFFSET_MASK 0xffffffe0
1955 # define RADEON_TXO_OFFSET_SHIFT 5
1957 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1958 #define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4
1959 #define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8
1960 #define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc
1961 #define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0
1962 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1963 #define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04
1964 #define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08
1965 #define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c
1966 #define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10
1967 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1968 #define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18
1969 #define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c
1970 #define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20
1971 #define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24
1973 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1974 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1975 #define RADEON_PP_TEX_SIZE_2 0x1d14
1976 # define RADEON_TEX_USIZE_MASK (0x7ff << 0)
1977 # define RADEON_TEX_USIZE_SHIFT 0
1978 # define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
1979 # define RADEON_TEX_VSIZE_SHIFT 16
1980 # define RADEON_SIGNED_RGB_MASK (1 << 30)
1981 # define RADEON_SIGNED_RGB_SHIFT 30
1982 # define RADEON_SIGNED_ALPHA_MASK (1 << 31)
1983 # define RADEON_SIGNED_ALPHA_SHIFT 31
1984 #define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
1985 #define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
1986 #define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */
1987 /* note: bits 13-5: 32 byte aligned stride of texture map */
1989 #define RADEON_PP_TXCBLEND_0 0x1c60
1990 #define RADEON_PP_TXCBLEND_1 0x1c78
1991 #define RADEON_PP_TXCBLEND_2 0x1c90
1992 # define RADEON_COLOR_ARG_A_SHIFT 0
1993 # define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
1994 # define RADEON_COLOR_ARG_A_ZERO (0 << 0)
1995 # define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)
1996 # define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)
1997 # define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)
1998 # define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)
1999 # define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)
2000 # define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)
2001 # define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)
2002 # define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)
2003 # define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)
2004 # define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)
2005 # define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)
2006 # define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)
2007 # define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)
2008 # define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)
2009 # define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)
2010 # define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)
2011 # define RADEON_COLOR_ARG_B_SHIFT 5
2012 # define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
2013 # define RADEON_COLOR_ARG_B_ZERO (0 << 5)
2014 # define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)
2015 # define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)
2016 # define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)
2017 # define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)
2018 # define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)
2019 # define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)
2020 # define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)
2021 # define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)
2022 # define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)
2023 # define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)
2024 # define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)
2025 # define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)
2026 # define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)
2027 # define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)
2028 # define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)
2029 # define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)
2030 # define RADEON_COLOR_ARG_C_SHIFT 10
2031 # define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
2032 # define RADEON_COLOR_ARG_C_ZERO (0 << 10)
2033 # define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)
2034 # define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)
2035 # define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)
2036 # define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)
2037 # define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)
2038 # define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)
2039 # define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)
2040 # define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)
2041 # define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)
2042 # define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)
2043 # define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)
2044 # define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)
2045 # define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)
2046 # define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)
2047 # define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)
2048 # define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)
2049 # define RADEON_COMP_ARG_A (1 << 15)
2050 # define RADEON_COMP_ARG_A_SHIFT 15
2051 # define RADEON_COMP_ARG_B (1 << 16)
2052 # define RADEON_COMP_ARG_B_SHIFT 16
2053 # define RADEON_COMP_ARG_C (1 << 17)
2054 # define RADEON_COMP_ARG_C_SHIFT 17
2055 # define RADEON_BLEND_CTL_MASK (7 << 18)
2056 # define RADEON_BLEND_CTL_ADD (0 << 18)
2057 # define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
2058 # define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
2059 # define RADEON_BLEND_CTL_BLEND (3 << 18)
2060 # define RADEON_BLEND_CTL_DOT3 (4 << 18)
2061 # define RADEON_SCALE_SHIFT 21
2062 # define RADEON_SCALE_MASK (3 << 21)
2063 # define RADEON_SCALE_1X (0 << 21)
2064 # define RADEON_SCALE_2X (1 << 21)
2065 # define RADEON_SCALE_4X (2 << 21)
2066 # define RADEON_CLAMP_TX (1 << 23)
2067 # define RADEON_T0_EQ_TCUR (1 << 24)
2068 # define RADEON_T1_EQ_TCUR (1 << 25)
2069 # define RADEON_T2_EQ_TCUR (1 << 26)
2070 # define RADEON_T3_EQ_TCUR (1 << 27)
2071 # define RADEON_COLOR_ARG_MASK 0x1f
2072 # define RADEON_COMP_ARG_SHIFT 15
2073 #define RADEON_PP_TXABLEND_0 0x1c64
2074 #define RADEON_PP_TXABLEND_1 0x1c7c
2075 #define RADEON_PP_TXABLEND_2 0x1c94
2076 # define RADEON_ALPHA_ARG_A_SHIFT 0
2077 # define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
2078 # define RADEON_ALPHA_ARG_A_ZERO (0 << 0)
2079 # define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)
2080 # define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)
2081 # define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)
2082 # define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)
2083 # define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)
2084 # define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)
2085 # define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)
2086 # define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)
2087 # define RADEON_ALPHA_ARG_B_SHIFT 4
2088 # define RADEON_ALPHA_ARG_B_MASK (0xf << 4)
2089 # define RADEON_ALPHA_ARG_B_ZERO (0 << 4)
2090 # define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)
2091 # define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)
2092 # define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)
2093 # define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)
2094 # define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)
2095 # define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)
2096 # define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)
2097 # define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)
2098 # define RADEON_ALPHA_ARG_C_SHIFT 8
2099 # define RADEON_ALPHA_ARG_C_MASK (0xf << 8)
2100 # define RADEON_ALPHA_ARG_C_ZERO (0 << 8)
2101 # define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)
2102 # define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)
2103 # define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)
2104 # define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)
2105 # define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)
2106 # define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)
2107 # define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)
2108 # define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)
2109 # define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)
2110 # define RADEON_ALPHA_ARG_MASK 0xf
2112 #define RADEON_PP_TFACTOR_0 0x1c68
2113 #define RADEON_PP_TFACTOR_1 0x1c80
2114 #define RADEON_PP_TFACTOR_2 0x1c98
2116 #define RADEON_RB3D_BLENDCNTL 0x1c20
2117 # define RADEON_COMB_FCN_MASK (3 << 12)
2118 # define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)
2119 # define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)
2120 # define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)
2121 # define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)
2122 # define RADEON_SRC_BLEND_GL_ZERO (32 << 16)
2123 # define RADEON_SRC_BLEND_GL_ONE (33 << 16)
2124 # define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)
2125 # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
2126 # define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)
2127 # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
2128 # define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
2129 # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
2130 # define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)
2131 # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
2132 # define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
2133 # define RADEON_SRC_BLEND_MASK (63 << 16)
2134 # define RADEON_DST_BLEND_GL_ZERO (32 << 24)
2135 # define RADEON_DST_BLEND_GL_ONE (33 << 24)
2136 # define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)
2137 # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
2138 # define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)
2139 # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
2140 # define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)
2141 # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
2142 # define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)
2143 # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
2144 # define RADEON_DST_BLEND_MASK (63 << 24)
2145 #define RADEON_RB3D_CNTL 0x1c3c
2146 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
2147 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
2148 # define RADEON_DITHER_ENABLE (1 << 2)
2149 # define RADEON_ROUND_ENABLE (1 << 3)
2150 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
2151 # define RADEON_DITHER_INIT (1 << 5)
2152 # define RADEON_ROP_ENABLE (1 << 6)
2153 # define RADEON_STENCIL_ENABLE (1 << 7)
2154 # define RADEON_Z_ENABLE (1 << 8)
2155 # define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
2156 # define RADEON_RB3D_COLOR_FORMAT_SHIFT 10
2158 # define RADEON_COLOR_FORMAT_ARGB1555 3
2159 # define RADEON_COLOR_FORMAT_RGB565 4
2160 # define RADEON_COLOR_FORMAT_ARGB8888 6
2161 # define RADEON_COLOR_FORMAT_RGB332 7
2162 # define RADEON_COLOR_FORMAT_Y8 8
2163 # define RADEON_COLOR_FORMAT_RGB8 9
2164 # define RADEON_COLOR_FORMAT_YUV422_VYUY 11
2165 # define RADEON_COLOR_FORMAT_YUV422_YVYU 12
2166 # define RADEON_COLOR_FORMAT_aYUV444 14
2167 # define RADEON_COLOR_FORMAT_ARGB4444 15
2169 # define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
2170 #define RADEON_RB3D_COLOROFFSET 0x1c40
2171 # define RADEON_COLOROFFSET_MASK 0xfffffff0
2172 #define RADEON_RB3D_COLORPITCH 0x1c48
2173 # define RADEON_COLORPITCH_MASK 0x000001ff8
2174 # define RADEON_COLOR_TILE_ENABLE (1 << 16)
2175 # define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)
2176 # define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)
2177 # define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)
2178 # define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
2179 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
2180 #define RADEON_RB3D_DEPTHPITCH 0x1c28
2181 # define RADEON_DEPTHPITCH_MASK 0x00001ff8
2182 # define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)
2183 # define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)
2184 # define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
2185 #define RADEON_RB3D_PLANEMASK 0x1d84
2186 #define RADEON_RB3D_ROPCNTL 0x1d80
2187 # define RADEON_ROP_MASK (15 << 8)
2188 # define RADEON_ROP_CLEAR (0 << 8)
2189 # define RADEON_ROP_NOR (1 << 8)
2190 # define RADEON_ROP_AND_INVERTED (2 << 8)
2191 # define RADEON_ROP_COPY_INVERTED (3 << 8)
2192 # define RADEON_ROP_AND_REVERSE (4 << 8)
2193 # define RADEON_ROP_INVERT (5 << 8)
2194 # define RADEON_ROP_XOR (6 << 8)
2195 # define RADEON_ROP_NAND (7 << 8)
2196 # define RADEON_ROP_AND (8 << 8)
2197 # define RADEON_ROP_EQUIV (9 << 8)
2198 # define RADEON_ROP_NOOP (10 << 8)
2199 # define RADEON_ROP_OR_INVERTED (11 << 8)
2200 # define RADEON_ROP_COPY (12 << 8)
2201 # define RADEON_ROP_OR_REVERSE (13 << 8)
2202 # define RADEON_ROP_OR (14 << 8)
2203 # define RADEON_ROP_SET (15 << 8)
2204 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
2205 # define RADEON_STENCIL_REF_SHIFT 0
2206 # define RADEON_STENCIL_REF_MASK (0xff << 0)
2207 # define RADEON_STENCIL_MASK_SHIFT 16
2208 # define RADEON_STENCIL_VALUE_MASK (0xff << 16)
2209 # define RADEON_STENCIL_WRITEMASK_SHIFT 24
2210 # define RADEON_STENCIL_WRITE_MASK (0xff << 24)
2211 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
2212 # define RADEON_DEPTH_FORMAT_MASK (0xf << 0)
2213 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
2214 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
2215 # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)
2216 # define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)
2217 # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)
2218 # define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)
2219 # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)
2220 # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)
2221 # define RADEON_Z_TEST_NEVER (0 << 4)
2222 # define RADEON_Z_TEST_LESS (1 << 4)
2223 # define RADEON_Z_TEST_LEQUAL (2 << 4)
2224 # define RADEON_Z_TEST_EQUAL (3 << 4)
2225 # define RADEON_Z_TEST_GEQUAL (4 << 4)
2226 # define RADEON_Z_TEST_GREATER (5 << 4)
2227 # define RADEON_Z_TEST_NEQUAL (6 << 4)
2228 # define RADEON_Z_TEST_ALWAYS (7 << 4)
2229 # define RADEON_Z_TEST_MASK (7 << 4)
2230 # define RADEON_STENCIL_TEST_NEVER (0 << 12)
2231 # define RADEON_STENCIL_TEST_LESS (1 << 12)
2232 # define RADEON_STENCIL_TEST_LEQUAL (2 << 12)
2233 # define RADEON_STENCIL_TEST_EQUAL (3 << 12)
2234 # define RADEON_STENCIL_TEST_GEQUAL (4 << 12)
2235 # define RADEON_STENCIL_TEST_GREATER (5 << 12)
2236 # define RADEON_STENCIL_TEST_NEQUAL (6 << 12)
2237 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
2238 # define RADEON_STENCIL_TEST_MASK (0x7 << 12)
2239 # define RADEON_STENCIL_FAIL_KEEP (0 << 16)
2240 # define RADEON_STENCIL_FAIL_ZERO (1 << 16)
2241 # define RADEON_STENCIL_FAIL_REPLACE (2 << 16)
2242 # define RADEON_STENCIL_FAIL_INC (3 << 16)
2243 # define RADEON_STENCIL_FAIL_DEC (4 << 16)
2244 # define RADEON_STENCIL_FAIL_INVERT (5 << 16)
2245 # define RADEON_STENCIL_FAIL_MASK (0x7 << 16)
2246 # define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
2247 # define RADEON_STENCIL_ZPASS_ZERO (1 << 20)
2248 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
2249 # define RADEON_STENCIL_ZPASS_INC (3 << 20)
2250 # define RADEON_STENCIL_ZPASS_DEC (4 << 20)
2251 # define RADEON_STENCIL_ZPASS_INVERT (5 << 20)
2252 # define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)
2253 # define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)
2254 # define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)
2255 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
2256 # define RADEON_STENCIL_ZFAIL_INC (3 << 24)
2257 # define RADEON_STENCIL_ZFAIL_DEC (4 << 24)
2258 # define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)
2259 # define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)
2260 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
2261 # define RADEON_FORCE_Z_DIRTY (1 << 29)
2262 # define RADEON_Z_WRITE_ENABLE (1 << 30)
2263 #define RADEON_RE_LINE_PATTERN 0x1cd0
2264 # define RADEON_LINE_PATTERN_MASK 0x0000ffff
2265 # define RADEON_LINE_REPEAT_COUNT_SHIFT 16
2266 # define RADEON_LINE_PATTERN_START_SHIFT 24
2267 # define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)
2268 # define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)
2269 # define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)
2270 #define RADEON_RE_LINE_STATE 0x1cd4
2271 # define RADEON_LINE_CURRENT_PTR_SHIFT 0
2272 # define RADEON_LINE_CURRENT_COUNT_SHIFT 8
2273 #define RADEON_RE_MISC 0x26c4
2274 # define RADEON_STIPPLE_COORD_MASK 0x1f
2275 # define RADEON_STIPPLE_X_OFFSET_SHIFT 0
2276 # define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)
2277 # define RADEON_STIPPLE_Y_OFFSET_SHIFT 8
2278 # define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)
2279 # define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)
2280 # define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)
2281 #define RADEON_RE_SOLID_COLOR 0x1c1c
2282 #define RADEON_RE_TOP_LEFT 0x26c0
2283 # define RADEON_RE_LEFT_SHIFT 0
2284 # define RADEON_RE_TOP_SHIFT 16
2285 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
2286 # define RADEON_RE_WIDTH_SHIFT 0
2287 # define RADEON_RE_HEIGHT_SHIFT 16
2289 #define RADEON_SE_CNTL 0x1c4c
2290 # define RADEON_FFACE_CULL_CW (0 << 0)
2291 # define RADEON_FFACE_CULL_CCW (1 << 0)
2292 # define RADEON_FFACE_CULL_DIR_MASK (1 << 0)
2293 # define RADEON_BFACE_CULL (0 << 1)
2294 # define RADEON_BFACE_SOLID (3 << 1)
2295 # define RADEON_FFACE_CULL (0 << 3)
2296 # define RADEON_FFACE_SOLID (3 << 3)
2297 # define RADEON_FFACE_CULL_MASK (3 << 3)
2298 # define RADEON_BADVTX_CULL_DISABLE (1 << 5)
2299 # define RADEON_FLAT_SHADE_VTX_0 (0 << 6)
2300 # define RADEON_FLAT_SHADE_VTX_1 (1 << 6)
2301 # define RADEON_FLAT_SHADE_VTX_2 (2 << 6)
2302 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
2303 # define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)
2304 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
2305 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
2306 # define RADEON_DIFFUSE_SHADE_MASK (3 << 8)
2307 # define RADEON_ALPHA_SHADE_SOLID (0 << 10)
2308 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
2309 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
2310 # define RADEON_ALPHA_SHADE_MASK (3 << 10)
2311 # define RADEON_SPECULAR_SHADE_SOLID (0 << 12)
2312 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
2313 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
2314 # define RADEON_SPECULAR_SHADE_MASK (3 << 12)
2315 # define RADEON_FOG_SHADE_SOLID (0 << 14)
2316 # define RADEON_FOG_SHADE_FLAT (1 << 14)
2317 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
2318 # define RADEON_FOG_SHADE_MASK (3 << 14)
2319 # define RADEON_ZBIAS_ENABLE_POINT (1 << 16)
2320 # define RADEON_ZBIAS_ENABLE_LINE (1 << 17)
2321 # define RADEON_ZBIAS_ENABLE_TRI (1 << 18)
2322 # define RADEON_WIDELINE_ENABLE (1 << 20)
2323 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
2324 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
2325 # define RADEON_VTX_PIX_CENTER_D3D (0 << 27)
2326 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
2327 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
2328 # define RADEON_ROUND_MODE_ROUND (1 << 28)
2329 # define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)
2330 # define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)
2331 # define RADEON_ROUND_PREC_16TH_PIX (0 << 30)
2332 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
2333 # define RADEON_ROUND_PREC_4TH_PIX (2 << 30)
2334 # define RADEON_ROUND_PREC_HALF_PIX (3 << 30)
2335 #define R200_RE_CNTL 0x1c50
2336 # define R200_STIPPLE_ENABLE 0x1
2337 # define R200_SCISSOR_ENABLE 0x2
2338 # define R200_PATTERN_ENABLE 0x4
2339 # define R200_PERSPECTIVE_ENABLE 0x8
2340 # define R200_POINT_SMOOTH 0x20
2341 # define R200_VTX_STQ0_D3D 0x00010000
2342 # define R200_VTX_STQ1_D3D 0x00040000
2343 # define R200_VTX_STQ2_D3D 0x00100000
2344 # define R200_VTX_STQ3_D3D 0x00400000
2345 # define R200_VTX_STQ4_D3D 0x01000000
2346 # define R200_VTX_STQ5_D3D 0x04000000
2347 #define RADEON_SE_CNTL_STATUS 0x2140
2348 # define RADEON_VC_NO_SWAP (0 << 0)
2349 # define RADEON_VC_16BIT_SWAP (1 << 0)
2350 # define RADEON_VC_32BIT_SWAP (2 << 0)
2351 # define RADEON_VC_HALF_DWORD_SWAP (3 << 0)
2352 # define RADEON_TCL_BYPASS (1 << 8)
2353 #define RADEON_SE_COORD_FMT 0x1c50
2354 # define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)
2355 # define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)
2356 # define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)
2357 # define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)
2358 # define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)
2359 # define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)
2360 # define RADEON_VTX_W0_NORMALIZE (1 << 12)
2361 # define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)
2362 # define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
2363 # define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
2364 # define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
2365 # define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
2366 # define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)
2367 # define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)
2368 #define RADEON_SE_LINE_WIDTH 0x1db8
2369 #define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c
2370 # define RADEON_LIGHTING_ENABLE (1 << 0)
2371 # define RADEON_LIGHT_IN_MODELSPACE (1 << 1)
2372 # define RADEON_LOCAL_VIEWER (1 << 2)
2373 # define RADEON_NORMALIZE_NORMALS (1 << 3)
2374 # define RADEON_RESCALE_NORMALS (1 << 4)
2375 # define RADEON_SPECULAR_LIGHTS (1 << 5)
2376 # define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)
2377 # define RADEON_LIGHT_ALPHA (1 << 7)
2378 # define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)
2379 # define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)
2380 # define RADEON_LM_SOURCE_STATE_PREMULT 0
2381 # define RADEON_LM_SOURCE_STATE_MULT 1
2382 # define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2
2383 # define RADEON_LM_SOURCE_VERTEX_SPECULAR 3
2384 # define RADEON_EMISSIVE_SOURCE_SHIFT 16
2385 # define RADEON_AMBIENT_SOURCE_SHIFT 18
2386 # define RADEON_DIFFUSE_SOURCE_SHIFT 20
2387 # define RADEON_SPECULAR_SOURCE_SHIFT 22
2388 #define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220
2389 #define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224
2390 #define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228
2391 #define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c
2392 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230
2393 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234
2394 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238
2395 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c
2396 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
2397 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214
2398 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218
2399 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c
2400 #define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240
2401 #define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244
2402 #define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248
2403 #define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c
2404 #define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c
2405 # define RADEON_MODELVIEW_0_SHIFT 0
2406 # define RADEON_MODELVIEW_1_SHIFT 4
2407 # define RADEON_MODELVIEW_2_SHIFT 8
2408 # define RADEON_MODELVIEW_3_SHIFT 12
2409 # define RADEON_IT_MODELVIEW_0_SHIFT 16
2410 # define RADEON_IT_MODELVIEW_1_SHIFT 20
2411 # define RADEON_IT_MODELVIEW_2_SHIFT 24
2412 # define RADEON_IT_MODELVIEW_3_SHIFT 28
2413 #define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260
2414 # define RADEON_MODELPROJECT_0_SHIFT 0
2415 # define RADEON_MODELPROJECT_1_SHIFT 4
2416 # define RADEON_MODELPROJECT_2_SHIFT 8
2417 # define RADEON_MODELPROJECT_3_SHIFT 12
2418 # define RADEON_TEXMAT_0_SHIFT 16
2419 # define RADEON_TEXMAT_1_SHIFT 20
2420 # define RADEON_TEXMAT_2_SHIFT 24
2421 # define RADEON_TEXMAT_3_SHIFT 28
2424 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
2425 # define RADEON_TCL_VTX_W0 (1 << 0)
2426 # define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)
2427 # define RADEON_TCL_VTX_FP_ALPHA (1 << 2)
2428 # define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)
2429 # define RADEON_TCL_VTX_FP_SPEC (1 << 4)
2430 # define RADEON_TCL_VTX_FP_FOG (1 << 5)
2431 # define RADEON_TCL_VTX_PK_SPEC (1 << 6)
2432 # define RADEON_TCL_VTX_ST0 (1 << 7)
2433 # define RADEON_TCL_VTX_ST1 (1 << 8)
2434 # define RADEON_TCL_VTX_Q1 (1 << 9)
2435 # define RADEON_TCL_VTX_ST2 (1 << 10)
2436 # define RADEON_TCL_VTX_Q2 (1 << 11)
2437 # define RADEON_TCL_VTX_ST3 (1 << 12)
2438 # define RADEON_TCL_VTX_Q3 (1 << 13)
2439 # define RADEON_TCL_VTX_Q0 (1 << 14)
2440 # define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15
2441 # define RADEON_TCL_VTX_NORM0 (1 << 18)
2442 # define RADEON_TCL_VTX_XY1 (1 << 27)
2443 # define RADEON_TCL_VTX_Z1 (1 << 28)
2444 # define RADEON_TCL_VTX_W1 (1 << 29)
2445 # define RADEON_TCL_VTX_NORM1 (1 << 30)
2446 # define RADEON_TCL_VTX_Z0 (1 << 31)
2448 #define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258
2449 # define RADEON_TCL_COMPUTE_XYZW (1 << 0)
2450 # define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)
2451 # define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)
2452 # define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)
2453 # define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)
2454 # define RADEON_TCL_TEX_INPUT_TEX_0 0
2455 # define RADEON_TCL_TEX_INPUT_TEX_1 1
2456 # define RADEON_TCL_TEX_INPUT_TEX_2 2
2457 # define RADEON_TCL_TEX_INPUT_TEX_3 3
2458 # define RADEON_TCL_TEX_COMPUTED_TEX_0 8
2459 # define RADEON_TCL_TEX_COMPUTED_TEX_1 9
2460 # define RADEON_TCL_TEX_COMPUTED_TEX_2 10
2461 # define RADEON_TCL_TEX_COMPUTED_TEX_3 11
2462 # define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16
2463 # define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20
2464 # define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24
2465 # define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28
2467 #define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270
2468 # define RADEON_LIGHT_0_ENABLE (1 << 0)
2469 # define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)
2470 # define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)
2471 # define RADEON_LIGHT_0_IS_LOCAL (1 << 3)
2472 # define RADEON_LIGHT_0_IS_SPOT (1 << 4)
2473 # define RADEON_LIGHT_0_DUAL_CONE (1 << 5)
2474 # define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)
2475 # define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)
2476 # define RADEON_LIGHT_0_SHIFT 0
2477 # define RADEON_LIGHT_1_ENABLE (1 << 16)
2478 # define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)
2479 # define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)
2480 # define RADEON_LIGHT_1_IS_LOCAL (1 << 19)
2481 # define RADEON_LIGHT_1_IS_SPOT (1 << 20)
2482 # define RADEON_LIGHT_1_DUAL_CONE (1 << 21)
2483 # define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)
2484 # define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)
2485 # define RADEON_LIGHT_1_SHIFT 16
2486 #define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274
2487 # define RADEON_LIGHT_2_SHIFT 0
2488 # define RADEON_LIGHT_3_SHIFT 16
2489 #define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278
2490 # define RADEON_LIGHT_4_SHIFT 0
2491 # define RADEON_LIGHT_5_SHIFT 16
2492 #define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c
2493 # define RADEON_LIGHT_6_SHIFT 0
2494 # define RADEON_LIGHT_7_SHIFT 16
2496 #define RADEON_SE_TCL_SHININESS 0x2250
2498 #define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268
2499 # define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)
2500 # define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)
2501 # define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)
2502 # define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)
2503 # define RADEON_TEXMAT_0_ENABLE (1 << 4)
2504 # define RADEON_TEXMAT_1_ENABLE (1 << 5)
2505 # define RADEON_TEXMAT_2_ENABLE (1 << 6)
2506 # define RADEON_TEXMAT_3_ENABLE (1 << 7)
2507 # define RADEON_TEXGEN_INPUT_MASK 0xf
2508 # define RADEON_TEXGEN_INPUT_TEXCOORD_0 0
2509 # define RADEON_TEXGEN_INPUT_TEXCOORD_1 1
2510 # define RADEON_TEXGEN_INPUT_TEXCOORD_2 2
2511 # define RADEON_TEXGEN_INPUT_TEXCOORD_3 3
2512 # define RADEON_TEXGEN_INPUT_OBJ 4
2513 # define RADEON_TEXGEN_INPUT_EYE 5
2514 # define RADEON_TEXGEN_INPUT_EYE_NORMAL 6
2515 # define RADEON_TEXGEN_INPUT_EYE_REFLECT 7
2516 # define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8
2517 # define RADEON_TEXGEN_0_INPUT_SHIFT 16
2518 # define RADEON_TEXGEN_1_INPUT_SHIFT 20
2519 # define RADEON_TEXGEN_2_INPUT_SHIFT 24
2520 # define RADEON_TEXGEN_3_INPUT_SHIFT 28
2522 #define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264
2523 # define RADEON_UCP_IN_CLIP_SPACE (1 << 0)
2524 # define RADEON_UCP_IN_MODEL_SPACE (1 << 1)
2525 # define RADEON_UCP_ENABLE_0 (1 << 2)
2526 # define RADEON_UCP_ENABLE_1 (1 << 3)
2527 # define RADEON_UCP_ENABLE_2 (1 << 4)
2528 # define RADEON_UCP_ENABLE_3 (1 << 5)
2529 # define RADEON_UCP_ENABLE_4 (1 << 6)
2530 # define RADEON_UCP_ENABLE_5 (1 << 7)
2531 # define RADEON_TCL_FOG_MASK (3 << 8)
2532 # define RADEON_TCL_FOG_DISABLE (0 << 8)
2533 # define RADEON_TCL_FOG_EXP (1 << 8)
2534 # define RADEON_TCL_FOG_EXP2 (2 << 8)
2535 # define RADEON_TCL_FOG_LINEAR (3 << 8)
2536 # define RADEON_RNG_BASED_FOG (1 << 10)
2537 # define RADEON_LIGHT_TWOSIDE (1 << 11)
2538 # define RADEON_BLEND_OP_COUNT_MASK (7 << 12)
2539 # define RADEON_BLEND_OP_COUNT_SHIFT 12
2540 # define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)
2541 # define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)
2542 # define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)
2543 # define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)
2544 # define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)
2545 # define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)
2546 # define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)
2547 # define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)
2548 # define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)
2549 # define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)
2550 # define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)
2551 # define RADEON_CULL_FRONT_IS_CW (0 << 28)
2552 # define RADEON_CULL_FRONT_IS_CCW (1 << 28)
2553 # define RADEON_CULL_FRONT (1 << 29)
2554 # define RADEON_CULL_BACK (1 << 30)
2555 # define RADEON_FORCE_W_TO_ONE (1 << 31)
2557 #define RADEON_SE_VPORT_XSCALE 0x1d98
2558 #define RADEON_SE_VPORT_XOFFSET 0x1d9c
2559 #define RADEON_SE_VPORT_YSCALE 0x1da0
2560 #define RADEON_SE_VPORT_YOFFSET 0x1da4
2561 #define RADEON_SE_VPORT_ZSCALE 0x1da8
2562 #define RADEON_SE_VPORT_ZOFFSET 0x1dac
2563 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
2564 #define RADEON_SE_ZBIAS_CONSTANT 0x1db4
2566 #define RADEON_SE_VTX_FMT 0x2080
2567 # define RADEON_SE_VTX_FMT_XY 0x00000000
2568 # define RADEON_SE_VTX_FMT_W0 0x00000001
2569 # define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002
2570 # define RADEON_SE_VTX_FMT_FPALPHA 0x00000004
2571 # define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008
2572 # define RADEON_SE_VTX_FMT_FPSPEC 0x00000010
2573 # define RADEON_SE_VTX_FMT_FPFOG 0x00000020
2574 # define RADEON_SE_VTX_FMT_PKSPEC 0x00000040
2575 # define RADEON_SE_VTX_FMT_ST0 0x00000080
2576 # define RADEON_SE_VTX_FMT_ST1 0x00000100
2577 # define RADEON_SE_VTX_FMT_Q1 0x00000200
2578 # define RADEON_SE_VTX_FMT_ST2 0x00000400
2579 # define RADEON_SE_VTX_FMT_Q2 0x00000800
2580 # define RADEON_SE_VTX_FMT_ST3 0x00001000
2581 # define RADEON_SE_VTX_FMT_Q3 0x00002000
2582 # define RADEON_SE_VTX_FMT_Q0 0x00004000
2583 # define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000
2584 # define RADEON_SE_VTX_FMT_N0 0x00040000
2585 # define RADEON_SE_VTX_FMT_XY1 0x08000000
2586 # define RADEON_SE_VTX_FMT_Z1 0x10000000
2587 # define RADEON_SE_VTX_FMT_W1 0x20000000
2588 # define RADEON_SE_VTX_FMT_N1 0x40000000
2589 # define RADEON_SE_VTX_FMT_Z 0x80000000
2591 #define RADEON_SE_VF_CNTL 0x2084
2592 # define RADEON_VF_PRIM_TYPE_POINT_LIST 1
2593 # define RADEON_VF_PRIM_TYPE_LINE_LIST 2
2594 # define RADEON_VF_PRIM_TYPE_LINE_STRIP 3
2595 # define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4
2596 # define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5
2597 # define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6
2598 # define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7
2599 # define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8
2600 # define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9
2601 # define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10
2602 # define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11
2603 # define RADEON_VF_PRIM_TYPE_LINE_LOOP 12
2604 # define RADEON_VF_PRIM_TYPE_QUAD_LIST 13
2605 # define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14
2606 # define RADEON_VF_PRIM_TYPE_POLYGON 15
2607 # define RADEON_VF_PRIM_WALK_STATE (0<<4)
2608 # define RADEON_VF_PRIM_WALK_INDEX (1<<4)
2609 # define RADEON_VF_PRIM_WALK_LIST (2<<4)
2610 # define RADEON_VF_PRIM_WALK_DATA (3<<4)
2611 # define RADEON_VF_COLOR_ORDER_RGBA (1<<6)
2612 # define RADEON_VF_RADEON_MODE (1<<8)
2613 # define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)
2614 # define RADEON_VF_PROG_STREAM_ENA (1<<10)
2615 # define RADEON_VF_INDEX_SIZE_SHIFT 11
2616 # define RADEON_VF_NUM_VERTICES_SHIFT 16
2618 #define RADEON_SE_PORT_DATA0 0x2000
2620 #define R200_SE_VAP_CNTL 0x2080
2621 # define R200_VAP_TCL_ENABLE 0x00000001
2622 # define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010
2623 # define R200_VAP_FORCE_W_TO_ONE 0x00010000
2624 # define R200_VAP_D3D_TEX_DEFAULT 0x00020000
2625 # define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18
2626 # define R200_VAP_VF_MAX_VTX_NUM (9 << 18)
2627 # define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000
2628 #define R200_VF_MAX_VTX_INDX 0x210c
2629 #define R200_VF_MIN_VTX_INDX 0x2110
2630 #define R200_SE_VTE_CNTL 0x20b0
2631 # define R200_VPORT_X_SCALE_ENA 0x00000001
2632 # define R200_VPORT_X_OFFSET_ENA 0x00000002
2633 # define R200_VPORT_Y_SCALE_ENA 0x00000004
2634 # define R200_VPORT_Y_OFFSET_ENA 0x00000008
2635 # define R200_VPORT_Z_SCALE_ENA 0x00000010
2636 # define R200_VPORT_Z_OFFSET_ENA 0x00000020
2637 # define R200_VTX_XY_FMT 0x00000100
2638 # define R200_VTX_Z_FMT 0x00000200
2639 # define R200_VTX_W0_FMT 0x00000400
2640 # define R200_VTX_W0_NORMALIZE 0x00000800
2641 # define R200_VTX_ST_DENORMALIZED 0x00001000
2642 #define R200_SE_VAP_CNTL_STATUS 0x2140
2643 # define R200_VC_NO_SWAP (0 << 0)
2644 # define R200_VC_16BIT_SWAP (1 << 0)
2645 # define R200_VC_32BIT_SWAP (2 << 0)
2646 #define R200_PP_TXFILTER_0 0x2c00
2647 #define R200_PP_TXFILTER_1 0x2c20
2648 #define R200_PP_TXFILTER_2 0x2c40
2649 #define R200_PP_TXFILTER_3 0x2c60
2650 #define R200_PP_TXFILTER_4 0x2c80
2651 #define R200_PP_TXFILTER_5 0x2ca0
2652 # define R200_MAG_FILTER_NEAREST (0 << 0)
2653 # define R200_MAG_FILTER_LINEAR (1 << 0)
2654 # define R200_MAG_FILTER_MASK (1 << 0)
2655 # define R200_MIN_FILTER_NEAREST (0 << 1)
2656 # define R200_MIN_FILTER_LINEAR (1 << 1)
2657 # define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
2658 # define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
2659 # define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
2660 # define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
2661 # define R200_MIN_FILTER_ANISO_NEAREST (8 << 1)
2662 # define R200_MIN_FILTER_ANISO_LINEAR (9 << 1)
2663 # define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
2664 # define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
2665 # define R200_MIN_FILTER_MASK (15 << 1)
2666 # define R200_MAX_ANISO_1_TO_1 (0 << 5)
2667 # define R200_MAX_ANISO_2_TO_1 (1 << 5)
2668 # define R200_MAX_ANISO_4_TO_1 (2 << 5)
2669 # define R200_MAX_ANISO_8_TO_1 (3 << 5)
2670 # define R200_MAX_ANISO_16_TO_1 (4 << 5)
2671 # define R200_MAX_ANISO_MASK (7 << 5)
2672 # define R200_MAX_MIP_LEVEL_MASK (0x0f << 16)
2673 # define R200_MAX_MIP_LEVEL_SHIFT 16
2674 # define R200_YUV_TO_RGB (1 << 20)
2675 # define R200_YUV_TEMPERATURE_COOL (0 << 21)
2676 # define R200_YUV_TEMPERATURE_HOT (1 << 21)
2677 # define R200_YUV_TEMPERATURE_MASK (1 << 21)
2678 # define R200_WRAPEN_S (1 << 22)
2679 # define R200_CLAMP_S_WRAP (0 << 23)
2680 # define R200_CLAMP_S_MIRROR (1 << 23)
2681 # define R200_CLAMP_S_CLAMP_LAST (2 << 23)
2682 # define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
2683 # define R200_CLAMP_S_CLAMP_BORDER (4 << 23)
2684 # define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
2685 # define R200_CLAMP_S_CLAMP_GL (6 << 23)
2686 # define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
2687 # define R200_CLAMP_S_MASK (7 << 23)
2688 # define R200_WRAPEN_T (1 << 26)
2689 # define R200_CLAMP_T_WRAP (0 << 27)
2690 # define R200_CLAMP_T_MIRROR (1 << 27)
2691 # define R200_CLAMP_T_CLAMP_LAST (2 << 27)
2692 # define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
2693 # define R200_CLAMP_T_CLAMP_BORDER (4 << 27)
2694 # define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
2695 # define R200_CLAMP_T_CLAMP_GL (6 << 27)
2696 # define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
2697 # define R200_CLAMP_T_MASK (7 << 27)
2698 # define R200_KILL_LT_ZERO (1 << 30)
2699 # define R200_BORDER_MODE_OGL (0 << 31)
2700 # define R200_BORDER_MODE_D3D (1 << 31)
2701 #define R200_PP_TXFORMAT_0 0x2c04
2702 #define R200_PP_TXFORMAT_1 0x2c24
2703 #define R200_PP_TXFORMAT_2 0x2c44
2704 #define R200_PP_TXFORMAT_3 0x2c64
2705 #define R200_PP_TXFORMAT_4 0x2c84
2706 #define R200_PP_TXFORMAT_5 0x2ca4
2707 # define R200_TXFORMAT_I8 (0 << 0)
2708 # define R200_TXFORMAT_AI88 (1 << 0)
2709 # define R200_TXFORMAT_RGB332 (2 << 0)
2710 # define R200_TXFORMAT_ARGB1555 (3 << 0)
2711 # define R200_TXFORMAT_RGB565 (4 << 0)
2712 # define R200_TXFORMAT_ARGB4444 (5 << 0)
2713 # define R200_TXFORMAT_ARGB8888 (6 << 0)
2714 # define R200_TXFORMAT_RGBA8888 (7 << 0)
2715 # define R200_TXFORMAT_Y8 (8 << 0)
2716 # define R200_TXFORMAT_AVYU4444 (9 << 0)
2717 # define R200_TXFORMAT_VYUY422 (10 << 0)
2718 # define R200_TXFORMAT_YVYU422 (11 << 0)
2719 # define R200_TXFORMAT_DXT1 (12 << 0)
2720 # define R200_TXFORMAT_DXT23 (14 << 0)
2721 # define R200_TXFORMAT_DXT45 (15 << 0)
2722 # define R200_TXFORMAT_ABGR8888 (22 << 0)
2723 # define R200_TXFORMAT_FORMAT_MASK (31 << 0)
2724 # define R200_TXFORMAT_FORMAT_SHIFT 0
2725 # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)
2726 # define R200_TXFORMAT_NON_POWER2 (1 << 7)
2727 # define R200_TXFORMAT_WIDTH_MASK (15 << 8)
2728 # define R200_TXFORMAT_WIDTH_SHIFT 8
2729 # define R200_TXFORMAT_HEIGHT_MASK (15 << 12)
2730 # define R200_TXFORMAT_HEIGHT_SHIFT 12
2731 # define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */
2732 # define R200_TXFORMAT_F5_WIDTH_SHIFT 16
2733 # define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
2734 # define R200_TXFORMAT_F5_HEIGHT_SHIFT 20
2735 # define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
2736 # define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
2737 # define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
2738 # define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24)
2739 # define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24)
2740 # define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24)
2741 # define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24)
2742 # define R200_TXFORMAT_ST_ROUTE_SHIFT 24
2743 # define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
2744 # define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
2745 # define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
2746 #define R200_PP_TXFORMAT_X_0 0x2c08
2747 #define R200_PP_TXFORMAT_X_1 0x2c28
2748 #define R200_PP_TXFORMAT_X_2 0x2c48
2749 #define R200_PP_TXFORMAT_X_3 0x2c68
2750 #define R200_PP_TXFORMAT_X_4 0x2c88
2751 #define R200_PP_TXFORMAT_X_5 0x2ca8
2753 #define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */
2754 #define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */
2755 #define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */
2756 #define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */
2757 #define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */
2758 #define R200_PP_TXSIZE_5 0x2cac /* NPOT only */
2760 #define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */
2761 #define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */
2762 #define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */
2763 #define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */
2764 #define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */
2765 #define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */
2767 #define R200_PP_TXOFFSET_0 0x2d00
2768 # define R200_TXO_ENDIAN_NO_SWAP (0 << 0)
2769 # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)
2770 # define R200_TXO_ENDIAN_WORD_SWAP (2 << 0)
2771 # define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
2772 # define R200_TXO_MACRO_LINEAR (0 << 2)
2773 # define R200_TXO_MACRO_TILE (1 << 2)
2774 # define R200_TXO_MICRO_LINEAR (0 << 3)
2775 # define R200_TXO_MICRO_TILE (1 << 3)
2776 # define R200_TXO_OFFSET_MASK 0xffffffe0
2777 # define R200_TXO_OFFSET_SHIFT 5
2778 #define R200_PP_TXOFFSET_1 0x2d18
2779 #define R200_PP_TXOFFSET_2 0x2d30
2780 #define R200_PP_TXOFFSET_3 0x2d48
2781 #define R200_PP_TXOFFSET_4 0x2d60
2782 #define R200_PP_TXOFFSET_5 0x2d78
2784 #define R200_PP_TFACTOR_0 0x2ee0
2785 #define R200_PP_TFACTOR_1 0x2ee4
2786 #define R200_PP_TFACTOR_2 0x2ee8
2787 #define R200_PP_TFACTOR_3 0x2eec
2788 #define R200_PP_TFACTOR_4 0x2ef0
2789 #define R200_PP_TFACTOR_5 0x2ef4
2791 #define R200_PP_TXCBLEND_0 0x2f00
2792 # define R200_TXC_ARG_A_ZERO (0)
2793 # define R200_TXC_ARG_A_CURRENT_COLOR (2)
2794 # define R200_TXC_ARG_A_CURRENT_ALPHA (3)
2795 # define R200_TXC_ARG_A_DIFFUSE_COLOR (4)
2796 # define R200_TXC_ARG_A_DIFFUSE_ALPHA (5)
2797 # define R200_TXC_ARG_A_SPECULAR_COLOR (6)
2798 # define R200_TXC_ARG_A_SPECULAR_ALPHA (7)
2799 # define R200_TXC_ARG_A_TFACTOR_COLOR (8)
2800 # define R200_TXC_ARG_A_TFACTOR_ALPHA (9)
2801 # define R200_TXC_ARG_A_R0_COLOR (10)
2802 # define R200_TXC_ARG_A_R0_ALPHA (11)
2803 # define R200_TXC_ARG_A_R1_COLOR (12)
2804 # define R200_TXC_ARG_A_R1_ALPHA (13)
2805 # define R200_TXC_ARG_A_R2_COLOR (14)
2806 # define R200_TXC_ARG_A_R2_ALPHA (15)
2807 # define R200_TXC_ARG_A_R3_COLOR (16)
2808 # define R200_TXC_ARG_A_R3_ALPHA (17)
2809 # define R200_TXC_ARG_A_R4_COLOR (18)
2810 # define R200_TXC_ARG_A_R4_ALPHA (19)
2811 # define R200_TXC_ARG_A_R5_COLOR (20)
2812 # define R200_TXC_ARG_A_R5_ALPHA (21)
2813 # define R200_TXC_ARG_A_TFACTOR1_COLOR (26)
2814 # define R200_TXC_ARG_A_TFACTOR1_ALPHA (27)
2815 # define R200_TXC_ARG_A_MASK (31 << 0)
2816 # define R200_TXC_ARG_A_SHIFT 0
2817 # define R200_TXC_ARG_B_ZERO (0 << 5)
2818 # define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5)
2819 # define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5)
2820 # define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5)
2821 # define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5)
2822 # define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5)
2823 # define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5)
2824 # define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5)
2825 # define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5)
2826 # define R200_TXC_ARG_B_R0_COLOR (10 << 5)
2827 # define R200_TXC_ARG_B_R0_ALPHA (11 << 5)
2828 # define R200_TXC_ARG_B_R1_COLOR (12 << 5)
2829 # define R200_TXC_ARG_B_R1_ALPHA (13 << 5)
2830 # define R200_TXC_ARG_B_R2_COLOR (14 << 5)
2831 # define R200_TXC_ARG_B_R2_ALPHA (15 << 5)
2832 # define R200_TXC_ARG_B_R3_COLOR (16 << 5)
2833 # define R200_TXC_ARG_B_R3_ALPHA (17 << 5)
2834 # define R200_TXC_ARG_B_R4_COLOR (18 << 5)
2835 # define R200_TXC_ARG_B_R4_ALPHA (19 << 5)
2836 # define R200_TXC_ARG_B_R5_COLOR (20 << 5)
2837 # define R200_TXC_ARG_B_R5_ALPHA (21 << 5)
2838 # define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5)
2839 # define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5)
2840 # define R200_TXC_ARG_B_MASK (31 << 5)
2841 # define R200_TXC_ARG_B_SHIFT 5
2842 # define R200_TXC_ARG_C_ZERO (0 << 10)
2843 # define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10)
2844 # define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10)
2845 # define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10)
2846 # define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10)
2847 # define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10)
2848 # define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10)
2849 # define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10)
2850 # define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10)
2851 # define R200_TXC_ARG_C_R0_COLOR (10 << 10)
2852 # define R200_TXC_ARG_C_R0_ALPHA (11 << 10)
2853 # define R200_TXC_ARG_C_R1_COLOR (12 << 10)
2854 # define R200_TXC_ARG_C_R1_ALPHA (13 << 10)
2855 # define R200_TXC_ARG_C_R2_COLOR (14 << 10)
2856 # define R200_TXC_ARG_C_R2_ALPHA (15 << 10)
2857 # define R200_TXC_ARG_C_R3_COLOR (16 << 10)
2858 # define R200_TXC_ARG_C_R3_ALPHA (17 << 10)
2859 # define R200_TXC_ARG_C_R4_COLOR (18 << 10)
2860 # define R200_TXC_ARG_C_R4_ALPHA (19 << 10)
2861 # define R200_TXC_ARG_C_R5_COLOR (20 << 10)
2862 # define R200_TXC_ARG_C_R5_ALPHA (21 << 10)
2863 # define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10)
2864 # define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10)
2865 # define R200_TXC_ARG_C_MASK (31 << 10)
2866 # define R200_TXC_ARG_C_SHIFT 10
2867 # define R200_TXC_COMP_ARG_A (1 << 16)
2868 # define R200_TXC_COMP_ARG_A_SHIFT (16)
2869 # define R200_TXC_BIAS_ARG_A (1 << 17)
2870 # define R200_TXC_SCALE_ARG_A (1 << 18)
2871 # define R200_TXC_NEG_ARG_A (1 << 19)
2872 # define R200_TXC_COMP_ARG_B (1 << 20)
2873 # define R200_TXC_COMP_ARG_B_SHIFT (20)
2874 # define R200_TXC_BIAS_ARG_B (1 << 21)
2875 # define R200_TXC_SCALE_ARG_B (1 << 22)
2876 # define R200_TXC_NEG_ARG_B (1 << 23)
2877 # define R200_TXC_COMP_ARG_C (1 << 24)
2878 # define R200_TXC_COMP_ARG_C_SHIFT (24)
2879 # define R200_TXC_BIAS_ARG_C (1 << 25)
2880 # define R200_TXC_SCALE_ARG_C (1 << 26)
2881 # define R200_TXC_NEG_ARG_C (1 << 27)
2882 # define R200_TXC_OP_MADD (0 << 28)
2883 # define R200_TXC_OP_CND0 (2 << 28)
2884 # define R200_TXC_OP_LERP (3 << 28)
2885 # define R200_TXC_OP_DOT3 (4 << 28)
2886 # define R200_TXC_OP_DOT4 (5 << 28)
2887 # define R200_TXC_OP_CONDITIONAL (6 << 28)
2888 # define R200_TXC_OP_DOT2_ADD (7 << 28)
2889 # define R200_TXC_OP_MASK (7 << 28)
2890 #define R200_PP_TXCBLEND2_0 0x2f04
2891 # define R200_TXC_TFACTOR_SEL_SHIFT 0
2892 # define R200_TXC_TFACTOR_SEL_MASK 0x7
2893 # define R200_TXC_TFACTOR1_SEL_SHIFT 4
2894 # define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4)
2895 # define R200_TXC_SCALE_SHIFT 8
2896 # define R200_TXC_SCALE_MASK (7 << 8)
2897 # define R200_TXC_SCALE_1X (0 << 8)
2898 # define R200_TXC_SCALE_2X (1 << 8)
2899 # define R200_TXC_SCALE_4X (2 << 8)
2900 # define R200_TXC_SCALE_8X (3 << 8)
2901 # define R200_TXC_SCALE_INV2 (5 << 8)
2902 # define R200_TXC_SCALE_INV4 (6 << 8)
2903 # define R200_TXC_SCALE_INV8 (7 << 8)
2904 # define R200_TXC_CLAMP_SHIFT 12
2905 # define R200_TXC_CLAMP_MASK (3 << 12)
2906 # define R200_TXC_CLAMP_WRAP (0 << 12)
2907 # define R200_TXC_CLAMP_0_1 (1 << 12)
2908 # define R200_TXC_CLAMP_8_8 (2 << 12)
2909 # define R200_TXC_OUTPUT_REG_MASK (7 << 16)
2910 # define R200_TXC_OUTPUT_REG_NONE (0 << 16)
2911 # define R200_TXC_OUTPUT_REG_R0 (1 << 16)
2912 # define R200_TXC_OUTPUT_REG_R1 (2 << 16)
2913 # define R200_TXC_OUTPUT_REG_R2 (3 << 16)
2914 # define R200_TXC_OUTPUT_REG_R3 (4 << 16)
2915 # define R200_TXC_OUTPUT_REG_R4 (5 << 16)
2916 # define R200_TXC_OUTPUT_REG_R5 (6 << 16)
2917 # define R200_TXC_OUTPUT_MASK_MASK (7 << 20)
2918 # define R200_TXC_OUTPUT_MASK_RGB (0 << 20)
2919 # define R200_TXC_OUTPUT_MASK_RG (1 << 20)
2920 # define R200_TXC_OUTPUT_MASK_RB (2 << 20)
2921 # define R200_TXC_OUTPUT_MASK_R (3 << 20)
2922 # define R200_TXC_OUTPUT_MASK_GB (4 << 20)
2923 # define R200_TXC_OUTPUT_MASK_G (5 << 20)
2924 # define R200_TXC_OUTPUT_MASK_B (6 << 20)
2925 # define R200_TXC_OUTPUT_MASK_NONE (7 << 20)
2926 # define R200_TXC_REPL_NORMAL 0
2927 # define R200_TXC_REPL_RED 1
2928 # define R200_TXC_REPL_GREEN 2
2929 # define R200_TXC_REPL_BLUE 3
2930 # define R200_TXC_REPL_ARG_A_SHIFT 26
2931 # define R200_TXC_REPL_ARG_A_MASK (3 << 26)
2932 # define R200_TXC_REPL_ARG_B_SHIFT 28
2933 # define R200_TXC_REPL_ARG_B_MASK (3 << 28)
2934 # define R200_TXC_REPL_ARG_C_SHIFT 30
2935 # define R200_TXC_REPL_ARG_C_MASK (3 << 30)
2936 #define R200_PP_TXABLEND_0 0x2f08
2937 # define R200_TXA_ARG_A_ZERO (0)
2938 # define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */
2939 # define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */
2940 # define R200_TXA_ARG_A_DIFFUSE_ALPHA (4)
2941 # define R200_TXA_ARG_A_DIFFUSE_BLUE (5)
2942 # define R200_TXA_ARG_A_SPECULAR_ALPHA (6)
2943 # define R200_TXA_ARG_A_SPECULAR_BLUE (7)
2944 # define R200_TXA_ARG_A_TFACTOR_ALPHA (8)
2945 # define R200_TXA_ARG_A_TFACTOR_BLUE (9)
2946 # define R200_TXA_ARG_A_R0_ALPHA (10)
2947 # define R200_TXA_ARG_A_R0_BLUE (11)
2948 # define R200_TXA_ARG_A_R1_ALPHA (12)
2949 # define R200_TXA_ARG_A_R1_BLUE (13)
2950 # define R200_TXA_ARG_A_R2_ALPHA (14)
2951 # define R200_TXA_ARG_A_R2_BLUE (15)
2952 # define R200_TXA_ARG_A_R3_ALPHA (16)
2953 # define R200_TXA_ARG_A_R3_BLUE (17)
2954 # define R200_TXA_ARG_A_R4_ALPHA (18)
2955 # define R200_TXA_ARG_A_R4_BLUE (19)
2956 # define R200_TXA_ARG_A_R5_ALPHA (20)
2957 # define R200_TXA_ARG_A_R5_BLUE (21)
2958 # define R200_TXA_ARG_A_TFACTOR1_ALPHA (26)
2959 # define R200_TXA_ARG_A_TFACTOR1_BLUE (27)
2960 # define R200_TXA_ARG_A_MASK (31 << 0)
2961 # define R200_TXA_ARG_A_SHIFT 0
2962 # define R200_TXA_ARG_B_ZERO (0 << 5)
2963 # define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */
2964 # define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */
2965 # define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5)
2966 # define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5)
2967 # define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5)
2968 # define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5)
2969 # define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5)
2970 # define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5)
2971 # define R200_TXA_ARG_B_R0_ALPHA (10 << 5)
2972 # define R200_TXA_ARG_B_R0_BLUE (11 << 5)
2973 # define R200_TXA_ARG_B_R1_ALPHA (12 << 5)
2974 # define R200_TXA_ARG_B_R1_BLUE (13 << 5)
2975 # define R200_TXA_ARG_B_R2_ALPHA (14 << 5)
2976 # define R200_TXA_ARG_B_R2_BLUE (15 << 5)
2977 # define R200_TXA_ARG_B_R3_ALPHA (16 << 5)
2978 # define R200_TXA_ARG_B_R3_BLUE (17 << 5)
2979 # define R200_TXA_ARG_B_R4_ALPHA (18 << 5)
2980 # define R200_TXA_ARG_B_R4_BLUE (19 << 5)
2981 # define R200_TXA_ARG_B_R5_ALPHA (20 << 5)
2982 # define R200_TXA_ARG_B_R5_BLUE (21 << 5)
2983 # define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5)
2984 # define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5)
2985 # define R200_TXA_ARG_B_MASK (31 << 5)
2986 # define R200_TXA_ARG_B_SHIFT 5
2987 # define R200_TXA_ARG_C_ZERO (0 << 10)
2988 # define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */
2989 # define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */
2990 # define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10)
2991 # define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10)
2992 # define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10)
2993 # define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10)
2994 # define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10)
2995 # define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10)
2996 # define R200_TXA_ARG_C_R0_ALPHA (10 << 10)
2997 # define R200_TXA_ARG_C_R0_BLUE (11 << 10)
2998 # define R200_TXA_ARG_C_R1_ALPHA (12 << 10)
2999 # define R200_TXA_ARG_C_R1_BLUE (13 << 10)
3000 # define R200_TXA_ARG_C_R2_ALPHA (14 << 10)
3001 # define R200_TXA_ARG_C_R2_BLUE (15 << 10)
3002 # define R200_TXA_ARG_C_R3_ALPHA (16 << 10)
3003 # define R200_TXA_ARG_C_R3_BLUE (17 << 10)
3004 # define R200_TXA_ARG_C_R4_ALPHA (18 << 10)
3005 # define R200_TXA_ARG_C_R4_BLUE (19 << 10)
3006 # define R200_TXA_ARG_C_R5_ALPHA (20 << 10)
3007 # define R200_TXA_ARG_C_R5_BLUE (21 << 10)
3008 # define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10)
3009 # define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10)
3010 # define R200_TXA_ARG_C_MASK (31 << 10)
3011 # define R200_TXA_ARG_C_SHIFT 10
3012 # define R200_TXA_COMP_ARG_A (1 << 16)
3013 # define R200_TXA_COMP_ARG_A_SHIFT (16)
3014 # define R200_TXA_BIAS_ARG_A (1 << 17)
3015 # define R200_TXA_SCALE_ARG_A (1 << 18)
3016 # define R200_TXA_NEG_ARG_A (1 << 19)
3017 # define R200_TXA_COMP_ARG_B (1 << 20)
3018 # define R200_TXA_COMP_ARG_B_SHIFT (20)
3019 # define R200_TXA_BIAS_ARG_B (1 << 21)
3020 # define R200_TXA_SCALE_ARG_B (1 << 22)
3021 # define R200_TXA_NEG_ARG_B (1 << 23)
3022 # define R200_TXA_COMP_ARG_C (1 << 24)
3023 # define R200_TXA_COMP_ARG_C_SHIFT (24)
3024 # define R200_TXA_BIAS_ARG_C (1 << 25)
3025 # define R200_TXA_SCALE_ARG_C (1 << 26)
3026 # define R200_TXA_NEG_ARG_C (1 << 27)
3027 # define R200_TXA_OP_MADD (0 << 28)
3028 # define R200_TXA_OP_CND0 (2 << 28)
3029 # define R200_TXA_OP_LERP (3 << 28)
3030 # define R200_TXA_OP_CONDITIONAL (6 << 28)
3031 # define R200_TXA_OP_MASK (7 << 28)
3032 #define R200_PP_TXABLEND2_0 0x2f0c
3033 # define R200_TXA_TFACTOR_SEL_SHIFT 0
3034 # define R200_TXA_TFACTOR_SEL_MASK 0x7
3035 # define R200_TXA_TFACTOR1_SEL_SHIFT 4
3036 # define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4)
3037 # define R200_TXA_SCALE_SHIFT 8
3038 # define R200_TXA_SCALE_MASK (7 << 8)
3039 # define R200_TXA_SCALE_1X (0 << 8)
3040 # define R200_TXA_SCALE_2X (1 << 8)
3041 # define R200_TXA_SCALE_4X (2 << 8)
3042 # define R200_TXA_SCALE_8X (3 << 8)
3043 # define R200_TXA_SCALE_INV2 (5 << 8)
3044 # define R200_TXA_SCALE_INV4 (6 << 8)
3045 # define R200_TXA_SCALE_INV8 (7 << 8)
3046 # define R200_TXA_CLAMP_SHIFT 12
3047 # define R200_TXA_CLAMP_MASK (3 << 12)
3048 # define R200_TXA_CLAMP_WRAP (0 << 12)
3049 # define R200_TXA_CLAMP_0_1 (1 << 12)
3050 # define R200_TXA_CLAMP_8_8 (2 << 12)
3051 # define R200_TXA_OUTPUT_REG_MASK (7 << 16)
3052 # define R200_TXA_OUTPUT_REG_NONE (0 << 16)
3053 # define R200_TXA_OUTPUT_REG_R0 (1 << 16)
3054 # define R200_TXA_OUTPUT_REG_R1 (2 << 16)
3055 # define R200_TXA_OUTPUT_REG_R2 (3 << 16)
3056 # define R200_TXA_OUTPUT_REG_R3 (4 << 16)
3057 # define R200_TXA_OUTPUT_REG_R4 (5 << 16)
3058 # define R200_TXA_OUTPUT_REG_R5 (6 << 16)
3059 # define R200_TXA_DOT_ALPHA (1 << 20)
3060 # define R200_TXA_REPL_NORMAL 0
3061 # define R200_TXA_REPL_RED 1
3062 # define R200_TXA_REPL_GREEN 2
3063 # define R200_TXA_REPL_ARG_A_SHIFT 26
3064 # define R200_TXA_REPL_ARG_A_MASK (3 << 26)
3065 # define R200_TXA_REPL_ARG_B_SHIFT 28
3066 # define R200_TXA_REPL_ARG_B_MASK (3 << 28)
3067 # define R200_TXA_REPL_ARG_C_SHIFT 30
3068 # define R200_TXA_REPL_ARG_C_MASK (3 << 30)
3070 #define R200_SE_VTX_FMT_0 0x2088
3071 # define R200_VTX_XY 0 /* always have xy */
3072 # define R200_VTX_Z0 (1<<0)
3073 # define R200_VTX_W0 (1<<1)
3074 # define R200_VTX_WEIGHT_COUNT_SHIFT (2)
3075 # define R200_VTX_PV_MATRIX_SEL (1<<5)
3076 # define R200_VTX_N0 (1<<6)
3077 # define R200_VTX_POINT_SIZE (1<<7)
3078 # define R200_VTX_DISCRETE_FOG (1<<8)
3079 # define R200_VTX_SHININESS_0 (1<<9)
3080 # define R200_VTX_SHININESS_1 (1<<10)
3081 # define R200_VTX_COLOR_NOT_PRESENT 0
3082 # define R200_VTX_PK_RGBA 1
3083 # define R200_VTX_FP_RGB 2
3084 # define R200_VTX_FP_RGBA 3
3085 # define R200_VTX_COLOR_MASK 3
3086 # define R200_VTX_COLOR_0_SHIFT 11
3087 # define R200_VTX_COLOR_1_SHIFT 13
3088 # define R200_VTX_COLOR_2_SHIFT 15
3089 # define R200_VTX_COLOR_3_SHIFT 17
3090 # define R200_VTX_COLOR_4_SHIFT 19
3091 # define R200_VTX_COLOR_5_SHIFT 21
3092 # define R200_VTX_COLOR_6_SHIFT 23
3093 # define R200_VTX_COLOR_7_SHIFT 25
3094 # define R200_VTX_XY1 (1<<28)
3095 # define R200_VTX_Z1 (1<<29)
3096 # define R200_VTX_W1 (1<<30)
3097 # define R200_VTX_N1 (1<<31)
3098 #define R200_SE_VTX_FMT_1 0x208c
3099 # define R200_VTX_TEX0_COMP_CNT_SHIFT 0
3100 # define R200_VTX_TEX1_COMP_CNT_SHIFT 3
3101 # define R200_VTX_TEX2_COMP_CNT_SHIFT 6
3102 # define R200_VTX_TEX3_COMP_CNT_SHIFT 9
3103 # define R200_VTX_TEX4_COMP_CNT_SHIFT 12
3104 # define R200_VTX_TEX5_COMP_CNT_SHIFT 15
3106 #define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090
3107 #define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094
3108 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
3109 # define R200_OUTPUT_XYZW (1<<0)
3110 # define R200_OUTPUT_COLOR_0 (1<<8)
3111 # define R200_OUTPUT_COLOR_1 (1<<9)
3112 # define R200_OUTPUT_TEX_0 (1<<16)
3113 # define R200_OUTPUT_TEX_1 (1<<17)
3114 # define R200_OUTPUT_TEX_2 (1<<18)
3115 # define R200_OUTPUT_TEX_3 (1<<19)
3116 # define R200_OUTPUT_TEX_4 (1<<20)
3117 # define R200_OUTPUT_TEX_5 (1<<21)
3118 # define R200_OUTPUT_TEX_MASK (0x3f<<16)
3119 # define R200_OUTPUT_DISCRETE_FOG (1<<24)
3120 # define R200_OUTPUT_PT_SIZE (1<<25)
3121 # define R200_FORCE_INORDER_PROC (1<<31)
3122 #define R200_PP_CNTL_X 0x2cc4
3123 #define R200_PP_TXMULTI_CTL_0 0x2c1c
3124 #define R200_SE_VTX_STATE_CNTL 0x2180
3125 # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
3127 /* Registers for CP and Microcode Engine */
3128 #define RADEON_CP_ME_RAM_ADDR 0x07d4
3129 #define RADEON_CP_ME_RAM_RADDR 0x07d8
3130 #define RADEON_CP_ME_RAM_DATAH 0x07dc
3131 #define RADEON_CP_ME_RAM_DATAL 0x07e0
3133 #define RADEON_CP_RB_BASE 0x0700
3134 #define RADEON_CP_RB_CNTL 0x0704
3135 #define RADEON_CP_RB_RPTR_ADDR 0x070c
3136 #define RADEON_CP_RB_RPTR 0x0710
3137 #define RADEON_CP_RB_WPTR 0x0714
3139 #define RADEON_CP_IB_BASE 0x0738
3140 #define RADEON_CP_IB_BUFSZ 0x073c
3142 #define RADEON_CP_CSQ_CNTL 0x0740
3143 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
3144 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
3145 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
3146 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
3147 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
3148 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
3149 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
3151 #define R300_CP_RESYNC_ADDR 0x778
3152 #define R300_CP_RESYNC_DATA 0x77c
3154 #define RADEON_CP_CSQ_STAT 0x07f8
3155 # define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)
3156 # define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)
3157 # define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)
3158 # define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)
3159 #define RADEON_CP_CSQ_ADDR 0x07f0
3160 #define RADEON_CP_CSQ_DATA 0x07f4
3161 #define RADEON_CP_CSQ_APER_PRIMARY 0x1000
3162 #define RADEON_CP_CSQ_APER_INDIRECT 0x1300
3164 #define RADEON_CP_RB_WPTR_DELAY 0x0718
3165 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
3166 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
3168 #define RADEON_AIC_CNTL 0x01d0
3169 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
3170 #define RADEON_AIC_LO_ADDR 0x01dc
3175 //#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0
3176 //efine RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2
3180 /* CP packet types */
3181 #define RADEON_CP_PACKET0 0x00000000
3182 #define RADEON_CP_PACKET1 0x40000000
3183 #define RADEON_CP_PACKET2 0x80000000
3184 #define RADEON_CP_PACKET3 0xC0000000
3185 # define RADEON_CP_PACKET_MASK 0xC0000000
3186 # define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
3187 # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)
3188 # define RADEON_CP_PACKET0_REG_MASK 0x000007ff
3189 # define R300_CP_PACKET0_REG_MASK 0x00001fff
3190 # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
3191 # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
3193 #define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000
3195 #define RADEON_CP_PACKET3_NOP 0xC0001000
3196 #define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
3197 #define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
3198 #define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
3199 #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
3200 #define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
3201 #define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
3202 #define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
3203 #define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
3204 #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
3205 #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
3206 #define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500
3207 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
3208 #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
3209 #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
3210 #define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
3211 #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
3212 #define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
3213 #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
3214 #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
3215 #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
3216 #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
3219 #define RADEON_CP_VC_FRMT_XY 0x00000000
3220 #define RADEON_CP_VC_FRMT_W0 0x00000001
3221 #define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002
3222 #define RADEON_CP_VC_FRMT_FPALPHA 0x00000004
3223 #define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008
3224 #define RADEON_CP_VC_FRMT_FPSPEC 0x00000010
3225 #define RADEON_CP_VC_FRMT_FPFOG 0x00000020
3226 #define RADEON_CP_VC_FRMT_PKSPEC 0x00000040
3227 #define RADEON_CP_VC_FRMT_ST0 0x00000080
3228 #define RADEON_CP_VC_FRMT_ST1 0x00000100
3229 #define RADEON_CP_VC_FRMT_Q1 0x00000200
3230 #define RADEON_CP_VC_FRMT_ST2 0x00000400
3231 #define RADEON_CP_VC_FRMT_Q2 0x00000800
3232 #define RADEON_CP_VC_FRMT_ST3 0x00001000
3233 #define RADEON_CP_VC_FRMT_Q3 0x00002000
3234 #define RADEON_CP_VC_FRMT_Q0 0x00004000
3235 #define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000
3236 #define RADEON_CP_VC_FRMT_N0 0x00040000
3237 #define RADEON_CP_VC_FRMT_XY1 0x08000000
3238 #define RADEON_CP_VC_FRMT_Z1 0x10000000
3239 #define RADEON_CP_VC_FRMT_W1 0x20000000
3240 #define RADEON_CP_VC_FRMT_N1 0x40000000
3241 #define RADEON_CP_VC_FRMT_Z 0x80000000
3243 #define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
3244 #define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
3245 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
3246 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
3247 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
3248 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
3249 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
3250 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
3251 #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
3252 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
3253 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
3254 #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
3255 #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
3256 #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
3257 #define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000
3258 #define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040
3259 #define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080
3260 #define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000
3261 #define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
3262 #define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000
3263 #define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200
3264 #define RADEON_CP_VC_CNTL_NUM_SHIFT 16
3266 #define RADEON_VS_MATRIX_0_ADDR 0
3267 #define RADEON_VS_MATRIX_1_ADDR 4
3268 #define RADEON_VS_MATRIX_2_ADDR 8
3269 #define RADEON_VS_MATRIX_3_ADDR 12
3270 #define RADEON_VS_MATRIX_4_ADDR 16
3271 #define RADEON_VS_MATRIX_5_ADDR 20
3272 #define RADEON_VS_MATRIX_6_ADDR 24
3273 #define RADEON_VS_MATRIX_7_ADDR 28
3274 #define RADEON_VS_MATRIX_8_ADDR 32
3275 #define RADEON_VS_MATRIX_9_ADDR 36
3276 #define RADEON_VS_MATRIX_10_ADDR 40
3277 #define RADEON_VS_MATRIX_11_ADDR 44
3278 #define RADEON_VS_MATRIX_12_ADDR 48
3279 #define RADEON_VS_MATRIX_13_ADDR 52
3280 #define RADEON_VS_MATRIX_14_ADDR 56
3281 #define RADEON_VS_MATRIX_15_ADDR 60
3282 #define RADEON_VS_LIGHT_AMBIENT_ADDR 64
3283 #define RADEON_VS_LIGHT_DIFFUSE_ADDR 72
3284 #define RADEON_VS_LIGHT_SPECULAR_ADDR 80
3285 #define RADEON_VS_LIGHT_DIRPOS_ADDR 88
3286 #define RADEON_VS_LIGHT_HWVSPOT_ADDR 96
3287 #define RADEON_VS_LIGHT_ATTENUATION_ADDR 104
3288 #define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112
3289 #define RADEON_VS_UCP_ADDR 116
3290 #define RADEON_VS_GLOBAL_AMBIENT_ADDR 122
3291 #define RADEON_VS_FOG_PARAM_ADDR 123
3292 #define RADEON_VS_EYE_VECTOR_ADDR 124
3294 #define RADEON_SS_LIGHT_DCD_ADDR 0
3295 #define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8
3296 #define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16
3297 #define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24
3298 #define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32
3299 #define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48
3300 #define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49
3301 #define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50
3302 #define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51
3303 #define RADEON_SS_SHININESS 60
3305 #define RADEON_TV_MASTER_CNTL 0x0800
3306 # define RADEON_TV_ASYNC_RST (1 << 0)
3307 # define RADEON_CRT_ASYNC_RST (1 << 1)
3308 # define RADEON_RESTART_PHASE_FIX (1 << 3)
3309 # define RADEON_TV_FIFO_ASYNC_RST (1 << 4)
3310 # define RADEON_VIN_ASYNC_RST (1 << 5)
3311 # define RADEON_AUD_ASYNC_RST (1 << 6)
3312 # define RADEON_DVS_ASYNC_RST (1 << 7)
3313 # define RADEON_CRT_FIFO_CE_EN (1 << 9)
3314 # define RADEON_TV_FIFO_CE_EN (1 << 10)
3315 # define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)
3316 # define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
3317 # define RADEON_TV_ON (1 << 31)
3318 #define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
3319 # define RADEON_Y_RED_EN (1 << 0)
3320 # define RADEON_C_GRN_EN (1 << 1)
3321 # define RADEON_CMP_BLU_EN (1 << 2)
3322 # define RADEON_DAC_DITHER_EN (1 << 3)
3323 # define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)
3324 # define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)
3325 # define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)
3326 # define RADEON_TV_FORCE_DAC_DATA_SHIFT 16
3327 #define RADEON_TV_RGB_CNTL 0x0804
3328 # define RADEON_SWITCH_TO_BLUE (1 << 4)
3329 # define RADEON_RGB_DITHER_EN (1 << 5)
3330 # define RADEON_RGB_SRC_SEL_MASK (3 << 8)
3331 # define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)
3332 # define RADEON_RGB_SRC_SEL_RMX (1 << 8)
3333 # define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)
3334 # define RADEON_RGB_CONVERT_BY_PASS (1 << 10)
3335 # define RADEON_UVRAM_READ_MARGIN_SHIFT 16
3336 # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20
3337 # define RADEON_TVOUT_SCALE_EN (1 << 26)
3338 #define RADEON_TV_SYNC_CNTL 0x0808
3339 # define RADEON_SYNC_OE (1 << 0)
3340 # define RADEON_SYNC_OUT (1 << 1)
3341 # define RADEON_SYNC_IN (1 << 2)
3342 # define RADEON_SYNC_PUB (1 << 3)
3343 # define RADEON_SYNC_PD (1 << 4)
3344 # define RADEON_TV_SYNC_IO_DRIVE (1 << 5)
3345 #define RADEON_TV_HTOTAL 0x080c
3346 #define RADEON_TV_HDISP 0x0810
3347 #define RADEON_TV_HSTART 0x0818
3348 #define RADEON_TV_HCOUNT 0x081C
3349 #define RADEON_TV_VTOTAL 0x0820
3350 #define RADEON_TV_VDISP 0x0824
3351 #define RADEON_TV_VCOUNT 0x0828
3352 #define RADEON_TV_FTOTAL 0x082c
3353 #define RADEON_TV_FCOUNT 0x0830
3354 #define RADEON_TV_FRESTART 0x0834
3355 #define RADEON_TV_HRESTART 0x0838
3356 #define RADEON_TV_VRESTART 0x083c
3357 #define RADEON_TV_HOST_READ_DATA 0x0840
3358 #define RADEON_TV_HOST_WRITE_DATA 0x0844
3359 #define RADEON_TV_HOST_RD_WT_CNTL 0x0848
3360 # define RADEON_HOST_FIFO_RD (1 << 12)
3361 # define RADEON_HOST_FIFO_RD_ACK (1 << 13)
3362 # define RADEON_HOST_FIFO_WT (1 << 14)
3363 # define RADEON_HOST_FIFO_WT_ACK (1 << 15)
3364 #define RADEON_TV_VSCALER_CNTL1 0x084c
3365 # define RADEON_UV_INC_MASK 0xffff
3366 # define RADEON_UV_INC_SHIFT 0
3367 # define RADEON_Y_W_EN (1 << 24)
3368 # define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */
3369 # define RADEON_Y_DEL_W_SIG_SHIFT 26
3370 #define RADEON_TV_TIMING_CNTL 0x0850
3371 # define RADEON_H_INC_MASK 0xfff
3372 # define RADEON_H_INC_SHIFT 0
3373 # define RADEON_REQ_Y_FIRST (1 << 19)
3374 # define RADEON_FORCE_BURST_ALWAYS (1 << 21)
3375 # define RADEON_UV_POST_SCALE_BYPASS (1 << 23)
3376 # define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24
3377 #define RADEON_TV_VSCALER_CNTL2 0x0854
3378 # define RADEON_DITHER_MODE (1 << 0)
3379 # define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)
3380 # define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)
3381 # define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)
3382 #define RADEON_TV_Y_FALL_CNTL 0x0858
3383 # define RADEON_Y_FALL_PING_PONG (1 << 16)
3384 # define RADEON_Y_COEF_EN (1 << 17)
3385 #define RADEON_TV_Y_RISE_CNTL 0x085c
3386 # define RADEON_Y_RISE_PING_PONG (1 << 16)
3387 #define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860
3388 #define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864
3389 # define RADEON_YUPSAMP_EN (1 << 0)
3390 # define RADEON_UVUPSAMP_EN (1 << 2)
3391 #define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868
3392 # define RADEON_Y_GAIN_LIMIT_SHIFT 0
3393 # define RADEON_UV_GAIN_LIMIT_SHIFT 16
3394 #define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c
3395 # define RADEON_Y_GAIN_SHIFT 0
3396 # define RADEON_UV_GAIN_SHIFT 16
3397 #define RADEON_TV_MODULATOR_CNTL1 0x0870
3398 # define RADEON_YFLT_EN (1 << 2)
3399 # define RADEON_UVFLT_EN (1 << 3)
3400 # define RADEON_ALT_PHASE_EN (1 << 6)
3401 # define RADEON_SYNC_TIP_LEVEL (1 << 7)
3402 # define RADEON_BLANK_LEVEL_SHIFT 8
3403 # define RADEON_SET_UP_LEVEL_SHIFT 16
3404 # define RADEON_SLEW_RATE_LIMIT (1 << 23)
3405 # define RADEON_CY_FILT_BLEND_SHIFT 28
3406 #define RADEON_TV_MODULATOR_CNTL2 0x0874
3407 # define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff
3408 # define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff
3409 # define RADEON_TV_V_BURST_LEVEL_SHIFT 16
3410 #define RADEON_TV_CRC_CNTL 0x0890
3411 #define RADEON_TV_UV_ADR 0x08ac
3412 # define RADEON_MAX_UV_ADR_MASK 0x000000ff
3413 # define RADEON_MAX_UV_ADR_SHIFT 0
3414 # define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00
3415 # define RADEON_TABLE1_BOT_ADR_SHIFT 8
3416 # define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000
3417 # define RADEON_TABLE3_TOP_ADR_SHIFT 16
3418 # define RADEON_HCODE_TABLE_SEL_MASK 0x06000000
3419 # define RADEON_HCODE_TABLE_SEL_SHIFT 25
3420 # define RADEON_VCODE_TABLE_SEL_MASK 0x18000000
3421 # define RADEON_VCODE_TABLE_SEL_SHIFT 27
3422 # define RADEON_TV_MAX_FIFO_ADDR 0x1a7
3423 # define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff
3424 #define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */
3425 #define RADEON_TV_PLL_CNTL 0x0021 /* PLL */
3426 # define RADEON_TV_M0LO_MASK 0xff
3427 # define RADEON_TV_M0HI_MASK 0x7
3428 # define RADEON_TV_M0HI_SHIFT 18
3429 # define RADEON_TV_N0LO_MASK 0x1ff
3430 # define RADEON_TV_N0LO_SHIFT 8
3431 # define RADEON_TV_N0HI_MASK 0x3
3432 # define RADEON_TV_N0HI_SHIFT 21
3433 # define RADEON_TV_P_MASK 0xf
3434 # define RADEON_TV_P_SHIFT 24
3435 # define RADEON_TV_SLIP_EN (1 << 23)
3436 # define RADEON_TV_DTO_EN (1 << 28)
3437 #define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */
3438 # define RADEON_TVPLL_RESET (1 << 1)
3439 # define RADEON_TVPLL_SLEEP (1 << 3)
3440 # define RADEON_TVPLL_REFCLK_SEL (1 << 4)
3441 # define RADEON_TVPCP_SHIFT 8
3442 # define RADEON_TVPCP_MASK (7 << 8)
3443 # define RADEON_TVPVG_SHIFT 11
3444 # define RADEON_TVPVG_MASK (7 << 11)
3445 # define RADEON_TVPDC_SHIFT 14
3446 # define RADEON_TVPDC_MASK (3 << 14)
3447 # define RADEON_TVPLL_TEST_DIS (1 << 31)
3448 # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)
3450 #define RS400_DISP2_REQ_CNTL1 0xe30
3451 # define RS400_DISP2_START_REQ_LEVEL_SHIFT 0
3452 # define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff
3453 # define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12
3454 # define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff
3455 # define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22
3456 # define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff
3457 #define RS400_DISP2_REQ_CNTL2 0xe34
3458 # define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12
3459 # define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff
3460 # define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22
3461 # define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff
3462 #define RS400_DMIF_MEM_CNTL1 0xe38
3463 # define RS400_DISP2_START_ADR_SHIFT 0
3464 # define RS400_DISP2_START_ADR_MASK 0x3ff
3465 # define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12
3466 # define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff
3467 # define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22
3468 # define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff
3469 #define RS400_DISP1_REQ_CNTL1 0xe3c
3470 # define RS400_DISP1_START_REQ_LEVEL_SHIFT 0
3471 # define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff
3472 # define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12
3473 # define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff
3474 # define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22
3475 # define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff
3477 #define RS690_MC_INDEX 0x78
3478 # define RS690_MC_INDEX_MASK 0x1ff
3479 # define RS690_MC_INDEX_WR_EN (1 << 9)
3480 # define RS690_MC_INDEX_WR_ACK 0x7f
3481 #define RS690_MC_DATA 0x7c
3483 #define RS690_MC_FB_LOCATION 0x100
3484 #define RS690_MC_AGP_LOCATION 0x101
3485 #define RS690_MC_AGP_BASE 0x102
3486 #define RS690_MC_AGP_BASE_2 0x103
3487 #define RS690_MC_STATUS 0x90
3488 #define RS690_MC_STATUS_IDLE (1 << 0)
3490 #define RS600_MC_INDEX 0x78
3491 # define RS600_MC_INDEX_MASK 0xff
3492 # define RS600_MC_INDEX_WR_EN (1 << 8)
3493 # define RS600_MC_INDEX_WR_ACK 0xff
3494 #define RS600_MC_DATA 0x7c
3496 #define RS600_MC_FB_LOCATION 0xA
3497 #define RS600_MC_STATUS 0x0
3498 #define RS600_MC_STATUS_IDLE (1 << 0)
3500 #define AVIVO_MC_INDEX 0x0070
3501 #define R520_MC_STATUS 0x00
3502 #define R520_MC_STATUS_IDLE (1<<1)
3503 #define RV515_MC_STATUS 0x08
3504 #define RV515_MC_STATUS_IDLE (1<<4)
3505 #define AVIVO_MC_DATA 0x0074
3507 #define RV515_MC_FB_LOCATION 0x1
3508 #define RV515_MC_AGP_LOCATION 0x2
3509 #define RV515_MC_AGP_BASE 0x3
3510 #define RV515_MC_AGP_BASE_2 0x4
3511 #define RV515_MC_CNTL 0x5
3512 # define RV515_MEM_NUM_CHANNELS_MASK 0x3
3513 #define R520_MC_FB_LOCATION 0x4
3514 #define R520_MC_AGP_LOCATION 0x5
3515 #define R520_MC_AGP_BASE 0x6
3516 #define R520_MC_AGP_BASE_2 0x7
3517 #define R520_MC_CNTL0 0x8
3518 # define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24)
3519 # define R520_MEM_NUM_CHANNELS_SHIFT 24
3520 # define R520_MC_CHANNEL_SIZE (1 << 23)
3522 #define R600_RAMCFG 0x2408
3523 # define R600_CHANSIZE (1 << 7)
3524 # define R600_CHANSIZE_OVERRIDE (1 << 10)
3526 #define AVIVO_HDP_FB_LOCATION 0x134
3528 #define AVIVO_VGA_RENDER_CONTROL 0x0300
3529 # define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16)
3530 #define AVIVO_D1VGA_CONTROL 0x0330
3531 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
3532 # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)
3533 # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)
3534 # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
3535 # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)
3536 # define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
3537 #define AVIVO_D2VGA_CONTROL 0x0338
3539 #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
3540 #define AVIVO_EXT1_PPLL_REF_DIV 0x404
3541 #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
3542 #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
3544 #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
3545 #define AVIVO_EXT2_PPLL_REF_DIV 0x414
3546 #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
3547 #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
3549 #define AVIVO_EXT1_PPLL_FB_DIV 0x430
3550 #define AVIVO_EXT2_PPLL_FB_DIV 0x434
3552 #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
3553 #define AVIVO_EXT1_PPLL_POST_DIV 0x43c
3555 #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
3556 #define AVIVO_EXT2_PPLL_POST_DIV 0x444
3558 #define AVIVO_EXT1_PPLL_CNTL 0x448
3559 #define AVIVO_EXT2_PPLL_CNTL 0x44c
3561 #define AVIVO_P1PLL_CNTL 0x450
3562 #define AVIVO_P2PLL_CNTL 0x454
3563 #define AVIVO_P1PLL_INT_SS_CNTL 0x458
3564 #define AVIVO_P2PLL_INT_SS_CNTL 0x45c
3565 #define AVIVO_P1PLL_TMDSA_CNTL 0x460
3566 #define AVIVO_P2PLL_LVTMA_CNTL 0x464
3568 #define AVIVO_PCLK_CRTC1_CNTL 0x480
3569 #define AVIVO_PCLK_CRTC2_CNTL 0x484
3571 #define AVIVO_D1CRTC_H_TOTAL 0x6000
3572 #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
3573 #define AVIVO_D1CRTC_H_SYNC_A 0x6008
3574 #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c
3575 #define AVIVO_D1CRTC_H_SYNC_B 0x6010
3576 #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
3578 #define AVIVO_D1CRTC_V_TOTAL 0x6020
3579 #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
3580 #define AVIVO_D1CRTC_V_SYNC_A 0x6028
3581 #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c
3582 #define AVIVO_D1CRTC_V_SYNC_B 0x6030
3583 #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
3585 #define AVIVO_D1CRTC_CONTROL 0x6080
3586 # define AVIVO_CRTC_EN (1 << 0)
3587 #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
3588 #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
3589 #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
3590 #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
3592 /* master controls */
3593 #define AVIVO_DC_CRTC_MASTER_EN 0x60f8
3594 #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
3596 #define AVIVO_D1GRPH_ENABLE 0x6100
3597 #define AVIVO_D1GRPH_CONTROL 0x6104
3598 # define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0)
3599 # define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0)
3600 # define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0)
3601 # define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0)
3603 # define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8)
3605 # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8)
3606 # define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8)
3607 # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8)
3608 # define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8)
3609 # define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8)
3611 # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8)
3612 # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8)
3613 # define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8)
3614 # define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8)
3617 # define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8)
3619 # define AVIVO_D1GRPH_SWAP_RB (1 << 16)
3620 # define AVIVO_D1GRPH_TILED (1 << 20)
3621 # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21)
3623 #define AVIVO_D1GRPH_LUT_SEL 0x6108
3624 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
3625 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
3626 #define AVIVO_D1GRPH_PITCH 0x6120
3627 #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
3628 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
3629 #define AVIVO_D1GRPH_X_START 0x612c
3630 #define AVIVO_D1GRPH_Y_START 0x6130
3631 #define AVIVO_D1GRPH_X_END 0x6134
3632 #define AVIVO_D1GRPH_Y_END 0x6138
3633 #define AVIVO_D1GRPH_UPDATE 0x6144
3634 # define AVIVO_D1GRPH_UPDATE_LOCK (1 << 16)
3635 #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
3637 #define AVIVO_D1CUR_CONTROL 0x6400
3638 # define AVIVO_D1CURSOR_EN (1 << 0)
3639 # define AVIVO_D1CURSOR_MODE_SHIFT 8
3640 # define AVIVO_D1CURSOR_MODE_MASK (3 << 8)
3641 # define AVIVO_D1CURSOR_MODE_24BPP 2
3642 #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
3643 #define AVIVO_D1CUR_SIZE 0x6410
3644 #define AVIVO_D1CUR_POSITION 0x6414
3645 #define AVIVO_D1CUR_HOT_SPOT 0x6418
3646 #define AVIVO_D1CUR_UPDATE 0x6424
3647 # define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)
3649 #define AVIVO_DC_LUT_RW_SELECT 0x6480
3650 #define AVIVO_DC_LUT_RW_MODE 0x6484
3651 #define AVIVO_DC_LUT_RW_INDEX 0x6488
3652 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c
3653 #define AVIVO_DC_LUT_PWL_DATA 0x6490
3654 #define AVIVO_DC_LUT_30_COLOR 0x6494
3655 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
3656 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
3657 #define AVIVO_DC_LUT_AUTOFILL 0x64a0
3659 #define AVIVO_DC_LUTA_CONTROL 0x64c0
3660 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
3661 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
3662 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
3663 #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
3664 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
3665 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
3667 #define AVIVO_D1MODE_DATA_FORMAT 0x6528
3668 # define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
3669 #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
3670 #define AVIVO_D1MODE_VIEWPORT_START 0x6580
3671 #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
3672 #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
3673 #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
3675 #define AVIVO_D1SCL_SCALER_ENABLE 0x6590
3676 #define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
3677 #define AVIVO_D1SCL_UPDATE 0x65cc
3678 # define AVIVO_D1SCL_UPDATE_LOCK (1 << 16)
3681 #define AVIVO_D2CRTC_H_TOTAL 0x6800
3682 #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
3683 #define AVIVO_D2CRTC_H_SYNC_A 0x6808
3684 #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
3685 #define AVIVO_D2CRTC_H_SYNC_B 0x6810
3686 #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
3688 #define AVIVO_D2CRTC_V_TOTAL 0x6820
3689 #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
3690 #define AVIVO_D2CRTC_V_SYNC_A 0x6828
3691 #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
3692 #define AVIVO_D2CRTC_V_SYNC_B 0x6830
3693 #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
3695 #define AVIVO_D2CRTC_CONTROL 0x6880
3696 #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
3697 #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
3698 #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
3699 #define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
3701 #define AVIVO_D2GRPH_ENABLE 0x6900
3702 #define AVIVO_D2GRPH_CONTROL 0x6904
3703 #define AVIVO_D2GRPH_LUT_SEL 0x6908
3704 #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
3705 #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
3706 #define AVIVO_D2GRPH_PITCH 0x6920
3707 #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
3708 #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
3709 #define AVIVO_D2GRPH_X_START 0x692c
3710 #define AVIVO_D2GRPH_Y_START 0x6930
3711 #define AVIVO_D2GRPH_X_END 0x6934
3712 #define AVIVO_D2GRPH_Y_END 0x6938
3713 #define AVIVO_D2GRPH_UPDATE 0x6944
3714 #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
3716 #define AVIVO_D2CUR_CONTROL 0x6c00
3717 #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
3718 #define AVIVO_D2CUR_SIZE 0x6c10
3719 #define AVIVO_D2CUR_POSITION 0x6c14
3721 #define AVIVO_D2MODE_VIEWPORT_START 0x6d80
3722 #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
3723 #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
3724 #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
3726 #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
3727 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
3729 #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214
3731 #define AVIVO_DACA_ENABLE 0x7800
3732 # define AVIVO_DAC_ENABLE (1 << 0)
3733 #define AVIVO_DACA_SOURCE_SELECT 0x7804
3734 # define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
3735 # define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
3736 # define AVIVO_DAC_SOURCE_TV (2 << 0)
3738 #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c
3739 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
3740 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
3741 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
3742 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
3743 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
3744 # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
3745 #define AVIVO_DACA_POWERDOWN 0x7850
3746 # define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
3747 # define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
3748 # define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
3749 # define AVIVO_DACA_POWERDOWN_RED (1 << 24)
3751 #define AVIVO_DACB_ENABLE 0x7a00
3752 #define AVIVO_DACB_SOURCE_SELECT 0x7a04
3753 #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c
3754 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
3755 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
3756 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
3757 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
3758 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
3759 # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
3760 #define AVIVO_DACB_POWERDOWN 0x7a50
3761 # define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
3762 # define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
3763 # define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
3764 # define AVIVO_DACB_POWERDOWN_RED
3766 #define AVIVO_TMDSA_CNTL 0x7880
3767 # define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
3768 # define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
3769 # define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
3770 # define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
3771 # define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
3772 # define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
3773 # define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
3774 #define AVIVO_TMDSA_SOURCE_SELECT 0x7884
3775 /* 78a8 appears to be some kind of (reasonably tolerant) clock?
3776 * 78d0 definitely hits the transmitter, definitely clock. */
3777 /* MYSTERY1 This appears to control dithering? */
3778 #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
3779 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
3780 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
3781 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
3782 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
3783 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
3784 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
3785 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
3786 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
3787 #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
3788 # define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
3789 # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
3790 # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
3791 # define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
3792 #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
3793 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
3794 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
3795 #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
3796 #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
3797 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
3798 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
3799 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
3800 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
3801 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
3802 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
3803 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
3804 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
3805 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
3806 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
3807 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
3808 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
3810 #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
3811 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
3812 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
3813 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
3814 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
3815 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
3816 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
3817 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
3818 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
3819 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
3820 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
3821 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
3822 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
3823 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
3824 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
3826 #define AVIVO_LVTMA_CNTL 0x7a80
3827 # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
3828 # define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
3829 # define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
3830 # define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
3831 # define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
3832 # define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
3833 # define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
3834 #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
3835 #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
3836 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
3837 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
3838 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
3839 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
3840 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
3841 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
3842 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
3843 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
3844 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
3848 #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
3849 # define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
3850 # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
3851 # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
3852 # define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
3854 #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
3855 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
3856 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
3857 #define R500_LVTMA_CLOCK_ENABLE 0x7b00
3858 #define R600_LVTMA_CLOCK_ENABLE 0x7b04
3860 #define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
3861 #define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
3862 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
3863 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
3864 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
3865 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
3866 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
3867 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
3868 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
3869 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
3870 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
3871 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
3872 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
3874 #define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
3875 #define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
3876 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
3877 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
3878 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
3879 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
3880 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
3881 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
3882 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
3883 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
3884 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
3885 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
3886 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
3887 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
3888 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
3889 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
3891 #define R500_LVTMA_PWRSEQ_CNTL 0x7af0
3892 #define R600_LVTMA_PWRSEQ_CNTL 0x7af4
3893 # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
3894 # define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
3895 # define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
3896 # define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
3897 # define AVIVO_LVTMA_SYNCEN (1 << 8)
3898 # define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
3899 # define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
3900 # define AVIVO_LVTMA_DIGON (1 << 16)
3901 # define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
3902 # define AVIVO_LVTMA_DIGON_POL (1 << 18)
3903 # define AVIVO_LVTMA_BLON (1 << 24)
3904 # define AVIVO_LVTMA_BLON_OVRD (1 << 25)
3905 # define AVIVO_LVTMA_BLON_POL (1 << 26)
3907 #define R500_LVTMA_PWRSEQ_STATE 0x7af4
3908 #define R600_LVTMA_PWRSEQ_STATE 0x7af8
3909 # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
3910 # define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
3911 # define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
3912 # define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
3913 # define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
3914 # define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
3916 #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
3917 # define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
3918 # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
3919 # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8
3921 #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988
3923 #define AVIVO_GPIO_0 0x7e30
3924 #define AVIVO_GPIO_1 0x7e40
3925 #define AVIVO_GPIO_2 0x7e50
3926 #define AVIVO_GPIO_3 0x7e60
3928 #define AVIVO_DC_GPIO_HPD_Y 0x7e9c
3930 #define AVIVO_I2C_STATUS 0x7d30
3931 # define AVIVO_I2C_STATUS_DONE (1 << 0)
3932 # define AVIVO_I2C_STATUS_NACK (1 << 1)
3933 # define AVIVO_I2C_STATUS_HALT (1 << 2)
3934 # define AVIVO_I2C_STATUS_GO (1 << 3)
3935 # define AVIVO_I2C_STATUS_MASK 0x7
3936 /* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
3938 # define AVIVO_I2C_STATUS_CMD_RESET 0x7
3939 # define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3)
3940 #define AVIVO_I2C_STOP 0x7d34
3941 #define AVIVO_I2C_START_CNTL 0x7d38
3942 # define AVIVO_I2C_START (1 << 8)
3943 # define AVIVO_I2C_CONNECTOR0 (0 << 16)
3944 # define AVIVO_I2C_CONNECTOR1 (1 << 16)
3945 #define R520_I2C_START (1<<0)
3946 #define R520_I2C_STOP (1<<1)
3947 #define R520_I2C_RX (1<<2)
3948 #define R520_I2C_EN (1<<8)
3949 #define R520_I2C_DDC1 (0<<16)
3950 #define R520_I2C_DDC2 (1<<16)
3951 #define R520_I2C_DDC3 (2<<16)
3952 #define R520_I2C_DDC_MASK (3<<16)
3953 #define AVIVO_I2C_CONTROL2 0x7d3c
3954 # define AVIVO_I2C_7D3C_SIZE_SHIFT 8
3955 # define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8)
3956 #define AVIVO_I2C_CONTROL3 0x7d40
3957 /* Reading is done 4 bytes at a time: read the bottom 8 bits from
3958 * 7d44, four times in a row.
3959 * Writing is a little more complex. First write DATA with
3960 * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
3961 * magic number, zz is, I think, the slave address, and yy is the byte
3962 * you want to write. */
3963 #define AVIVO_I2C_DATA 0x7d44
3964 #define R520_I2C_ADDR_COUNT_MASK (0x7)
3965 #define R520_I2C_DATA_COUNT_SHIFT (8)
3966 #define R520_I2C_DATA_COUNT_MASK (0xF00)
3967 #define AVIVO_I2C_CNTL 0x7d50
3968 # define AVIVO_I2C_EN (1 << 0)
3969 # define AVIVO_I2C_RESET (1 << 8)
3971 #define R600_GENERAL_PWRMGT 0x618
3972 # define R600_OPEN_DRAIN_PADS (1 << 11)
3974 #define R600_LOWER_GPIO_ENABLE 0x710
3975 #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
3976 #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
3977 #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
3978 #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
3980 #define R600_MC_VM_FB_LOCATION 0x2180
3981 #define R600_MC_VM_AGP_TOP 0x2184
3982 #define R600_MC_VM_AGP_BOT 0x2188
3983 #define R600_MC_VM_AGP_BASE 0x218c
3984 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
3985 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
3986 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
3988 #define R700_MC_VM_FB_LOCATION 0x2024
3990 #define R600_HDP_NONSURFACE_BASE 0x2c04
3992 #define R600_BUS_CNTL 0x5420
3993 #define R600_CONFIG_CNTL 0x5424
3994 #define R600_CONFIG_MEMSIZE 0x5428
3995 #define R600_CONFIG_F0_BASE 0x542C
3996 #define R600_CONFIG_APER_SIZE 0x5430
3998 #define R600_ROM_CNTL 0x1600
3999 # define R600_SCK_OVERWRITE (1 << 1)
4000 # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
4001 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
4003 #define R600_BIOS_0_SCRATCH 0x1724
4004 #define R600_BIOS_1_SCRATCH 0x1728
4005 #define R600_BIOS_2_SCRATCH 0x172c
4006 #define R600_BIOS_3_SCRATCH 0x1730
4007 #define R600_BIOS_4_SCRATCH 0x1734
4008 #define R600_BIOS_5_SCRATCH 0x1738
4009 #define R600_BIOS_6_SCRATCH 0x173c
4010 #define R600_BIOS_7_SCRATCH 0x1740
4012 #define R300_GB_TILE_CONFIG 0x4018
4013 # define R300_ENABLE_TILING (1 << 0)
4014 # define R300_PIPE_COUNT_RV350 (0 << 1)
4015 # define R300_PIPE_COUNT_R300 (3 << 1)
4016 # define R300_PIPE_COUNT_R420_3P (6 << 1)
4017 # define R300_PIPE_COUNT_R420 (7 << 1)
4018 # define R300_TILE_SIZE_8 (0 << 4)
4019 # define R300_TILE_SIZE_16 (1 << 4)
4020 # define R300_TILE_SIZE_32 (2 << 4)
4021 # define R300_SUBPIXEL_1_12 (0 << 16)
4022 # define R300_SUBPIXEL_1_16 (1 << 16)
4023 #define R300_GB_ENABLE 0x4008
4024 #define R300_GB_AA_CONFIG 0x4020
4025 #define R400_GB_PIPE_SELECT 0x402c
4026 #define R300_GB_MSPOS0 0x4010
4027 # define R300_MS_X0_SHIFT 0
4028 # define R300_MS_Y0_SHIFT 4
4029 # define R300_MS_X1_SHIFT 8
4030 # define R300_MS_Y1_SHIFT 12
4031 # define R300_MS_X2_SHIFT 16
4032 # define R300_MS_Y2_SHIFT 20
4033 # define R300_MSBD0_Y_SHIFT 24
4034 # define R300_MSBD0_X_SHIFT 28
4035 #define R300_GB_MSPOS1 0x4014
4036 # define R300_MS_X3_SHIFT 0
4037 # define R300_MS_Y3_SHIFT 4
4038 # define R300_MS_X4_SHIFT 8
4039 # define R300_MS_Y4_SHIFT 12
4040 # define R300_MS_X5_SHIFT 16
4041 # define R300_MS_Y5_SHIFT 20
4042 # define R300_MSBD1_SHIFT 24
4044 #define R300_GA_ENHANCE 0x4274
4045 # define R300_GA_DEADLOCK_CNTL (1 << 0)
4046 # define R300_GA_FASTSYNC_CNTL (1 << 1)
4048 #define R300_GA_POLY_MODE 0x4288
4049 # define R300_FRONT_PTYPE_POINT (0 << 4)
4050 # define R300_FRONT_PTYPE_LINE (1 << 4)
4051 # define R300_FRONT_PTYPE_TRIANGE (2 << 4)
4052 # define R300_BACK_PTYPE_POINT (0 << 7)
4053 # define R300_BACK_PTYPE_LINE (1 << 7)
4054 # define R300_BACK_PTYPE_TRIANGE (2 << 7)
4055 #define R300_GA_ROUND_MODE 0x428c
4056 # define R300_GEOMETRY_ROUND_TRUNC (0 << 0)
4057 # define R300_GEOMETRY_ROUND_NEAREST (1 << 0)
4058 # define R300_COLOR_ROUND_TRUNC (0 << 2)
4059 # define R300_COLOR_ROUND_NEAREST (1 << 2)
4060 #define R300_GA_COLOR_CONTROL 0x4278
4061 # define R300_RGB0_SHADING_SOLID (0 << 0)
4062 # define R300_RGB0_SHADING_FLAT (1 << 0)
4063 # define R300_RGB0_SHADING_GOURAUD (2 << 0)
4064 # define R300_ALPHA0_SHADING_SOLID (0 << 2)
4065 # define R300_ALPHA0_SHADING_FLAT (1 << 2)
4066 # define R300_ALPHA0_SHADING_GOURAUD (2 << 2)
4067 # define R300_RGB1_SHADING_SOLID (0 << 4)
4068 # define R300_RGB1_SHADING_FLAT (1 << 4)
4069 # define R300_RGB1_SHADING_GOURAUD (2 << 4)
4070 # define R300_ALPHA1_SHADING_SOLID (0 << 6)
4071 # define R300_ALPHA1_SHADING_FLAT (1 << 6)
4072 # define R300_ALPHA1_SHADING_GOURAUD (2 << 6)
4073 # define R300_RGB2_SHADING_SOLID (0 << 8)
4074 # define R300_RGB2_SHADING_FLAT (1 << 8)
4075 # define R300_RGB2_SHADING_GOURAUD (2 << 8)
4076 # define R300_ALPHA2_SHADING_SOLID (0 << 10)
4077 # define R300_ALPHA2_SHADING_FLAT (1 << 10)
4078 # define R300_ALPHA2_SHADING_GOURAUD (2 << 10)
4079 # define R300_RGB3_SHADING_SOLID (0 << 12)
4080 # define R300_RGB3_SHADING_FLAT (1 << 12)
4081 # define R300_RGB3_SHADING_GOURAUD (2 << 12)
4082 # define R300_ALPHA3_SHADING_SOLID (0 << 14)
4083 # define R300_ALPHA3_SHADING_FLAT (1 << 14)
4084 # define R300_ALPHA3_SHADING_GOURAUD (2 << 14)
4085 #define R300_GA_OFFSET 0x4290
4087 #define R500_SU_REG_DEST 0x42c8
4089 #define R300_VAP_CNTL_STATUS 0x2140
4090 # define R300_PVS_BYPASS (1 << 8)
4091 #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
4092 #define R300_VAP_CNTL 0x2080
4093 # define R300_PVS_NUM_SLOTS_SHIFT 0
4094 # define R300_PVS_NUM_CNTLRS_SHIFT 4
4095 # define R300_PVS_NUM_FPUS_SHIFT 8
4096 # define R300_VF_MAX_VTX_NUM_SHIFT 18
4097 # define R300_GL_CLIP_SPACE_DEF (0 << 22)
4098 # define R300_DX_CLIP_SPACE_DEF (1 << 22)
4099 # define R500_TCL_STATE_OPTIMIZATION (1 << 23)
4100 #define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC
4101 #define R300_VAP_PROG_STREAM_CNTL_0 0x2150
4102 # define R300_DATA_TYPE_0_SHIFT 0
4103 # define R300_DATA_TYPE_FLOAT_1 0
4104 # define R300_DATA_TYPE_FLOAT_2 1
4105 # define R300_DATA_TYPE_FLOAT_3 2
4106 # define R300_DATA_TYPE_FLOAT_4 3
4107 # define R300_DATA_TYPE_BYTE 4
4108 # define R300_DATA_TYPE_D3DCOLOR 5
4109 # define R300_DATA_TYPE_SHORT_2 6
4110 # define R300_DATA_TYPE_SHORT_4 7
4111 # define R300_DATA_TYPE_VECTOR_3_TTT 8
4112 # define R300_DATA_TYPE_VECTOR_3_EET 9
4113 # define R300_SKIP_DWORDS_0_SHIFT 4
4114 # define R300_DST_VEC_LOC_0_SHIFT 8
4115 # define R300_LAST_VEC_0 (1 << 13)
4116 # define R300_SIGNED_0 (1 << 14)
4117 # define R300_NORMALIZE_0 (1 << 15)
4118 # define R300_DATA_TYPE_1_SHIFT 16
4119 # define R300_SKIP_DWORDS_1_SHIFT 20
4120 # define R300_DST_VEC_LOC_1_SHIFT 24
4121 # define R300_LAST_VEC_1 (1 << 29)
4122 # define R300_SIGNED_1 (1 << 30)
4123 # define R300_NORMALIZE_1 (1 << 31)
4124 #define R300_VAP_PROG_STREAM_CNTL_1 0x2154
4125 # define R300_DATA_TYPE_2_SHIFT 0
4126 # define R300_SKIP_DWORDS_2_SHIFT 4
4127 # define R300_DST_VEC_LOC_2_SHIFT 8
4128 # define R300_LAST_VEC_2 (1 << 13)
4129 # define R300_SIGNED_2 (1 << 14)
4130 # define R300_NORMALIZE_2 (1 << 15)
4131 # define R300_DATA_TYPE_3_SHIFT 16
4132 # define R300_SKIP_DWORDS_3_SHIFT 20
4133 # define R300_DST_VEC_LOC_3_SHIFT 24
4134 # define R300_LAST_VEC_3 (1 << 29)
4135 # define R300_SIGNED_3 (1 << 30)
4136 # define R300_NORMALIZE_3 (1 << 31)
4137 #define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0
4138 # define R300_SWIZZLE_SELECT_X_0_SHIFT 0
4139 # define R300_SWIZZLE_SELECT_Y_0_SHIFT 3
4140 # define R300_SWIZZLE_SELECT_Z_0_SHIFT 6
4141 # define R300_SWIZZLE_SELECT_W_0_SHIFT 9
4142 # define R300_SWIZZLE_SELECT_X 0
4143 # define R300_SWIZZLE_SELECT_Y 1
4144 # define R300_SWIZZLE_SELECT_Z 2
4145 # define R300_SWIZZLE_SELECT_W 3
4146 # define R300_SWIZZLE_SELECT_FP_ZERO 4
4147 # define R300_SWIZZLE_SELECT_FP_ONE 5
4148 # define R300_WRITE_ENA_0_SHIFT 12
4149 # define R300_WRITE_ENA_X 1
4150 # define R300_WRITE_ENA_Y 2
4151 # define R300_WRITE_ENA_Z 4
4152 # define R300_WRITE_ENA_W 8
4153 # define R300_SWIZZLE_SELECT_X_1_SHIFT 16
4154 # define R300_SWIZZLE_SELECT_Y_1_SHIFT 19
4155 # define R300_SWIZZLE_SELECT_Z_1_SHIFT 22
4156 # define R300_SWIZZLE_SELECT_W_1_SHIFT 25
4157 # define R300_WRITE_ENA_1_SHIFT 28
4158 #define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4
4159 # define R300_SWIZZLE_SELECT_X_2_SHIFT 0
4160 # define R300_SWIZZLE_SELECT_Y_2_SHIFT 3
4161 # define R300_SWIZZLE_SELECT_Z_2_SHIFT 6
4162 # define R300_SWIZZLE_SELECT_W_2_SHIFT 9
4163 # define R300_WRITE_ENA_2_SHIFT 12
4164 # define R300_SWIZZLE_SELECT_X_3_SHIFT 16
4165 # define R300_SWIZZLE_SELECT_Y_3_SHIFT 19
4166 # define R300_SWIZZLE_SELECT_Z_3_SHIFT 22
4167 # define R300_SWIZZLE_SELECT_W_3_SHIFT 25
4168 # define R300_WRITE_ENA_3_SHIFT 28
4169 #define R300_VAP_PVS_CODE_CNTL_0 0x22D0
4170 # define R300_PVS_FIRST_INST_SHIFT 0
4171 # define R300_PVS_XYZW_VALID_INST_SHIFT 10
4172 # define R300_PVS_LAST_INST_SHIFT 20
4173 #define R300_VAP_PVS_CODE_CNTL_1 0x22D8
4174 # define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0
4175 #define R300_VAP_PVS_VECTOR_INDX_REG 0x2200
4176 #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204
4177 /* PVS instructions */
4178 /* Opcode and dst instruction */
4179 #define R300_PVS_DST_OPCODE(x) (x << 0)
4181 # define R300_VECTOR_NO_OP 0
4182 # define R300_VE_DOT_PRODUCT 1
4183 # define R300_VE_MULTIPLY 2
4184 # define R300_VE_ADD 3
4185 # define R300_VE_MULTIPLY_ADD 4
4186 # define R300_VE_DISTANCE_VECTOR 5
4187 # define R300_VE_FRACTION 6
4188 # define R300_VE_MAXIMUM 7
4189 # define R300_VE_MINIMUM 8
4190 # define R300_VE_SET_GREATER_THAN_EQUAL 9
4191 # define R300_VE_SET_LESS_THAN 10
4192 # define R300_VE_MULTIPLYX2_ADD 11
4193 # define R300_VE_MULTIPLY_CLAMP 12
4194 # define R300_VE_FLT2FIX_DX 13
4195 # define R300_VE_FLT2FIX_DX_RND 14
4196 /* R500 additions */
4197 # define R500_VE_PRED_SET_EQ_PUSH 15
4198 # define R500_VE_PRED_SET_GT_PUSH 16
4199 # define R500_VE_PRED_SET_GTE_PUSH 17
4200 # define R500_VE_PRED_SET_NEQ_PUSH 18
4201 # define R500_VE_COND_WRITE_EQ 19
4202 # define R500_VE_COND_WRITE_GT 20
4203 # define R500_VE_COND_WRITE_GTE 21
4204 # define R500_VE_COND_WRITE_NEQ 22
4205 # define R500_VE_COND_MUX_EQ 23
4206 # define R500_VE_COND_MUX_GT 24
4207 # define R500_VE_COND_MUX_GTE 25
4208 # define R500_VE_SET_GREATER_THAN 26
4209 # define R500_VE_SET_EQUAL 27
4210 # define R500_VE_SET_NOT_EQUAL 28
4212 # define R300_MATH_NO_OP 0
4213 # define R300_ME_EXP_BASE2_DX 1
4214 # define R300_ME_LOG_BASE2_DX 2
4215 # define R300_ME_EXP_BASEE_FF 3
4216 # define R300_ME_LIGHT_COEFF_DX 4
4217 # define R300_ME_POWER_FUNC_FF 5
4218 # define R300_ME_RECIP_DX 6
4219 # define R300_ME_RECIP_FF 7
4220 # define R300_ME_RECIP_SQRT_DX 8
4221 # define R300_ME_RECIP_SQRT_FF 9
4222 # define R300_ME_MULTIPLY 10
4223 # define R300_ME_EXP_BASE2_FULL_DX 11
4224 # define R300_ME_LOG_BASE2_FULL_DX 12
4225 # define R300_ME_POWER_FUNC_FF_CLAMP_B 13
4226 # define R300_ME_POWER_FUNC_FF_CLAMP_B1 14
4227 # define R300_ME_POWER_FUNC_FF_CLAMP_01 15
4228 # define R300_ME_SIN 16
4229 # define R300_ME_COS 17
4230 /* R500 additions */
4231 # define R500_ME_LOG_BASE2_IEEE 18
4232 # define R500_ME_RECIP_IEEE 19
4233 # define R500_ME_RECIP_SQRT_IEEE 20
4234 # define R500_ME_PRED_SET_EQ 21
4235 # define R500_ME_PRED_SET_GT 22
4236 # define R500_ME_PRED_SET_GTE 23
4237 # define R500_ME_PRED_SET_NEQ 24
4238 # define R500_ME_PRED_SET_CLR 25
4239 # define R500_ME_PRED_SET_INV 26
4240 # define R500_ME_PRED_SET_POP 27
4241 # define R500_ME_PRED_SET_RESTORE 28
4243 # define R300_PVS_MACRO_OP_2CLK_MADD 0
4244 # define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1
4245 #define R300_PVS_DST_MATH_INST (1 << 6)
4246 #define R300_PVS_DST_MACRO_INST (1 << 7)
4247 #define R300_PVS_DST_REG_TYPE(x) (x << 8)
4248 # define R300_PVS_DST_REG_TEMPORARY 0
4249 # define R300_PVS_DST_REG_A0 1
4250 # define R300_PVS_DST_REG_OUT 2
4251 # define R500_PVS_DST_REG_OUT_REPL_X 3
4252 # define R300_PVS_DST_REG_ALT_TEMPORARY 4
4253 # define R300_PVS_DST_REG_INPUT 5
4254 #define R300_PVS_DST_ADDR_MODE_1 (1 << 12)
4255 #define R300_PVS_DST_OFFSET(x) (x << 13)
4256 #define R300_PVS_DST_WE_X (1 << 20)
4257 #define R300_PVS_DST_WE_Y (1 << 21)
4258 #define R300_PVS_DST_WE_Z (1 << 22)
4259 #define R300_PVS_DST_WE_W (1 << 23)
4260 #define R300_PVS_DST_VE_SAT (1 << 24)
4261 #define R300_PVS_DST_ME_SAT (1 << 25)
4262 #define R300_PVS_DST_PRED_ENABLE (1 << 26)
4263 #define R300_PVS_DST_PRED_SENSE (1 << 27)
4264 #define R300_PVS_DST_DUAL_MATH_OP (1 << 28)
4265 #define R300_PVS_DST_ADDR_SEL(x) (x << 29)
4266 #define R300_PVS_DST_ADDR_MODE_0 (1 << 31)
4267 /* src operand instruction */
4268 #define R300_PVS_SRC_REG_TYPE(x) (x << 0)
4269 # define R300_PVS_SRC_REG_TEMPORARY 0
4270 # define R300_PVS_SRC_REG_INPUT 1
4271 # define R300_PVS_SRC_REG_CONSTANT 2
4272 # define R300_PVS_SRC_REG_ALT_TEMPORARY 3
4273 #define R300_SPARE_0 (1 << 2)
4274 #define R300_PVS_SRC_ABS_XYZW (1 << 3)
4275 #define R300_PVS_SRC_ADDR_MODE_0 (1 << 4)
4276 #define R300_PVS_SRC_OFFSET(x) (x << 5)
4277 #define R300_PVS_SRC_SWIZZLE_X(x) (x << 13)
4278 #define R300_PVS_SRC_SWIZZLE_Y(x) (x << 16)
4279 #define R300_PVS_SRC_SWIZZLE_Z(x) (x << 19)
4280 #define R300_PVS_SRC_SWIZZLE_W(x) (x << 22)
4281 # define R300_PVS_SRC_SELECT_X 0
4282 # define R300_PVS_SRC_SELECT_Y 1
4283 # define R300_PVS_SRC_SELECT_Z 2
4284 # define R300_PVS_SRC_SELECT_W 3
4285 # define R300_PVS_SRC_SELECT_FORCE_0 4
4286 # define R300_PVS_SRC_SELECT_FORCE_1 5
4287 #define R300_PVS_SRC_NEG_X (1 << 25)
4288 #define R300_PVS_SRC_NEG_Y (1 << 26)
4289 #define R300_PVS_SRC_NEG_Z (1 << 27)
4290 #define R300_PVS_SRC_NEG_W (1 << 28)
4291 #define R300_PVS_SRC_ADDR_SEL(x) (x << 29)
4292 #define R300_PVS_SRC_ADDR_MODE_1 (1 << 31)
4294 #define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC
4295 #define R300_VAP_OUT_VTX_FMT_0 0x2090
4296 # define R300_VTX_POS_PRESENT (1 << 0)
4297 # define R300_VTX_COLOR_0_PRESENT (1 << 1)
4298 # define R300_VTX_COLOR_1_PRESENT (1 << 2)
4299 # define R300_VTX_COLOR_2_PRESENT (1 << 3)
4300 # define R300_VTX_COLOR_3_PRESENT (1 << 4)
4301 # define R300_VTX_PT_SIZE_PRESENT (1 << 16)
4302 #define R300_VAP_OUT_VTX_FMT_1 0x2094
4303 # define R300_TEX_0_COMP_CNT_SHIFT 0
4304 # define R300_TEX_1_COMP_CNT_SHIFT 3
4305 # define R300_TEX_2_COMP_CNT_SHIFT 6
4306 # define R300_TEX_3_COMP_CNT_SHIFT 9
4307 # define R300_TEX_4_COMP_CNT_SHIFT 12
4308 # define R300_TEX_5_COMP_CNT_SHIFT 15
4309 # define R300_TEX_6_COMP_CNT_SHIFT 18
4310 # define R300_TEX_7_COMP_CNT_SHIFT 21
4311 #define R300_VAP_VTX_SIZE 0x20b4
4312 #define R300_VAP_GB_VERT_CLIP_ADJ 0x2220
4313 #define R300_VAP_GB_VERT_DISC_ADJ 0x2224
4314 #define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228
4315 #define R300_VAP_GB_HORZ_DISC_ADJ 0x222c
4316 #define R300_VAP_CLIP_CNTL 0x221c
4317 # define R300_UCP_ENA_0 (1 << 0)
4318 # define R300_UCP_ENA_1 (1 << 1)
4319 # define R300_UCP_ENA_2 (1 << 2)
4320 # define R300_UCP_ENA_3 (1 << 3)
4321 # define R300_UCP_ENA_4 (1 << 4)
4322 # define R300_UCP_ENA_5 (1 << 5)
4323 # define R300_PS_UCP_MODE_SHIFT 14
4324 # define R300_CLIP_DISABLE (1 << 16)
4325 # define R300_UCP_CULL_ONLY_ENA (1 << 17)
4326 # define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18)
4327 #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
4329 #define R500_VAP_INDEX_OFFSET 0x208c
4331 #define R300_SU_TEX_WRAP 0x42a0
4332 #define R300_SU_POLY_OFFSET_ENABLE 0x42b4
4333 #define R300_SU_CULL_MODE 0x42b8
4334 # define R300_CULL_FRONT (1 << 0)
4335 # define R300_CULL_BACK (1 << 1)
4336 # define R300_FACE_POS (0 << 2)
4337 # define R300_FACE_NEG (1 << 2)
4338 #define R300_SU_DEPTH_SCALE 0x42c0
4339 #define R300_SU_DEPTH_OFFSET 0x42c4
4341 #define R300_RS_COUNT 0x4300
4342 # define R300_RS_COUNT_IT_COUNT_SHIFT 0
4343 # define R300_RS_COUNT_IC_COUNT_SHIFT 7
4344 # define R300_RS_COUNT_HIRES_EN (1 << 18)
4346 #define R300_RS_IP_0 0x4310
4347 #define R300_RS_IP_1 0x4314
4348 # define R300_RS_TEX_PTR(x) (x << 0)
4349 # define R300_RS_COL_PTR(x) (x << 6)
4350 # define R300_RS_COL_FMT(x) (x << 9)
4351 # define R300_RS_COL_FMT_RGBA 0
4352 # define R300_RS_COL_FMT_RGB0 2
4353 # define R300_RS_COL_FMT_RGB1 3
4354 # define R300_RS_COL_FMT_000A 4
4355 # define R300_RS_COL_FMT_0000 5
4356 # define R300_RS_COL_FMT_0001 6
4357 # define R300_RS_COL_FMT_111A 8
4358 # define R300_RS_COL_FMT_1110 9
4359 # define R300_RS_COL_FMT_1111 10
4360 # define R300_RS_SEL_S(x) (x << 13)
4361 # define R300_RS_SEL_T(x) (x << 16)
4362 # define R300_RS_SEL_R(x) (x << 19)
4363 # define R300_RS_SEL_Q(x) (x << 22)
4364 # define R300_RS_SEL_C0 0
4365 # define R300_RS_SEL_C1 1
4366 # define R300_RS_SEL_C2 2
4367 # define R300_RS_SEL_C3 3
4368 # define R300_RS_SEL_K0 4
4369 # define R300_RS_SEL_K1 5
4370 #define R300_RS_INST_COUNT 0x4304
4371 # define R300_INST_COUNT_RS(x) (x << 0)
4372 # define R300_RS_W_EN (1 << 4)
4373 # define R300_TX_OFFSET_RS(x) (x << 5)
4374 #define R300_RS_INST_0 0x4330
4375 #define R300_RS_INST_1 0x4334
4376 # define R300_INST_TEX_ID(x) (x << 0)
4377 # define R300_RS_INST_TEX_CN_WRITE (1 << 3)
4378 # define R300_INST_TEX_ADDR(x) (x << 6)
4380 #define R300_TX_INVALTAGS 0x4100
4381 #define R300_TX_FILTER0_0 0x4400
4382 # define R300_TX_CLAMP_S(x) (x << 0)
4383 # define R300_TX_CLAMP_T(x) (x << 3)
4384 # define R300_TX_CLAMP_R(x) (x << 6)
4385 # define R300_TX_CLAMP_WRAP 0
4386 # define R300_TX_CLAMP_MIRROR 1
4387 # define R300_TX_CLAMP_CLAMP_LAST 2
4388 # define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3
4389 # define R300_TX_CLAMP_CLAMP_BORDER 4
4390 # define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5
4391 # define R300_TX_CLAMP_CLAMP_GL 6
4392 # define R300_TX_CLAMP_MIRROR_CLAMP_GL 7
4393 # define R300_TX_MAG_FILTER_NEAREST (1 << 9)
4394 # define R300_TX_MIN_FILTER_NEAREST (1 << 11)
4395 # define R300_TX_MAG_FILTER_LINEAR (2 << 9)
4396 # define R300_TX_MIN_FILTER_LINEAR (2 << 11)
4397 # define R300_TX_ID_SHIFT 28
4398 #define R300_TX_FILTER1_0 0x4440
4399 #define R300_TX_FORMAT0_0 0x4480
4400 # define R300_TXWIDTH_SHIFT 0
4401 # define R300_TXHEIGHT_SHIFT 11
4402 # define R300_NUM_LEVELS_SHIFT 26
4403 # define R300_NUM_LEVELS_MASK 0x
4404 # define R300_TXPROJECTED (1 << 30)
4405 # define R300_TXPITCH_EN (1 << 31)
4406 #define R300_TX_FORMAT1_0 0x44c0
4407 # define R300_TX_FORMAT_X8 0x0
4408 # define R300_TX_FORMAT_X16 0x1
4409 # define R300_TX_FORMAT_Y4X4 0x2
4410 # define R300_TX_FORMAT_Y8X8 0x3
4411 # define R300_TX_FORMAT_Y16X16 0x4
4412 # define R300_TX_FORMAT_Z3Y3X2 0x5
4413 # define R300_TX_FORMAT_Z5Y6X5 0x6
4414 # define R300_TX_FORMAT_Z6Y5X5 0x7
4415 # define R300_TX_FORMAT_Z11Y11X10 0x8
4416 # define R300_TX_FORMAT_Z10Y11X11 0x9
4417 # define R300_TX_FORMAT_W4Z4Y4X4 0xA
4418 # define R300_TX_FORMAT_W1Z5Y5X5 0xB
4419 # define R300_TX_FORMAT_W8Z8Y8X8 0xC
4420 # define R300_TX_FORMAT_W2Z10Y10X10 0xD
4421 # define R300_TX_FORMAT_W16Z16Y16X16 0xE
4422 # define R300_TX_FORMAT_DXT1 0xF
4423 # define R300_TX_FORMAT_DXT3 0x10
4424 # define R300_TX_FORMAT_DXT5 0x11
4425 # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
4426 # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
4427 # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
4428 # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
4429 # define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */
4430 # define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */
4431 # define R300_TX_FORMAT_X24_Y8 0x1e
4432 # define R300_TX_FORMAT_X32 0x1e
4433 /* Floating point formats */
4434 /* Note - hardware supports both 16 and 32 bit floating point */
4435 # define R300_TX_FORMAT_FL_I16 0x18
4436 # define R300_TX_FORMAT_FL_I16A16 0x19
4437 # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
4438 # define R300_TX_FORMAT_FL_I32 0x1B
4439 # define R300_TX_FORMAT_FL_I32A32 0x1C
4440 # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
4441 /* alpha modes, convenience mostly */
4442 /* if you have alpha, pick constant appropriate to the
4443 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
4444 # define R300_TX_FORMAT_ALPHA_1CH 0x000
4445 # define R300_TX_FORMAT_ALPHA_2CH 0x200
4446 # define R300_TX_FORMAT_ALPHA_4CH 0x600
4447 # define R300_TX_FORMAT_ALPHA_NONE 0xA00
4450 # define R300_TX_FORMAT_X 0
4451 # define R300_TX_FORMAT_Y 1
4452 # define R300_TX_FORMAT_Z 2
4453 # define R300_TX_FORMAT_W 3
4454 # define R300_TX_FORMAT_ZERO 4
4455 # define R300_TX_FORMAT_ONE 5
4456 /* 2.0*Z, everything above 1.0 is set to 0.0 */
4457 # define R300_TX_FORMAT_CUT_Z 6
4458 /* 2.0*W, everything above 1.0 is set to 0.0 */
4459 # define R300_TX_FORMAT_CUT_W 7
4461 # define R300_TX_FORMAT_B_SHIFT 18
4462 # define R300_TX_FORMAT_G_SHIFT 15
4463 # define R300_TX_FORMAT_R_SHIFT 12
4464 # define R300_TX_FORMAT_A_SHIFT 9
4466 /* Convenience macro to take care of layout and swizzling */
4467 # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
4468 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
4469 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
4470 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
4471 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
4472 | (R300_TX_FORMAT_##FMT) \
4475 # define R300_TX_FORMAT_YUV_TO_RGB_CLAMP (1 << 22)
4476 # define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP (2 << 22)
4477 # define R300_TX_FORMAT_SWAP_YUV (1 << 24)
4479 #define R300_TX_FORMAT2_0 0x4500
4480 # define R500_TXWIDTH_11 (1 << 15)
4481 # define R500_TXHEIGHT_11 (1 << 16)
4483 #define R300_TX_OFFSET_0 0x4540
4484 # define R300_ENDIAN_SWAP_16_BIT (1 << 0)
4485 # define R300_ENDIAN_SWAP_32_BIT (2 << 0)
4486 # define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0)
4487 # define R300_MACRO_TILE (1 << 2)
4489 #define R300_TX_BORDER_COLOR_0 0x45c0
4491 #define R300_TX_ENABLE 0x4104
4492 # define R300_TEX_0_ENABLE (1 << 0)
4493 # define R300_TEX_1_ENABLE (1 << 1)
4495 #define R300_US_W_FMT 0x46b4
4496 #define R300_US_OUT_FMT_1 0x46a8
4497 #define R300_US_OUT_FMT_2 0x46ac
4498 #define R300_US_OUT_FMT_3 0x46b0
4499 #define R300_US_OUT_FMT_0 0x46a4
4500 # define R300_OUT_FMT_C4_8 (0 << 0)
4501 # define R300_OUT_FMT_C4_10 (1 << 0)
4502 # define R300_OUT_FMT_C4_10_GAMMA (2 << 0)
4503 # define R300_OUT_FMT_C_16 (3 << 0)
4504 # define R300_OUT_FMT_C2_16 (4 << 0)
4505 # define R300_OUT_FMT_C4_16 (5 << 0)
4506 # define R300_OUT_FMT_C_16_MPEG (6 << 0)
4507 # define R300_OUT_FMT_C2_16_MPEG (7 << 0)
4508 # define R300_OUT_FMT_C2_4 (8 << 0)
4509 # define R300_OUT_FMT_C_3_3_2 (9 << 0)
4510 # define R300_OUT_FMT_C_5_6_5 (10 << 0)
4511 # define R300_OUT_FMT_C_11_11_10 (11 << 0)
4512 # define R300_OUT_FMT_C_10_11_11 (12 << 0)
4513 # define R300_OUT_FMT_C_2_10_10_10 (13 << 0)
4514 # define R300_OUT_FMT_UNUSED (15 << 0)
4515 # define R300_OUT_FMT_C_16_FP (16 << 0)
4516 # define R300_OUT_FMT_C2_16_FP (17 << 0)
4517 # define R300_OUT_FMT_C4_16_FP (18 << 0)
4518 # define R300_OUT_FMT_C_32_FP (19 << 0)
4519 # define R300_OUT_FMT_C2_32_FP (20 << 0)
4520 # define R300_OUT_FMT_C4_32_FP (21 << 0)
4521 # define R300_OUT_FMT_C0_SEL_ALPHA (0 << 8)
4522 # define R300_OUT_FMT_C0_SEL_RED (1 << 8)
4523 # define R300_OUT_FMT_C0_SEL_GREEN (2 << 8)
4524 # define R300_OUT_FMT_C0_SEL_BLUE (3 << 8)
4525 # define R300_OUT_FMT_C1_SEL_ALPHA (0 << 10)
4526 # define R300_OUT_FMT_C1_SEL_RED (1 << 10)
4527 # define R300_OUT_FMT_C1_SEL_GREEN (2 << 10)
4528 # define R300_OUT_FMT_C1_SEL_BLUE (3 << 10)
4529 # define R300_OUT_FMT_C2_SEL_ALPHA (0 << 12)
4530 # define R300_OUT_FMT_C2_SEL_RED (1 << 12)
4531 # define R300_OUT_FMT_C2_SEL_GREEN (2 << 12)
4532 # define R300_OUT_FMT_C2_SEL_BLUE (3 << 12)
4533 # define R300_OUT_FMT_C3_SEL_ALPHA (0 << 14)
4534 # define R300_OUT_FMT_C3_SEL_RED (1 << 14)
4535 # define R300_OUT_FMT_C3_SEL_GREEN (2 << 14)
4536 # define R300_OUT_FMT_C3_SEL_BLUE (3 << 14)
4537 #define R300_US_CONFIG 0x4600
4538 # define R300_NLEVEL_SHIFT 0
4539 # define R300_FIRST_TEX (1 << 3)
4540 # define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
4541 #define R300_US_PIXSIZE 0x4604
4542 #define R300_US_CODE_OFFSET 0x4608
4543 # define R300_ALU_CODE_OFFSET(x) (x << 0)
4544 # define R300_ALU_CODE_SIZE(x) (x << 6)
4545 # define R300_TEX_CODE_OFFSET(x) (x << 13)
4546 # define R300_TEX_CODE_SIZE(x) (x << 18)
4547 #define R300_US_CODE_ADDR_0 0x4610
4548 # define R300_ALU_START(x) (x << 0)
4549 # define R300_ALU_SIZE(x) (x << 6)
4550 # define R300_TEX_START(x) (x << 12)
4551 # define R300_TEX_SIZE(x) (x << 17)
4552 # define R300_RGBA_OUT (1 << 22)
4553 # define R300_W_OUT (1 << 23)
4554 #define R300_US_CODE_ADDR_1 0x4614
4555 #define R300_US_CODE_ADDR_2 0x4618
4556 #define R300_US_CODE_ADDR_3 0x461c
4557 #define R300_US_TEX_INST_0 0x4620
4558 #define R300_US_TEX_INST_1 0x4624
4559 #define R300_US_TEX_INST_2 0x4628
4560 # define R300_TEX_SRC_ADDR(x) (x << 0)
4561 # define R300_TEX_DST_ADDR(x) (x << 6)
4562 # define R300_TEX_ID(x) (x << 11)
4563 # define R300_TEX_INST(x) (x << 15)
4564 # define R300_TEX_INST_NOP 0
4565 # define R300_TEX_INST_LD 1
4566 # define R300_TEX_INST_TEXKILL 2
4567 # define R300_TEX_INST_PROJ 3
4568 # define R300_TEX_INST_LODBIAS 4
4569 #define R300_US_ALU_RGB_ADDR_0 0x46c0
4570 #define R300_US_ALU_RGB_ADDR_1 0x46c4
4571 #define R300_US_ALU_RGB_ADDR_2 0x46c8
4572 /* for ADDR0-2, values 0-31 specify a location in the pixel stack,
4573 values 32-63 specify a constant */
4574 # define R300_ALU_RGB_ADDR0(x) (x << 0)
4575 # define R300_ALU_RGB_ADDR1(x) (x << 6)
4576 # define R300_ALU_RGB_ADDR2(x) (x << 12)
4577 /* ADDRD - where on the pixel stack the result of this instruction
4579 # define R300_ALU_RGB_ADDRD(x) (x << 18)
4580 # define R300_ALU_RGB_WMASK(x) (x << 23)
4581 # define R300_ALU_RGB_OMASK(x) (x << 26)
4582 # define R300_ALU_RGB_MASK_NONE 0
4583 # define R300_ALU_RGB_MASK_R 1
4584 # define R300_ALU_RGB_MASK_G 2
4585 # define R300_ALU_RGB_MASK_B 4
4586 # define R300_ALU_RGB_TARGET_A (0 << 29)
4587 # define R300_ALU_RGB_TARGET_B (1 << 29)
4588 # define R300_ALU_RGB_TARGET_C (2 << 29)
4589 # define R300_ALU_RGB_TARGET_D (3 << 29)
4590 #define R300_US_ALU_RGB_INST_0 0x48c0
4591 #define R300_US_ALU_RGB_INST_1 0x48c4
4592 #define R300_US_ALU_RGB_INST_2 0x48c8
4593 # define R300_ALU_RGB_SEL_A(x) (x << 0)
4594 # define R300_ALU_RGB_SRC0_RGB 0
4595 # define R300_ALU_RGB_SRC0_RRR 1
4596 # define R300_ALU_RGB_SRC0_GGG 2
4597 # define R300_ALU_RGB_SRC0_BBB 3
4598 # define R300_ALU_RGB_SRC1_RGB 4
4599 # define R300_ALU_RGB_SRC1_RRR 5
4600 # define R300_ALU_RGB_SRC1_GGG 6
4601 # define R300_ALU_RGB_SRC1_BBB 7
4602 # define R300_ALU_RGB_SRC2_RGB 8
4603 # define R300_ALU_RGB_SRC2_RRR 9
4604 # define R300_ALU_RGB_SRC2_GGG 10
4605 # define R300_ALU_RGB_SRC2_BBB 11
4606 # define R300_ALU_RGB_SRC0_AAA 12
4607 # define R300_ALU_RGB_SRC1_AAA 13
4608 # define R300_ALU_RGB_SRC2_AAA 14
4609 # define R300_ALU_RGB_SRCP_RGB 15
4610 # define R300_ALU_RGB_SRCP_RRR 16
4611 # define R300_ALU_RGB_SRCP_GGG 17
4612 # define R300_ALU_RGB_SRCP_BBB 18
4613 # define R300_ALU_RGB_SRCP_AAA 19
4614 # define R300_ALU_RGB_0_0 20
4615 # define R300_ALU_RGB_1_0 21
4616 # define R300_ALU_RGB_0_5 22
4617 # define R300_ALU_RGB_SRC0_GBR 23
4618 # define R300_ALU_RGB_SRC1_GBR 24
4619 # define R300_ALU_RGB_SRC2_GBR 25
4620 # define R300_ALU_RGB_SRC0_BRG 26
4621 # define R300_ALU_RGB_SRC1_BRG 27
4622 # define R300_ALU_RGB_SRC2_BRG 28
4623 # define R300_ALU_RGB_SRC0_ABG 29
4624 # define R300_ALU_RGB_SRC1_ABG 30
4625 # define R300_ALU_RGB_SRC2_ABG 31
4626 # define R300_ALU_RGB_MOD_A(x) (x << 5)
4627 # define R300_ALU_RGB_MOD_NOP 0
4628 # define R300_ALU_RGB_MOD_NEG 1
4629 # define R300_ALU_RGB_MOD_ABS 2
4630 # define R300_ALU_RGB_MOD_NAB 3
4631 # define R300_ALU_RGB_SEL_B(x) (x << 7)
4632 # define R300_ALU_RGB_MOD_B(x) (x << 12)
4633 # define R300_ALU_RGB_SEL_C(x) (x << 14)
4634 # define R300_ALU_RGB_MOD_C(x) (x << 19)
4635 # define R300_ALU_RGB_SRCP_OP(x) (x << 21)
4636 # define R300_ALU_RGB_SRCP_OP_1_MINUS_2RGB0 0
4637 # define R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0 1
4638 # define R300_ALU_RGB_SRCP_OP_RGB1_PLUS_RGB0 2
4639 # define R300_ALU_RGB_SRCP_OP_1_MINUS_RGB0 3
4640 # define R300_ALU_RGB_OP(x) (x << 23)
4641 # define R300_ALU_RGB_OP_MAD 0
4642 # define R300_ALU_RGB_OP_DP3 1
4643 # define R300_ALU_RGB_OP_DP4 2
4644 # define R300_ALU_RGB_OP_D2A 3
4645 # define R300_ALU_RGB_OP_MIN 4
4646 # define R300_ALU_RGB_OP_MAX 5
4647 # define R300_ALU_RGB_OP_CND 7
4648 # define R300_ALU_RGB_OP_CMP 8
4649 # define R300_ALU_RGB_OP_FRC 9
4650 # define R300_ALU_RGB_OP_SOP 10
4651 # define R300_ALU_RGB_OMOD(x) (x << 27)
4652 # define R300_ALU_RGB_OMOD_NONE 0
4653 # define R300_ALU_RGB_OMOD_MUL_2 1
4654 # define R300_ALU_RGB_OMOD_MUL_4 2
4655 # define R300_ALU_RGB_OMOD_MUL_8 3
4656 # define R300_ALU_RGB_OMOD_DIV_2 4
4657 # define R300_ALU_RGB_OMOD_DIV_4 5
4658 # define R300_ALU_RGB_OMOD_DIV_8 6
4659 # define R300_ALU_RGB_CLAMP (1 << 30)
4660 # define R300_ALU_RGB_INSERT_NOP (1 << 31)
4661 #define R300_US_ALU_ALPHA_ADDR_0 0x47c0
4662 #define R300_US_ALU_ALPHA_ADDR_1 0x47c4
4663 #define R300_US_ALU_ALPHA_ADDR_2 0x47c8
4664 /* for ADDR0-2, values 0-31 specify a location in the pixel stack,
4665 values 32-63 specify a constant */
4666 # define R300_ALU_ALPHA_ADDR0(x) (x << 0)
4667 # define R300_ALU_ALPHA_ADDR1(x) (x << 6)
4668 # define R300_ALU_ALPHA_ADDR2(x) (x << 12)
4669 /* ADDRD - where on the pixel stack the result of this instruction
4671 # define R300_ALU_ALPHA_ADDRD(x) (x << 18)
4672 # define R300_ALU_ALPHA_WMASK(x) (x << 23)
4673 # define R300_ALU_ALPHA_OMASK(x) (x << 24)
4674 # define R300_ALU_ALPHA_OMASK_W(x) (x << 27)
4675 # define R300_ALU_ALPHA_MASK_NONE 0
4676 # define R300_ALU_ALPHA_MASK_A 1
4677 # define R300_ALU_ALPHA_TARGET_A (0 << 25)
4678 # define R300_ALU_ALPHA_TARGET_B (1 << 25)
4679 # define R300_ALU_ALPHA_TARGET_C (2 << 25)
4680 # define R300_ALU_ALPHA_TARGET_D (3 << 25)
4681 #define R300_US_ALU_ALPHA_INST_0 0x49c0
4682 #define R300_US_ALU_ALPHA_INST_1 0x49c4
4683 #define R300_US_ALU_ALPHA_INST_2 0x49c8
4684 # define R300_ALU_ALPHA_SEL_A(x) (x << 0)
4685 # define R300_ALU_ALPHA_SRC0_R 0
4686 # define R300_ALU_ALPHA_SRC0_G 1
4687 # define R300_ALU_ALPHA_SRC0_B 2
4688 # define R300_ALU_ALPHA_SRC1_R 3
4689 # define R300_ALU_ALPHA_SRC1_G 4
4690 # define R300_ALU_ALPHA_SRC1_B 5
4691 # define R300_ALU_ALPHA_SRC2_R 6
4692 # define R300_ALU_ALPHA_SRC2_G 7
4693 # define R300_ALU_ALPHA_SRC2_B 8
4694 # define R300_ALU_ALPHA_SRC0_A 9
4695 # define R300_ALU_ALPHA_SRC1_A 10
4696 # define R300_ALU_ALPHA_SRC2_A 11
4697 # define R300_ALU_ALPHA_SRCP_R 12
4698 # define R300_ALU_ALPHA_SRCP_G 13
4699 # define R300_ALU_ALPHA_SRCP_B 14
4700 # define R300_ALU_ALPHA_SRCP_A 15
4701 # define R300_ALU_ALPHA_0_0 16
4702 # define R300_ALU_ALPHA_1_0 17
4703 # define R300_ALU_ALPHA_0_5 18
4704 # define R300_ALU_ALPHA_MOD_A(x) (x << 5)
4705 # define R300_ALU_ALPHA_MOD_NOP 0
4706 # define R300_ALU_ALPHA_MOD_NEG 1
4707 # define R300_ALU_ALPHA_MOD_ABS 2
4708 # define R300_ALU_ALPHA_MOD_NAB 3
4709 # define R300_ALU_ALPHA_SEL_B(x) (x << 7)
4710 # define R300_ALU_ALPHA_MOD_B(x) (x << 12)
4711 # define R300_ALU_ALPHA_SEL_C(x) (x << 14)
4712 # define R300_ALU_ALPHA_MOD_C(x) (x << 19)
4713 # define R300_ALU_ALPHA_SRCP_OP(x) (x << 21)
4714 # define R300_ALU_ALPHA_SRCP_OP_1_MINUS_2RGB0 0
4715 # define R300_ALU_ALPHA_SRCP_OP_RGB1_MINUS_RGB0 1
4716 # define R300_ALU_ALPHA_SRCP_OP_RGB1_PLUS_RGB0 2
4717 # define R300_ALU_ALPHA_SRCP_OP_1_MINUS_RGB0 3
4718 # define R300_ALU_ALPHA_OP(x) (x << 23)
4719 # define R300_ALU_ALPHA_OP_MAD 0
4720 # define R300_ALU_ALPHA_OP_DP 1
4721 # define R300_ALU_ALPHA_OP_MIN 2
4722 # define R300_ALU_ALPHA_OP_MAX 3
4723 # define R300_ALU_ALPHA_OP_CND 5
4724 # define R300_ALU_ALPHA_OP_CMP 6
4725 # define R300_ALU_ALPHA_OP_FRC 7
4726 # define R300_ALU_ALPHA_OP_EX2 8
4727 # define R300_ALU_ALPHA_OP_LN2 9
4728 # define R300_ALU_ALPHA_OP_RCP 10
4729 # define R300_ALU_ALPHA_OP_RSQ 11
4730 # define R300_ALU_ALPHA_OMOD(x) (x << 27)
4731 # define R300_ALU_ALPHA_OMOD_NONE 0
4732 # define R300_ALU_ALPHA_OMOD_MUL_2 1
4733 # define R300_ALU_ALPHA_OMOD_MUL_4 2
4734 # define R300_ALU_ALPHA_OMOD_MUL_8 3
4735 # define R300_ALU_ALPHA_OMOD_DIV_2 4
4736 # define R300_ALU_ALPHA_OMOD_DIV_4 5
4737 # define R300_ALU_ALPHA_OMOD_DIV_8 6
4738 # define R300_ALU_ALPHA_CLAMP (1 << 30)
4740 #define R300_FG_DEPTH_SRC 0x4bd8
4741 #define R300_FG_FOG_BLEND 0x4bc0
4742 #define R300_FG_ALPHA_FUNC 0x4bd4
4744 #define R300_DST_PIPE_CONFIG 0x170c
4745 # define R300_PIPE_AUTO_CONFIG (1 << 31)
4746 #define R300_RB2D_DSTCACHE_MODE 0x3428
4747 #define R300_RB2D_DSTCACHE_MODE 0x3428
4748 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
4749 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
4750 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use DSTCACHE_CTLSTAT instead */
4751 #define R300_DSTCACHE_CTLSTAT 0x1714
4752 # define R300_DC_FLUSH_2D (1 << 0)
4753 # define R300_DC_FREE_2D (1 << 2)
4754 # define R300_RB2D_DC_FLUSH_ALL (R300_DC_FLUSH_2D | R300_DC_FREE_2D)
4755 # define R300_RB2D_DC_BUSY (1 << 31)
4756 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
4757 # define R300_DC_FLUSH_3D (2 << 0)
4758 # define R300_DC_FREE_3D (2 << 2)
4759 # define R300_RB3D_DC_FLUSH_ALL (R300_DC_FLUSH_3D | R300_DC_FREE_3D)
4760 # define R300_DC_FINISH_3D (1 << 4)
4761 #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18
4762 # define R300_ZC_FLUSH (1 << 0)
4763 # define R300_ZC_FREE (1 << 1)
4764 # define R300_ZC_FLUSH_ALL 0x3
4765 #define R300_RB3D_ZSTENCILCNTL 0x4f04
4766 #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18
4767 #define R300_RB3D_BW_CNTL 0x4f1c
4768 #define R300_RB3D_ZCNTL 0x4f00
4769 #define R300_RB3D_ZTOP 0x4f14
4770 #define R300_RB3D_ROPCNTL 0x4e18
4771 #define R300_RB3D_BLENDCNTL 0x4e04
4772 # define R300_ALPHA_BLEND_ENABLE (1 << 0)
4773 # define R300_SEPARATE_ALPHA_ENABLE (1 << 1)
4774 # define R300_READ_ENABLE (1 << 2)
4775 #define R300_RB3D_ABLENDCNTL 0x4e08
4776 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
4777 #define R300_RB3D_COLOROFFSET0 0x4e28
4778 #define R300_RB3D_COLORPITCH0 0x4e38
4779 # define R300_COLORTILE (1 << 16)
4780 # define R300_COLORENDIAN_WORD (1 << 19)
4781 # define R300_COLORENDIAN_DWORD (2 << 19)
4782 # define R300_COLORENDIAN_HALF_DWORD (3 << 19)
4783 # define R300_COLORFORMAT_ARGB1555 (3 << 21)
4784 # define R300_COLORFORMAT_RGB565 (4 << 21)
4785 # define R300_COLORFORMAT_ARGB8888 (6 << 21)
4786 # define R300_COLORFORMAT_ARGB32323232 (7 << 21)
4787 # define R300_COLORFORMAT_I8 (9 << 21)
4788 # define R300_COLORFORMAT_ARGB16161616 (10 << 21)
4789 # define R300_COLORFORMAT_VYUY (11 << 21)
4790 # define R300_COLORFORMAT_YVYU (12 << 21)
4791 # define R300_COLORFORMAT_UV88 (13 << 21)
4792 # define R300_COLORFORMAT_ARGB4444 (15 << 21)
4794 #define R300_RB3D_AARESOLVE_CTL 0x4e88
4795 #define R300_RB3D_COLOR_CHANNEL_MASK 0x4e0c
4796 # define R300_BLUE_MASK_EN (1 << 0)
4797 # define R300_GREEN_MASK_EN (1 << 1)
4798 # define R300_RED_MASK_EN (1 << 2)
4799 # define R300_ALPHA_MASK_EN (1 << 3)
4800 #define R300_RB3D_COLOR_CLEAR_VALUE 0x4e14
4801 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
4802 #define R300_RB3D_CCTL 0x4e00
4803 #define R300_RB3D_DITHER_CTL 0x4e50
4805 #define R300_SC_EDGERULE 0x43a8
4806 #define R300_SC_SCISSOR0 0x43e0
4807 #define R300_SC_SCISSOR1 0x43e4
4808 # define R300_SCISSOR_X_SHIFT 0
4809 # define R300_SCISSOR_Y_SHIFT 13
4810 #define R300_SC_CLIP_0_A 0x43b0
4811 #define R300_SC_CLIP_0_B 0x43b4
4812 # define R300_CLIP_X_SHIFT 0
4813 # define R300_CLIP_Y_SHIFT 13
4814 #define R300_SC_CLIP_RULE 0x43d0
4815 #define R300_SC_SCREENDOOR 0x43e8
4817 /* R500 US has to be loaded through an index/data pair */
4818 #define R500_GA_US_VECTOR_INDEX 0x4250
4819 # define R500_US_VECTOR_INDEX(x) (x << 0)
4820 # define R500_US_VECTOR_TYPE_INST (0 << 16)
4821 # define R500_US_VECTOR_TYPE_CONST (1 << 16)
4822 # define R500_US_VECTOR_CLAMP (1 << 17)
4823 #define R500_GA_US_VECTOR_DATA 0x4254
4826 * The R500 unified shader (US) registers come in banks of 512 each, one
4827 * for each instruction slot in the shader. You can't touch them directly.
4828 * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive
4829 * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the
4830 * instruction is fully specified.
4832 #define R500_US_ALU_ALPHA_INST_0 0xa800
4833 # define R500_ALPHA_OP_MAD 0
4834 # define R500_ALPHA_OP_DP 1
4835 # define R500_ALPHA_OP_MIN 2
4836 # define R500_ALPHA_OP_MAX 3
4837 /* #define R500_ALPHA_OP_RESERVED 4 */
4838 # define R500_ALPHA_OP_CND 5
4839 # define R500_ALPHA_OP_CMP 6
4840 # define R500_ALPHA_OP_FRC 7
4841 # define R500_ALPHA_OP_EX2 8
4842 # define R500_ALPHA_OP_LN2 9
4843 # define R500_ALPHA_OP_RCP 10
4844 # define R500_ALPHA_OP_RSQ 11
4845 # define R500_ALPHA_OP_SIN 12
4846 # define R500_ALPHA_OP_COS 13
4847 # define R500_ALPHA_OP_MDH 14
4848 # define R500_ALPHA_OP_MDV 15
4849 # define R500_ALPHA_ADDRD(x) (x << 4)
4850 # define R500_ALPHA_ADDRD_REL (1 << 11)
4851 # define R500_ALPHA_SEL_A_SRC0 (0 << 12)
4852 # define R500_ALPHA_SEL_A_SRC1 (1 << 12)
4853 # define R500_ALPHA_SEL_A_SRC2 (2 << 12)
4854 # define R500_ALPHA_SEL_A_SRCP (3 << 12)
4855 # define R500_ALPHA_SWIZ_A_R (0 << 14)
4856 # define R500_ALPHA_SWIZ_A_G (1 << 14)
4857 # define R500_ALPHA_SWIZ_A_B (2 << 14)
4858 # define R500_ALPHA_SWIZ_A_A (3 << 14)
4859 # define R500_ALPHA_SWIZ_A_0 (4 << 14)
4860 # define R500_ALPHA_SWIZ_A_HALF (5 << 14)
4861 # define R500_ALPHA_SWIZ_A_1 (6 << 14)
4862 /* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */
4863 # define R500_ALPHA_MOD_A_NOP (0 << 17)
4864 # define R500_ALPHA_MOD_A_NEG (1 << 17)
4865 # define R500_ALPHA_MOD_A_ABS (2 << 17)
4866 # define R500_ALPHA_MOD_A_NAB (3 << 17)
4867 # define R500_ALPHA_SEL_B_SRC0 (0 << 19)
4868 # define R500_ALPHA_SEL_B_SRC1 (1 << 19)
4869 # define R500_ALPHA_SEL_B_SRC2 (2 << 19)
4870 # define R500_ALPHA_SEL_B_SRCP (3 << 19)
4871 # define R500_ALPHA_SWIZ_B_R (0 << 21)
4872 # define R500_ALPHA_SWIZ_B_G (1 << 21)
4873 # define R500_ALPHA_SWIZ_B_B (2 << 21)
4874 # define R500_ALPHA_SWIZ_B_A (3 << 21)
4875 # define R500_ALPHA_SWIZ_B_0 (4 << 21)
4876 # define R500_ALPHA_SWIZ_B_HALF (5 << 21)
4877 # define R500_ALPHA_SWIZ_B_1 (6 << 21)
4878 /* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */
4879 # define R500_ALPHA_MOD_B_NOP (0 << 24)
4880 # define R500_ALPHA_MOD_B_NEG (1 << 24)
4881 # define R500_ALPHA_MOD_B_ABS (2 << 24)
4882 # define R500_ALPHA_MOD_B_NAB (3 << 24)
4883 # define R500_ALPHA_OMOD_IDENTITY (0 << 26)
4884 # define R500_ALPHA_OMOD_MUL_2 (1 << 26)
4885 # define R500_ALPHA_OMOD_MUL_4 (2 << 26)
4886 # define R500_ALPHA_OMOD_MUL_8 (3 << 26)
4887 # define R500_ALPHA_OMOD_DIV_2 (4 << 26)
4888 # define R500_ALPHA_OMOD_DIV_4 (5 << 26)
4889 # define R500_ALPHA_OMOD_DIV_8 (6 << 26)
4890 # define R500_ALPHA_OMOD_DISABLE (7 << 26)
4891 # define R500_ALPHA_TARGET(x) (x << 29)
4892 # define R500_ALPHA_W_OMASK (1 << 31)
4893 #define R500_US_ALU_ALPHA_ADDR_0 0x9800
4894 # define R500_ALPHA_ADDR0(x) (x << 0)
4895 # define R500_ALPHA_ADDR0_CONST (1 << 8)
4896 # define R500_ALPHA_ADDR0_REL (1 << 9)
4897 # define R500_ALPHA_ADDR1(x) (x << 10)
4898 # define R500_ALPHA_ADDR1_CONST (1 << 18)
4899 # define R500_ALPHA_ADDR1_REL (1 << 19)
4900 # define R500_ALPHA_ADDR2(x) (x << 20)
4901 # define R500_ALPHA_ADDR2_CONST (1 << 28)
4902 # define R500_ALPHA_ADDR2_REL (1 << 29)
4903 # define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30)
4904 # define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30)
4905 # define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30)
4906 # define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30)
4907 #define R500_US_ALU_RGBA_INST_0 0xb000
4908 # define R500_ALU_RGBA_OP_MAD (0 << 0)
4909 # define R500_ALU_RGBA_OP_DP3 (1 << 0)
4910 # define R500_ALU_RGBA_OP_DP4 (2 << 0)
4911 # define R500_ALU_RGBA_OP_D2A (3 << 0)
4912 # define R500_ALU_RGBA_OP_MIN (4 << 0)
4913 # define R500_ALU_RGBA_OP_MAX (5 << 0)
4914 /* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */
4915 # define R500_ALU_RGBA_OP_CND (7 << 0)
4916 # define R500_ALU_RGBA_OP_CMP (8 << 0)
4917 # define R500_ALU_RGBA_OP_FRC (9 << 0)
4918 # define R500_ALU_RGBA_OP_SOP (10 << 0)
4919 # define R500_ALU_RGBA_OP_MDH (11 << 0)
4920 # define R500_ALU_RGBA_OP_MDV (12 << 0)
4921 # define R500_ALU_RGBA_ADDRD(x) (x << 4)
4922 # define R500_ALU_RGBA_ADDRD_REL (1 << 11)
4923 # define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12)
4924 # define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12)
4925 # define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12)
4926 # define R500_ALU_RGBA_SEL_C_SRCP (3 << 12)
4927 # define R500_ALU_RGBA_R_SWIZ_R (0 << 14)
4928 # define R500_ALU_RGBA_R_SWIZ_G (1 << 14)
4929 # define R500_ALU_RGBA_R_SWIZ_B (2 << 14)
4930 # define R500_ALU_RGBA_R_SWIZ_A (3 << 14)
4931 # define R500_ALU_RGBA_R_SWIZ_0 (4 << 14)
4932 # define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14)
4933 # define R500_ALU_RGBA_R_SWIZ_1 (6 << 14)
4934 /* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */
4935 # define R500_ALU_RGBA_G_SWIZ_R (0 << 17)
4936 # define R500_ALU_RGBA_G_SWIZ_G (1 << 17)
4937 # define R500_ALU_RGBA_G_SWIZ_B (2 << 17)
4938 # define R500_ALU_RGBA_G_SWIZ_A (3 << 17)
4939 # define R500_ALU_RGBA_G_SWIZ_0 (4 << 17)
4940 # define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17)
4941 # define R500_ALU_RGBA_G_SWIZ_1 (6 << 17)
4942 /* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */
4943 # define R500_ALU_RGBA_B_SWIZ_R (0 << 20)
4944 # define R500_ALU_RGBA_B_SWIZ_G (1 << 20)
4945 # define R500_ALU_RGBA_B_SWIZ_B (2 << 20)
4946 # define R500_ALU_RGBA_B_SWIZ_A (3 << 20)
4947 # define R500_ALU_RGBA_B_SWIZ_0 (4 << 20)
4948 # define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20)
4949 # define R500_ALU_RGBA_B_SWIZ_1 (6 << 20)
4950 /* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */
4951 # define R500_ALU_RGBA_MOD_C_NOP (0 << 23)
4952 # define R500_ALU_RGBA_MOD_C_NEG (1 << 23)
4953 # define R500_ALU_RGBA_MOD_C_ABS (2 << 23)
4954 # define R500_ALU_RGBA_MOD_C_NAB (3 << 23)
4955 # define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25)
4956 # define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25)
4957 # define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25)
4958 # define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25)
4959 # define R500_ALU_RGBA_A_SWIZ_R (0 << 27)
4960 # define R500_ALU_RGBA_A_SWIZ_G (1 << 27)
4961 # define R500_ALU_RGBA_A_SWIZ_B (2 << 27)
4962 # define R500_ALU_RGBA_A_SWIZ_A (3 << 27)
4963 # define R500_ALU_RGBA_A_SWIZ_0 (4 << 27)
4964 # define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27)
4965 # define R500_ALU_RGBA_A_SWIZ_1 (6 << 27)
4966 /* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */
4967 # define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30)
4968 # define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30)
4969 # define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30)
4970 # define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30)
4971 #define R500_US_ALU_RGB_INST_0 0xa000
4972 # define R500_ALU_RGB_SEL_A_SRC0 (0 << 0)
4973 # define R500_ALU_RGB_SEL_A_SRC1 (1 << 0)
4974 # define R500_ALU_RGB_SEL_A_SRC2 (2 << 0)
4975 # define R500_ALU_RGB_SEL_A_SRCP (3 << 0)
4976 # define R500_ALU_RGB_R_SWIZ_A_R (0 << 2)
4977 # define R500_ALU_RGB_R_SWIZ_A_G (1 << 2)
4978 # define R500_ALU_RGB_R_SWIZ_A_B (2 << 2)
4979 # define R500_ALU_RGB_R_SWIZ_A_A (3 << 2)
4980 # define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2)
4981 # define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2)
4982 # define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2)
4983 /* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */
4984 # define R500_ALU_RGB_G_SWIZ_A_R (0 << 5)
4985 # define R500_ALU_RGB_G_SWIZ_A_G (1 << 5)
4986 # define R500_ALU_RGB_G_SWIZ_A_B (2 << 5)
4987 # define R500_ALU_RGB_G_SWIZ_A_A (3 << 5)
4988 # define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5)
4989 # define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5)
4990 # define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5)
4991 /* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */
4992 # define R500_ALU_RGB_B_SWIZ_A_R (0 << 8)
4993 # define R500_ALU_RGB_B_SWIZ_A_G (1 << 8)
4994 # define R500_ALU_RGB_B_SWIZ_A_B (2 << 8)
4995 # define R500_ALU_RGB_B_SWIZ_A_A (3 << 8)
4996 # define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8)
4997 # define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8)
4998 # define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8)
4999 /* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */
5000 # define R500_ALU_RGB_MOD_A_NOP (0 << 11)
5001 # define R500_ALU_RGB_MOD_A_NEG (1 << 11)
5002 # define R500_ALU_RGB_MOD_A_ABS (2 << 11)
5003 # define R500_ALU_RGB_MOD_A_NAB (3 << 11)
5004 # define R500_ALU_RGB_SEL_B_SRC0 (0 << 13)
5005 # define R500_ALU_RGB_SEL_B_SRC1 (1 << 13)
5006 # define R500_ALU_RGB_SEL_B_SRC2 (2 << 13)
5007 # define R500_ALU_RGB_SEL_B_SRCP (3 << 13)
5008 # define R500_ALU_RGB_R_SWIZ_B_R (0 << 15)
5009 # define R500_ALU_RGB_R_SWIZ_B_G (1 << 15)
5010 # define R500_ALU_RGB_R_SWIZ_B_B (2 << 15)
5011 # define R500_ALU_RGB_R_SWIZ_B_A (3 << 15)
5012 # define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15)
5013 # define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15)
5014 # define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15)
5015 /* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */
5016 # define R500_ALU_RGB_G_SWIZ_B_R (0 << 18)
5017 # define R500_ALU_RGB_G_SWIZ_B_G (1 << 18)
5018 # define R500_ALU_RGB_G_SWIZ_B_B (2 << 18)
5019 # define R500_ALU_RGB_G_SWIZ_B_A (3 << 18)
5020 # define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18)
5021 # define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18)
5022 # define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18)
5023 /* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */
5024 # define R500_ALU_RGB_B_SWIZ_B_R (0 << 21)
5025 # define R500_ALU_RGB_B_SWIZ_B_G (1 << 21)
5026 # define R500_ALU_RGB_B_SWIZ_B_B (2 << 21)
5027 # define R500_ALU_RGB_B_SWIZ_B_A (3 << 21)
5028 # define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21)
5029 # define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21)
5030 # define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21)
5031 /* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */
5032 # define R500_ALU_RGB_MOD_B_NOP (0 << 24)
5033 # define R500_ALU_RGB_MOD_B_NEG (1 << 24)
5034 # define R500_ALU_RGB_MOD_B_ABS (2 << 24)
5035 # define R500_ALU_RGB_MOD_B_NAB (3 << 24)
5036 # define R500_ALU_RGB_OMOD_IDENTITY (0 << 26)
5037 # define R500_ALU_RGB_OMOD_MUL_2 (1 << 26)
5038 # define R500_ALU_RGB_OMOD_MUL_4 (2 << 26)
5039 # define R500_ALU_RGB_OMOD_MUL_8 (3 << 26)
5040 # define R500_ALU_RGB_OMOD_DIV_2 (4 << 26)
5041 # define R500_ALU_RGB_OMOD_DIV_4 (5 << 26)
5042 # define R500_ALU_RGB_OMOD_DIV_8 (6 << 26)
5043 # define R500_ALU_RGB_OMOD_DISABLE (7 << 26)
5044 # define R500_ALU_RGB_TARGET(x) (x << 29)
5045 # define R500_ALU_RGB_WMASK (1 << 31)
5046 #define R500_US_ALU_RGB_ADDR_0 0x9000
5047 # define R500_RGB_ADDR0(x) (x << 0)
5048 # define R500_RGB_ADDR0_CONST (1 << 8)
5049 # define R500_RGB_ADDR0_REL (1 << 9)
5050 # define R500_RGB_ADDR1(x) (x << 10)
5051 # define R500_RGB_ADDR1_CONST (1 << 18)
5052 # define R500_RGB_ADDR1_REL (1 << 19)
5053 # define R500_RGB_ADDR2(x) (x << 20)
5054 # define R500_RGB_ADDR2_CONST (1 << 28)
5055 # define R500_RGB_ADDR2_REL (1 << 29)
5056 # define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30)
5057 # define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30)
5058 # define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30)
5059 # define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30)
5060 #define R500_US_CMN_INST_0 0xb800
5061 # define R500_INST_TYPE_ALU (0 << 0)
5062 # define R500_INST_TYPE_OUT (1 << 0)
5063 # define R500_INST_TYPE_FC (2 << 0)
5064 # define R500_INST_TYPE_TEX (3 << 0)
5065 # define R500_INST_TEX_SEM_WAIT (1 << 2)
5066 # define R500_INST_RGB_PRED_SEL_NONE (0 << 3)
5067 # define R500_INST_RGB_PRED_SEL_RGBA (1 << 3)
5068 # define R500_INST_RGB_PRED_SEL_RRRR (2 << 3)
5069 # define R500_INST_RGB_PRED_SEL_GGGG (3 << 3)
5070 # define R500_INST_RGB_PRED_SEL_BBBB (4 << 3)
5071 # define R500_INST_RGB_PRED_SEL_AAAA (5 << 3)
5072 # define R500_INST_RGB_PRED_INV (1 << 6)
5073 # define R500_INST_WRITE_INACTIVE (1 << 7)
5074 # define R500_INST_LAST (1 << 8)
5075 # define R500_INST_NOP (1 << 9)
5076 # define R500_INST_ALU_WAIT (1 << 10)
5077 # define R500_INST_RGB_WMASK_R (1 << 11)
5078 # define R500_INST_RGB_WMASK_G (1 << 12)
5079 # define R500_INST_RGB_WMASK_B (1 << 13)
5080 # define R500_INST_ALPHA_WMASK (1 << 14)
5081 # define R500_INST_RGB_OMASK_R (1 << 15)
5082 # define R500_INST_RGB_OMASK_G (1 << 16)
5083 # define R500_INST_RGB_OMASK_B (1 << 17)
5084 # define R500_INST_ALPHA_OMASK (1 << 18)
5085 # define R500_INST_RGB_CLAMP (1 << 19)
5086 # define R500_INST_ALPHA_CLAMP (1 << 20)
5087 # define R500_INST_ALU_RESULT_SEL (1 << 21)
5088 # define R500_INST_ALPHA_PRED_INV (1 << 22)
5089 # define R500_INST_ALU_RESULT_OP_EQ (0 << 23)
5090 # define R500_INST_ALU_RESULT_OP_LT (1 << 23)
5091 # define R500_INST_ALU_RESULT_OP_GE (2 << 23)
5092 # define R500_INST_ALU_RESULT_OP_NE (3 << 23)
5093 # define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25)
5094 # define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25)
5095 # define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25)
5096 # define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25)
5097 # define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25)
5098 # define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25)
5099 /* XXX next four are kind of guessed */
5100 # define R500_INST_STAT_WE_R (1 << 28)
5101 # define R500_INST_STAT_WE_G (1 << 29)
5102 # define R500_INST_STAT_WE_B (1 << 30)
5103 # define R500_INST_STAT_WE_A (1 << 31)
5104 /* note that these are 8 bit lengths, despite the offsets, at least for R500 */
5105 #define R500_US_CODE_ADDR 0x4630
5106 # define R500_US_CODE_START_ADDR(x) (x << 0)
5107 # define R500_US_CODE_END_ADDR(x) (x << 16)
5108 #define R500_US_CODE_OFFSET 0x4638
5109 # define R500_US_CODE_OFFSET_ADDR(x) (x << 0)
5110 #define R500_US_CODE_RANGE 0x4634
5111 # define R500_US_CODE_RANGE_ADDR(x) (x << 0)
5112 # define R500_US_CODE_RANGE_SIZE(x) (x << 16)
5113 #define R500_US_CONFIG 0x4600
5114 # define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
5115 #define R500_US_FC_ADDR_0 0xa000
5116 # define R500_FC_BOOL_ADDR(x) (x << 0)
5117 # define R500_FC_INT_ADDR(x) (x << 8)
5118 # define R500_FC_JUMP_ADDR(x) (x << 16)
5119 # define R500_FC_JUMP_GLOBAL (1 << 31)
5120 #define R500_US_FC_BOOL_CONST 0x4620
5121 # define R500_FC_KBOOL(x) (x)
5122 #define R500_US_FC_CTRL 0x4624
5123 # define R500_FC_TEST_EN (1 << 30)
5124 # define R500_FC_FULL_FC_EN (1 << 31)
5125 #define R500_US_FC_INST_0 0x9800
5126 # define R500_FC_OP_JUMP (0 << 0)
5127 # define R500_FC_OP_LOOP (1 << 0)
5128 # define R500_FC_OP_ENDLOOP (2 << 0)
5129 # define R500_FC_OP_REP (3 << 0)
5130 # define R500_FC_OP_ENDREP (4 << 0)
5131 # define R500_FC_OP_BREAKLOOP (5 << 0)
5132 # define R500_FC_OP_BREAKREP (6 << 0)
5133 # define R500_FC_OP_CONTINUE (7 << 0)
5134 # define R500_FC_B_ELSE (1 << 4)
5135 # define R500_FC_JUMP_ANY (1 << 5)
5136 # define R500_FC_A_OP_NONE (0 << 6)
5137 # define R500_FC_A_OP_POP (1 << 6)
5138 # define R500_FC_A_OP_PUSH (2 << 6)
5139 # define R500_FC_JUMP_FUNC(x) (x << 8)
5140 # define R500_FC_B_POP_CNT(x) (x << 16)
5141 # define R500_FC_B_OP0_NONE (0 << 24)
5142 # define R500_FC_B_OP0_DECR (1 << 24)
5143 # define R500_FC_B_OP0_INCR (2 << 24)
5144 # define R500_FC_B_OP1_DECR (0 << 26)
5145 # define R500_FC_B_OP1_NONE (1 << 26)
5146 # define R500_FC_B_OP1_INCR (2 << 26)
5147 # define R500_FC_IGNORE_UNCOVERED (1 << 28)
5148 #define R500_US_FC_INT_CONST_0 0x4c00
5149 # define R500_FC_INT_CONST_KR(x) (x << 0)
5150 # define R500_FC_INT_CONST_KG(x) (x << 8)
5151 # define R500_FC_INT_CONST_KB(x) (x << 16)
5152 /* _0 through _15 */
5153 #define R500_US_FORMAT0_0 0x4640
5154 # define R500_FORMAT_TXWIDTH(x) (x << 0)
5155 # define R500_FORMAT_TXHEIGHT(x) (x << 11)
5156 # define R500_FORMAT_TXDEPTH(x) (x << 22)
5158 #define R500_US_OUT_FMT_0 0x46a4
5159 # define R500_OUT_FMT_C4_8 (0 << 0)
5160 # define R500_OUT_FMT_C4_10 (1 << 0)
5161 # define R500_OUT_FMT_C4_10_GAMMA (2 << 0)
5162 # define R500_OUT_FMT_C_16 (3 << 0)
5163 # define R500_OUT_FMT_C2_16 (4 << 0)
5164 # define R500_OUT_FMT_C4_16 (5 << 0)
5165 # define R500_OUT_FMT_C_16_MPEG (6 << 0)
5166 # define R500_OUT_FMT_C2_16_MPEG (7 << 0)
5167 # define R500_OUT_FMT_C2_4 (8 << 0)
5168 # define R500_OUT_FMT_C_3_3_2 (9 << 0)
5169 # define R500_OUT_FMT_C_6_5_6 (10 << 0)
5170 # define R500_OUT_FMT_C_11_11_10 (11 << 0)
5171 # define R500_OUT_FMT_C_10_11_11 (12 << 0)
5172 # define R500_OUT_FMT_C_2_10_10_10 (13 << 0)
5173 /* #define R500_OUT_FMT_RESERVED (14 << 0) */
5174 # define R500_OUT_FMT_UNUSED (15 << 0)
5175 # define R500_OUT_FMT_C_16_FP (16 << 0)
5176 # define R500_OUT_FMT_C2_16_FP (17 << 0)
5177 # define R500_OUT_FMT_C4_16_FP (18 << 0)
5178 # define R500_OUT_FMT_C_32_FP (19 << 0)
5179 # define R500_OUT_FMT_C2_32_FP (20 << 0)
5180 # define R500_OUT_FMT_C4_32_FP (21 << 0)
5181 # define R500_C0_SEL_A (0 << 8)
5182 # define R500_C0_SEL_R (1 << 8)
5183 # define R500_C0_SEL_G (2 << 8)
5184 # define R500_C0_SEL_B (3 << 8)
5185 # define R500_C1_SEL_A (0 << 10)
5186 # define R500_C1_SEL_R (1 << 10)
5187 # define R500_C1_SEL_G (2 << 10)
5188 # define R500_C1_SEL_B (3 << 10)
5189 # define R500_C2_SEL_A (0 << 12)
5190 # define R500_C2_SEL_R (1 << 12)
5191 # define R500_C2_SEL_G (2 << 12)
5192 # define R500_C2_SEL_B (3 << 12)
5193 # define R500_C3_SEL_A (0 << 14)
5194 # define R500_C3_SEL_R (1 << 14)
5195 # define R500_C3_SEL_G (2 << 14)
5196 # define R500_C3_SEL_B (3 << 14)
5197 # define R500_OUT_SIGN(x) (x << 16)
5198 # define R500_ROUND_ADJ (1 << 20)
5199 #define R500_US_PIXSIZE 0x4604
5200 # define R500_PIX_SIZE(x) (x)
5201 #define R500_US_TEX_ADDR_0 0x9800
5202 # define R500_TEX_SRC_ADDR(x) (x << 0)
5203 # define R500_TEX_SRC_ADDR_REL (1 << 7)
5204 # define R500_TEX_SRC_S_SWIZ_R (0 << 8)
5205 # define R500_TEX_SRC_S_SWIZ_G (1 << 8)
5206 # define R500_TEX_SRC_S_SWIZ_B (2 << 8)
5207 # define R500_TEX_SRC_S_SWIZ_A (3 << 8)
5208 # define R500_TEX_SRC_T_SWIZ_R (0 << 10)
5209 # define R500_TEX_SRC_T_SWIZ_G (1 << 10)
5210 # define R500_TEX_SRC_T_SWIZ_B (2 << 10)
5211 # define R500_TEX_SRC_T_SWIZ_A (3 << 10)
5212 # define R500_TEX_SRC_R_SWIZ_R (0 << 12)
5213 # define R500_TEX_SRC_R_SWIZ_G (1 << 12)
5214 # define R500_TEX_SRC_R_SWIZ_B (2 << 12)
5215 # define R500_TEX_SRC_R_SWIZ_A (3 << 12)
5216 # define R500_TEX_SRC_Q_SWIZ_R (0 << 14)
5217 # define R500_TEX_SRC_Q_SWIZ_G (1 << 14)
5218 # define R500_TEX_SRC_Q_SWIZ_B (2 << 14)
5219 # define R500_TEX_SRC_Q_SWIZ_A (3 << 14)
5220 # define R500_TEX_DST_ADDR(x) (x << 16)
5221 # define R500_TEX_DST_ADDR_REL (1 << 23)
5222 # define R500_TEX_DST_R_SWIZ_R (0 << 24)
5223 # define R500_TEX_DST_R_SWIZ_G (1 << 24)
5224 # define R500_TEX_DST_R_SWIZ_B (2 << 24)
5225 # define R500_TEX_DST_R_SWIZ_A (3 << 24)
5226 # define R500_TEX_DST_G_SWIZ_R (0 << 26)
5227 # define R500_TEX_DST_G_SWIZ_G (1 << 26)
5228 # define R500_TEX_DST_G_SWIZ_B (2 << 26)
5229 # define R500_TEX_DST_G_SWIZ_A (3 << 26)
5230 # define R500_TEX_DST_B_SWIZ_R (0 << 28)
5231 # define R500_TEX_DST_B_SWIZ_G (1 << 28)
5232 # define R500_TEX_DST_B_SWIZ_B (2 << 28)
5233 # define R500_TEX_DST_B_SWIZ_A (3 << 28)
5234 # define R500_TEX_DST_A_SWIZ_R (0 << 30)
5235 # define R500_TEX_DST_A_SWIZ_G (1 << 30)
5236 # define R500_TEX_DST_A_SWIZ_B (2 << 30)
5237 # define R500_TEX_DST_A_SWIZ_A (3 << 30)
5238 #define R500_US_TEX_ADDR_DXDY_0 0xa000
5239 # define R500_DX_ADDR(x) (x << 0)
5240 # define R500_DX_ADDR_REL (1 << 7)
5241 # define R500_DX_S_SWIZ_R (0 << 8)
5242 # define R500_DX_S_SWIZ_G (1 << 8)
5243 # define R500_DX_S_SWIZ_B (2 << 8)
5244 # define R500_DX_S_SWIZ_A (3 << 8)
5245 # define R500_DX_T_SWIZ_R (0 << 10)
5246 # define R500_DX_T_SWIZ_G (1 << 10)
5247 # define R500_DX_T_SWIZ_B (2 << 10)
5248 # define R500_DX_T_SWIZ_A (3 << 10)
5249 # define R500_DX_R_SWIZ_R (0 << 12)
5250 # define R500_DX_R_SWIZ_G (1 << 12)
5251 # define R500_DX_R_SWIZ_B (2 << 12)
5252 # define R500_DX_R_SWIZ_A (3 << 12)
5253 # define R500_DX_Q_SWIZ_R (0 << 14)
5254 # define R500_DX_Q_SWIZ_G (1 << 14)
5255 # define R500_DX_Q_SWIZ_B (2 << 14)
5256 # define R500_DX_Q_SWIZ_A (3 << 14)
5257 # define R500_DY_ADDR(x) (x << 16)
5258 # define R500_DY_ADDR_REL (1 << 17)
5259 # define R500_DY_S_SWIZ_R (0 << 24)
5260 # define R500_DY_S_SWIZ_G (1 << 24)
5261 # define R500_DY_S_SWIZ_B (2 << 24)
5262 # define R500_DY_S_SWIZ_A (3 << 24)
5263 # define R500_DY_T_SWIZ_R (0 << 26)
5264 # define R500_DY_T_SWIZ_G (1 << 26)
5265 # define R500_DY_T_SWIZ_B (2 << 26)
5266 # define R500_DY_T_SWIZ_A (3 << 26)
5267 # define R500_DY_R_SWIZ_R (0 << 28)
5268 # define R500_DY_R_SWIZ_G (1 << 28)
5269 # define R500_DY_R_SWIZ_B (2 << 28)
5270 # define R500_DY_R_SWIZ_A (3 << 28)
5271 # define R500_DY_Q_SWIZ_R (0 << 30)
5272 # define R500_DY_Q_SWIZ_G (1 << 30)
5273 # define R500_DY_Q_SWIZ_B (2 << 30)
5274 # define R500_DY_Q_SWIZ_A (3 << 30)
5275 #define R500_US_TEX_INST_0 0x9000
5276 # define R500_TEX_ID(x) (x << 16)
5277 # define R500_TEX_INST_NOP (0 << 22)
5278 # define R500_TEX_INST_LD (1 << 22)
5279 # define R500_TEX_INST_TEXKILL (2 << 22)
5280 # define R500_TEX_INST_PROJ (3 << 22)
5281 # define R500_TEX_INST_LODBIAS (4 << 22)
5282 # define R500_TEX_INST_LOD (5 << 22)
5283 # define R500_TEX_INST_DXDY (6 << 22)
5284 # define R500_TEX_SEM_ACQUIRE (1 << 25)
5285 # define R500_TEX_IGNORE_UNCOVERED (1 << 26)
5286 # define R500_TEX_UNSCALED (1 << 27)
5287 #define R500_US_W_FMT 0x46b4
5288 # define R500_W_FMT_W0 (0 << 0)
5289 # define R500_W_FMT_W24 (1 << 0)
5290 # define R500_W_FMT_W24FP (2 << 0)
5291 # define R500_W_SRC_US (0 << 2)
5292 # define R500_W_SRC_RAS (1 << 2)
5294 #define R500_GA_US_VECTOR_INDEX 0x4250
5295 #define R500_GA_US_VECTOR_DATA 0x4254
5297 #define R500_RS_INST_0 0x4320
5298 #define R500_RS_INST_1 0x4324
5299 # define R500_RS_INST_TEX_ID_SHIFT 0
5300 # define R500_RS_INST_TEX_CN_WRITE (1 << 4)
5301 # define R500_RS_INST_TEX_ADDR_SHIFT 5
5302 # define R500_RS_INST_COL_ID_SHIFT 12
5303 # define R500_RS_INST_COL_CN_NO_WRITE (0 << 16)
5304 # define R500_RS_INST_COL_CN_WRITE (1 << 16)
5305 # define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16)
5306 # define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16)
5307 # define R500_RS_INST_COL_COL_ADDR_SHIFT 18
5308 # define R500_RS_INST_TEX_ADJ (1 << 25)
5309 # define R500_RS_INST_W_CN (1 << 26)
5311 #define R500_US_FC_CTRL 0x4624
5312 #define R500_US_CODE_ADDR 0x4630
5313 #define R500_US_CODE_RANGE 0x4634
5314 #define R500_US_CODE_OFFSET 0x4638
5316 #define R500_RS_IP_0 0x4074
5317 #define R500_RS_IP_1 0x4078
5318 # define R500_RS_IP_PTR_K0 62
5319 # define R500_RS_IP_PTR_K1 63
5320 # define R500_RS_IP_TEX_PTR_S_SHIFT 0
5321 # define R500_RS_IP_TEX_PTR_T_SHIFT 6
5322 # define R500_RS_IP_TEX_PTR_R_SHIFT 12
5323 # define R500_RS_IP_TEX_PTR_Q_SHIFT 18
5324 # define R500_RS_IP_COL_PTR_SHIFT 24
5325 # define R500_RS_IP_COL_FMT_SHIFT 27
5326 # define R500_RS_IP_COL_FMT_RGBA (0 << 27)
5327 # define R500_RS_IP_OFFSET_EN (1 << 31)
5329 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */