2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
28 #include "radeon_drv.h"
32 #include "drm_crtc_helper.h"
34 int radeon_suspend(struct drm_device *dev, pm_message_t state)
36 struct drm_radeon_private *dev_priv = dev->dev_private;
37 struct drm_framebuffer *fb;
40 if (!dev || !dev_priv) {
44 if (state.event == PM_EVENT_PRETHAW)
47 if (!drm_core_check_feature(dev, DRIVER_MODESET))
50 /* unpin the front buffers */
51 list_for_each_entry(fb, &dev->mode_config.fb_kernel_list, filp_head) {
52 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
57 if (!radeon_fb->base.mm_private)
60 radeon_gem_object_unpin(radeon_fb->base.mm_private);
63 if (!(dev_priv->flags & RADEON_IS_IGP))
64 drm_bo_evict_mm(dev, DRM_BO_MEM_VRAM, 0);
66 if (dev_priv->flags & RADEON_IS_PCIE) {
67 memcpy_fromio(dev_priv->mm.pcie_table_backup, dev_priv->mm.pcie_table.kmap.virtual, RADEON_PCIGART_TABLE_SIZE);
70 dev_priv->pmregs.crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
71 for (i = 0; i < 8; i++)
72 dev_priv->pmregs.bios_scratch[i] = RADEON_READ(RADEON_BIOS_0_SCRATCH + (i * 4));
74 radeon_modeset_cp_suspend(dev);
76 pci_save_state(dev->pdev);
78 if (state.event == PM_EVENT_SUSPEND) {
79 /* Shut down the device */
80 pci_disable_device(dev->pdev);
81 pci_set_power_state(dev->pdev, PCI_D3hot);
86 int radeon_resume(struct drm_device *dev)
88 struct drm_radeon_private *dev_priv = dev->dev_private;
89 struct drm_framebuffer *fb;
93 if (!drm_core_check_feature(dev, DRIVER_MODESET))
96 pci_set_power_state(dev->pdev, PCI_D0);
97 pci_restore_state(dev->pdev);
98 if (pci_enable_device(dev->pdev))
100 pci_set_master(dev->pdev);
102 /* Turn on bus mastering */
103 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
104 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
106 /* on atom cards re init the whole card
107 and set the modes again */
109 if (dev_priv->is_atom_bios) {
110 struct atom_context *ctx = dev_priv->mode_info.atom_context;
113 radeon_combios_asic_init(dev);
116 for (i = 0; i < 8; i++)
117 RADEON_WRITE(RADEON_BIOS_0_SCRATCH + (i * 4), dev_priv->pmregs.bios_scratch[i]);
119 /* VGA render mayhaps */
120 if (dev_priv->chip_family >= CHIP_RS600) {
123 RADEON_WRITE(AVIVO_D1VGA_CONTROL, 0);
124 RADEON_WRITE(AVIVO_D2VGA_CONTROL, 0);
125 tmp = RADEON_READ(0x300);
127 RADEON_WRITE(0x300, tmp);
128 RADEON_WRITE(0x308, (1 << 8));
129 RADEON_WRITE(0x310, dev_priv->fb_location);
130 RADEON_WRITE(0x594, 0);
133 RADEON_WRITE(RADEON_CRTC_EXT_CNTL, dev_priv->pmregs.crtc_ext_cntl);
135 radeon_static_clocks_init(dev);
137 radeon_init_memory_map(dev);
139 if (dev_priv->flags & RADEON_IS_PCIE) {
140 memcpy_toio(dev_priv->mm.pcie_table.kmap.virtual, dev_priv->mm.pcie_table_backup, RADEON_PCIGART_TABLE_SIZE);
143 if (dev_priv->mm.ring.kmap.virtual)
144 memset(dev_priv->mm.ring.kmap.virtual, 0, RADEON_DEFAULT_RING_SIZE);
146 if (dev_priv->mm.ring_read.kmap.virtual)
147 memset(dev_priv->mm.ring_read.kmap.virtual, 0, PAGE_SIZE);
149 radeon_modeset_cp_resume(dev);
152 RADEON_WRITE(RADEON_LAST_SWI_REG, dev_priv->counter);
154 // radeon_enable_interrupt(dev);
156 /* reset the context for userspace */
157 if (dev->primary->master) {
158 struct drm_radeon_master_private *master_priv = dev->primary->master->driver_priv;
159 if (master_priv->sarea_priv)
160 master_priv->sarea_priv->ctx_owner = 0;
163 /* unpin the front buffers */
164 list_for_each_entry(fb, &dev->mode_config.fb_kernel_list, filp_head) {
166 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
171 if (!radeon_fb->base.mm_private)
174 radeon_gem_object_pin(radeon_fb->base.mm_private,
175 PAGE_SIZE, RADEON_GEM_DOMAIN_VRAM);
177 /* blat the mode back in */
178 drm_helper_resume_force_mode(dev);
183 bool radeon_set_pcie_lanes(struct drm_device *dev, int lanes)
185 drm_radeon_private_t *dev_priv = dev->dev_private;
186 uint32_t link_width_cntl, mask;
188 /* FIXME wait for idle */
193 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
196 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
199 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
202 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
205 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
208 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
212 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
216 link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
218 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
219 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
222 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
223 RADEON_PCIE_LC_RECONFIG_NOW |
224 RADEON_PCIE_LC_RECONFIG_LATER |
225 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
226 link_width_cntl |= mask;
227 RADEON_WRITE_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
228 RADEON_WRITE_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW);
230 /* wait for lane set to complete */
231 link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
232 while (link_width_cntl == 0xffffffff)
233 link_width_cntl = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_LC_LINK_WIDTH_CNTL);
235 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
236 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))