2 * Copyright © 2007 David Airlie
3 * Copyright © 2007 Jerome Glisse
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/errno.h>
31 #include <linux/string.h>
33 #include <linux/tty.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
37 #include <linux/init.h>
42 #include "radeon_ms.h"
46 static int radeonfb_setcolreg(unsigned regno, unsigned red,
47 unsigned green, unsigned blue,
48 unsigned transp, struct fb_info *info)
50 struct amd_fb *par = info->par;
51 struct drm_framebuffer *fb = par->fb;
52 struct drm_crtc *crtc = par->crtc;
57 // if (crtc->funcs->gamma_set) {
58 // crtc->funcs->gamma_set(crtc, red, green, blue, regno);
63 fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
64 ((green & 0xf800) >> 6) |
65 ((blue & 0xf800) >> 11);
68 fb->pseudo_palette[regno] = (red & 0xf800) |
69 ((green & 0xfc00) >> 5) |
70 ((blue & 0xf800) >> 11);
74 fb->pseudo_palette[regno] = ((red & 0xff00) << 8) |
76 ((blue & 0xff00) >> 8);
83 static int radeonfb_check_var(struct fb_var_screeninfo *var,
86 struct amd_fb *par = info->par;
87 struct drm_framebuffer *fb = par->fb;
92 /* Need to resize the fb object !!! */
93 if (var->xres > fb->width || var->yres > fb->height) {
94 DRM_ERROR("Requested width/height is greater than "
95 "current fb object %dx%d > %dx%d\n",
96 var->xres, var->yres, fb->width, fb->height);
97 DRM_ERROR("Need resizing code.\n");
101 switch (var->bits_per_pixel) {
103 if (var->green.length == 5) {
104 var->red.offset = 10;
105 var->green.offset = 5;
106 var->blue.offset = 0;
108 var->green.length = 5;
109 var->blue.length = 5;
110 var->transp.length = 0;
111 var->transp.offset = 0;
113 var->red.offset = 11;
114 var->green.offset = 6;
115 var->blue.offset = 0;
117 var->green.length = 6;
118 var->blue.length = 5;
119 var->transp.length = 0;
120 var->transp.offset = 0;
124 if (var->transp.length) {
125 var->red.offset = 16;
126 var->green.offset = 8;
127 var->blue.offset = 0;
129 var->green.length = 8;
130 var->blue.length = 8;
131 var->transp.length = 8;
132 var->transp.offset = 24;
134 var->red.offset = 16;
135 var->green.offset = 8;
136 var->blue.offset = 0;
138 var->green.length = 8;
139 var->blue.length = 8;
140 var->transp.length = 0;
141 var->transp.offset = 0;
150 static bool radeonfb_mode_equal(struct drm_display_mode *mode1,
151 struct drm_display_mode *mode2)
153 if (mode1->hdisplay == mode2->hdisplay &&
154 mode1->hsync_start == mode2->hsync_start &&
155 mode1->hsync_end == mode2->hsync_end &&
156 mode1->htotal == mode2->htotal &&
157 mode1->hskew == mode2->hskew &&
158 mode1->vdisplay == mode2->vdisplay &&
159 mode1->vsync_start == mode2->vsync_start &&
160 mode1->vsync_end == mode2->vsync_end &&
161 mode1->vtotal == mode2->vtotal &&
162 mode1->vscan == mode2->vscan &&
163 mode1->flags == mode2->flags) {
164 /* FIXME: what about adding a margin for clock ? */
165 if (mode1->clock == mode2->clock)
173 static int radeonfb_set_par(struct fb_info *info)
175 struct amd_fb *par = info->par;
176 struct drm_framebuffer *fb = par->fb;
177 struct drm_device *dev = par->dev;
178 struct drm_display_mode *drm_mode, *search_mode;
179 struct drm_output *output;
180 struct fb_var_screeninfo *var = &info->var;
183 switch (var->bits_per_pixel) {
185 fb->depth = (var->green.length == 6) ? 16 : 15;
188 fb->depth = (var->transp.length > 0) ? 32 : 24;
193 fb->bits_per_pixel = var->bits_per_pixel;
195 info->fix.line_length = fb->pitch;
196 info->fix.smem_len = info->fix.line_length * fb->height;
197 info->fix.visual = FB_VISUAL_TRUECOLOR;
198 info->screen_size = info->fix.smem_len; /* ??? */
200 /* Should we walk the output's modelist or just create our own ???
201 * For now, we create and destroy a mode based on the incoming
202 * parameters. But there's commented out code below which scans
203 * the output list too.
205 drm_mode = drm_mode_create(dev);
206 drm_mode->hdisplay = var->xres;
207 drm_mode->hsync_start = drm_mode->hdisplay + var->right_margin;
208 drm_mode->hsync_end = drm_mode->hsync_start + var->hsync_len;
209 drm_mode->htotal = drm_mode->hsync_end + var->left_margin;
210 drm_mode->vdisplay = var->yres;
211 drm_mode->vsync_start = drm_mode->vdisplay + var->lower_margin;
212 drm_mode->vsync_end = drm_mode->vsync_start + var->vsync_len;
213 drm_mode->vtotal = drm_mode->vsync_end + var->upper_margin;
214 drm_mode->clock = PICOS2KHZ(var->pixclock);
215 drm_mode->vrefresh = drm_mode_vrefresh(drm_mode);
216 drm_mode_set_name(drm_mode);
217 drm_mode_set_crtcinfo(drm_mode, CRTC_INTERLACE_HALVE_V);
219 list_for_each_entry(output, &dev->mode_config.output_list, head) {
220 if (output->crtc == par->crtc)
224 drm_mode_debug_printmodeline(drm_mode);
225 list_for_each_entry(search_mode, &output->modes, head) {
226 drm_mode_debug_printmodeline(search_mode);
227 if (radeonfb_mode_equal(drm_mode, search_mode)) {
228 drm_mode_destroy(dev, drm_mode);
229 drm_mode = search_mode;
237 drm_mode_detachmode_crtc(dev, par->fb_mode);
239 par->fb_mode = drm_mode;
240 drm_mode_debug_printmodeline(drm_mode);
242 drm_mode_attachmode_crtc(dev, par->crtc, par->fb_mode);
245 if (par->crtc->enabled) {
246 if (!drm_mode_equal(&par->crtc->mode, drm_mode) ||
247 par->crtc->fb != par->fb) {
248 par->crtc->fb = par->fb;
249 if (!drm_crtc_set_mode(par->crtc, drm_mode, 0, 0)) {
258 static struct fb_ops radeonfb_ops = {
259 .owner = THIS_MODULE,
260 // .fb_open = radeonfb_open,
261 // .fb_read = radeonfb_read,
262 // .fb_write = radeonfb_write,
263 // .fb_release = radeonfb_release,
264 // .fb_ioctl = radeonfb_ioctl,
265 .fb_check_var = radeonfb_check_var,
266 .fb_set_par = radeonfb_set_par,
267 .fb_setcolreg = radeonfb_setcolreg,
268 .fb_fillrect = cfb_fillrect,
269 .fb_copyarea = cfb_copyarea,
270 .fb_imageblit = cfb_imageblit,
273 int radeonfb_probe(struct drm_device *dev, struct drm_crtc *crtc, struct drm_output *output)
275 struct drm_radeon_private *dev_priv = dev->dev_private;
276 struct fb_info *info;
278 struct device *device = &dev->pdev->dev;
279 struct drm_framebuffer *fb;
280 struct drm_display_mode *mode = crtc->desired_mode;
283 info = framebuffer_alloc(sizeof(struct amd_fb), device);
285 DRM_INFO("[radeon_ms] framebuffer_alloc failed\n");
289 fb = drm_framebuffer_create(dev);
291 framebuffer_release(info);
292 DRM_ERROR("[radeon_ms] failed to allocate fb.\n");
297 fb->width = crtc->desired_mode->hdisplay;
298 fb->height = crtc->desired_mode->vdisplay;
299 fb->bits_per_pixel = 32;
300 fb->pitch = fb->width * ((fb->bits_per_pixel + 1) / 8);
302 /* one page alignment should be fine for constraint (micro|macro tiling,
303 * bit depth, color buffer offset, ...) */
304 ret = drm_buffer_object_create(dev, fb->width * fb->height * 4,
308 DRM_BO_FLAG_NO_EVICT |
309 DRM_BO_FLAG_MEM_VRAM,
310 DRM_BO_HINT_DONT_FENCE,
314 if (ret || fb->bo == NULL) {
315 DRM_ERROR("[radeon_ms] failed to allocate framebuffer\n");
316 drm_framebuffer_destroy(fb);
317 framebuffer_release(info);
321 DRM_INFO("[radeon_ms] framebuffer %dx%d at 0x%08lX\n",
322 fb->width, fb->height, fb->bo->offset);
330 info->fbops = &radeonfb_ops;
331 strcpy(info->fix.id, "radeonfb");
332 info->fix.type = FB_TYPE_PACKED_PIXELS;
333 info->fix.visual = FB_VISUAL_TRUECOLOR;
334 info->fix.type_aux = 0;
335 info->fix.xpanstep = 8;
336 info->fix.ypanstep = 1;
337 info->fix.ywrapstep = 0;
338 info->fix.accel = FB_ACCEL_ATI_RADEON;
339 info->fix.type_aux = 0;
340 info->fix.mmio_start = 0;
341 info->fix.mmio_len = 0;
342 info->fix.line_length = fb->pitch;
343 info->fix.smem_start = fb->bo->offset + dev->mode_config.fb_base;
344 info->fix.smem_len = info->fix.line_length * fb->height;
345 info->flags = FBINFO_DEFAULT;
346 DRM_INFO("[radeon_ms] fb physical start : 0x%lX\n", info->fix.smem_start);
347 DRM_INFO("[radeon_ms] fb physical size : %d\n", info->fix.smem_len);
349 ret = drm_bo_kmap(fb->bo, 0, fb->bo->num_pages, &fb->kmap);
351 DRM_ERROR("error mapping fb: %d\n", ret);
353 info->screen_base = fb->kmap.virtual;
354 info->screen_size = info->fix.smem_len; /* FIXME */
355 info->pseudo_palette = fb->pseudo_palette;
356 info->var.xres_virtual = fb->width;
357 info->var.yres_virtual = fb->height;
358 info->var.bits_per_pixel = fb->bits_per_pixel;
359 info->var.xoffset = 0;
360 info->var.yoffset = 0;
361 info->var.activate = FB_ACTIVATE_NOW;
362 info->var.height = -1;
363 info->var.width = -1;
364 info->var.vmode = FB_VMODE_NONINTERLACED;
366 info->var.xres = mode->hdisplay;
367 info->var.right_margin = mode->hsync_start - mode->hdisplay;
368 info->var.hsync_len = mode->hsync_end - mode->hsync_start;
369 info->var.left_margin = mode->htotal - mode->hsync_end;
370 info->var.yres = mode->vdisplay;
371 info->var.lower_margin = mode->vsync_start - mode->vdisplay;
372 info->var.vsync_len = mode->vsync_end - mode->vsync_start;
373 info->var.upper_margin = mode->vtotal - mode->vsync_end;
374 info->var.pixclock = 10000000 / mode->htotal * 1000 /
377 info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;
379 info->pixmap.size = 64*1024;
380 info->pixmap.buf_align = 8;
381 info->pixmap.access_align = 32;
382 info->pixmap.flags = FB_PIXMAP_SYSTEM;
383 info->pixmap.scan_align = 1;
385 DRM_DEBUG("fb depth is %d\n", fb->depth);
386 DRM_DEBUG(" pitch is %d\n", fb->pitch);
389 info->var.red.offset = 10;
390 info->var.green.offset = 5;
391 info->var.blue.offset = 0;
392 info->var.red.length = info->var.green.length =
393 info->var.blue.length = 5;
394 info->var.transp.offset = 15;
395 info->var.transp.length = 1;
398 info->var.red.offset = 11;
399 info->var.green.offset = 5;
400 info->var.blue.offset = 0;
401 info->var.red.length = 5;
402 info->var.green.length = 6;
403 info->var.blue.length = 5;
404 info->var.transp.offset = 0;
407 info->var.red.offset = 16;
408 info->var.green.offset = 8;
409 info->var.blue.offset = 0;
410 info->var.red.length = info->var.green.length =
411 info->var.blue.length = 8;
412 info->var.transp.offset = 0;
413 info->var.transp.length = 0;
416 info->var.red.offset = 16;
417 info->var.green.offset = 8;
418 info->var.blue.offset = 0;
419 info->var.red.length = info->var.green.length =
420 info->var.blue.length = 8;
421 info->var.transp.offset = 24;
422 info->var.transp.length = 8;
425 DRM_ERROR("only support 15, 16, 24 or 32bits per pixel "
426 "got %d\n", fb->depth);
431 if (register_framebuffer(info) < 0) {
435 DRM_INFO("[radeon_ms] fb%d: %s frame buffer device\n", info->node,
439 EXPORT_SYMBOL(radeonfb_probe);
441 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *kern_fb)
443 struct drm_radeon_private *dev_priv = dev->dev_private;
444 struct amd_fb *fb = dev_priv->fb;
445 struct fb_info *info;
447 if (fb == NULL || fb->fb == NULL || fb->fb->fbdev == NULL) {
448 DRM_INFO("[radeon_ms] %s: no crtc, or fb or fbdev\n",
452 info = fb->fb->fbdev;
453 unregister_framebuffer(info);
454 drm_bo_kunmap(&fb->fb->kmap);
455 drm_bo_usage_deref_unlocked(&fb->fb->bo);
456 drm_framebuffer_destroy(fb->fb);
457 framebuffer_release(info);
461 EXPORT_SYMBOL(radeonfb_remove);
462 MODULE_LICENSE("GPL");