2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
27 * Kernel port Author: Dave Airlie
33 #include <linux/i2c.h>
34 #include <linux/i2c-id.h>
35 #include <linux/i2c-algo-bit.h>
37 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
38 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
39 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
40 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
42 enum radeon_connector_type {
53 CONNECTOR_HDMI_TYPE_A,
54 CONNECTOR_HDMI_TYPE_B,
58 CONNECTOR_DISPLAY_PORT,
62 enum radeon_dac_type {
69 enum radeon_tmds_type {
78 enum radeon_dvi_type {
84 enum radeon_rmx_type {
101 struct radeon_i2c_bus_rec {
103 uint32_t mask_clk_reg;
104 uint32_t mask_data_reg;
107 uint32_t put_clk_reg;
108 uint32_t put_data_reg;
109 uint32_t get_clk_reg;
110 uint32_t get_data_reg;
111 uint32_t mask_clk_mask;
112 uint32_t mask_data_mask;
113 uint32_t put_clk_mask;
114 uint32_t put_data_mask;
115 uint32_t get_clk_mask;
116 uint32_t get_data_mask;
118 uint32_t a_data_mask;
121 struct radeon_bios_connector {
122 enum radeon_dac_type dac_type;
123 enum radeon_tmds_type tmds_type;
124 enum radeon_connector_type connector_type;
129 struct radeon_i2c_bus_rec ddc_i2c;
133 struct radeon_tmds_pll {
138 #define RADEON_MAX_BIOS_CONNECTOR 16
140 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
141 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
142 #define RADEON_PLL_USE_REF_DIV (1 << 2)
143 #define RADEON_PLL_LEGACY (1 << 3)
144 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
147 uint16_t reference_freq;
148 uint16_t reference_div;
151 uint32_t pll_out_min;
152 uint32_t pll_out_max;
155 uint32_t min_ref_div;
156 uint32_t max_ref_div;
157 uint32_t min_post_div;
158 uint32_t max_post_div;
159 uint32_t min_feedback_div;
160 uint32_t max_feedback_div;
164 #define MAX_H_CODE_TIMING_LEN 32
165 #define MAX_V_CODE_TIMING_LEN 32
167 struct radeon_legacy_state {
174 uint32_t dac_macro_cntl;
177 uint32_t crtc_gen_cntl;
178 uint32_t crtc_ext_cntl;
179 uint32_t crtc_h_total_disp;
180 uint32_t crtc_h_sync_strt_wid;
181 uint32_t crtc_v_total_disp;
182 uint32_t crtc_v_sync_strt_wid;
183 uint32_t crtc_offset;
184 uint32_t crtc_offset_cntl;
186 uint32_t disp_merge_cntl;
187 uint32_t grph_buffer_cntl;
188 uint32_t crtc_more_cntl;
189 uint32_t crtc_tile_x0_y0;
192 uint32_t crtc2_gen_cntl;
193 uint32_t crtc2_h_total_disp;
194 uint32_t crtc2_h_sync_strt_wid;
195 uint32_t crtc2_v_total_disp;
196 uint32_t crtc2_v_sync_strt_wid;
197 uint32_t crtc2_offset;
198 uint32_t crtc2_offset_cntl;
199 uint32_t crtc2_pitch;
200 uint32_t crtc2_tile_x0_y0;
202 uint32_t disp_output_cntl;
203 uint32_t disp_tv_out_cntl;
204 uint32_t disp_hw_debug;
205 uint32_t disp2_merge_cntl;
206 uint32_t grph2_buffer_cntl;
209 uint32_t fp_crtc_h_total_disp;
210 uint32_t fp_crtc_v_total_disp;
211 uint32_t fp_gen_cntl;
212 uint32_t fp2_gen_cntl;
213 uint32_t fp_h_sync_strt_wid;
214 uint32_t fp_h2_sync_strt_wid;
215 uint32_t fp_horz_stretch;
216 uint32_t fp_horz_vert_active;
217 uint32_t fp_panel_cntl;
218 uint32_t fp_v_sync_strt_wid;
219 uint32_t fp_v2_sync_strt_wid;
220 uint32_t fp_vert_stretch;
221 uint32_t lvds_gen_cntl;
222 uint32_t lvds_pll_cntl;
223 uint32_t tmds_pll_cntl;
224 uint32_t tmds_transmitter_cntl;
226 /* Computed values for PLL */
227 uint32_t dot_clock_freq;
228 uint32_t pll_output_freq;
234 uint32_t ppll_ref_div;
236 uint32_t htotal_cntl;
237 uint32_t vclk_ecp_cntl;
239 /* Computed values for PLL2 */
240 uint32_t dot_clock_freq_2;
241 uint32_t pll_output_freq_2;
247 uint32_t p2pll_ref_div;
248 uint32_t p2pll_div_0;
249 uint32_t htotal_cntl2;
250 uint32_t pixclks_cntl;
253 uint32_t palette[256];
254 uint32_t palette2[256];
256 uint32_t disp2_req_cntl1;
257 uint32_t disp2_req_cntl2;
258 uint32_t dmif_mem_cntl1;
259 uint32_t disp1_req_cntl1;
261 uint32_t fp_2nd_gen_cntl;
262 uint32_t fp2_2_gen_cntl;
264 uint32_t tmds2_transmitter_cntl;
266 /* TV out registers */
267 uint32_t tv_master_cntl;
274 uint32_t tv_timing_cntl;
275 uint32_t tv_vscaler_cntl1;
276 uint32_t tv_vscaler_cntl2;
277 uint32_t tv_sync_size;
278 uint32_t tv_vrestart;
279 uint32_t tv_hrestart;
280 uint32_t tv_frestart;
282 uint32_t tv_clock_sel_cntl;
283 uint32_t tv_clkout_cntl;
284 uint32_t tv_data_delay_a;
285 uint32_t tv_data_delay_b;
286 uint32_t tv_dac_cntl;
287 uint32_t tv_pll_cntl;
288 uint32_t tv_pll_cntl1;
289 uint32_t tv_pll_fine_cntl;
290 uint32_t tv_modulator_cntl1;
291 uint32_t tv_modulator_cntl2;
292 uint32_t tv_frame_lock_cntl;
293 uint32_t tv_pre_dac_mux_cntl;
294 uint32_t tv_rgb_cntl;
295 uint32_t tv_y_saw_tooth_cntl;
296 uint32_t tv_y_rise_cntl;
297 uint32_t tv_y_fall_cntl;
299 uint32_t tv_upsamp_and_gain_cntl;
300 uint32_t tv_gain_limit_settings;
301 uint32_t tv_linear_gain_settings;
302 uint32_t tv_crc_cntl;
303 uint32_t tv_sync_cntl;
305 uint32_t pll_test_cntl;
307 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
308 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
313 struct radeon_mode_info {
314 struct atom_context *atom_context;
315 struct radeon_bios_connector bios_connector[RADEON_MAX_BIOS_CONNECTOR];
316 struct radeon_pll pll;
317 struct radeon_legacy_state legacy_state;
321 struct drm_crtc base;
323 u8 lut_r[256], lut_g[256], lut_b[256];
326 uint32_t crtc_offset;
327 struct radeon_framebuffer *fbdev_fb;
328 struct drm_mode_set mode_set;
331 struct radeon_i2c_chan {
332 struct drm_device *dev;
333 struct i2c_adapter adapter;
334 struct i2c_algo_bit_data algo;
335 struct radeon_i2c_bus_rec rec;
339 #define RADEON_USE_RMX 1
341 struct radeon_encoder {
342 struct drm_encoder base;
343 uint32_t encoder_mode;
345 enum radeon_rmx_type rmx_type;
347 enum radeon_dac_type dac;
348 enum radeon_tmds_type tmds;
350 int atom_device; /* atom devices */
353 uint32_t panel_xres, panel_yres;
354 uint32_t hoverplus, hsync_width;
356 uint32_t voverplus, vsync_width;
361 uint16_t panel_vcc_delay;
362 uint16_t panel_pwr_delay;
363 uint16_t panel_digon_delay;
364 uint16_t panel_blon_delay;
365 uint32_t panel_ref_divider;
366 uint32_t panel_post_divider;
367 uint32_t panel_fb_divider;
368 bool use_bios_dividers;
369 uint32_t lvds_gen_cntl;
372 uint32_t ps2_tvdac_adj;
373 uint32_t ntsc_tvdac_adj;
374 uint32_t pal_tvdac_adj;
375 enum radeon_tv_std tv_std;
377 /* legacy int tmds */
378 struct radeon_tmds_pll tmds_pll[4];
381 struct radeon_connector {
382 struct drm_connector base;
383 struct radeon_i2c_chan *ddc_bus;
387 struct radeon_framebuffer {
388 struct drm_framebuffer base;
389 struct drm_gem_object *obj;
390 struct drm_bo_kmap_obj kmap_obj;
393 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
394 struct radeon_i2c_bus_rec *rec,
396 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
397 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
398 extern struct drm_connector *radeon_connector_add(struct drm_device *dev, int bios_index);
400 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
402 extern void radeon_compute_pll(struct radeon_pll *pll,
404 uint32_t *dot_clock_p,
407 uint32_t *post_div_p,
410 struct drm_encoder *radeon_encoder_lvtma_add(struct drm_device *dev, int bios_index);
411 struct drm_encoder *radeon_encoder_atom_dac_add(struct drm_device *dev, int bios_index, int dac_id, int with_tv);
412 struct drm_encoder *radeon_encoder_atom_tmds_add(struct drm_device *dev, int bios_index, int tmds_type);
413 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
414 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
415 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
416 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
417 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
419 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
420 extern void atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y);
421 extern void atombios_crtc_mode_set(struct drm_crtc *crtc,
422 struct drm_display_mode *mode,
423 struct drm_display_mode *adjusted_mode,
425 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
427 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
428 struct drm_file *file_priv,
432 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
435 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
436 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
437 extern void radeon_get_lvds_info(struct radeon_encoder *encoder);
438 extern bool radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
439 extern bool radeon_combios_get_tmds_info(struct radeon_encoder *encoder);
440 extern bool radeon_combios_get_tv_info(struct radeon_encoder *encoder);
441 extern bool radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
442 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
443 u16 blue, int regno);
444 struct drm_framebuffer *radeon_user_framebuffer_create(struct drm_device *dev,
445 struct drm_file *filp,
446 struct drm_mode_fb_cmd *mode_cmd);
448 int radeonfb_probe(struct drm_device *dev);
450 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
451 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
452 void radeon_atombios_init_crtc(struct drm_device *dev,
453 struct radeon_crtc *radeon_crtc);
454 void radeon_legacy_init_crtc(struct drm_device *dev,
455 struct radeon_crtc *radeon_crtc);
456 void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state);
458 void radeon_atom_static_pwrmgt_setup(struct drm_device *dev, int enable);
459 void radeon_atom_dyn_clk_setup(struct drm_device *dev, int enable);
460 void radeon_get_clock_info(struct drm_device *dev);
461 extern bool radeon_get_atom_connector_info_from_bios_connector_table(struct drm_device *dev);
463 void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
464 struct drm_display_mode *mode,
465 struct drm_display_mode *adjusted_mode);
466 void radeon_enc_destroy(struct drm_encoder *encoder);