linux-core/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31
  32 static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder,
  33                                        struct drm_display_mode *mode,
  34                                        struct drm_display_mode *adjusted_mode)
  35 {
  36         struct drm_device *dev = encoder->dev;
  37         struct drm_radeon_private *dev_priv = dev->dev_private;
  38         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  39         int    xres = mode->hdisplay;
  40         int    yres = mode->vdisplay;
  41         bool   hscale = true, vscale = true;
  42         int    hsync_wid;
  43         int    vsync_wid;
  44         int    hsync_start;
  45         uint32_t scale, inc;
  46         uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active;
  47         uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp;
  48
  49         DRM_DEBUG("\n");
  50
  51         fp_vert_stretch = RADEON_READ(RADEON_FP_VERT_STRETCH) &
  52                 (RADEON_VERT_STRETCH_RESERVED |
  53                  RADEON_VERT_AUTO_RATIO_INC);
  54         fp_horz_stretch = RADEON_READ(RADEON_FP_HORZ_STRETCH) &
  55                 (RADEON_HORZ_FP_LOOP_STRETCH |
  56                  RADEON_HORZ_AUTO_RATIO_INC);
  57
  58         crtc_more_cntl = 0;
  59         if ((dev_priv->chip_family == CHIP_RS100) ||
  60             (dev_priv->chip_family == CHIP_RS200)) {
  61                 /* This is to workaround the asic bug for RMX, some versions
  62                    of BIOS dosen't have this register initialized correctly. */
  63                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  64         }
  65
  66
  67         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  68                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  69
  70         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  71         if (!hsync_wid)
  72                 hsync_wid = 1;
  73         hsync_start = mode->crtc_hsync_start - 8;
  74
  75         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  76                               | ((hsync_wid & 0x3f) << 16)
  77                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  78                                  ? RADEON_CRTC_H_SYNC_POL
  79                                  : 0));
  80
  81         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  82                                 | ((mode->crtc_vdisplay - 1) << 16));
  83
  84         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  85         if (!vsync_wid)
  86                 vsync_wid = 1;
  87
  88         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
  89                               | ((vsync_wid & 0x1f) << 16)
  90                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
  91                                  ? RADEON_CRTC_V_SYNC_POL
  92                                  : 0));
  93
  94         fp_horz_vert_active = 0;
  95
  96         if (radeon_encoder->panel_xres == 0 ||
  97             radeon_encoder->panel_yres == 0) {
  98                 hscale = false;
  99                 vscale = false;
 100         } else {
 101                 if (xres > radeon_encoder->panel_xres)
 102                         xres = radeon_encoder->panel_xres;
 103                 if (yres > radeon_encoder->panel_yres)
 104                         yres = radeon_encoder->panel_yres;
 105
 106                 if (xres == radeon_encoder->panel_xres)
 107                         hscale = false;
 108                 if (yres == radeon_encoder->panel_yres)
 109                         vscale = false;
 110         }
 111
 112         if (radeon_encoder->flags & RADEON_USE_RMX) {
 113                 if (radeon_encoder->rmx_type != RMX_CENTER) {
 114                         if (!hscale)
 115                                 fp_horz_stretch |= ((xres/8-1) << 16);
 116                         else {
 117                                 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 118                                 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 119                                         / radeon_encoder->panel_xres + 1;
 120                                 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 121                                                     RADEON_HORZ_STRETCH_BLEND |
 122                                                     RADEON_HORZ_STRETCH_ENABLE |
 123                                                     ((radeon_encoder->panel_xres/8-1) << 16));
 124                         }
 125
 126                         if (!vscale)
 127                                 fp_vert_stretch |= ((yres-1) << 12);
 128                         else {
 129                                 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 130                                 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 131                                         / radeon_encoder->panel_yres + 1;
 132                                 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 133                                                     RADEON_VERT_STRETCH_ENABLE |
 134                                                     RADEON_VERT_STRETCH_BLEND |
 135                                                     ((radeon_encoder->panel_yres-1) << 12));
 136                         }
 137                 } else if (radeon_encoder->rmx_type == RMX_CENTER) {
 138                         int    blank_width;
 139
 140                         fp_horz_stretch |= ((xres/8-1) << 16);
 141                         fp_vert_stretch |= ((yres-1) << 12);
 142
 143                         crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 144                                            RADEON_CRTC_AUTO_VERT_CENTER_EN);
 145
 146                         blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 147                         if (blank_width > 110)
 148                                 blank_width = 110;
 149
 150                         fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 151                                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 152
 153                         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 154                         if (!hsync_wid)
 155                                 hsync_wid = 1;
 156
 157                         fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 158                                               | ((hsync_wid & 0x3f) << 16)
 159                                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 160                                                  ? RADEON_CRTC_H_SYNC_POL
 161                                                  : 0));
 162
 163                         fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 164                                                 | ((mode->crtc_vdisplay - 1) << 16));
 165
 166                         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 167                         if (!vsync_wid)
 168                                 vsync_wid = 1;
 169
 170                         fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 171                                                | ((vsync_wid & 0x1f) << 16)
 172                                                | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 173                                                   ? RADEON_CRTC_V_SYNC_POL
 174                                                   : 0)));
 175
 176                         fp_horz_vert_active = (((radeon_encoder->panel_yres) & 0xfff) |
 177                                                (((radeon_encoder->panel_xres / 8) & 0x1ff) << 16));
 178                 }
 179         } else {
 180                 fp_horz_stretch |= ((xres/8-1) << 16);
 181                 fp_vert_stretch |= ((yres-1) << 12);
 182         }
 183
 184         RADEON_WRITE(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 185         RADEON_WRITE(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 186         RADEON_WRITE(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 187         RADEON_WRITE(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 188         RADEON_WRITE(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 189         RADEON_WRITE(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 190         RADEON_WRITE(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 191         RADEON_WRITE(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 192
 193 }
 194
 195 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 196 {
 197         struct drm_device *dev = encoder->dev;
 198         struct drm_radeon_private *dev_priv = dev->dev_private;
 199         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 200         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 201         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
 202         uint32_t bios_5_scratch, bios_6_scratch;
 203
 204         DRM_DEBUG("\n");
 205
 206         // FIXME atom/legacy cards like r4xx
 207         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 208         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 209
 210         bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
 211         bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_LCD1_CRTC_SHIFT);
 212
 213         switch (mode) {
 214         case DRM_MODE_DPMS_ON:
 215                 disp_pwr_man = RADEON_READ(RADEON_DISP_PWR_MAN);
 216                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
 217                 RADEON_WRITE(RADEON_DISP_PWR_MAN, disp_pwr_man);
 218                 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 219                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
 220                 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 221                 udelay(1000);
 222                 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 223                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
 224                 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 225
 226                 /* enable lvds, turn on voltage */
 227                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 228                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 229                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 230                 udelay(radeon_encoder->panel_digon_delay * 1000);
 231
 232                 /* enable data */
 233                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
 234                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 235                 udelay(radeon_encoder->panel_blon_delay * 1000);
 236
 237                 /* enable backlight */
 238                 lvds_gen_cntl |= RADEON_LVDS_BLON;
 239                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 240
 241                 /* update bios scratch regs */
 242                 bios_5_scratch |= RADEON_LCD1_ON;
 243                 bios_6_scratch |= RADEON_LCD_DPMS_ON;
 244
 245                 break;
 246         case DRM_MODE_DPMS_STANDBY:
 247         case DRM_MODE_DPMS_SUSPEND:
 248         case DRM_MODE_DPMS_OFF:
 249                 pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
 250                 RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
 251                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 252                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 253                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 254                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 255                 RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
 256
 257                 bios_5_scratch &= ~RADEON_LCD1_ON;
 258                 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
 259                 break;
 260         }
 261         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 262         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 263 }
 264
 265 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 266 {
 267         // fix me: atom/legacy r4xx
 268         radeon_combios_output_lock(encoder, true);
 269         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 270 }
 271
 272 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 273 {
 274         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 275         // fix me: atom/legacy r4xx
 276         radeon_combios_output_lock(encoder, false);
 277 }
 278
 279 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 280                                         struct drm_display_mode *mode,
 281                                         struct drm_display_mode *adjusted_mode)
 282 {
 283         struct drm_device *dev = encoder->dev;
 284         struct drm_radeon_private *dev_priv = dev->dev_private;
 285         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 286         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 287         uint32_t lvds_pll_cntl, lvds_gen_cntl;
 288
 289         DRM_DEBUG("\n");
 290
 291         if (radeon_crtc->crtc_id == 0)
 292                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 293
 294         lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 295         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 296         if (radeon_encoder->lvds_gen_cntl)
 297                 lvds_gen_cntl = radeon_encoder->lvds_gen_cntl;
 298         else
 299                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 300         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 301         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 302                            RADEON_LVDS_BLON |
 303                            RADEON_LVDS_EN |
 304                            RADEON_LVDS_RST_FM);
 305
 306         if (radeon_is_r300(dev_priv))
 307                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 308
 309         if (radeon_crtc->crtc_id == 0) {
 310                 if (radeon_is_r300(dev_priv)) {
 311                         if (radeon_encoder->flags & RADEON_USE_RMX)
 312                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 313                 } else
 314                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 315         } else {
 316                 if (radeon_is_r300(dev_priv)) {
 317                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 318                 } else
 319                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 320         }
 321
 322         RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 323         RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 324
 325         if (dev_priv->chip_family == CHIP_RV410)
 326                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
 327 }
 328
 329 static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
 330                                           struct drm_display_mode *mode,
 331                                           struct drm_display_mode *adjusted_mode)
 332 {
 333         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 334
 335         radeon_encoder->flags &= ~RADEON_USE_RMX;
 336
 337         if (radeon_encoder->rmx_type != RMX_OFF)
 338                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
 339
 340         return true;
 341 }
 342
 343 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 344         .dpms = radeon_legacy_lvds_dpms,
 345         .mode_fixup = radeon_legacy_lvds_mode_fixup,
 346         .prepare = radeon_legacy_lvds_prepare,
 347         .mode_set = radeon_legacy_lvds_mode_set,
 348         .commit = radeon_legacy_lvds_commit,
 349 };
 350
 351
 352 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 353         .destroy = radeon_enc_destroy,
 354 };
 355
 356
 357 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index)
 358 {
 359         struct radeon_encoder *radeon_encoder;
 360         struct drm_encoder *encoder;
 361
 362         DRM_DEBUG("\n");
 363
 364         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 365         if (!radeon_encoder) {
 366                 return NULL;
 367         }
 368
 369         encoder = &radeon_encoder->base;
 370
 371         encoder->possible_crtcs = 0x3;
 372         encoder->possible_clones = 0;
 373         drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
 374                          DRM_MODE_ENCODER_LVDS);
 375
 376         drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
 377
 378         /* get the lvds info from the bios */
 379         radeon_combios_get_lvds_info(radeon_encoder);
 380
 381         /* LVDS gets default RMX full scaling */
 382         radeon_encoder->rmx_type = RMX_FULL;
 383
 384         return encoder;
 385 }
 386
 387 static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
 388                                                  struct drm_display_mode *mode,
 389                                                  struct drm_display_mode *adjusted_mode)
 390 {
 391         return true;
 392 }
 393
 394 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 395 {
 396         struct drm_device *dev = encoder->dev;
 397         struct drm_radeon_private *dev_priv = dev->dev_private;
 398         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 399         uint32_t crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 400         uint32_t dac_cntl = RADEON_READ(RADEON_DAC_CNTL);
 401         uint32_t dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 402         uint32_t bios_5_scratch, bios_6_scratch;
 403
 404         DRM_DEBUG("\n");
 405
 406         // FIXME atom/legacy cards like r4xx
 407         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 408         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 409
 410         bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
 411         bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT1_CRTC_SHIFT);
 412
 413         DRM_DEBUG("\n");
 414
 415         switch(mode) {
 416         case DRM_MODE_DPMS_ON:
 417                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 418                 dac_cntl &= ~RADEON_DAC_PDWN;
 419                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 420                                     RADEON_DAC_PDWN_G |
 421                                     RADEON_DAC_PDWN_B);
 422                 bios_5_scratch |= RADEON_CRT1_ON;
 423                 bios_6_scratch |= RADEON_CRT_DPMS_ON;
 424                 break;
 425         case DRM_MODE_DPMS_STANDBY:
 426         case DRM_MODE_DPMS_SUSPEND:
 427         case DRM_MODE_DPMS_OFF:
 428                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 429                 dac_cntl |= RADEON_DAC_PDWN;
 430                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 431                                    RADEON_DAC_PDWN_G |
 432                                    RADEON_DAC_PDWN_B);
 433                 bios_5_scratch &= ~RADEON_CRT1_ON;
 434                 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
 435                 break;
 436         }
 437
 438         RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 439         RADEON_WRITE(RADEON_DAC_CNTL, dac_cntl);
 440         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 441
 442         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 443         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 444 }
 445
 446 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 447 {
 448         // fix me: atom/legacy r4xx
 449         radeon_combios_output_lock(encoder, true);
 450         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 451 }
 452
 453 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 454 {
 455         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 456         // fix me: atom/legacy r4xx
 457         radeon_combios_output_lock(encoder, false);
 458 }
 459
 460 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 461                                                struct drm_display_mode *mode,
 462                                                struct drm_display_mode *adjusted_mode)
 463 {
 464         struct drm_device *dev = encoder->dev;
 465         struct drm_radeon_private *dev_priv = dev->dev_private;
 466         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 467         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 468         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 469
 470         DRM_DEBUG("\n");
 471
 472         if (radeon_crtc->crtc_id == 0)
 473                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 474
 475         if (radeon_crtc->crtc_id == 0) {
 476                 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
 477                         disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
 478                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 479                         RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 480                 } else {
 481                         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 482                         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 483                 }
 484         } else {
 485                 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
 486                         disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
 487                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 488                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 489                         RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 490                 } else {
 491                         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 492                         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 493                 }
 494         }
 495
 496         dac_cntl = (RADEON_DAC_MASK_ALL |
 497                     RADEON_DAC_VGA_ADR_EN |
 498                     /* TODO 6-bits */
 499                     RADEON_DAC_8BIT_EN);
 500
 501         RADEON_WRITE_P(RADEON_DAC_CNTL,
 502                        dac_cntl,
 503                        RADEON_DAC_RANGE_CNTL |
 504                        RADEON_DAC_BLANKING);
 505
 506         if (radeon_encoder->ps2_pdac_adj)
 507                 dac_macro_cntl = radeon_encoder->ps2_pdac_adj;
 508         else
 509                 dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 510         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 511         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 512 }
 513
 514 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 515 {
 516         // FIXME
 517         return connector_status_disconnected;
 518
 519 }
 520
 521 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 522         .dpms = radeon_legacy_primary_dac_dpms,
 523         .mode_fixup = radeon_legacy_primary_dac_mode_fixup,
 524         .prepare = radeon_legacy_primary_dac_prepare,
 525         .mode_set = radeon_legacy_primary_dac_mode_set,
 526         .commit = radeon_legacy_primary_dac_commit,
 527         .detect = radeon_legacy_primary_dac_detect,
 528 };
 529
 530
 531 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 532         .destroy = radeon_enc_destroy,
 533 };
 534
 535 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int has_tv)
 536 {
 537         struct radeon_encoder *radeon_encoder;
 538         struct drm_encoder *encoder;
 539
 540         DRM_DEBUG("\n");
 541
 542         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 543         if (!radeon_encoder) {
 544                 return NULL;
 545         }
 546
 547         encoder = &radeon_encoder->base;
 548
 549         encoder->possible_crtcs = 0x3;
 550         encoder->possible_clones = 0;
 551         drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
 552                          DRM_MODE_ENCODER_DAC);
 553
 554         drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
 555
 556         /* get the primary dac bg/adj vals from bios tables */
 557         radeon_combios_get_primary_dac_info(radeon_encoder);
 558
 559         return encoder;
 560 }
 561
 562
 563 static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
 564                                               struct drm_display_mode *mode,
 565                                               struct drm_display_mode *adjusted_mode)
 566 {
 567         return true;
 568 }
 569
 570 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 571 {
 572         struct drm_device *dev = encoder->dev;
 573         struct drm_radeon_private *dev_priv = dev->dev_private;
 574         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 575         uint32_t fp_gen_cntl = RADEON_READ(RADEON_FP_GEN_CNTL);
 576         uint32_t bios_5_scratch, bios_6_scratch;
 577
 578         DRM_DEBUG("\n");
 579
 580         // FIXME atom/legacy cards like r4xx
 581         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 582         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 583
 584         bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
 585         bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP1_CRTC_SHIFT);
 586
 587         switch(mode) {
 588         case DRM_MODE_DPMS_ON:
 589                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 590                 bios_5_scratch |= RADEON_DFP1_ON;
 591                 bios_6_scratch |= RADEON_DFP_DPMS_ON;
 592                 break;
 593         case DRM_MODE_DPMS_STANDBY:
 594         case DRM_MODE_DPMS_SUSPEND:
 595         case DRM_MODE_DPMS_OFF:
 596                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 597                 bios_5_scratch &= ~RADEON_DFP1_ON;
 598                 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
 599                 break;
 600         }
 601
 602         RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 603
 604         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 605         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 606 }
 607
 608 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 609 {
 610         // fix me: atom/legacy r4xx
 611         radeon_combios_output_lock(encoder, true);
 612         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 613 }
 614
 615 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 616 {
 617         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 618         // fix me: atom/legacy r4xx
 619         radeon_combios_output_lock(encoder, true);
 620 }
 621
 622 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 623                                             struct drm_display_mode *mode,
 624                                             struct drm_display_mode *adjusted_mode)
 625 {
 626         struct drm_device *dev = encoder->dev;
 627         struct drm_radeon_private *dev_priv = dev->dev_private;
 628         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 629         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 630         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 631         int i;
 632
 633         DRM_DEBUG("\n");
 634
 635         if (radeon_crtc->crtc_id == 0)
 636                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 637
 638         tmp = tmds_pll_cntl = RADEON_READ(RADEON_TMDS_PLL_CNTL);
 639         tmp &= 0xfffff;
 640         if (dev_priv->chip_family == CHIP_RV280) {
 641                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 642                 tmp ^= (1 << 22);
 643                 tmds_pll_cntl ^= (1 << 22);
 644         }
 645
 646         for (i = 0; i < 4; i++) {
 647                 if (radeon_encoder->tmds_pll[i].freq == 0)
 648                         break;
 649                 if ((uint32_t)(mode->clock / 10) < radeon_encoder->tmds_pll[i].freq) {
 650                         tmp = radeon_encoder->tmds_pll[i].value ;
 651                         break;
 652                 }
 653         }
 654
 655         if (radeon_is_r300(dev_priv) || (dev_priv->chip_family == CHIP_RV280)) {
 656                 if (tmp & 0xfff00000)
 657                         tmds_pll_cntl = tmp;
 658                 else {
 659                         tmds_pll_cntl &= 0xfff00000;
 660                         tmds_pll_cntl |= tmp;
 661                 }
 662         } else
 663                 tmds_pll_cntl = tmp;
 664
 665         tmds_transmitter_cntl = RADEON_READ(RADEON_TMDS_TRANSMITTER_CNTL) &
 666                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 667
 668     if (dev_priv->chip_family == CHIP_R200 ||
 669         dev_priv->chip_family == CHIP_R100 ||
 670         radeon_is_r300(dev_priv))
 671             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 672     else /* RV chips got this bit reversed */
 673             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 674
 675     fp_gen_cntl = (RADEON_READ(RADEON_FP_GEN_CNTL) |
 676                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 677                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 678
 679     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 680
 681     if (1) // FIXME rgbBits == 8
 682             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 683     else
 684             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 685
 686     if (radeon_crtc->crtc_id == 0) {
 687             if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
 688                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 689                     if (radeon_encoder->flags & RADEON_USE_RMX)
 690                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 691                     else
 692                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 693             } else
 694                     fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
 695     } else {
 696             if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
 697                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 698                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 699             } else
 700                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 701     }
 702
 703     RADEON_WRITE(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 704     RADEON_WRITE(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 705     RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 706 }
 707
 708 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 709         .dpms = radeon_legacy_tmds_int_dpms,
 710         .mode_fixup = radeon_legacy_tmds_int_mode_fixup,
 711         .prepare = radeon_legacy_tmds_int_prepare,
 712         .mode_set = radeon_legacy_tmds_int_mode_set,
 713         .commit = radeon_legacy_tmds_int_commit,
 714 };
 715
 716
 717 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 718         .destroy = radeon_enc_destroy,
 719 };
 720
 721 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index)
 722 {
 723         struct radeon_encoder *radeon_encoder;
 724         struct drm_encoder *encoder;
 725
 726         DRM_DEBUG("\n");
 727
 728         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 729         if (!radeon_encoder) {
 730                 return NULL;
 731         }
 732
 733         encoder = &radeon_encoder->base;
 734
 735         encoder->possible_crtcs = 0x3;
 736         encoder->possible_clones = 0;
 737         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
 738                          DRM_MODE_ENCODER_TMDS);
 739
 740         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
 741
 742         radeon_combios_get_tmds_info(radeon_encoder);
 743
 744         return encoder;
 745 }
 746
 747 static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
 748                                               struct drm_display_mode *mode,
 749                                               struct drm_display_mode *adjusted_mode)
 750 {
 751         return true;
 752 }
 753
 754 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 755 {
 756         struct drm_device *dev = encoder->dev;
 757         struct drm_radeon_private *dev_priv = dev->dev_private;
 758         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 759         uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 760         uint32_t bios_5_scratch, bios_6_scratch;
 761
 762         DRM_DEBUG("\n");
 763
 764         // FIXME atom/legacy cards like r4xx
 765         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 766         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 767
 768         bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
 769         bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP2_CRTC_SHIFT);
 770
 771         switch(mode) {
 772         case DRM_MODE_DPMS_ON:
 773                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 774                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 775                 bios_5_scratch |= RADEON_DFP2_ON;
 776                 bios_6_scratch |= RADEON_DFP_DPMS_ON;
 777                 break;
 778         case DRM_MODE_DPMS_STANDBY:
 779         case DRM_MODE_DPMS_SUSPEND:
 780         case DRM_MODE_DPMS_OFF:
 781                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 782                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 783                 bios_5_scratch &= ~RADEON_DFP2_ON;
 784                 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
 785                 break;
 786         }
 787
 788         RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 789
 790         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 791         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 792 }
 793
 794 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 795 {
 796         // fix me: atom/legacy r4xx
 797         radeon_combios_output_lock(encoder, true);
 798         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 799 }
 800
 801 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 802 {
 803         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 804         // fix me: atom/legacy r4xx
 805         radeon_combios_output_lock(encoder, false);
 806 }
 807
 808 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 809                                             struct drm_display_mode *mode,
 810                                             struct drm_display_mode *adjusted_mode)
 811 {
 812         struct drm_device *dev = encoder->dev;
 813         struct drm_radeon_private *dev_priv = dev->dev_private;
 814         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 815         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 816         uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 817
 818         DRM_DEBUG("\n");
 819
 820         if (radeon_crtc->crtc_id == 0)
 821                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 822
 823         if (1) // FIXME rgbBits == 8
 824                 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 825         else
 826                 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 827
 828         fp2_gen_cntl &= ~(RADEON_FP2_ON |
 829                           RADEON_FP2_DVO_EN |
 830                           RADEON_FP2_DVO_RATE_SEL_SDR);
 831
 832         /* XXX: these are oem specific */
 833         if (radeon_is_r300(dev_priv)) {
 834                 if ((dev->pdev->device == 0x4850) &&
 835                     (dev->pdev->subsystem_vendor == 0x1028) &&
 836                     (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 837                         fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 838                 else
 839                         fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 840
 841                 /*if (mode->clock > 165000)
 842                         fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 843         }
 844
 845         if (radeon_crtc->crtc_id == 0) {
 846                 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
 847                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 848                         if (radeon_encoder->flags & RADEON_USE_RMX)
 849                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 850                         else
 851                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 852                 } else
 853                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 854         } else {
 855                 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
 856                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 857                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 858                 } else
 859                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 860         }
 861
 862         RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 863 }
 864
 865 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 866         .dpms = radeon_legacy_tmds_ext_dpms,
 867         .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
 868         .prepare = radeon_legacy_tmds_ext_prepare,
 869         .mode_set = radeon_legacy_tmds_ext_mode_set,
 870         .commit = radeon_legacy_tmds_ext_commit,
 871 };
 872
 873
 874 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 875         .destroy = radeon_enc_destroy,
 876 };
 877
 878 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index)
 879 {
 880         struct radeon_encoder *radeon_encoder;
 881         struct drm_encoder *encoder;
 882
 883         DRM_DEBUG("\n");
 884
 885         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 886         if (!radeon_encoder) {
 887                 return NULL;
 888         }
 889
 890         encoder = &radeon_encoder->base;
 891
 892         encoder->possible_crtcs = 0x3;
 893         encoder->possible_clones = 0;
 894         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
 895                          DRM_MODE_ENCODER_TMDS);
 896
 897         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
 898
 899         //radeon_combios_get_tmds_info(radeon_encoder);
 900         return encoder;
 901 }
 902
 903 static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
 904                                             struct drm_display_mode *mode,
 905                                             struct drm_display_mode *adjusted_mode)
 906 {
 907         return true;
 908 }
 909
 910 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 911 {
 912         struct drm_device *dev = encoder->dev;
 913         struct drm_radeon_private *dev_priv = dev->dev_private;
 914         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 915         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
 916         //uint32_t tv_master_cntl = 0;
 917         uint32_t bios_5_scratch, bios_6_scratch;
 918
 919         DRM_DEBUG("\n");
 920
 921         // FIXME atom/legacy cards like r4xx
 922         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 923         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 924
 925         bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
 926         bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT2_CRTC_SHIFT);
 927         // FIXME TV
 928         //bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
 929         //bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_TV1_CRTC_SHIFT);
 930
 931         if (dev_priv->chip_family == CHIP_R200)
 932                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 933         else {
 934                 crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
 935                 // FIXME TV
 936                 //tv_master_cntl = RADEON_READ(RADEON_TV_MASTER_CNTL);
 937                 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
 938         }
 939
 940         switch(mode) {
 941         case DRM_MODE_DPMS_ON:
 942                 if (dev_priv->chip_family == CHIP_R200)
 943                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 944                 else {
 945                         crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
 946                         //tv_master_cntl |= RADEON_TV_ON;
 947                         if (dev_priv->chip_family == CHIP_R420 ||
 948                             dev_priv->chip_family == CHIP_RV410)
 949                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
 950                                                  R420_TV_DAC_GDACPD |
 951                                                  R420_TV_DAC_BDACPD |
 952                                                  RADEON_TV_DAC_BGSLEEP);
 953                         else
 954                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
 955                                                  RADEON_TV_DAC_GDACPD |
 956                                                  RADEON_TV_DAC_BDACPD |
 957                                                  RADEON_TV_DAC_BGSLEEP);
 958                 }
 959                 //bios_5_scratch |= RADEON_TV1_ON;
 960                 //bios_6_scratch |= RADEON_TV_DPMS_ON;
 961                 bios_5_scratch |= RADEON_CRT2_ON;
 962                 bios_6_scratch |= RADEON_CRT_DPMS_ON;
 963                 break;
 964         case DRM_MODE_DPMS_STANDBY:
 965         case DRM_MODE_DPMS_SUSPEND:
 966         case DRM_MODE_DPMS_OFF:
 967                 if (dev_priv->chip_family == CHIP_R200)
 968                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 969                 else {
 970                         crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
 971                         //tv_master_cntl &= ~RADEON_TV_ON;
 972                         if (dev_priv->chip_family == CHIP_R420 ||
 973                             dev_priv->chip_family == CHIP_RV410)
 974                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
 975                                                 R420_TV_DAC_GDACPD |
 976                                                 R420_TV_DAC_BDACPD |
 977                                                 RADEON_TV_DAC_BGSLEEP);
 978                         else
 979                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
 980                                                 RADEON_TV_DAC_GDACPD |
 981                                                 RADEON_TV_DAC_BDACPD |
 982                                                 RADEON_TV_DAC_BGSLEEP);
 983                 }
 984                 //bios_5_scratch &= ~RADEON_TV1_ON;
 985                 //bios_6_scratch &= ~RADEON_TV_DPMS_ON;
 986                 bios_5_scratch &= ~RADEON_CRT2_ON;
 987                 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
 988                 break;
 989         }
 990
 991         if (dev_priv->chip_family == CHIP_R200)
 992                 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 993         else {
 994                 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 995                 //RADEON_WRITE(RADEON_TV_MASTER_CNTL, tv_master_cntl);
 996                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 997         }
 998
 999         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
1000         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1001 }
1002
1003 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1004 {
1005         // fix me: atom/legacy r4xx
1006         radeon_combios_output_lock(encoder, true);
1007         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1008 }
1009
1010 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1011 {
1012         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1013         // fix me: atom/legacy r4xx
1014         radeon_combios_output_lock(encoder, false);
1015 }
1016
1017 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1018                                           struct drm_display_mode *mode,
1019                                           struct drm_display_mode *adjusted_mode)
1020 {
1021         struct drm_device *dev = encoder->dev;
1022         struct drm_radeon_private *dev_priv = dev->dev_private;
1023         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1024         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1025         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1026         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0;
1027
1028         DRM_DEBUG("\n");
1029
1030         if (radeon_crtc->crtc_id == 0)
1031                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
1032
1033         if (dev_priv->chip_family != CHIP_R200) {
1034                 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
1035                 if (dev_priv->chip_family == CHIP_R420 ||
1036                     dev_priv->chip_family == CHIP_RV410) {
1037                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1038                                          RADEON_TV_DAC_BGADJ_MASK |
1039                                          R420_TV_DAC_DACADJ_MASK |
1040                                          R420_TV_DAC_RDACPD |
1041                                          R420_TV_DAC_GDACPD |
1042                                          R420_TV_DAC_GDACPD |
1043                                          R420_TV_DAC_TVENABLE);
1044                 } else {
1045                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1046                                          RADEON_TV_DAC_BGADJ_MASK |
1047                                          RADEON_TV_DAC_DACADJ_MASK |
1048                                          RADEON_TV_DAC_RDACPD |
1049                                          RADEON_TV_DAC_GDACPD |
1050                                          RADEON_TV_DAC_GDACPD);
1051                 }
1052
1053                 // FIXME TV
1054                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1055                                 RADEON_TV_DAC_NHOLD |
1056                                 RADEON_TV_DAC_STD_PS2 |
1057                                 radeon_encoder->ps2_tvdac_adj);
1058
1059                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1060         }
1061
1062         if (radeon_is_r300(dev_priv)) {
1063                 gpiopad_a = RADEON_READ(RADEON_GPIOPAD_A) | 1;
1064                 disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL);
1065         } else if (dev_priv->chip_family == CHIP_R200)
1066                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
1067         else
1068                 disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
1069
1070         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1071
1072         if (radeon_crtc->crtc_id == 0) {
1073                 if (radeon_is_r300(dev_priv)) {
1074                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1075                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1076                 } else if (dev_priv->chip_family == CHIP_R200) {
1077                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1078                                           RADEON_FP2_DVO_RATE_SEL_SDR);
1079                 } else
1080                         disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1081         } else {
1082                 if (radeon_is_r300(dev_priv)) {
1083                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1084                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1085                 } else if (dev_priv->chip_family == CHIP_R200) {
1086                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1087                                           RADEON_FP2_DVO_RATE_SEL_SDR);
1088                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1089                 } else
1090                         disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1091         }
1092
1093         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
1094
1095         if (radeon_is_r300(dev_priv)) {
1096                 RADEON_WRITE_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1097                 RADEON_WRITE(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
1098         } else if (dev_priv->chip_family == CHIP_R200)
1099                 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1100         else
1101                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1102
1103 }
1104
1105 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1106 {
1107         // FIXME
1108         return connector_status_disconnected;
1109
1110 }
1111
1112 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1113         .dpms = radeon_legacy_tv_dac_dpms,
1114         .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
1115         .prepare = radeon_legacy_tv_dac_prepare,
1116         .mode_set = radeon_legacy_tv_dac_mode_set,
1117         .commit = radeon_legacy_tv_dac_commit,
1118         .detect = radeon_legacy_tv_dac_detect,
1119 };
1120
1121
1122 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1123         .destroy = radeon_enc_destroy,
1124 };
1125
1126 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int has_tv)
1127 {
1128         struct radeon_encoder *radeon_encoder;
1129         struct drm_encoder *encoder;
1130
1131         DRM_DEBUG("\n");
1132
1133         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1134         if (!radeon_encoder) {
1135                 return NULL;
1136         }
1137
1138         encoder = &radeon_encoder->base;
1139
1140         encoder->possible_crtcs = 0x3;
1141         encoder->possible_clones = 0;
1142         drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1143                          DRM_MODE_ENCODER_DAC);
1144
1145         drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1146
1147         /* get the tv dac vals from bios tables */
1148         radeon_combios_get_tv_info(radeon_encoder);
1149         radeon_combios_get_tv_dac_info(radeon_encoder);
1150
1151         return encoder;
1152 }