2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon_drv.h"
32 static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder,
33 struct drm_display_mode *mode,
34 struct drm_display_mode *adjusted_mode)
36 struct drm_device *dev = encoder->dev;
37 struct drm_radeon_private *dev_priv = dev->dev_private;
38 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
39 int xres = mode->hdisplay;
40 int yres = mode->vdisplay;
41 bool hscale = true, vscale = true;
46 uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active;
47 uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp;
51 fp_vert_stretch = RADEON_READ(RADEON_FP_VERT_STRETCH) &
52 (RADEON_VERT_STRETCH_RESERVED |
53 RADEON_VERT_AUTO_RATIO_INC);
54 fp_horz_stretch = RADEON_READ(RADEON_FP_HORZ_STRETCH) &
55 (RADEON_HORZ_FP_LOOP_STRETCH |
56 RADEON_HORZ_AUTO_RATIO_INC);
59 if ((dev_priv->chip_family == CHIP_RS100) ||
60 (dev_priv->chip_family == CHIP_RS200)) {
61 /* This is to workaround the asic bug for RMX, some versions
62 of BIOS dosen't have this register initialized correctly. */
63 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
67 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
68 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
70 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
73 hsync_start = mode->crtc_hsync_start - 8;
75 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
76 | ((hsync_wid & 0x3f) << 16)
77 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
78 ? RADEON_CRTC_H_SYNC_POL
81 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
82 | ((mode->crtc_vdisplay - 1) << 16));
84 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
88 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
89 | ((vsync_wid & 0x1f) << 16)
90 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
91 ? RADEON_CRTC_V_SYNC_POL
94 fp_horz_vert_active = 0;
96 if (radeon_encoder->panel_xres == 0 ||
97 radeon_encoder->panel_yres == 0) {
101 if (xres > radeon_encoder->panel_xres)
102 xres = radeon_encoder->panel_xres;
103 if (yres > radeon_encoder->panel_yres)
104 yres = radeon_encoder->panel_yres;
106 if (xres == radeon_encoder->panel_xres)
108 if (yres == radeon_encoder->panel_yres)
112 if (radeon_encoder->flags & RADEON_USE_RMX) {
113 if (radeon_encoder->rmx_type != RMX_CENTER) {
115 fp_horz_stretch |= ((xres/8-1) << 16);
117 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
118 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
119 / radeon_encoder->panel_xres + 1;
120 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
121 RADEON_HORZ_STRETCH_BLEND |
122 RADEON_HORZ_STRETCH_ENABLE |
123 ((radeon_encoder->panel_xres/8-1) << 16));
127 fp_vert_stretch |= ((yres-1) << 12);
129 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
130 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
131 / radeon_encoder->panel_yres + 1;
132 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
133 RADEON_VERT_STRETCH_ENABLE |
134 RADEON_VERT_STRETCH_BLEND |
135 ((radeon_encoder->panel_yres-1) << 12));
137 } else if (radeon_encoder->rmx_type == RMX_CENTER) {
140 fp_horz_stretch |= ((xres/8-1) << 16);
141 fp_vert_stretch |= ((yres-1) << 12);
143 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
144 RADEON_CRTC_AUTO_VERT_CENTER_EN);
146 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
147 if (blank_width > 110)
150 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
151 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
153 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
157 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
158 | ((hsync_wid & 0x3f) << 16)
159 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
160 ? RADEON_CRTC_H_SYNC_POL
163 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
164 | ((mode->crtc_vdisplay - 1) << 16));
166 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
170 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
171 | ((vsync_wid & 0x1f) << 16)
172 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
173 ? RADEON_CRTC_V_SYNC_POL
176 fp_horz_vert_active = (((radeon_encoder->panel_yres) & 0xfff) |
177 (((radeon_encoder->panel_xres / 8) & 0x1ff) << 16));
180 fp_horz_stretch |= ((xres/8-1) << 16);
181 fp_vert_stretch |= ((yres-1) << 12);
184 RADEON_WRITE(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
185 RADEON_WRITE(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
186 RADEON_WRITE(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
187 RADEON_WRITE(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
188 RADEON_WRITE(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
189 RADEON_WRITE(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
190 RADEON_WRITE(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
191 RADEON_WRITE(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
195 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
197 struct drm_device *dev = encoder->dev;
198 struct drm_radeon_private *dev_priv = dev->dev_private;
199 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
200 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
205 case DRM_MODE_DPMS_ON:
206 disp_pwr_man = RADEON_READ(RADEON_DISP_PWR_MAN);
207 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
208 RADEON_WRITE(RADEON_DISP_PWR_MAN, disp_pwr_man);
209 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
210 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
211 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
213 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
214 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
215 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
217 /* enable lvds, turn on voltage */
218 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
219 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
220 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
221 udelay(radeon_encoder->panel_digon_delay * 1000);
224 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
225 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
226 udelay(radeon_encoder->panel_blon_delay * 1000);
228 /* enable backlight */
229 lvds_gen_cntl |= RADEON_LVDS_BLON;
230 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
232 case DRM_MODE_DPMS_STANDBY:
233 case DRM_MODE_DPMS_SUSPEND:
234 case DRM_MODE_DPMS_OFF:
235 pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
236 RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
237 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
238 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
239 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
240 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
241 RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
246 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
248 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
251 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
253 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
256 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
257 struct drm_display_mode *mode,
258 struct drm_display_mode *adjusted_mode)
260 struct drm_device *dev = encoder->dev;
261 struct drm_radeon_private *dev_priv = dev->dev_private;
262 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
263 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
264 uint32_t lvds_pll_cntl, lvds_gen_cntl;
268 if (radeon_crtc->crtc_id == 0)
269 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
271 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
272 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
273 if (radeon_encoder->lvds_gen_cntl)
274 lvds_gen_cntl = radeon_encoder->lvds_gen_cntl;
276 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
277 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
278 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
283 if (radeon_is_r300(dev_priv))
284 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
286 if (radeon_crtc->crtc_id == 0) {
287 if (radeon_is_r300(dev_priv)) {
288 if (radeon_encoder->flags & RADEON_USE_RMX)
289 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
291 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
293 if (radeon_is_r300(dev_priv)) {
294 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
296 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
299 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
300 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
302 if (dev_priv->chip_family == CHIP_RV410)
303 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
306 static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
307 struct drm_display_mode *mode,
308 struct drm_display_mode *adjusted_mode)
310 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
312 radeon_encoder->flags &= ~RADEON_USE_RMX;
314 if (radeon_encoder->rmx_type != RMX_OFF)
315 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
320 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
321 .dpms = radeon_legacy_lvds_dpms,
322 .mode_fixup = radeon_legacy_lvds_mode_fixup,
323 .prepare = radeon_legacy_lvds_prepare,
324 .mode_set = radeon_legacy_lvds_mode_set,
325 .commit = radeon_legacy_lvds_commit,
329 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
330 .destroy = radeon_enc_destroy,
334 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index)
336 struct radeon_encoder *radeon_encoder;
337 struct drm_encoder *encoder;
341 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
342 if (!radeon_encoder) {
346 encoder = &radeon_encoder->base;
348 encoder->possible_crtcs = 0x3;
349 encoder->possible_clones = 0;
350 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
351 DRM_MODE_ENCODER_LVDS);
353 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
355 /* get the lvds info from the bios */
356 radeon_combios_get_lvds_info(radeon_encoder);
358 /* LVDS gets default RMX full scaling */
359 radeon_encoder->rmx_type = RMX_FULL;
364 static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
365 struct drm_display_mode *mode,
366 struct drm_display_mode *adjusted_mode)
371 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
373 struct drm_device *dev = encoder->dev;
374 struct drm_radeon_private *dev_priv = dev->dev_private;
375 uint32_t crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
376 uint32_t dac_cntl = RADEON_READ(RADEON_DAC_CNTL);
377 uint32_t dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
382 case DRM_MODE_DPMS_ON:
383 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
384 dac_cntl &= ~RADEON_DAC_PDWN;
385 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
389 case DRM_MODE_DPMS_STANDBY:
390 case DRM_MODE_DPMS_SUSPEND:
391 case DRM_MODE_DPMS_OFF:
392 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
393 dac_cntl |= RADEON_DAC_PDWN;
394 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
400 RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
401 RADEON_WRITE(RADEON_DAC_CNTL, dac_cntl);
402 RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
406 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
408 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
411 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
413 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
416 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
417 struct drm_display_mode *mode,
418 struct drm_display_mode *adjusted_mode)
420 struct drm_device *dev = encoder->dev;
421 struct drm_radeon_private *dev_priv = dev->dev_private;
422 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
423 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
424 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
428 if (radeon_crtc->crtc_id == 0)
429 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
431 if (radeon_crtc->crtc_id == 0) {
432 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
433 disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
434 ~(RADEON_DISP_DAC_SOURCE_MASK);
435 RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
437 dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
438 RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
441 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
442 disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
443 ~(RADEON_DISP_DAC_SOURCE_MASK);
444 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
445 RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
447 dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
448 RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
452 dac_cntl = (RADEON_DAC_MASK_ALL |
453 RADEON_DAC_VGA_ADR_EN |
457 RADEON_WRITE_P(RADEON_DAC_CNTL,
459 RADEON_DAC_RANGE_CNTL |
460 RADEON_DAC_BLANKING);
462 if (radeon_encoder->ps2_pdac_adj)
463 dac_macro_cntl = radeon_encoder->ps2_pdac_adj;
465 dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
466 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
467 RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
470 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
473 return connector_status_disconnected;
477 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
478 .dpms = radeon_legacy_primary_dac_dpms,
479 .mode_fixup = radeon_legacy_primary_dac_mode_fixup,
480 .prepare = radeon_legacy_primary_dac_prepare,
481 .mode_set = radeon_legacy_primary_dac_mode_set,
482 .commit = radeon_legacy_primary_dac_commit,
483 .detect = radeon_legacy_primary_dac_detect,
487 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
488 .destroy = radeon_enc_destroy,
491 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int has_tv)
493 struct radeon_encoder *radeon_encoder;
494 struct drm_encoder *encoder;
498 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
499 if (!radeon_encoder) {
503 encoder = &radeon_encoder->base;
505 encoder->possible_crtcs = 0x3;
506 encoder->possible_clones = 0;
507 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
508 DRM_MODE_ENCODER_DAC);
510 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
512 /* get the primary dac bg/adj vals from bios tables */
513 radeon_combios_get_primary_dac_info(radeon_encoder);
519 static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
520 struct drm_display_mode *mode,
521 struct drm_display_mode *adjusted_mode)
526 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
528 struct drm_device *dev = encoder->dev;
529 struct drm_radeon_private *dev_priv = dev->dev_private;
530 uint32_t fp_gen_cntl = RADEON_READ(RADEON_FP_GEN_CNTL);
535 case DRM_MODE_DPMS_ON:
536 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
538 case DRM_MODE_DPMS_STANDBY:
539 case DRM_MODE_DPMS_SUSPEND:
540 case DRM_MODE_DPMS_OFF:
541 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
545 RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
548 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
550 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
553 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
555 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
558 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
559 struct drm_display_mode *mode,
560 struct drm_display_mode *adjusted_mode)
562 struct drm_device *dev = encoder->dev;
563 struct drm_radeon_private *dev_priv = dev->dev_private;
564 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
565 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
566 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
571 if (radeon_crtc->crtc_id == 0)
572 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
574 tmp = tmds_pll_cntl = RADEON_READ(RADEON_TMDS_PLL_CNTL);
576 if (dev_priv->chip_family == CHIP_RV280) {
577 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
579 tmds_pll_cntl ^= (1 << 22);
582 for (i = 0; i < 4; i++) {
583 if (radeon_encoder->tmds_pll[i].freq == 0)
585 if ((uint32_t)(mode->clock / 10) < radeon_encoder->tmds_pll[i].freq) {
586 tmp = radeon_encoder->tmds_pll[i].value ;
591 if (radeon_is_r300(dev_priv) || (dev_priv->chip_family == CHIP_RV280)) {
592 if (tmp & 0xfff00000)
595 tmds_pll_cntl &= 0xfff00000;
596 tmds_pll_cntl |= tmp;
601 tmds_transmitter_cntl = RADEON_READ(RADEON_TMDS_TRANSMITTER_CNTL) &
602 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
604 if (dev_priv->chip_family == CHIP_R200 ||
605 dev_priv->chip_family == CHIP_R100 ||
606 radeon_is_r300(dev_priv))
607 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
608 else /* RV chips got this bit reversed */
609 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
611 fp_gen_cntl = (RADEON_READ(RADEON_FP_GEN_CNTL) |
612 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
613 RADEON_FP_CRTC_DONT_SHADOW_HEND));
615 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
617 if (1) // FIXME rgbBits == 8
618 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
620 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
622 if (radeon_crtc->crtc_id == 0) {
623 if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
624 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
625 if (radeon_encoder->flags & RADEON_USE_RMX)
626 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
628 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
630 fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
632 if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
633 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
634 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
636 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
639 RADEON_WRITE(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
640 RADEON_WRITE(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
641 RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
644 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
645 .dpms = radeon_legacy_tmds_int_dpms,
646 .mode_fixup = radeon_legacy_tmds_int_mode_fixup,
647 .prepare = radeon_legacy_tmds_int_prepare,
648 .mode_set = radeon_legacy_tmds_int_mode_set,
649 .commit = radeon_legacy_tmds_int_commit,
653 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
654 .destroy = radeon_enc_destroy,
657 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index)
659 struct radeon_encoder *radeon_encoder;
660 struct drm_encoder *encoder;
664 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
665 if (!radeon_encoder) {
669 encoder = &radeon_encoder->base;
671 encoder->possible_crtcs = 0x3;
672 encoder->possible_clones = 0;
673 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
674 DRM_MODE_ENCODER_TMDS);
676 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
678 radeon_combios_get_tmds_info(radeon_encoder);
683 static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
684 struct drm_display_mode *mode,
685 struct drm_display_mode *adjusted_mode)
690 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
692 struct drm_device *dev = encoder->dev;
693 struct drm_radeon_private *dev_priv = dev->dev_private;
694 uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
699 case DRM_MODE_DPMS_ON:
700 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
701 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
703 case DRM_MODE_DPMS_STANDBY:
704 case DRM_MODE_DPMS_SUSPEND:
705 case DRM_MODE_DPMS_OFF:
706 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
707 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
711 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
714 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
716 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
719 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
721 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
724 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
725 struct drm_display_mode *mode,
726 struct drm_display_mode *adjusted_mode)
728 struct drm_device *dev = encoder->dev;
729 struct drm_radeon_private *dev_priv = dev->dev_private;
730 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
731 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
732 uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
736 if (radeon_crtc->crtc_id == 0)
737 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
739 if (1) // FIXME rgbBits == 8
740 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
742 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
744 fp2_gen_cntl &= ~(RADEON_FP2_ON |
746 RADEON_FP2_DVO_RATE_SEL_SDR);
748 /* XXX: these are oem specific */
749 if (radeon_is_r300(dev_priv)) {
750 if ((dev->pdev->device == 0x4850) &&
751 (dev->pdev->subsystem_vendor == 0x1028) &&
752 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
753 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
755 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
757 /*if (mode->clock > 165000)
758 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
761 if (radeon_crtc->crtc_id == 0) {
762 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
763 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
764 if (radeon_encoder->flags & RADEON_USE_RMX)
765 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
767 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
769 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
771 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
772 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
773 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
775 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
778 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
781 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
782 .dpms = radeon_legacy_tmds_ext_dpms,
783 .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
784 .prepare = radeon_legacy_tmds_ext_prepare,
785 .mode_set = radeon_legacy_tmds_ext_mode_set,
786 .commit = radeon_legacy_tmds_ext_commit,
790 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
791 .destroy = radeon_enc_destroy,
794 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index)
796 struct radeon_encoder *radeon_encoder;
797 struct drm_encoder *encoder;
801 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
802 if (!radeon_encoder) {
806 encoder = &radeon_encoder->base;
808 encoder->possible_crtcs = 0x3;
809 encoder->possible_clones = 0;
810 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
811 DRM_MODE_ENCODER_TMDS);
813 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
815 //radeon_combios_get_tmds_info(radeon_encoder);
819 static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
820 struct drm_display_mode *mode,
821 struct drm_display_mode *adjusted_mode)
826 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
828 struct drm_device *dev = encoder->dev;
829 struct drm_radeon_private *dev_priv = dev->dev_private;
830 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
831 //uint32_t tv_master_cntl = 0;
835 if (dev_priv->chip_family == CHIP_R200)
836 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
838 crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
840 //tv_master_cntl = RADEON_READ(RADEON_TV_MASTER_CNTL);
841 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
845 case DRM_MODE_DPMS_ON:
846 if (dev_priv->chip_family == CHIP_R200)
847 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
849 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
850 //tv_master_cntl |= RADEON_TV_ON;
851 if (dev_priv->chip_family == CHIP_R420 ||
852 dev_priv->chip_family == CHIP_RV410)
853 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
856 RADEON_TV_DAC_BGSLEEP);
858 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
859 RADEON_TV_DAC_GDACPD |
860 RADEON_TV_DAC_BDACPD |
861 RADEON_TV_DAC_BGSLEEP);
864 case DRM_MODE_DPMS_STANDBY:
865 case DRM_MODE_DPMS_SUSPEND:
866 case DRM_MODE_DPMS_OFF:
867 if (dev_priv->chip_family == CHIP_R200)
868 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
870 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
871 //tv_master_cntl &= ~RADEON_TV_ON;
872 if (dev_priv->chip_family == CHIP_R420 ||
873 dev_priv->chip_family == CHIP_RV410)
874 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
877 RADEON_TV_DAC_BGSLEEP);
879 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
880 RADEON_TV_DAC_GDACPD |
881 RADEON_TV_DAC_BDACPD |
882 RADEON_TV_DAC_BGSLEEP);
887 if (dev_priv->chip_family == CHIP_R200)
888 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
890 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
891 //RADEON_WRITE(RADEON_TV_MASTER_CNTL, tv_master_cntl);
892 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
897 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
899 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
902 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
904 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
907 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
908 struct drm_display_mode *mode,
909 struct drm_display_mode *adjusted_mode)
911 struct drm_device *dev = encoder->dev;
912 struct drm_radeon_private *dev_priv = dev->dev_private;
913 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
914 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
915 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
916 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0;
920 if (radeon_crtc->crtc_id == 0)
921 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
923 if (dev_priv->chip_family != CHIP_R200) {
924 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
925 if (dev_priv->chip_family == CHIP_R420 ||
926 dev_priv->chip_family == CHIP_RV410) {
927 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
928 RADEON_TV_DAC_BGADJ_MASK |
929 R420_TV_DAC_DACADJ_MASK |
933 R420_TV_DAC_TVENABLE);
935 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
936 RADEON_TV_DAC_BGADJ_MASK |
937 RADEON_TV_DAC_DACADJ_MASK |
938 RADEON_TV_DAC_RDACPD |
939 RADEON_TV_DAC_GDACPD |
940 RADEON_TV_DAC_GDACPD);
944 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
945 RADEON_TV_DAC_NHOLD |
946 RADEON_TV_DAC_STD_PS2 |
947 radeon_encoder->ps2_tvdac_adj);
949 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
952 if (radeon_is_r300(dev_priv)) {
953 gpiopad_a = RADEON_READ(RADEON_GPIOPAD_A) | 1;
954 disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL);
955 } else if (dev_priv->chip_family == CHIP_R200)
956 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
958 disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
960 dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
962 if (radeon_crtc->crtc_id == 0) {
963 if (radeon_is_r300(dev_priv)) {
964 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
965 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
966 } else if (dev_priv->chip_family == CHIP_R200) {
967 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
968 RADEON_FP2_DVO_RATE_SEL_SDR);
970 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
972 if (radeon_is_r300(dev_priv)) {
973 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
974 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
975 } else if (dev_priv->chip_family == CHIP_R200) {
976 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
977 RADEON_FP2_DVO_RATE_SEL_SDR);
978 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
980 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
983 RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
985 if (radeon_is_r300(dev_priv)) {
986 RADEON_WRITE_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
987 RADEON_WRITE(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
988 } else if (dev_priv->chip_family == CHIP_R200)
989 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
991 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
995 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
998 return connector_status_disconnected;
1002 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1003 .dpms = radeon_legacy_tv_dac_dpms,
1004 .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
1005 .prepare = radeon_legacy_tv_dac_prepare,
1006 .mode_set = radeon_legacy_tv_dac_mode_set,
1007 .commit = radeon_legacy_tv_dac_commit,
1008 .detect = radeon_legacy_tv_dac_detect,
1012 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1013 .destroy = radeon_enc_destroy,
1016 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int has_tv)
1018 struct radeon_encoder *radeon_encoder;
1019 struct drm_encoder *encoder;
1023 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1024 if (!radeon_encoder) {
1028 encoder = &radeon_encoder->base;
1030 encoder->possible_crtcs = 0x3;
1031 encoder->possible_clones = 0;
1032 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1033 DRM_MODE_ENCODER_DAC);
1035 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1037 /* get the tv dac vals from bios tables */
1038 radeon_combios_get_tv_info(radeon_encoder);
1039 radeon_combios_get_tv_dac_info(radeon_encoder);