linux-core/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31
  32 static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder,
  33                                        struct drm_display_mode *mode,
  34                                        struct drm_display_mode *adjusted_mode)
  35 {
  36         struct drm_device *dev = encoder->dev;
  37         struct drm_radeon_private *dev_priv = dev->dev_private;
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  39         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  40         int    xres = mode->hdisplay;
  41         int    yres = mode->vdisplay;
  42         bool   hscale = true, vscale = true;
  43         int    hsync_wid;
  44         int    vsync_wid;
  45         int    hsync_start;
  46         uint32_t scale, inc;
  47         uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active;
  48         uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp;
  49
  50
  51         fp_vert_stretch = RADEON_READ(RADEON_FP_VERT_STRETCH) &
  52                 (RADEON_VERT_STRETCH_RESERVED |
  53                  RADEON_VERT_AUTO_RATIO_INC);
  54         fp_horz_stretch = RADEON_READ(RADEON_FP_HORZ_STRETCH) &
  55                 (RADEON_HORZ_FP_LOOP_STRETCH |
  56                  RADEON_HORZ_AUTO_RATIO_INC);
  57
  58         crtc_more_cntl = 0;
  59         if ((dev_priv->chip_family == CHIP_RS100) ||
  60             (dev_priv->chip_family == CHIP_RS200)) {
  61                 /* This is to workaround the asic bug for RMX, some versions
  62                    of BIOS dosen't have this register initialized correctly. */
  63                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  64         }
  65
  66
  67         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  68                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  69
  70         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  71         if (!hsync_wid)
  72                 hsync_wid = 1;
  73         hsync_start = mode->crtc_hsync_start - 8;
  74
  75         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  76                               | ((hsync_wid & 0x3f) << 16)
  77                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  78                                  ? RADEON_CRTC_H_SYNC_POL
  79                                  : 0));
  80
  81         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  82                                 | ((mode->crtc_vdisplay - 1) << 16));
  83
  84         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  85         if (!vsync_wid)
  86                 vsync_wid = 1;
  87
  88         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
  89                               | ((vsync_wid & 0x1f) << 16)
  90                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
  91                                  ? RADEON_CRTC_V_SYNC_POL
  92                                  : 0));
  93
  94         fp_horz_vert_active = 0;
  95
  96         if (radeon_encoder->panel_xres == 0 ||
  97             radeon_encoder->panel_yres == 0) {
  98                 hscale = false;
  99                 vscale = false;
 100         } else {
 101                 if (xres > radeon_encoder->panel_xres)
 102                         xres = radeon_encoder->panel_xres;
 103                 if (yres > radeon_encoder->panel_yres)
 104                         yres = radeon_encoder->panel_yres;
 105
 106                 if (xres == radeon_encoder->panel_xres)
 107                         hscale = false;
 108                 if (yres == radeon_encoder->panel_yres)
 109                         vscale = false;
 110         }
 111
 112         if (radeon_encoder->flags & RADEON_USE_RMX) {
 113                 if (radeon_encoder->rmx_type != RMX_CENTER) {
 114                         if (!hscale)
 115                                 fp_horz_stretch |= ((xres/8-1) << 16);
 116                         else {
 117                                 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 118                                 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 119                                         / radeon_encoder->panel_xres + 1;
 120                                 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 121                                                     RADEON_HORZ_STRETCH_BLEND |
 122                                                     RADEON_HORZ_STRETCH_ENABLE |
 123                                                     ((radeon_encoder->panel_xres/8-1) << 16));
 124                         }
 125
 126                         if (!vscale)
 127                                 fp_vert_stretch |= ((yres-1) << 12);
 128                         else {
 129                                 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 130                                 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 131                                         / radeon_encoder->panel_yres + 1;
 132                                 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 133                                                     RADEON_VERT_STRETCH_ENABLE |
 134                                                     RADEON_VERT_STRETCH_BLEND |
 135                                                     ((radeon_encoder->panel_yres-1) << 12));
 136                         }
 137                 } else if (radeon_encoder->rmx_type == RMX_CENTER) {
 138                         int    blank_width;
 139
 140                         fp_horz_stretch |= ((xres/8-1) << 16);
 141                         fp_vert_stretch |= ((yres-1) << 12);
 142
 143                         crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 144                                            RADEON_CRTC_AUTO_VERT_CENTER_EN);
 145
 146                         blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 147                         if (blank_width > 110)
 148                                 blank_width = 110;
 149
 150                         fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 151                                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 152
 153                         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 154                         if (!hsync_wid)
 155                                 hsync_wid = 1;
 156
 157                         fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 158                                               | ((hsync_wid & 0x3f) << 16)
 159                                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 160                                                  ? RADEON_CRTC_H_SYNC_POL
 161                                                  : 0));
 162
 163                         fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 164                                                 | ((mode->crtc_vdisplay - 1) << 16));
 165
 166                         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 167                         if (!vsync_wid)
 168                                 vsync_wid = 1;
 169
 170                         fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 171                                                | ((vsync_wid & 0x1f) << 16)
 172                                                | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 173                                                   ? RADEON_CRTC_V_SYNC_POL
 174                                                   : 0)));
 175
 176                         fp_horz_vert_active = (((radeon_encoder->panel_yres) & 0xfff) |
 177                                                (((radeon_encoder->panel_xres / 8) & 0x1ff) << 16));
 178                 }
 179         } else {
 180                 fp_horz_stretch |= ((xres/8-1) << 16);
 181                 fp_vert_stretch |= ((yres-1) << 12);
 182         }
 183
 184         RADEON_WRITE(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 185         RADEON_WRITE(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 186         RADEON_WRITE(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 187         RADEON_WRITE(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 188         RADEON_WRITE(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 189         RADEON_WRITE(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 190         RADEON_WRITE(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 191         RADEON_WRITE(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 192
 193 }
 194
 195 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 196 {
 197         struct drm_device *dev = encoder->dev;
 198         struct drm_radeon_private *dev_priv = dev->dev_private;
 199         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 200         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
 201
 202         switch(mode) {
 203         case DRM_MODE_DPMS_ON:
 204                 disp_pwr_man = RADEON_READ(RADEON_DISP_PWR_MAN);
 205                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
 206                 RADEON_WRITE(RADEON_DISP_PWR_MAN, disp_pwr_man);
 207                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
 208                 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 209                 udelay(1000);
 210                 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 211                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
 212                 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 213                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 214                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
 215                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
 216                 udelay(radeon_encoder->panel_pwr_delay * 1000);
 217                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 218                 break;
 219         case DRM_MODE_DPMS_STANDBY:
 220         case DRM_MODE_DPMS_SUSPEND:
 221         case DRM_MODE_DPMS_OFF:
 222                 pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
 223                 RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
 224                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 225                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 226                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
 227                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 228                 RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
 229                 break;
 230         }
 231 }
 232
 233 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 234 {
 235         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 236 }
 237
 238 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 239 {
 240         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 241 }
 242
 243 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 244                                         struct drm_display_mode *mode,
 245                                         struct drm_display_mode *adjusted_mode)
 246 {
 247         struct drm_device *dev = encoder->dev;
 248         struct drm_radeon_private *dev_priv = dev->dev_private;
 249         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 250         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 251         uint32_t lvds_pll_cntl, lvds_gen_cntl;
 252
 253         if (radeon_crtc->crtc_id == 0)
 254                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 255
 256         lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 257         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 258         lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 259         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 260         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 261                            RADEON_LVDS_BLON |
 262                            RADEON_LVDS_EN |
 263                            RADEON_LVDS_RST_FM);
 264
 265         if (radeon_is_r300(dev_priv))
 266                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 267
 268         if (radeon_crtc->crtc_id == 0) {
 269                 if (radeon_is_r300(dev_priv)) {
 270                         if (radeon_encoder->flags & RADEON_USE_RMX)
 271                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 272                 } else
 273                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 274         } else {
 275                 if (radeon_is_r300(dev_priv)) {
 276                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 277                 } else
 278                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 279         }
 280
 281         RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 282         RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 283
 284         if (dev_priv->chip_family == CHIP_RV410)
 285                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
 286 }
 287
 288 static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
 289                                           struct drm_display_mode *mode,
 290                                           struct drm_display_mode *adjusted_mode)
 291 {
 292         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 293
 294         radeon_encoder->flags &= ~RADEON_USE_RMX;
 295
 296         if (radeon_encoder->rmx_type != RMX_OFF)
 297                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
 298
 299         return true;
 300 }
 301
 302 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 303         .dpms = radeon_legacy_lvds_dpms,
 304         .mode_fixup = radeon_legacy_lvds_mode_fixup,
 305         .prepare = radeon_legacy_lvds_prepare,
 306         .mode_set = radeon_legacy_lvds_mode_set,
 307         .commit = radeon_legacy_lvds_commit,
 308 };
 309
 310
 311 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 312         .destroy = radeon_enc_destroy,
 313 };
 314
 315
 316 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index)
 317 {
 318         struct drm_radeon_private *dev_priv = dev->dev_private;
 319         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 320         struct radeon_encoder *radeon_encoder;
 321         struct drm_encoder *encoder;
 322         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 323         if (!radeon_encoder) {
 324                 return NULL;
 325         }
 326
 327         encoder = &radeon_encoder->base;
 328
 329         encoder->possible_crtcs = 0x3;
 330         encoder->possible_clones = 0;
 331         drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
 332                          DRM_MODE_ENCODER_LVDS);
 333
 334         drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
 335
 336         /* TODO get the LVDS info from the BIOS for panel size etc. */
 337         /* get the lvds info from the bios */
 338         radeon_combios_get_lvds_info(radeon_encoder);
 339
 340         /* LVDS gets default RMX full scaling */
 341         radeon_encoder->rmx_type = RMX_FULL;
 342
 343         return encoder;
 344 }
 345
 346 static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
 347                                                  struct drm_display_mode *mode,
 348                                                  struct drm_display_mode *adjusted_mode)
 349 {
 350         return true;
 351 }
 352
 353 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 354 {
 355         struct drm_device *dev = encoder->dev;
 356         struct drm_radeon_private *dev_priv = dev->dev_private;
 357         uint32_t crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 358         uint32_t dac_cntl = RADEON_READ(RADEON_DAC_CNTL);
 359         uint32_t dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 360
 361         switch(mode) {
 362         case DRM_MODE_DPMS_ON:
 363                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 364                 dac_cntl &= ~RADEON_DAC_PDWN;
 365                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 366                                     RADEON_DAC_PDWN_G |
 367                                     RADEON_DAC_PDWN_B);
 368                 break;
 369         case DRM_MODE_DPMS_STANDBY:
 370         case DRM_MODE_DPMS_SUSPEND:
 371         case DRM_MODE_DPMS_OFF:
 372                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 373                 dac_cntl |= RADEON_DAC_PDWN;
 374                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 375                                    RADEON_DAC_PDWN_G |
 376                                    RADEON_DAC_PDWN_B);
 377                 break;
 378         }
 379
 380         RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 381         RADEON_WRITE(RADEON_DAC_CNTL, dac_cntl);
 382         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 383
 384 }
 385
 386 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 387 {
 388         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 389 }
 390
 391 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 392 {
 393         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 394 }
 395
 396 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 397                                                struct drm_display_mode *mode,
 398                                                struct drm_display_mode *adjusted_mode)
 399 {
 400         struct drm_device *dev = encoder->dev;
 401         struct drm_radeon_private *dev_priv = dev->dev_private;
 402         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 403         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 404
 405         if (radeon_crtc->crtc_id == 0)
 406                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 407
 408         if (radeon_crtc->crtc_id == 0) {
 409                 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
 410                         disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
 411                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 412                         RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 413                 } else {
 414                         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 415                         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 416                 }
 417         } else {
 418                 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
 419                         disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
 420                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 421                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 422                         RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 423                 } else {
 424                         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 425                         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 426                 }
 427         }
 428
 429         dac_cntl = (RADEON_DAC_MASK_ALL |
 430                     RADEON_DAC_VGA_ADR_EN |
 431                     /* TODO 6-bits */
 432                     RADEON_DAC_8BIT_EN);
 433
 434         RADEON_WRITE_P(RADEON_DAC_CNTL,
 435                        dac_cntl,
 436                        RADEON_DAC_RANGE_CNTL |
 437                        RADEON_DAC_BLANKING);
 438
 439         dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 440         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 441 }
 442
 443 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 444 {
 445         struct drm_device *dev = encoder->dev;
 446         struct drm_radeon_private *dev_priv = dev->dev_private;
 447         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 448
 449         return connector_status_disconnected;
 450
 451 }
 452
 453 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 454         .dpms = radeon_legacy_primary_dac_dpms,
 455         .mode_fixup = radeon_legacy_primary_dac_mode_fixup,
 456         .prepare = radeon_legacy_primary_dac_prepare,
 457         .mode_set = radeon_legacy_primary_dac_mode_set,
 458         .commit = radeon_legacy_primary_dac_commit,
 459         .detect = radeon_legacy_primary_dac_detect,
 460 };
 461
 462
 463 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 464         .destroy = radeon_enc_destroy,
 465 };
 466
 467 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int has_tv)
 468 {
 469         struct drm_radeon_private *dev_priv = dev->dev_private;
 470         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 471         struct radeon_encoder *radeon_encoder;
 472         struct drm_encoder *encoder;
 473         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 474         if (!radeon_encoder) {
 475                 return NULL;
 476         }
 477
 478         encoder = &radeon_encoder->base;
 479
 480         encoder->possible_crtcs = 0x3;
 481         encoder->possible_clones = 0;
 482         drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
 483                          DRM_MODE_ENCODER_DAC);
 484
 485         drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
 486
 487         /* TODO get the primary dac vals from bios tables */
 488         //radeon_combios_get_lvds_info(radeon_encoder);
 489
 490         return encoder;
 491 }
 492
 493
 494 static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
 495                                                  struct drm_display_mode *mode,
 496                                                  struct drm_display_mode *adjusted_mode)
 497 {
 498         return true;
 499 }
 500
 501 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 502 {
 503         struct drm_device *dev = encoder->dev;
 504         struct drm_radeon_private *dev_priv = dev->dev_private;
 505         uint32_t fp_gen_cntl = RADEON_READ(RADEON_FP_GEN_CNTL);
 506
 507         switch(mode) {
 508         case DRM_MODE_DPMS_ON:
 509                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 510                 break;
 511         case DRM_MODE_DPMS_STANDBY:
 512         case DRM_MODE_DPMS_SUSPEND:
 513         case DRM_MODE_DPMS_OFF:
 514                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 515                 break;
 516         }
 517
 518         RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 519 }
 520
 521 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 522 {
 523         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 524 }
 525
 526 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 527 {
 528         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 529 }
 530
 531 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 532                                             struct drm_display_mode *mode,
 533                                             struct drm_display_mode *adjusted_mode)
 534 {
 535         struct drm_device *dev = encoder->dev;
 536         struct drm_radeon_private *dev_priv = dev->dev_private;
 537         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 538         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 539         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 540         int i;
 541
 542         if (radeon_crtc->crtc_id == 0)
 543                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 544
 545         tmp = tmds_pll_cntl = RADEON_READ(RADEON_TMDS_PLL_CNTL);
 546         tmp &= 0xfffff;
 547         if (dev_priv->chip_family == CHIP_RV280) {
 548                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 549                 tmp ^= (1 << 22);
 550                 tmds_pll_cntl ^= (1 << 22);
 551         }
 552
 553         for (i = 0; i < 4; i++) {
 554                 if (radeon_encoder->tmds_pll[i].freq == 0)
 555                         break;
 556                 if ((uint32_t)(mode->clock / 10) < radeon_encoder->tmds_pll[i].freq) {
 557                         tmp = radeon_encoder->tmds_pll[i].value ;
 558                         break;
 559                 }
 560         }
 561
 562         if (radeon_is_r300(dev_priv) || (dev_priv->chip_family == CHIP_RV280)) {
 563                 if (tmp & 0xfff00000)
 564                         tmds_pll_cntl = tmp;
 565                 else {
 566                         tmds_pll_cntl &= 0xfff00000;
 567                         tmds_pll_cntl |= tmp;
 568                 }
 569         } else
 570                 tmds_pll_cntl = tmp;
 571
 572         tmds_transmitter_cntl = RADEON_READ(RADEON_TMDS_TRANSMITTER_CNTL) &
 573                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 574
 575     if (dev_priv->chip_family == CHIP_R200 ||
 576         dev_priv->chip_family == CHIP_R100 ||
 577         radeon_is_r300(dev_priv))
 578             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 579     else /* RV chips got this bit reversed */
 580             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 581
 582     fp_gen_cntl = (RADEON_READ(RADEON_FP_GEN_CNTL) |
 583                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 584                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 585
 586     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 587
 588     if (1) // FIXME rgbBits == 8
 589             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 590     else
 591             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 592
 593     if (radeon_crtc->crtc_id == 0) {
 594             if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
 595                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 596                     if (radeon_encoder->flags & RADEON_USE_RMX)
 597                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 598                     else
 599                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 600             } else
 601                     fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
 602     } else {
 603             if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
 604                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 605                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 606             } else
 607                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 608     }
 609
 610     RADEON_WRITE(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 611     RADEON_WRITE(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 612     RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 613 }
 614
 615 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 616         .dpms = radeon_legacy_tmds_int_dpms,
 617         .mode_fixup = radeon_legacy_tmds_int_mode_fixup,
 618         .prepare = radeon_legacy_tmds_int_prepare,
 619         .mode_set = radeon_legacy_tmds_int_mode_set,
 620         .commit = radeon_legacy_tmds_int_commit,
 621 };
 622
 623
 624 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 625         .destroy = radeon_enc_destroy,
 626 };
 627
 628 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index)
 629 {
 630         struct drm_radeon_private *dev_priv = dev->dev_private;
 631         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 632         struct radeon_encoder *radeon_encoder;
 633         struct drm_encoder *encoder;
 634         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 635         if (!radeon_encoder) {
 636                 return NULL;
 637         }
 638
 639         encoder = &radeon_encoder->base;
 640
 641         encoder->possible_crtcs = 0x3;
 642         encoder->possible_clones = 0;
 643         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
 644                          DRM_MODE_ENCODER_TMDS);
 645
 646         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
 647
 648         radeon_combios_get_tmds_info(radeon_encoder);
 649         return encoder;
 650 }
 651
 652 static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
 653                                               struct drm_display_mode *mode,
 654                                               struct drm_display_mode *adjusted_mode)
 655 {
 656         return true;
 657 }
 658
 659 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 660 {
 661         struct drm_device *dev = encoder->dev;
 662         struct drm_radeon_private *dev_priv = dev->dev_private;
 663         uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 664
 665         switch(mode) {
 666         case DRM_MODE_DPMS_ON:
 667                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 668                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 669                 break;
 670         case DRM_MODE_DPMS_STANDBY:
 671         case DRM_MODE_DPMS_SUSPEND:
 672         case DRM_MODE_DPMS_OFF:
 673                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 674                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 675                 break;
 676         }
 677
 678         RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 679 }
 680
 681 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 682 {
 683         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 684 }
 685
 686 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 687 {
 688         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 689 }
 690
 691 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 692                                             struct drm_display_mode *mode,
 693                                             struct drm_display_mode *adjusted_mode)
 694 {
 695         struct drm_device *dev = encoder->dev;
 696         struct drm_radeon_private *dev_priv = dev->dev_private;
 697         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 698         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 699         uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 700
 701         if (radeon_crtc->crtc_id == 0)
 702                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 703
 704         if (1) // FIXME rgbBits == 8
 705                 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 706         else
 707                 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 708
 709         fp2_gen_cntl &= ~(RADEON_FP2_ON |
 710                           RADEON_FP2_DVO_EN |
 711                           RADEON_FP2_DVO_RATE_SEL_SDR);
 712
 713         /* XXX: these are oem specific */
 714         if (radeon_is_r300(dev_priv)) {
 715                 if ((dev->pdev->device == 0x4850) &&
 716                     (dev->pdev->subsystem_vendor == 0x1028) &&
 717                     (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 718                         fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 719                 else
 720                         fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 721
 722                 /*if (mode->clock > 165000)
 723                         fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 724         }
 725
 726         if (radeon_crtc->crtc_id == 0) {
 727                 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
 728                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 729                         if (radeon_encoder->flags & RADEON_USE_RMX)
 730                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 731                         else
 732                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 733                 } else
 734                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 735         } else {
 736                 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
 737                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 738                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 739                 } else
 740                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 741         }
 742
 743         RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 744 }
 745
 746 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 747         .dpms = radeon_legacy_tmds_ext_dpms,
 748         .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
 749         .prepare = radeon_legacy_tmds_ext_prepare,
 750         .mode_set = radeon_legacy_tmds_ext_mode_set,
 751         .commit = radeon_legacy_tmds_ext_commit,
 752 };
 753
 754
 755 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 756         .destroy = radeon_enc_destroy,
 757 };
 758
 759 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index)
 760 {
 761         struct drm_radeon_private *dev_priv = dev->dev_private;
 762         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 763         struct radeon_encoder *radeon_encoder;
 764         struct drm_encoder *encoder;
 765         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 766         if (!radeon_encoder) {
 767                 return NULL;
 768         }
 769
 770         encoder = &radeon_encoder->base;
 771
 772         encoder->possible_crtcs = 0x3;
 773         encoder->possible_clones = 0;
 774         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
 775                          DRM_MODE_ENCODER_TMDS);
 776
 777         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
 778
 779         //radeon_combios_get_tmds_info(radeon_encoder);
 780         return encoder;
 781 }
 782
 783 static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
 784                                             struct drm_display_mode *mode,
 785                                             struct drm_display_mode *adjusted_mode)
 786 {
 787         return true;
 788 }
 789
 790 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 791 {
 792         struct drm_device *dev = encoder->dev;
 793         struct drm_radeon_private *dev_priv = dev->dev_private;
 794         uint32_t fp2_gen_cntl, crtc2_gen_cntl, tv_master_cntl, tv_dac_cntl;
 795
 796         if (dev_priv->chip_family == CHIP_R200)
 797                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 798         else {
 799                 crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
 800                 // FIXME TV
 801                 //tv_master_cntl = RADEON_READ(RADEON_TV_MASTER_CNTL);
 802                 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
 803         }
 804
 805         switch(mode) {
 806         case DRM_MODE_DPMS_ON:
 807                 if (dev_priv->chip_family == CHIP_R200)
 808                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 809                 else {
 810                         crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
 811                         //tv_master_cntl |= RADEON_TV_ON;
 812                         if (dev_priv->chip_family == CHIP_R420 ||
 813                             dev_priv->chip_family == CHIP_RV410)
 814                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
 815                                                  R420_TV_DAC_GDACPD |
 816                                                  R420_TV_DAC_BDACPD |
 817                                                  RADEON_TV_DAC_BGSLEEP);
 818                         else
 819                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
 820                                                  RADEON_TV_DAC_GDACPD |
 821                                                  RADEON_TV_DAC_BDACPD |
 822                                                  RADEON_TV_DAC_BGSLEEP);
 823                 }
 824                 break;
 825         case DRM_MODE_DPMS_STANDBY:
 826         case DRM_MODE_DPMS_SUSPEND:
 827         case DRM_MODE_DPMS_OFF:
 828                 if (dev_priv->chip_family == CHIP_R200)
 829                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 830                 else {
 831                         crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
 832                         //tv_master_cntl &= ~RADEON_TV_ON;
 833                         if (dev_priv->chip_family == CHIP_R420 ||
 834                             dev_priv->chip_family == CHIP_RV410)
 835                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
 836                                                 R420_TV_DAC_GDACPD |
 837                                                 R420_TV_DAC_BDACPD |
 838                                                 RADEON_TV_DAC_BGSLEEP);
 839                         else
 840                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
 841                                                 RADEON_TV_DAC_GDACPD |
 842                                                 RADEON_TV_DAC_BDACPD |
 843                                                 RADEON_TV_DAC_BGSLEEP);
 844                 }
 845                 break;
 846         }
 847
 848         if (dev_priv->chip_family == CHIP_R200)
 849                 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 850         else {
 851                 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 852                 //RADEON_WRITE(RADEON_TV_MASTER_CNTL, tv_master_cntl);
 853                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 854         }
 855
 856 }
 857
 858 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
 859 {
 860         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 861 }
 862
 863 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
 864 {
 865         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 866 }
 867
 868 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 869                                           struct drm_display_mode *mode,
 870                                           struct drm_display_mode *adjusted_mode)
 871 {
 872         struct drm_device *dev = encoder->dev;
 873         struct drm_radeon_private *dev_priv = dev->dev_private;
 874         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 875         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 876         uint32_t tv_dac_cntl, gpiopad_a, dac2_cntl, disp_output_cntl, fp2_gen_cntl;
 877         uint32_t disp_hw_debug;
 878
 879         if (radeon_crtc->crtc_id == 0)
 880                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 881
 882         if (dev_priv->chip_family != CHIP_R200) {
 883                 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
 884                 if (dev_priv->chip_family == CHIP_R420 ||
 885                     dev_priv->chip_family == CHIP_RV410) {
 886                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 887                                          RADEON_TV_DAC_BGADJ_MASK |
 888                                          R420_TV_DAC_DACADJ_MASK |
 889                                          R420_TV_DAC_RDACPD |
 890                                          R420_TV_DAC_GDACPD |
 891                                          R420_TV_DAC_GDACPD |
 892                                          R420_TV_DAC_TVENABLE);
 893                 } else {
 894                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 895                                          RADEON_TV_DAC_BGADJ_MASK |
 896                                          RADEON_TV_DAC_DACADJ_MASK |
 897                                          RADEON_TV_DAC_RDACPD |
 898                                          RADEON_TV_DAC_GDACPD |
 899                                          RADEON_TV_DAC_GDACPD);
 900                 }
 901
 902                 // FIXME TV
 903                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 904                                 RADEON_TV_DAC_NHOLD |
 905                                 RADEON_TV_DAC_STD_PS2 /*|
 906                                 radeon_encoder->ps2_tvdac_adj*/); // fixme, get from bios
 907
 908                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 909         }
 910
 911         if (radeon_is_r300(dev_priv)) {
 912                 gpiopad_a = RADEON_READ(RADEON_GPIOPAD_A) | 1;
 913                 disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL);
 914         } else if (dev_priv->chip_family == CHIP_R200)
 915                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 916         else
 917                 disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
 918
 919         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
 920
 921         if (radeon_crtc->crtc_id == 0) {
 922                 if (radeon_is_r300(dev_priv)) {
 923                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 924                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
 925                 } else if (dev_priv->chip_family == CHIP_R200) {
 926                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 927                                           RADEON_FP2_DVO_RATE_SEL_SDR);
 928                 } else
 929                         disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 930         } else {
 931                 if (radeon_is_r300(dev_priv)) {
 932                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 933                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
 934                 } else if (dev_priv->chip_family == CHIP_R200) {
 935                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 936                                           RADEON_FP2_DVO_RATE_SEL_SDR);
 937                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 938                 } else
 939                         disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 940         }
 941
 942         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 943
 944         if (radeon_is_r300(dev_priv)) {
 945                 RADEON_WRITE_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
 946                 RADEON_WRITE(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
 947         } else if (dev_priv->chip_family == CHIP_R200)
 948                 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 949         else
 950                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 951
 952 }
 953
 954 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 955 {
 956         struct drm_device *dev = encoder->dev;
 957         struct drm_radeon_private *dev_priv = dev->dev_private;
 958         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 959
 960         return connector_status_disconnected;
 961
 962 }
 963
 964 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
 965         .dpms = radeon_legacy_tv_dac_dpms,
 966         .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
 967         .prepare = radeon_legacy_tv_dac_prepare,
 968         .mode_set = radeon_legacy_tv_dac_mode_set,
 969         .commit = radeon_legacy_tv_dac_commit,
 970         .detect = radeon_legacy_tv_dac_detect,
 971 };
 972
 973
 974 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
 975         .destroy = radeon_enc_destroy,
 976 };
 977
 978 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int has_tv)
 979 {
 980         struct drm_radeon_private *dev_priv = dev->dev_private;
 981         struct radeon_mode_info *mode_info = &dev_priv->mode_info;
 982         struct radeon_encoder *radeon_encoder;
 983         struct drm_encoder *encoder;
 984         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 985         if (!radeon_encoder) {
 986                 return NULL;
 987         }
 988
 989         encoder = &radeon_encoder->base;
 990
 991         encoder->possible_crtcs = 0x3;
 992         encoder->possible_clones = 0;
 993         drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
 994                          DRM_MODE_ENCODER_DAC);
 995
 996         drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
 997
 998         /* TODO get the tv dac vals from bios tables */
 999         //radeon_combios_get_lvds_info(radeon_encoder);
1000
1001         return encoder;
1002 }