linux-core/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31
  32 static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder,
  33                                        struct drm_display_mode *mode,
  34                                        struct drm_display_mode *adjusted_mode)
  35 {
  36         struct drm_device *dev = encoder->dev;
  37         struct drm_radeon_private *dev_priv = dev->dev_private;
  38         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  39         int    xres = mode->hdisplay;
  40         int    yres = mode->vdisplay;
  41         bool   hscale = true, vscale = true;
  42         int    hsync_wid;
  43         int    vsync_wid;
  44         int    hsync_start;
  45         uint32_t scale, inc;
  46         uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active;
  47         uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp;
  48
  49         DRM_DEBUG("\n");
  50
  51         fp_vert_stretch = RADEON_READ(RADEON_FP_VERT_STRETCH) &
  52                 (RADEON_VERT_STRETCH_RESERVED |
  53                  RADEON_VERT_AUTO_RATIO_INC);
  54         fp_horz_stretch = RADEON_READ(RADEON_FP_HORZ_STRETCH) &
  55                 (RADEON_HORZ_FP_LOOP_STRETCH |
  56                  RADEON_HORZ_AUTO_RATIO_INC);
  57
  58         crtc_more_cntl = 0;
  59         if ((dev_priv->chip_family == CHIP_RS100) ||
  60             (dev_priv->chip_family == CHIP_RS200)) {
  61                 /* This is to workaround the asic bug for RMX, some versions
  62                    of BIOS dosen't have this register initialized correctly. */
  63                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  64         }
  65
  66
  67         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  68                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  69
  70         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  71         if (!hsync_wid)
  72                 hsync_wid = 1;
  73         hsync_start = mode->crtc_hsync_start - 8;
  74
  75         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  76                               | ((hsync_wid & 0x3f) << 16)
  77                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  78                                  ? RADEON_CRTC_H_SYNC_POL
  79                                  : 0));
  80
  81         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  82                                 | ((mode->crtc_vdisplay - 1) << 16));
  83
  84         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  85         if (!vsync_wid)
  86                 vsync_wid = 1;
  87
  88         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
  89                               | ((vsync_wid & 0x1f) << 16)
  90                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
  91                                  ? RADEON_CRTC_V_SYNC_POL
  92                                  : 0));
  93
  94         fp_horz_vert_active = 0;
  95
  96         if (radeon_encoder->panel_xres == 0 ||
  97             radeon_encoder->panel_yres == 0) {
  98                 hscale = false;
  99                 vscale = false;
 100         } else {
 101                 if (xres > radeon_encoder->panel_xres)
 102                         xres = radeon_encoder->panel_xres;
 103                 if (yres > radeon_encoder->panel_yres)
 104                         yres = radeon_encoder->panel_yres;
 105
 106                 if (xres == radeon_encoder->panel_xres)
 107                         hscale = false;
 108                 if (yres == radeon_encoder->panel_yres)
 109                         vscale = false;
 110         }
 111
 112         if (radeon_encoder->flags & RADEON_USE_RMX) {
 113                 if (radeon_encoder->rmx_type != RMX_CENTER) {
 114                         if (!hscale)
 115                                 fp_horz_stretch |= ((xres/8-1) << 16);
 116                         else {
 117                                 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 118                                 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 119                                         / radeon_encoder->panel_xres + 1;
 120                                 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 121                                                     RADEON_HORZ_STRETCH_BLEND |
 122                                                     RADEON_HORZ_STRETCH_ENABLE |
 123                                                     ((radeon_encoder->panel_xres/8-1) << 16));
 124                         }
 125
 126                         if (!vscale)
 127                                 fp_vert_stretch |= ((yres-1) << 12);
 128                         else {
 129                                 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 130                                 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 131                                         / radeon_encoder->panel_yres + 1;
 132                                 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 133                                                     RADEON_VERT_STRETCH_ENABLE |
 134                                                     RADEON_VERT_STRETCH_BLEND |
 135                                                     ((radeon_encoder->panel_yres-1) << 12));
 136                         }
 137                 } else if (radeon_encoder->rmx_type == RMX_CENTER) {
 138                         int    blank_width;
 139
 140                         fp_horz_stretch |= ((xres/8-1) << 16);
 141                         fp_vert_stretch |= ((yres-1) << 12);
 142
 143                         crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 144                                            RADEON_CRTC_AUTO_VERT_CENTER_EN);
 145
 146                         blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 147                         if (blank_width > 110)
 148                                 blank_width = 110;
 149
 150                         fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 151                                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 152
 153                         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 154                         if (!hsync_wid)
 155                                 hsync_wid = 1;
 156
 157                         fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 158                                               | ((hsync_wid & 0x3f) << 16)
 159                                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 160                                                  ? RADEON_CRTC_H_SYNC_POL
 161                                                  : 0));
 162
 163                         fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 164                                                 | ((mode->crtc_vdisplay - 1) << 16));
 165
 166                         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 167                         if (!vsync_wid)
 168                                 vsync_wid = 1;
 169
 170                         fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 171                                                | ((vsync_wid & 0x1f) << 16)
 172                                                | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 173                                                   ? RADEON_CRTC_V_SYNC_POL
 174                                                   : 0)));
 175
 176                         fp_horz_vert_active = (((radeon_encoder->panel_yres) & 0xfff) |
 177                                                (((radeon_encoder->panel_xres / 8) & 0x1ff) << 16));
 178                 }
 179         } else {
 180                 fp_horz_stretch |= ((xres/8-1) << 16);
 181                 fp_vert_stretch |= ((yres-1) << 12);
 182         }
 183
 184         RADEON_WRITE(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 185         RADEON_WRITE(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 186         RADEON_WRITE(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 187         RADEON_WRITE(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 188         RADEON_WRITE(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 189         RADEON_WRITE(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 190         RADEON_WRITE(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 191         RADEON_WRITE(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 192
 193 }
 194
 195 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 196 {
 197         struct drm_device *dev = encoder->dev;
 198         struct drm_radeon_private *dev_priv = dev->dev_private;
 199         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 200         struct radeon_crtc *radeon_crtc;
 201         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
 202         uint32_t bios_5_scratch, bios_6_scratch;
 203         int crtc_id = 0;
 204         DRM_DEBUG("\n");
 205
 206         if (encoder->crtc) {
 207                 radeon_crtc = to_radeon_crtc(encoder->crtc);
 208                 crtc_id = radeon_crtc->crtc_id;
 209         }
 210
 211         // FIXME atom/legacy cards like r4xx
 212         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 213         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 214
 215         bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
 216         bios_5_scratch |= (crtc_id << RADEON_LCD1_CRTC_SHIFT);
 217
 218         switch (mode) {
 219         case DRM_MODE_DPMS_ON:
 220                 disp_pwr_man = RADEON_READ(RADEON_DISP_PWR_MAN);
 221                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
 222                 RADEON_WRITE(RADEON_DISP_PWR_MAN, disp_pwr_man);
 223                 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 224                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
 225                 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 226                 udelay(1000);
 227
 228                 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 229                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
 230                 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 231
 232                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 233                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
 234                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
 235                 udelay(radeon_encoder->panel_pwr_delay * 1000);
 236                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 237
 238                 /* update bios scratch regs */
 239                 bios_5_scratch |= RADEON_LCD1_ON;
 240                 bios_6_scratch |= RADEON_LCD_DPMS_ON;
 241
 242                 break;
 243         case DRM_MODE_DPMS_STANDBY:
 244         case DRM_MODE_DPMS_SUSPEND:
 245         case DRM_MODE_DPMS_OFF:
 246                 pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
 247                 RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
 248                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 249                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 250                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 251                 udelay(radeon_encoder->panel_pwr_delay * 1000);
 252                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 253                 RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
 254
 255                 bios_5_scratch &= ~RADEON_LCD1_ON;
 256                 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
 257                 break;
 258         }
 259         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 260         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 261 }
 262
 263 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 264 {
 265         struct drm_radeon_private *dev_priv = encoder->dev->dev_private;
 266         // fix me: atom/legacy r4xx
 267         if (!dev_priv->is_atom_bios)
 268                 radeon_combios_output_lock(encoder, true);
 269         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 270 }
 271
 272 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 273 {
 274         struct drm_radeon_private *dev_priv = encoder->dev->dev_private;
 275         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 276         // fix me: atom/legacy r4xx
 277         if (!dev_priv->is_atom_bios)
 278                 radeon_combios_output_lock(encoder, false);
 279 }
 280
 281 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 282                                         struct drm_display_mode *mode,
 283                                         struct drm_display_mode *adjusted_mode)
 284 {
 285         struct drm_device *dev = encoder->dev;
 286         struct drm_radeon_private *dev_priv = dev->dev_private;
 287         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 288         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 289         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
 290
 291         DRM_DEBUG("\n");
 292
 293         if (radeon_crtc->crtc_id == 0)
 294                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 295
 296         lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 297         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 298         if (radeon_encoder->lvds_gen_cntl)
 299                 lvds_gen_cntl = radeon_encoder->lvds_gen_cntl;
 300         else
 301                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 302         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 303         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 304                            RADEON_LVDS_BLON |
 305                            RADEON_LVDS_EN |
 306                            RADEON_LVDS_RST_FM);
 307
 308         DRM_INFO("bios LVDS_GEN_CNTL: 0x%x\n", radeon_encoder->lvds_gen_cntl);
 309
 310         if (radeon_is_r300(dev_priv))
 311                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 312
 313         if (radeon_crtc->crtc_id == 0) {
 314                 if (radeon_is_r300(dev_priv)) {
 315                         if (radeon_encoder->flags & RADEON_USE_RMX)
 316                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 317                 } else
 318                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 319         } else {
 320                 if (radeon_is_r300(dev_priv))
 321                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 322                 else
 323                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 324         }
 325
 326         RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 327         RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 328
 329         lvds_ss_gen_cntl = RADEON_READ(RADEON_LVDS_SS_GEN_CNTL);
 330         if (radeon_encoder->panel_digon_delay &&
 331             radeon_encoder->panel_blon_delay) {
 332                 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 333                                       (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 334                 lvds_ss_gen_cntl |= ((radeon_encoder->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 335                                      (radeon_encoder->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 336                 RADEON_WRITE(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
 337         }
 338
 339         if (dev_priv->chip_family == CHIP_RV410)
 340                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
 341 }
 342
 343 static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
 344                                           struct drm_display_mode *mode,
 345                                           struct drm_display_mode *adjusted_mode)
 346 {
 347         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 348
 349         radeon_encoder->flags &= ~RADEON_USE_RMX;
 350
 351         if (radeon_encoder->rmx_type != RMX_OFF)
 352                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
 353
 354         return true;
 355 }
 356
 357 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 358         .dpms = radeon_legacy_lvds_dpms,
 359         .mode_fixup = radeon_legacy_lvds_mode_fixup,
 360         .prepare = radeon_legacy_lvds_prepare,
 361         .mode_set = radeon_legacy_lvds_mode_set,
 362         .commit = radeon_legacy_lvds_commit,
 363 };
 364
 365
 366 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 367         .destroy = radeon_enc_destroy,
 368 };
 369
 370
 371 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index)
 372 {
 373         struct drm_radeon_private *dev_priv = dev->dev_private;
 374         struct radeon_encoder *radeon_encoder;
 375         struct drm_encoder *encoder;
 376
 377         DRM_DEBUG("\n");
 378
 379         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 380         if (!radeon_encoder) {
 381                 return NULL;
 382         }
 383
 384         encoder = &radeon_encoder->base;
 385
 386         /* Limit LVDS to crtc 0 for RMX */
 387         encoder->possible_crtcs = 0x1;
 388         encoder->possible_clones = 0;
 389         drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
 390                          DRM_MODE_ENCODER_LVDS);
 391
 392         drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
 393
 394         /* get the lvds info from the bios */
 395         if (dev_priv->is_atom_bios)
 396                 radeon_atombios_get_lvds_info(radeon_encoder);
 397         else
 398                 radeon_combios_get_lvds_info(radeon_encoder);
 399
 400         /* LVDS gets default RMX full scaling */
 401         radeon_encoder->rmx_type = RMX_FULL;
 402
 403         return encoder;
 404 }
 405
 406 static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
 407                                                  struct drm_display_mode *mode,
 408                                                  struct drm_display_mode *adjusted_mode)
 409 {
 410         return true;
 411 }
 412
 413 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 414 {
 415         struct drm_device *dev = encoder->dev;
 416         struct drm_radeon_private *dev_priv = dev->dev_private;
 417         struct radeon_crtc *radeon_crtc;
 418         uint32_t crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 419         uint32_t dac_cntl = RADEON_READ(RADEON_DAC_CNTL);
 420         uint32_t dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 421         uint32_t bios_5_scratch, bios_6_scratch;
 422         int crtc_id = 0;
 423
 424         DRM_DEBUG("\n");
 425
 426         if (encoder->crtc) {
 427                 radeon_crtc = to_radeon_crtc(encoder->crtc);
 428                 crtc_id = radeon_crtc->crtc_id;
 429         }
 430
 431         // FIXME atom/legacy cards like r4xx
 432         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 433         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 434
 435         bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
 436         bios_5_scratch |= (crtc_id << RADEON_CRT1_CRTC_SHIFT);
 437
 438         DRM_DEBUG("\n");
 439
 440         switch(mode) {
 441         case DRM_MODE_DPMS_ON:
 442                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 443                 dac_cntl &= ~RADEON_DAC_PDWN;
 444                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 445                                     RADEON_DAC_PDWN_G |
 446                                     RADEON_DAC_PDWN_B);
 447                 bios_5_scratch |= RADEON_CRT1_ON;
 448                 bios_6_scratch |= RADEON_CRT_DPMS_ON;
 449                 break;
 450         case DRM_MODE_DPMS_STANDBY:
 451         case DRM_MODE_DPMS_SUSPEND:
 452         case DRM_MODE_DPMS_OFF:
 453                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 454                 dac_cntl |= RADEON_DAC_PDWN;
 455                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 456                                    RADEON_DAC_PDWN_G |
 457                                    RADEON_DAC_PDWN_B);
 458                 bios_5_scratch &= ~RADEON_CRT1_ON;
 459                 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
 460                 break;
 461         }
 462
 463         RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 464         RADEON_WRITE(RADEON_DAC_CNTL, dac_cntl);
 465         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 466
 467         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 468         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 469 }
 470
 471 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 472 {
 473         struct drm_radeon_private *dev_priv = encoder->dev->dev_private;
 474         // fix me: atom/legacy r4xx
 475         if (!dev_priv->is_atom_bios)
 476                 radeon_combios_output_lock(encoder, true);
 477         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 478 }
 479
 480 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 481 {
 482         struct drm_radeon_private *dev_priv = encoder->dev->dev_private;
 483         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 484         // fix me: atom/legacy r4xx
 485         if (!dev_priv->is_atom_bios)
 486                 radeon_combios_output_lock(encoder, false);
 487 }
 488
 489 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 490                                                struct drm_display_mode *mode,
 491                                                struct drm_display_mode *adjusted_mode)
 492 {
 493         struct drm_device *dev = encoder->dev;
 494         struct drm_radeon_private *dev_priv = dev->dev_private;
 495         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 496         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 497         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 498
 499         DRM_DEBUG("\n");
 500
 501         if (radeon_crtc->crtc_id == 0)
 502                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 503
 504         if (radeon_crtc->crtc_id == 0) {
 505                 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
 506                         disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
 507                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 508                         RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 509                 } else {
 510                         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 511                         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 512                 }
 513         } else {
 514                 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
 515                         disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
 516                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 517                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 518                         RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 519                 } else {
 520                         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 521                         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 522                 }
 523         }
 524
 525         dac_cntl = (RADEON_DAC_MASK_ALL |
 526                     RADEON_DAC_VGA_ADR_EN |
 527                     /* TODO 6-bits */
 528                     RADEON_DAC_8BIT_EN);
 529
 530         RADEON_WRITE_P(RADEON_DAC_CNTL,
 531                        dac_cntl,
 532                        RADEON_DAC_RANGE_CNTL |
 533                        RADEON_DAC_BLANKING);
 534
 535         if (radeon_encoder->ps2_pdac_adj)
 536                 dac_macro_cntl = radeon_encoder->ps2_pdac_adj;
 537         else
 538                 dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 539         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 540         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 541 }
 542
 543 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
 544                                                                   struct drm_connector *connector)
 545 {
 546         struct drm_device *dev = encoder->dev;
 547         struct drm_radeon_private *dev_priv = dev->dev_private;
 548         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
 549         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
 550         enum drm_connector_status found = connector_status_disconnected;
 551         bool color = true;
 552
 553         /* save the regs we need */
 554         vclk_ecp_cntl = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
 555         crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 556         dac_ext_cntl = RADEON_READ(RADEON_DAC_EXT_CNTL);
 557         dac_cntl = RADEON_READ(RADEON_DAC_CNTL);
 558         dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 559
 560         tmp = vclk_ecp_cntl &
 561                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
 562         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
 563
 564         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
 565         RADEON_WRITE(RADEON_CRTC_EXT_CNTL, tmp);
 566
 567         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
 568                 RADEON_DAC_FORCE_DATA_EN;
 569
 570         if (color)
 571                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
 572         else
 573                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
 574
 575         if (radeon_is_r300(dev_priv))
 576                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
 577         else
 578                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
 579
 580         RADEON_WRITE(RADEON_DAC_EXT_CNTL, tmp);
 581
 582         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
 583         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
 584         RADEON_WRITE(RADEON_DAC_CNTL, tmp);
 585
 586         tmp &= ~(RADEON_DAC_PDWN_R |
 587                  RADEON_DAC_PDWN_G |
 588                  RADEON_DAC_PDWN_B);
 589
 590         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, tmp);
 591
 592         udelay(2000);
 593
 594         if (RADEON_READ(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
 595                 found = connector_status_connected;
 596
 597         /* restore the regs we used */
 598         RADEON_WRITE(RADEON_DAC_CNTL, dac_cntl);
 599         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 600         RADEON_WRITE(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
 601         RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 602         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
 603
 604         return found;
 605 }
 606
 607 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 608         .dpms = radeon_legacy_primary_dac_dpms,
 609         .mode_fixup = radeon_legacy_primary_dac_mode_fixup,
 610         .prepare = radeon_legacy_primary_dac_prepare,
 611         .mode_set = radeon_legacy_primary_dac_mode_set,
 612         .commit = radeon_legacy_primary_dac_commit,
 613         .detect = radeon_legacy_primary_dac_detect,
 614 };
 615
 616
 617 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 618         .destroy = radeon_enc_destroy,
 619 };
 620
 621 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int has_tv)
 622 {
 623         struct drm_radeon_private *dev_priv = dev->dev_private;
 624         struct radeon_encoder *radeon_encoder;
 625         struct drm_encoder *encoder;
 626
 627         DRM_DEBUG("\n");
 628
 629         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 630         if (!radeon_encoder) {
 631                 return NULL;
 632         }
 633
 634         encoder = &radeon_encoder->base;
 635
 636         encoder->possible_crtcs = 0x3;
 637         encoder->possible_clones = 0;
 638         drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
 639                          DRM_MODE_ENCODER_DAC);
 640
 641         drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
 642
 643         /* get the primary dac bg/adj vals from bios tables */
 644         if (!dev_priv->is_atom_bios)
 645                 radeon_combios_get_primary_dac_info(radeon_encoder);
 646
 647         return encoder;
 648 }
 649
 650
 651 static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
 652                                               struct drm_display_mode *mode,
 653                                               struct drm_display_mode *adjusted_mode)
 654 {
 655         return true;
 656 }
 657
 658 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 659 {
 660         struct drm_device *dev = encoder->dev;
 661         struct drm_radeon_private *dev_priv = dev->dev_private;
 662         struct radeon_crtc *radeon_crtc;
 663         uint32_t fp_gen_cntl = RADEON_READ(RADEON_FP_GEN_CNTL);
 664         uint32_t bios_5_scratch, bios_6_scratch;
 665         int crtc_id = 0;
 666         DRM_DEBUG("\n");
 667
 668         if (encoder->crtc) {
 669                 radeon_crtc = to_radeon_crtc(encoder->crtc);
 670                 crtc_id = radeon_crtc->crtc_id;
 671         }
 672
 673         // FIXME atom/legacy cards like r4xx
 674         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 675         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 676
 677         bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
 678         bios_5_scratch |= (crtc_id << RADEON_DFP1_CRTC_SHIFT);
 679
 680         switch(mode) {
 681         case DRM_MODE_DPMS_ON:
 682                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 683                 bios_5_scratch |= RADEON_DFP1_ON;
 684                 bios_6_scratch |= RADEON_DFP_DPMS_ON;
 685                 break;
 686         case DRM_MODE_DPMS_STANDBY:
 687         case DRM_MODE_DPMS_SUSPEND:
 688         case DRM_MODE_DPMS_OFF:
 689                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 690                 bios_5_scratch &= ~RADEON_DFP1_ON;
 691                 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
 692                 break;
 693         }
 694
 695         RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 696
 697         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 698         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 699 }
 700
 701 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 702 {
 703         struct drm_radeon_private *dev_priv = encoder->dev->dev_private;
 704         // fix me: atom/legacy r4xx
 705         if (!dev_priv->is_atom_bios)
 706                 radeon_combios_output_lock(encoder, true);
 707         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 708 }
 709
 710 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 711 {
 712         struct drm_radeon_private *dev_priv = encoder->dev->dev_private;
 713         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 714         // fix me: atom/legacy r4xx
 715         if (!dev_priv->is_atom_bios)
 716                 radeon_combios_output_lock(encoder, true);
 717 }
 718
 719 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 720                                             struct drm_display_mode *mode,
 721                                             struct drm_display_mode *adjusted_mode)
 722 {
 723         struct drm_device *dev = encoder->dev;
 724         struct drm_radeon_private *dev_priv = dev->dev_private;
 725         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 726         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 727         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 728         int i;
 729
 730         DRM_DEBUG("\n");
 731
 732         if (radeon_crtc->crtc_id == 0)
 733                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 734
 735         tmp = tmds_pll_cntl = RADEON_READ(RADEON_TMDS_PLL_CNTL);
 736         tmp &= 0xfffff;
 737         if (dev_priv->chip_family == CHIP_RV280) {
 738                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 739                 tmp ^= (1 << 22);
 740                 tmds_pll_cntl ^= (1 << 22);
 741         }
 742
 743         for (i = 0; i < 4; i++) {
 744                 if (radeon_encoder->tmds_pll[i].freq == 0)
 745                         break;
 746                 if ((uint32_t)(mode->clock / 10) < radeon_encoder->tmds_pll[i].freq) {
 747                         tmp = radeon_encoder->tmds_pll[i].value ;
 748                         break;
 749                 }
 750         }
 751
 752         if (radeon_is_r300(dev_priv) || (dev_priv->chip_family == CHIP_RV280)) {
 753                 if (tmp & 0xfff00000)
 754                         tmds_pll_cntl = tmp;
 755                 else {
 756                         tmds_pll_cntl &= 0xfff00000;
 757                         tmds_pll_cntl |= tmp;
 758                 }
 759         } else
 760                 tmds_pll_cntl = tmp;
 761
 762         tmds_transmitter_cntl = RADEON_READ(RADEON_TMDS_TRANSMITTER_CNTL) &
 763                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 764
 765     if (dev_priv->chip_family == CHIP_R200 ||
 766         dev_priv->chip_family == CHIP_R100 ||
 767         radeon_is_r300(dev_priv))
 768             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 769     else /* RV chips got this bit reversed */
 770             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 771
 772     fp_gen_cntl = (RADEON_READ(RADEON_FP_GEN_CNTL) |
 773                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 774                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 775
 776     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 777
 778     if (1) // FIXME rgbBits == 8
 779             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 780     else
 781             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 782
 783     if (radeon_crtc->crtc_id == 0) {
 784             if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
 785                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 786                     if (radeon_encoder->flags & RADEON_USE_RMX)
 787                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 788                     else
 789                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 790             } else
 791                     fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
 792     } else {
 793             if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
 794                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 795                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 796             } else
 797                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 798     }
 799
 800     RADEON_WRITE(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 801     RADEON_WRITE(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 802     RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 803 }
 804
 805 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 806         .dpms = radeon_legacy_tmds_int_dpms,
 807         .mode_fixup = radeon_legacy_tmds_int_mode_fixup,
 808         .prepare = radeon_legacy_tmds_int_prepare,
 809         .mode_set = radeon_legacy_tmds_int_mode_set,
 810         .commit = radeon_legacy_tmds_int_commit,
 811 };
 812
 813
 814 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 815         .destroy = radeon_enc_destroy,
 816 };
 817
 818 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index)
 819 {
 820         struct drm_radeon_private *dev_priv = dev->dev_private;
 821         struct radeon_encoder *radeon_encoder;
 822         struct drm_encoder *encoder;
 823
 824         DRM_DEBUG("\n");
 825
 826         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 827         if (!radeon_encoder) {
 828                 return NULL;
 829         }
 830
 831         encoder = &radeon_encoder->base;
 832
 833         encoder->possible_crtcs = 0x3;
 834         encoder->possible_clones = 0;
 835         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
 836                          DRM_MODE_ENCODER_TMDS);
 837
 838         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
 839
 840         if (dev_priv->is_atom_bios)
 841                 radeon_atombios_get_tmds_info(radeon_encoder);
 842         else
 843                 radeon_combios_get_tmds_info(radeon_encoder);
 844
 845         return encoder;
 846 }
 847
 848 static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
 849                                               struct drm_display_mode *mode,
 850                                               struct drm_display_mode *adjusted_mode)
 851 {
 852         return true;
 853 }
 854
 855 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 856 {
 857         struct drm_device *dev = encoder->dev;
 858         struct drm_radeon_private *dev_priv = dev->dev_private;
 859         struct radeon_crtc *radeon_crtc;
 860         uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 861         uint32_t bios_5_scratch, bios_6_scratch;
 862         int crtc_id = 0;
 863         DRM_DEBUG("\n");
 864
 865         if (encoder->crtc) {
 866                 radeon_crtc = to_radeon_crtc(encoder->crtc);
 867                 crtc_id = radeon_crtc->crtc_id;
 868         }
 869
 870         // FIXME atom/legacy cards like r4xx
 871         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 872         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 873
 874         bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
 875         bios_5_scratch |= (crtc_id << RADEON_DFP2_CRTC_SHIFT);
 876
 877         switch(mode) {
 878         case DRM_MODE_DPMS_ON:
 879                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 880                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 881                 bios_5_scratch |= RADEON_DFP2_ON;
 882                 bios_6_scratch |= RADEON_DFP_DPMS_ON;
 883                 break;
 884         case DRM_MODE_DPMS_STANDBY:
 885         case DRM_MODE_DPMS_SUSPEND:
 886         case DRM_MODE_DPMS_OFF:
 887                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 888                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 889                 bios_5_scratch &= ~RADEON_DFP2_ON;
 890                 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
 891                 break;
 892         }
 893
 894         RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 895
 896         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 897         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 898 }
 899
 900 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 901 {
 902         struct drm_radeon_private *dev_priv = encoder->dev->dev_private;
 903         // fix me: atom/legacy r4xx
 904         if (!dev_priv->is_atom_bios)
 905                 radeon_combios_output_lock(encoder, true);
 906         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 907 }
 908
 909 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 910 {
 911         struct drm_radeon_private *dev_priv = encoder->dev->dev_private;
 912         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 913         // fix me: atom/legacy r4xx
 914         if (!dev_priv->is_atom_bios)
 915                 radeon_combios_output_lock(encoder, false);
 916 }
 917
 918 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 919                                             struct drm_display_mode *mode,
 920                                             struct drm_display_mode *adjusted_mode)
 921 {
 922         struct drm_device *dev = encoder->dev;
 923         struct drm_radeon_private *dev_priv = dev->dev_private;
 924         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 925         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 926         uint32_t fp2_gen_cntl;
 927
 928         DRM_DEBUG("\n");
 929
 930         if (radeon_crtc->crtc_id == 0)
 931                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 932
 933         if (dev_priv->is_atom_bios) {
 934                 atombios_ext_tmds_setup(encoder, adjusted_mode);
 935                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 936         } else {
 937                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 938
 939                 if (1) // FIXME rgbBits == 8
 940                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 941                 else
 942                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 943
 944                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
 945                                   RADEON_FP2_DVO_EN |
 946                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 947
 948                 /* XXX: these are oem specific */
 949                 if (radeon_is_r300(dev_priv)) {
 950                         if ((dev->pdev->device == 0x4850) &&
 951                             (dev->pdev->subsystem_vendor == 0x1028) &&
 952                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 953                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 954                         else
 955                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 956
 957                         /*if (mode->clock > 165000)
 958                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 959                 }
 960         }
 961
 962         if (radeon_crtc->crtc_id == 0) {
 963                 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
 964                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 965                         if (radeon_encoder->flags & RADEON_USE_RMX)
 966                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 967                         else
 968                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 969                 } else
 970                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 971         } else {
 972                 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
 973                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 974                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 975                 } else
 976                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 977         }
 978
 979         RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 980 }
 981
 982 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 983         .dpms = radeon_legacy_tmds_ext_dpms,
 984         .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
 985         .prepare = radeon_legacy_tmds_ext_prepare,
 986         .mode_set = radeon_legacy_tmds_ext_mode_set,
 987         .commit = radeon_legacy_tmds_ext_commit,
 988 };
 989
 990
 991 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 992         .destroy = radeon_enc_destroy,
 993 };
 994
 995 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index)
 996 {
 997         struct drm_radeon_private *dev_priv = dev->dev_private;
 998         struct radeon_encoder *radeon_encoder;
 999         struct drm_encoder *encoder;
1000
1001         DRM_DEBUG("\n");
1002
1003         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1004         if (!radeon_encoder) {
1005                 return NULL;
1006         }
1007
1008         encoder = &radeon_encoder->base;
1009
1010         encoder->possible_crtcs = 0x3;
1011         encoder->possible_clones = 0;
1012         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
1013                          DRM_MODE_ENCODER_TMDS);
1014
1015         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1016
1017         if (!dev_priv->is_atom_bios)
1018                 radeon_combios_get_ext_tmds_info(radeon_encoder);
1019         return encoder;
1020 }
1021
1022 static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
1023                                             struct drm_display_mode *mode,
1024                                             struct drm_display_mode *adjusted_mode)
1025 {
1026         return true;
1027 }
1028
1029 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1030 {
1031         struct drm_device *dev = encoder->dev;
1032         struct drm_radeon_private *dev_priv = dev->dev_private;
1033         struct radeon_crtc *radeon_crtc;
1034         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1035         //uint32_t tv_master_cntl = 0;
1036         uint32_t bios_5_scratch, bios_6_scratch;
1037         int crtc_id = 0;
1038
1039         DRM_DEBUG("\n");
1040
1041         if (encoder->crtc) {
1042                 radeon_crtc = to_radeon_crtc(encoder->crtc);
1043                 crtc_id = radeon_crtc->crtc_id;
1044         }
1045
1046         // FIXME atom/legacy cards like r4xx
1047         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
1048         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
1049
1050         bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
1051         bios_5_scratch |= (crtc_id << RADEON_CRT2_CRTC_SHIFT);
1052         // FIXME TV
1053         //bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
1054         //bios_5_scratch |= (crtc_id << RADEON_TV1_CRTC_SHIFT);
1055
1056         if (dev_priv->chip_family == CHIP_R200)
1057                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
1058         else {
1059                 crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
1060                 // FIXME TV
1061                 //tv_master_cntl = RADEON_READ(RADEON_TV_MASTER_CNTL);
1062                 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
1063         }
1064
1065         switch(mode) {
1066         case DRM_MODE_DPMS_ON:
1067                 if (dev_priv->chip_family == CHIP_R200)
1068                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1069                 else {
1070                         crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1071                         //tv_master_cntl |= RADEON_TV_ON;
1072                         if (dev_priv->chip_family == CHIP_R420 ||
1073                             dev_priv->chip_family == CHIP_RV410)
1074                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1075                                                  R420_TV_DAC_GDACPD |
1076                                                  R420_TV_DAC_BDACPD |
1077                                                  RADEON_TV_DAC_BGSLEEP);
1078                         else
1079                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1080                                                  RADEON_TV_DAC_GDACPD |
1081                                                  RADEON_TV_DAC_BDACPD |
1082                                                  RADEON_TV_DAC_BGSLEEP);
1083                 }
1084                 //bios_5_scratch |= RADEON_TV1_ON;
1085                 //bios_6_scratch |= RADEON_TV_DPMS_ON;
1086                 bios_5_scratch |= RADEON_CRT2_ON;
1087                 bios_6_scratch |= RADEON_CRT_DPMS_ON;
1088                 break;
1089         case DRM_MODE_DPMS_STANDBY:
1090         case DRM_MODE_DPMS_SUSPEND:
1091         case DRM_MODE_DPMS_OFF:
1092                 if (dev_priv->chip_family == CHIP_R200)
1093                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1094                 else {
1095                         crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1096                         //tv_master_cntl &= ~RADEON_TV_ON;
1097                         if (dev_priv->chip_family == CHIP_R420 ||
1098                             dev_priv->chip_family == CHIP_RV410)
1099                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1100                                                 R420_TV_DAC_GDACPD |
1101                                                 R420_TV_DAC_BDACPD |
1102                                                 RADEON_TV_DAC_BGSLEEP);
1103                         else
1104                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1105                                                 RADEON_TV_DAC_GDACPD |
1106                                                 RADEON_TV_DAC_BDACPD |
1107                                                 RADEON_TV_DAC_BGSLEEP);
1108                 }
1109                 //bios_5_scratch &= ~RADEON_TV1_ON;
1110                 //bios_6_scratch &= ~RADEON_TV_DPMS_ON;
1111                 bios_5_scratch &= ~RADEON_CRT2_ON;
1112                 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
1113                 break;
1114         }
1115
1116         if (dev_priv->chip_family == CHIP_R200)
1117                 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1118         else {
1119                 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1120                 //RADEON_WRITE(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1121                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1122         }
1123
1124         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
1125         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1126 }
1127
1128 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1129 {
1130         // fix me: atom/legacy r4xx
1131         radeon_combios_output_lock(encoder, true);
1132         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1133 }
1134
1135 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1136 {
1137         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1138         // fix me: atom/legacy r4xx
1139         radeon_combios_output_lock(encoder, false);
1140 }
1141
1142 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1143                                           struct drm_display_mode *mode,
1144                                           struct drm_display_mode *adjusted_mode)
1145 {
1146         struct drm_device *dev = encoder->dev;
1147         struct drm_radeon_private *dev_priv = dev->dev_private;
1148         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1149         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1150         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1151         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0;
1152
1153         DRM_DEBUG("\n");
1154
1155         if (radeon_crtc->crtc_id == 0)
1156                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
1157
1158         if (dev_priv->chip_family != CHIP_R200) {
1159                 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
1160                 if (dev_priv->chip_family == CHIP_R420 ||
1161                     dev_priv->chip_family == CHIP_RV410) {
1162                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1163                                          RADEON_TV_DAC_BGADJ_MASK |
1164                                          R420_TV_DAC_DACADJ_MASK |
1165                                          R420_TV_DAC_RDACPD |
1166                                          R420_TV_DAC_GDACPD |
1167                                          R420_TV_DAC_GDACPD |
1168                                          R420_TV_DAC_TVENABLE);
1169                 } else {
1170                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1171                                          RADEON_TV_DAC_BGADJ_MASK |
1172                                          RADEON_TV_DAC_DACADJ_MASK |
1173                                          RADEON_TV_DAC_RDACPD |
1174                                          RADEON_TV_DAC_GDACPD |
1175                                          RADEON_TV_DAC_GDACPD);
1176                 }
1177
1178                 // FIXME TV
1179                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1180                                 RADEON_TV_DAC_NHOLD |
1181                                 RADEON_TV_DAC_STD_PS2 |
1182                                 radeon_encoder->ps2_tvdac_adj);
1183
1184                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1185         }
1186
1187         if (radeon_is_r300(dev_priv)) {
1188                 gpiopad_a = RADEON_READ(RADEON_GPIOPAD_A) | 1;
1189                 disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL);
1190         } else if (dev_priv->chip_family == CHIP_R200)
1191                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
1192         else
1193                 disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
1194
1195         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1196
1197         if (radeon_crtc->crtc_id == 0) {
1198                 if (radeon_is_r300(dev_priv)) {
1199                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1200                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1201                 } else if (dev_priv->chip_family == CHIP_R200) {
1202                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1203                                           RADEON_FP2_DVO_RATE_SEL_SDR);
1204                 } else
1205                         disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1206         } else {
1207                 if (radeon_is_r300(dev_priv)) {
1208                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1209                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1210                 } else if (dev_priv->chip_family == CHIP_R200) {
1211                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1212                                           RADEON_FP2_DVO_RATE_SEL_SDR);
1213                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1214                 } else
1215                         disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1216         }
1217
1218         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
1219
1220         if (radeon_is_r300(dev_priv)) {
1221                 RADEON_WRITE_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1222                 RADEON_WRITE(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
1223         } else if (dev_priv->chip_family == CHIP_R200)
1224                 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1225         else
1226                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1227
1228 }
1229
1230 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1231                                                              struct drm_connector *connector)
1232 {
1233         struct drm_device *dev = encoder->dev;
1234         struct drm_radeon_private *dev_priv = dev->dev_private;
1235         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1236         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1237         enum drm_connector_status found = connector_status_disconnected;
1238         bool color = true;
1239
1240         // FIXME tv
1241
1242         /* save the regs we need */
1243         pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
1244         gpiopad_a = radeon_is_r300(dev_priv) ? RADEON_READ(RADEON_GPIOPAD_A) : 0;
1245         disp_output_cntl = radeon_is_r300(dev_priv) ? RADEON_READ(RADEON_DISP_OUTPUT_CNTL) : 0;
1246         disp_hw_debug = radeon_is_r300(dev_priv) ? 0 : RADEON_READ(RADEON_DISP_HW_DEBUG);
1247         crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
1248         tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
1249         dac_ext_cntl = RADEON_READ(RADEON_DAC_EXT_CNTL);
1250         dac_cntl2 = RADEON_READ(RADEON_DAC_CNTL2);
1251
1252         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1253                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1254         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
1255
1256         if (radeon_is_r300(dev_priv))
1257                 RADEON_WRITE_P(RADEON_GPIOPAD_A, 1, ~1);
1258
1259         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1260         tmp |= RADEON_CRTC2_CRT2_ON |
1261                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1262
1263         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, tmp);
1264
1265         if (radeon_is_r300(dev_priv)) {
1266                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1267                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1268                 RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, tmp);
1269         } else {
1270                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1271                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, tmp);
1272         }
1273
1274         tmp = RADEON_TV_DAC_NBLANK |
1275                 RADEON_TV_DAC_NHOLD |
1276                 RADEON_TV_MONITOR_DETECT_EN |
1277                 RADEON_TV_DAC_STD_PS2;
1278
1279         RADEON_WRITE(RADEON_TV_DAC_CNTL, tmp);
1280
1281         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1282                 RADEON_DAC2_FORCE_DATA_EN;
1283
1284         if (color)
1285                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1286         else
1287                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1288
1289         if (radeon_is_r300(dev_priv))
1290                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1291         else
1292                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1293
1294         RADEON_WRITE(RADEON_DAC_EXT_CNTL, tmp);
1295
1296         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1297         RADEON_WRITE(RADEON_DAC_CNTL2, tmp);
1298
1299         udelay(10000);
1300
1301         if (radeon_is_r300(dev_priv)) {
1302                 if (RADEON_READ(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1303                         found = connector_status_connected;
1304         } else {
1305                 if (RADEON_READ(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1306                         found = connector_status_connected;
1307         }
1308
1309         /* restore regs we used */
1310         RADEON_WRITE(RADEON_DAC_CNTL2, dac_cntl2);
1311         RADEON_WRITE(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1312         RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1313         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1314
1315         if (radeon_is_r300(dev_priv)) {
1316                 RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1317                 RADEON_WRITE_P(RADEON_GPIOPAD_A, gpiopad_a, ~1 );
1318         } else {
1319                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1320         }
1321         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
1322
1323         //return found;
1324         return connector_status_disconnected;
1325
1326 }
1327
1328 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1329         .dpms = radeon_legacy_tv_dac_dpms,
1330         .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
1331         .prepare = radeon_legacy_tv_dac_prepare,
1332         .mode_set = radeon_legacy_tv_dac_mode_set,
1333         .commit = radeon_legacy_tv_dac_commit,
1334         .detect = radeon_legacy_tv_dac_detect,
1335 };
1336
1337
1338 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1339         .destroy = radeon_enc_destroy,
1340 };
1341
1342 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int has_tv)
1343 {
1344         struct radeon_encoder *radeon_encoder;
1345         struct drm_encoder *encoder;
1346
1347         DRM_DEBUG("\n");
1348
1349         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1350         if (!radeon_encoder) {
1351                 return NULL;
1352         }
1353
1354         encoder = &radeon_encoder->base;
1355
1356         encoder->possible_crtcs = 0x3;
1357         encoder->possible_clones = 0;
1358         drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1359                          DRM_MODE_ENCODER_DAC);
1360
1361         drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1362
1363         /* get the tv dac vals from bios tables */
1364         radeon_combios_get_tv_info(radeon_encoder);
1365         radeon_combios_get_tv_dac_info(radeon_encoder);
1366
1367         return encoder;
1368 }