linux-core/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31
  32 static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder,
  33                                        struct drm_display_mode *mode,
  34                                        struct drm_display_mode *adjusted_mode)
  35 {
  36         struct drm_device *dev = encoder->dev;
  37         struct drm_radeon_private *dev_priv = dev->dev_private;
  38         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  39         int    xres = mode->hdisplay;
  40         int    yres = mode->vdisplay;
  41         bool   hscale = true, vscale = true;
  42         int    hsync_wid;
  43         int    vsync_wid;
  44         int    hsync_start;
  45         uint32_t scale, inc;
  46         uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active;
  47         uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp;
  48
  49         DRM_DEBUG("\n");
  50
  51         fp_vert_stretch = RADEON_READ(RADEON_FP_VERT_STRETCH) &
  52                 (RADEON_VERT_STRETCH_RESERVED |
  53                  RADEON_VERT_AUTO_RATIO_INC);
  54         fp_horz_stretch = RADEON_READ(RADEON_FP_HORZ_STRETCH) &
  55                 (RADEON_HORZ_FP_LOOP_STRETCH |
  56                  RADEON_HORZ_AUTO_RATIO_INC);
  57
  58         crtc_more_cntl = 0;
  59         if ((dev_priv->chip_family == CHIP_RS100) ||
  60             (dev_priv->chip_family == CHIP_RS200)) {
  61                 /* This is to workaround the asic bug for RMX, some versions
  62                    of BIOS dosen't have this register initialized correctly. */
  63                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  64         }
  65
  66
  67         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  68                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  69
  70         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  71         if (!hsync_wid)
  72                 hsync_wid = 1;
  73         hsync_start = mode->crtc_hsync_start - 8;
  74
  75         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  76                               | ((hsync_wid & 0x3f) << 16)
  77                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  78                                  ? RADEON_CRTC_H_SYNC_POL
  79                                  : 0));
  80
  81         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  82                                 | ((mode->crtc_vdisplay - 1) << 16));
  83
  84         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  85         if (!vsync_wid)
  86                 vsync_wid = 1;
  87
  88         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
  89                               | ((vsync_wid & 0x1f) << 16)
  90                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
  91                                  ? RADEON_CRTC_V_SYNC_POL
  92                                  : 0));
  93
  94         fp_horz_vert_active = 0;
  95
  96         if (radeon_encoder->panel_xres == 0 ||
  97             radeon_encoder->panel_yres == 0) {
  98                 hscale = false;
  99                 vscale = false;
 100         } else {
 101                 if (xres > radeon_encoder->panel_xres)
 102                         xres = radeon_encoder->panel_xres;
 103                 if (yres > radeon_encoder->panel_yres)
 104                         yres = radeon_encoder->panel_yres;
 105
 106                 if (xres == radeon_encoder->panel_xres)
 107                         hscale = false;
 108                 if (yres == radeon_encoder->panel_yres)
 109                         vscale = false;
 110         }
 111
 112         if (radeon_encoder->flags & RADEON_USE_RMX) {
 113                 if (radeon_encoder->rmx_type != RMX_CENTER) {
 114                         if (!hscale)
 115                                 fp_horz_stretch |= ((xres/8-1) << 16);
 116                         else {
 117                                 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 118                                 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 119                                         / radeon_encoder->panel_xres + 1;
 120                                 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 121                                                     RADEON_HORZ_STRETCH_BLEND |
 122                                                     RADEON_HORZ_STRETCH_ENABLE |
 123                                                     ((radeon_encoder->panel_xres/8-1) << 16));
 124                         }
 125
 126                         if (!vscale)
 127                                 fp_vert_stretch |= ((yres-1) << 12);
 128                         else {
 129                                 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 130                                 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 131                                         / radeon_encoder->panel_yres + 1;
 132                                 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 133                                                     RADEON_VERT_STRETCH_ENABLE |
 134                                                     RADEON_VERT_STRETCH_BLEND |
 135                                                     ((radeon_encoder->panel_yres-1) << 12));
 136                         }
 137                 } else if (radeon_encoder->rmx_type == RMX_CENTER) {
 138                         int    blank_width;
 139
 140                         fp_horz_stretch |= ((xres/8-1) << 16);
 141                         fp_vert_stretch |= ((yres-1) << 12);
 142
 143                         crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 144                                            RADEON_CRTC_AUTO_VERT_CENTER_EN);
 145
 146                         blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 147                         if (blank_width > 110)
 148                                 blank_width = 110;
 149
 150                         fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 151                                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 152
 153                         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 154                         if (!hsync_wid)
 155                                 hsync_wid = 1;
 156
 157                         fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 158                                               | ((hsync_wid & 0x3f) << 16)
 159                                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 160                                                  ? RADEON_CRTC_H_SYNC_POL
 161                                                  : 0));
 162
 163                         fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 164                                                 | ((mode->crtc_vdisplay - 1) << 16));
 165
 166                         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 167                         if (!vsync_wid)
 168                                 vsync_wid = 1;
 169
 170                         fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 171                                                | ((vsync_wid & 0x1f) << 16)
 172                                                | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 173                                                   ? RADEON_CRTC_V_SYNC_POL
 174                                                   : 0)));
 175
 176                         fp_horz_vert_active = (((radeon_encoder->panel_yres) & 0xfff) |
 177                                                (((radeon_encoder->panel_xres / 8) & 0x1ff) << 16));
 178                 }
 179         } else {
 180                 fp_horz_stretch |= ((xres/8-1) << 16);
 181                 fp_vert_stretch |= ((yres-1) << 12);
 182         }
 183
 184         RADEON_WRITE(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 185         RADEON_WRITE(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 186         RADEON_WRITE(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 187         RADEON_WRITE(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 188         RADEON_WRITE(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 189         RADEON_WRITE(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 190         RADEON_WRITE(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 191         RADEON_WRITE(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 192
 193 }
 194
 195 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 196 {
 197         struct drm_device *dev = encoder->dev;
 198         struct drm_radeon_private *dev_priv = dev->dev_private;
 199         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 200         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
 201
 202         DRM_DEBUG("\n");
 203
 204         switch (mode) {
 205         case DRM_MODE_DPMS_ON:
 206                 disp_pwr_man = RADEON_READ(RADEON_DISP_PWR_MAN);
 207                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
 208                 RADEON_WRITE(RADEON_DISP_PWR_MAN, disp_pwr_man);
 209                 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 210                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
 211                 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 212                 udelay(1000);
 213                 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 214                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
 215                 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 216
 217                 /* enable lvds, turn on voltage */
 218                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 219                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 220                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 221                 udelay(radeon_encoder->panel_digon_delay * 1000);
 222
 223                 /* enable data */
 224                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
 225                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 226                 udelay(radeon_encoder->panel_blon_delay * 1000);
 227
 228                 /* enable backlight */
 229                 lvds_gen_cntl |= RADEON_LVDS_BLON;
 230                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 231                 break;
 232         case DRM_MODE_DPMS_STANDBY:
 233         case DRM_MODE_DPMS_SUSPEND:
 234         case DRM_MODE_DPMS_OFF:
 235                 pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
 236                 RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
 237                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 238                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 239                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 240                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 241                 RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
 242                 break;
 243         }
 244 }
 245
 246 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 247 {
 248         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 249 }
 250
 251 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 252 {
 253         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 254 }
 255
 256 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 257                                         struct drm_display_mode *mode,
 258                                         struct drm_display_mode *adjusted_mode)
 259 {
 260         struct drm_device *dev = encoder->dev;
 261         struct drm_radeon_private *dev_priv = dev->dev_private;
 262         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 263         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 264         uint32_t lvds_pll_cntl, lvds_gen_cntl;
 265
 266         DRM_DEBUG("\n");
 267
 268         if (radeon_crtc->crtc_id == 0)
 269                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 270
 271         lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 272         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 273         if (radeon_encoder->lvds_gen_cntl)
 274                 lvds_gen_cntl = radeon_encoder->lvds_gen_cntl;
 275         else
 276                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 277         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 278         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 279                            RADEON_LVDS_BLON |
 280                            RADEON_LVDS_EN |
 281                            RADEON_LVDS_RST_FM);
 282
 283         if (radeon_is_r300(dev_priv))
 284                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 285
 286         if (radeon_crtc->crtc_id == 0) {
 287                 if (radeon_is_r300(dev_priv)) {
 288                         if (radeon_encoder->flags & RADEON_USE_RMX)
 289                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 290                 } else
 291                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 292         } else {
 293                 if (radeon_is_r300(dev_priv)) {
 294                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 295                 } else
 296                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 297         }
 298
 299         RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 300         RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 301
 302         if (dev_priv->chip_family == CHIP_RV410)
 303                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
 304 }
 305
 306 static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
 307                                           struct drm_display_mode *mode,
 308                                           struct drm_display_mode *adjusted_mode)
 309 {
 310         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 311
 312         radeon_encoder->flags &= ~RADEON_USE_RMX;
 313
 314         if (radeon_encoder->rmx_type != RMX_OFF)
 315                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
 316
 317         return true;
 318 }
 319
 320 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 321         .dpms = radeon_legacy_lvds_dpms,
 322         .mode_fixup = radeon_legacy_lvds_mode_fixup,
 323         .prepare = radeon_legacy_lvds_prepare,
 324         .mode_set = radeon_legacy_lvds_mode_set,
 325         .commit = radeon_legacy_lvds_commit,
 326 };
 327
 328
 329 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 330         .destroy = radeon_enc_destroy,
 331 };
 332
 333
 334 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index)
 335 {
 336         struct radeon_encoder *radeon_encoder;
 337         struct drm_encoder *encoder;
 338
 339         DRM_DEBUG("\n");
 340
 341         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 342         if (!radeon_encoder) {
 343                 return NULL;
 344         }
 345
 346         encoder = &radeon_encoder->base;
 347
 348         encoder->possible_crtcs = 0x3;
 349         encoder->possible_clones = 0;
 350         drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
 351                          DRM_MODE_ENCODER_LVDS);
 352
 353         drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
 354
 355         /* get the lvds info from the bios */
 356         radeon_combios_get_lvds_info(radeon_encoder);
 357
 358         /* LVDS gets default RMX full scaling */
 359         radeon_encoder->rmx_type = RMX_FULL;
 360
 361         return encoder;
 362 }
 363
 364 static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
 365                                                  struct drm_display_mode *mode,
 366                                                  struct drm_display_mode *adjusted_mode)
 367 {
 368         return true;
 369 }
 370
 371 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 372 {
 373         struct drm_device *dev = encoder->dev;
 374         struct drm_radeon_private *dev_priv = dev->dev_private;
 375         uint32_t crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 376         uint32_t dac_cntl = RADEON_READ(RADEON_DAC_CNTL);
 377         uint32_t dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 378
 379         DRM_DEBUG("\n");
 380
 381         switch(mode) {
 382         case DRM_MODE_DPMS_ON:
 383                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 384                 dac_cntl &= ~RADEON_DAC_PDWN;
 385                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 386                                     RADEON_DAC_PDWN_G |
 387                                     RADEON_DAC_PDWN_B);
 388                 break;
 389         case DRM_MODE_DPMS_STANDBY:
 390         case DRM_MODE_DPMS_SUSPEND:
 391         case DRM_MODE_DPMS_OFF:
 392                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 393                 dac_cntl |= RADEON_DAC_PDWN;
 394                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 395                                    RADEON_DAC_PDWN_G |
 396                                    RADEON_DAC_PDWN_B);
 397                 break;
 398         }
 399
 400         RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 401         RADEON_WRITE(RADEON_DAC_CNTL, dac_cntl);
 402         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 403
 404 }
 405
 406 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 407 {
 408         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 409 }
 410
 411 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 412 {
 413         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 414 }
 415
 416 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 417                                                struct drm_display_mode *mode,
 418                                                struct drm_display_mode *adjusted_mode)
 419 {
 420         struct drm_device *dev = encoder->dev;
 421         struct drm_radeon_private *dev_priv = dev->dev_private;
 422         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 423         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 424
 425         DRM_DEBUG("\n");
 426
 427         if (radeon_crtc->crtc_id == 0)
 428                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 429
 430         if (radeon_crtc->crtc_id == 0) {
 431                 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
 432                         disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
 433                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 434                         RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 435                 } else {
 436                         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 437                         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 438                 }
 439         } else {
 440                 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
 441                         disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
 442                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 443                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 444                         RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 445                 } else {
 446                         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 447                         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 448                 }
 449         }
 450
 451         dac_cntl = (RADEON_DAC_MASK_ALL |
 452                     RADEON_DAC_VGA_ADR_EN |
 453                     /* TODO 6-bits */
 454                     RADEON_DAC_8BIT_EN);
 455
 456         RADEON_WRITE_P(RADEON_DAC_CNTL,
 457                        dac_cntl,
 458                        RADEON_DAC_RANGE_CNTL |
 459                        RADEON_DAC_BLANKING);
 460
 461         dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 462         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 463 }
 464
 465 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 466 {
 467         // FIXME
 468         return connector_status_disconnected;
 469
 470 }
 471
 472 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 473         .dpms = radeon_legacy_primary_dac_dpms,
 474         .mode_fixup = radeon_legacy_primary_dac_mode_fixup,
 475         .prepare = radeon_legacy_primary_dac_prepare,
 476         .mode_set = radeon_legacy_primary_dac_mode_set,
 477         .commit = radeon_legacy_primary_dac_commit,
 478         .detect = radeon_legacy_primary_dac_detect,
 479 };
 480
 481
 482 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 483         .destroy = radeon_enc_destroy,
 484 };
 485
 486 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int has_tv)
 487 {
 488         struct radeon_encoder *radeon_encoder;
 489         struct drm_encoder *encoder;
 490
 491         DRM_DEBUG("\n");
 492
 493         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 494         if (!radeon_encoder) {
 495                 return NULL;
 496         }
 497
 498         encoder = &radeon_encoder->base;
 499
 500         encoder->possible_crtcs = 0x3;
 501         encoder->possible_clones = 0;
 502         drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
 503                          DRM_MODE_ENCODER_DAC);
 504
 505         drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
 506
 507         /* TODO get the primary dac vals from bios tables */
 508         //radeon_combios_get_lvds_info(radeon_encoder);
 509
 510         return encoder;
 511 }
 512
 513
 514 static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
 515                                               struct drm_display_mode *mode,
 516                                               struct drm_display_mode *adjusted_mode)
 517 {
 518         return true;
 519 }
 520
 521 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 522 {
 523         struct drm_device *dev = encoder->dev;
 524         struct drm_radeon_private *dev_priv = dev->dev_private;
 525         uint32_t fp_gen_cntl = RADEON_READ(RADEON_FP_GEN_CNTL);
 526
 527         DRM_DEBUG("\n");
 528
 529         switch(mode) {
 530         case DRM_MODE_DPMS_ON:
 531                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 532                 break;
 533         case DRM_MODE_DPMS_STANDBY:
 534         case DRM_MODE_DPMS_SUSPEND:
 535         case DRM_MODE_DPMS_OFF:
 536                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 537                 break;
 538         }
 539
 540         RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 541 }
 542
 543 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 544 {
 545         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 546 }
 547
 548 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 549 {
 550         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 551 }
 552
 553 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 554                                             struct drm_display_mode *mode,
 555                                             struct drm_display_mode *adjusted_mode)
 556 {
 557         struct drm_device *dev = encoder->dev;
 558         struct drm_radeon_private *dev_priv = dev->dev_private;
 559         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 560         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 561         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 562         int i;
 563
 564         DRM_DEBUG("\n");
 565
 566         if (radeon_crtc->crtc_id == 0)
 567                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 568
 569         tmp = tmds_pll_cntl = RADEON_READ(RADEON_TMDS_PLL_CNTL);
 570         tmp &= 0xfffff;
 571         if (dev_priv->chip_family == CHIP_RV280) {
 572                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 573                 tmp ^= (1 << 22);
 574                 tmds_pll_cntl ^= (1 << 22);
 575         }
 576
 577         for (i = 0; i < 4; i++) {
 578                 if (radeon_encoder->tmds_pll[i].freq == 0)
 579                         break;
 580                 if ((uint32_t)(mode->clock / 10) < radeon_encoder->tmds_pll[i].freq) {
 581                         tmp = radeon_encoder->tmds_pll[i].value ;
 582                         break;
 583                 }
 584         }
 585
 586         if (radeon_is_r300(dev_priv) || (dev_priv->chip_family == CHIP_RV280)) {
 587                 if (tmp & 0xfff00000)
 588                         tmds_pll_cntl = tmp;
 589                 else {
 590                         tmds_pll_cntl &= 0xfff00000;
 591                         tmds_pll_cntl |= tmp;
 592                 }
 593         } else
 594                 tmds_pll_cntl = tmp;
 595
 596         tmds_transmitter_cntl = RADEON_READ(RADEON_TMDS_TRANSMITTER_CNTL) &
 597                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 598
 599     if (dev_priv->chip_family == CHIP_R200 ||
 600         dev_priv->chip_family == CHIP_R100 ||
 601         radeon_is_r300(dev_priv))
 602             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 603     else /* RV chips got this bit reversed */
 604             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 605
 606     fp_gen_cntl = (RADEON_READ(RADEON_FP_GEN_CNTL) |
 607                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 608                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 609
 610     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 611
 612     if (1) // FIXME rgbBits == 8
 613             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 614     else
 615             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 616
 617     if (radeon_crtc->crtc_id == 0) {
 618             if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
 619                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 620                     if (radeon_encoder->flags & RADEON_USE_RMX)
 621                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 622                     else
 623                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 624             } else
 625                     fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
 626     } else {
 627             if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
 628                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 629                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 630             } else
 631                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 632     }
 633
 634     RADEON_WRITE(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 635     RADEON_WRITE(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 636     RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 637 }
 638
 639 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 640         .dpms = radeon_legacy_tmds_int_dpms,
 641         .mode_fixup = radeon_legacy_tmds_int_mode_fixup,
 642         .prepare = radeon_legacy_tmds_int_prepare,
 643         .mode_set = radeon_legacy_tmds_int_mode_set,
 644         .commit = radeon_legacy_tmds_int_commit,
 645 };
 646
 647
 648 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 649         .destroy = radeon_enc_destroy,
 650 };
 651
 652 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index)
 653 {
 654         struct radeon_encoder *radeon_encoder;
 655         struct drm_encoder *encoder;
 656
 657         DRM_DEBUG("\n");
 658
 659         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 660         if (!radeon_encoder) {
 661                 return NULL;
 662         }
 663
 664         encoder = &radeon_encoder->base;
 665
 666         encoder->possible_crtcs = 0x3;
 667         encoder->possible_clones = 0;
 668         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
 669                          DRM_MODE_ENCODER_TMDS);
 670
 671         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
 672
 673         radeon_combios_get_tmds_info(radeon_encoder);
 674
 675         return encoder;
 676 }
 677
 678 static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
 679                                               struct drm_display_mode *mode,
 680                                               struct drm_display_mode *adjusted_mode)
 681 {
 682         return true;
 683 }
 684
 685 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 686 {
 687         struct drm_device *dev = encoder->dev;
 688         struct drm_radeon_private *dev_priv = dev->dev_private;
 689         uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 690
 691         DRM_DEBUG("\n");
 692
 693         switch(mode) {
 694         case DRM_MODE_DPMS_ON:
 695                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 696                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 697                 break;
 698         case DRM_MODE_DPMS_STANDBY:
 699         case DRM_MODE_DPMS_SUSPEND:
 700         case DRM_MODE_DPMS_OFF:
 701                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 702                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 703                 break;
 704         }
 705
 706         RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 707 }
 708
 709 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 710 {
 711         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 712 }
 713
 714 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 715 {
 716         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 717 }
 718
 719 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 720                                             struct drm_display_mode *mode,
 721                                             struct drm_display_mode *adjusted_mode)
 722 {
 723         struct drm_device *dev = encoder->dev;
 724         struct drm_radeon_private *dev_priv = dev->dev_private;
 725         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 726         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 727         uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 728
 729         DRM_DEBUG("\n");
 730
 731         if (radeon_crtc->crtc_id == 0)
 732                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 733
 734         if (1) // FIXME rgbBits == 8
 735                 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 736         else
 737                 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 738
 739         fp2_gen_cntl &= ~(RADEON_FP2_ON |
 740                           RADEON_FP2_DVO_EN |
 741                           RADEON_FP2_DVO_RATE_SEL_SDR);
 742
 743         /* XXX: these are oem specific */
 744         if (radeon_is_r300(dev_priv)) {
 745                 if ((dev->pdev->device == 0x4850) &&
 746                     (dev->pdev->subsystem_vendor == 0x1028) &&
 747                     (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 748                         fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 749                 else
 750                         fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 751
 752                 /*if (mode->clock > 165000)
 753                         fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 754         }
 755
 756         if (radeon_crtc->crtc_id == 0) {
 757                 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
 758                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 759                         if (radeon_encoder->flags & RADEON_USE_RMX)
 760                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 761                         else
 762                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 763                 } else
 764                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 765         } else {
 766                 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
 767                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 768                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 769                 } else
 770                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 771         }
 772
 773         RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 774 }
 775
 776 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 777         .dpms = radeon_legacy_tmds_ext_dpms,
 778         .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
 779         .prepare = radeon_legacy_tmds_ext_prepare,
 780         .mode_set = radeon_legacy_tmds_ext_mode_set,
 781         .commit = radeon_legacy_tmds_ext_commit,
 782 };
 783
 784
 785 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 786         .destroy = radeon_enc_destroy,
 787 };
 788
 789 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index)
 790 {
 791         struct radeon_encoder *radeon_encoder;
 792         struct drm_encoder *encoder;
 793
 794         DRM_DEBUG("\n");
 795
 796         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 797         if (!radeon_encoder) {
 798                 return NULL;
 799         }
 800
 801         encoder = &radeon_encoder->base;
 802
 803         encoder->possible_crtcs = 0x3;
 804         encoder->possible_clones = 0;
 805         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
 806                          DRM_MODE_ENCODER_TMDS);
 807
 808         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
 809
 810         //radeon_combios_get_tmds_info(radeon_encoder);
 811         return encoder;
 812 }
 813
 814 static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
 815                                             struct drm_display_mode *mode,
 816                                             struct drm_display_mode *adjusted_mode)
 817 {
 818         return true;
 819 }
 820
 821 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 822 {
 823         struct drm_device *dev = encoder->dev;
 824         struct drm_radeon_private *dev_priv = dev->dev_private;
 825         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
 826         //uint32_t tv_master_cntl = 0;
 827
 828         DRM_DEBUG("\n");
 829
 830         if (dev_priv->chip_family == CHIP_R200)
 831                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 832         else {
 833                 crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
 834                 // FIXME TV
 835                 //tv_master_cntl = RADEON_READ(RADEON_TV_MASTER_CNTL);
 836                 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
 837         }
 838
 839         switch(mode) {
 840         case DRM_MODE_DPMS_ON:
 841                 if (dev_priv->chip_family == CHIP_R200)
 842                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 843                 else {
 844                         crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
 845                         //tv_master_cntl |= RADEON_TV_ON;
 846                         if (dev_priv->chip_family == CHIP_R420 ||
 847                             dev_priv->chip_family == CHIP_RV410)
 848                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
 849                                                  R420_TV_DAC_GDACPD |
 850                                                  R420_TV_DAC_BDACPD |
 851                                                  RADEON_TV_DAC_BGSLEEP);
 852                         else
 853                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
 854                                                  RADEON_TV_DAC_GDACPD |
 855                                                  RADEON_TV_DAC_BDACPD |
 856                                                  RADEON_TV_DAC_BGSLEEP);
 857                 }
 858                 break;
 859         case DRM_MODE_DPMS_STANDBY:
 860         case DRM_MODE_DPMS_SUSPEND:
 861         case DRM_MODE_DPMS_OFF:
 862                 if (dev_priv->chip_family == CHIP_R200)
 863                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 864                 else {
 865                         crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
 866                         //tv_master_cntl &= ~RADEON_TV_ON;
 867                         if (dev_priv->chip_family == CHIP_R420 ||
 868                             dev_priv->chip_family == CHIP_RV410)
 869                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
 870                                                 R420_TV_DAC_GDACPD |
 871                                                 R420_TV_DAC_BDACPD |
 872                                                 RADEON_TV_DAC_BGSLEEP);
 873                         else
 874                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
 875                                                 RADEON_TV_DAC_GDACPD |
 876                                                 RADEON_TV_DAC_BDACPD |
 877                                                 RADEON_TV_DAC_BGSLEEP);
 878                 }
 879                 break;
 880         }
 881
 882         if (dev_priv->chip_family == CHIP_R200)
 883                 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 884         else {
 885                 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 886                 //RADEON_WRITE(RADEON_TV_MASTER_CNTL, tv_master_cntl);
 887                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 888         }
 889
 890 }
 891
 892 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
 893 {
 894         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 895 }
 896
 897 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
 898 {
 899         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 900 }
 901
 902 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 903                                           struct drm_display_mode *mode,
 904                                           struct drm_display_mode *adjusted_mode)
 905 {
 906         struct drm_device *dev = encoder->dev;
 907         struct drm_radeon_private *dev_priv = dev->dev_private;
 908         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 909         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 910         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
 911         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0;
 912
 913         DRM_DEBUG("\n");
 914
 915         if (radeon_crtc->crtc_id == 0)
 916                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 917
 918         if (dev_priv->chip_family != CHIP_R200) {
 919                 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
 920                 if (dev_priv->chip_family == CHIP_R420 ||
 921                     dev_priv->chip_family == CHIP_RV410) {
 922                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 923                                          RADEON_TV_DAC_BGADJ_MASK |
 924                                          R420_TV_DAC_DACADJ_MASK |
 925                                          R420_TV_DAC_RDACPD |
 926                                          R420_TV_DAC_GDACPD |
 927                                          R420_TV_DAC_GDACPD |
 928                                          R420_TV_DAC_TVENABLE);
 929                 } else {
 930                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 931                                          RADEON_TV_DAC_BGADJ_MASK |
 932                                          RADEON_TV_DAC_DACADJ_MASK |
 933                                          RADEON_TV_DAC_RDACPD |
 934                                          RADEON_TV_DAC_GDACPD |
 935                                          RADEON_TV_DAC_GDACPD);
 936                 }
 937
 938                 // FIXME TV
 939                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 940                                 RADEON_TV_DAC_NHOLD |
 941                                 RADEON_TV_DAC_STD_PS2 |
 942                                 radeon_encoder->ps2_tvdac_adj);
 943
 944                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 945         }
 946
 947         if (radeon_is_r300(dev_priv)) {
 948                 gpiopad_a = RADEON_READ(RADEON_GPIOPAD_A) | 1;
 949                 disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL);
 950         } else if (dev_priv->chip_family == CHIP_R200)
 951                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 952         else
 953                 disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
 954
 955         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
 956
 957         if (radeon_crtc->crtc_id == 0) {
 958                 if (radeon_is_r300(dev_priv)) {
 959                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 960                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
 961                 } else if (dev_priv->chip_family == CHIP_R200) {
 962                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 963                                           RADEON_FP2_DVO_RATE_SEL_SDR);
 964                 } else
 965                         disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 966         } else {
 967                 if (radeon_is_r300(dev_priv)) {
 968                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 969                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
 970                 } else if (dev_priv->chip_family == CHIP_R200) {
 971                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 972                                           RADEON_FP2_DVO_RATE_SEL_SDR);
 973                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 974                 } else
 975                         disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 976         }
 977
 978         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 979
 980         if (radeon_is_r300(dev_priv)) {
 981                 RADEON_WRITE_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
 982                 RADEON_WRITE(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
 983         } else if (dev_priv->chip_family == CHIP_R200)
 984                 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 985         else
 986                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 987
 988 }
 989
 990 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 991 {
 992         // FIXME
 993         return connector_status_disconnected;
 994
 995 }
 996
 997 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
 998         .dpms = radeon_legacy_tv_dac_dpms,
 999         .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
1000         .prepare = radeon_legacy_tv_dac_prepare,
1001         .mode_set = radeon_legacy_tv_dac_mode_set,
1002         .commit = radeon_legacy_tv_dac_commit,
1003         .detect = radeon_legacy_tv_dac_detect,
1004 };
1005
1006
1007 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1008         .destroy = radeon_enc_destroy,
1009 };
1010
1011 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int has_tv)
1012 {
1013         struct radeon_encoder *radeon_encoder;
1014         struct drm_encoder *encoder;
1015
1016         DRM_DEBUG("\n");
1017
1018         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1019         if (!radeon_encoder) {
1020                 return NULL;
1021         }
1022
1023         encoder = &radeon_encoder->base;
1024
1025         encoder->possible_crtcs = 0x3;
1026         encoder->possible_clones = 0;
1027         drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1028                          DRM_MODE_ENCODER_DAC);
1029
1030         drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1031
1032         /* get the tv dac vals from bios tables */
1033         radeon_combios_get_tv_info(radeon_encoder);
1034         radeon_combios_get_tv_dac_info(radeon_encoder);
1035
1036         return encoder;
1037 }