linux-core/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #include "drm_crtc_helper.h"
  31
  32 void radeon_restore_common_regs(struct drm_device *dev)
  33 {
  34         /* don't need this yet */
  35 }
  36
  37 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
  38 {
  39         struct drm_radeon_private *dev_priv = dev->dev_private;
  40         int i = 0;
  41
  42         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
  43            the cause yet, but this workaround will mask the problem for now.
  44            Other chips usually will pass at the very first test, so the
  45            workaround shouldn't have any effect on them. */
  46         for (i = 0;
  47              (i < 10000 &&
  48               RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
  49              i++);
  50 }
  51
  52 static void radeon_pll_write_update(struct drm_device *dev)
  53 {
  54         struct drm_radeon_private *dev_priv = dev->dev_private;
  55
  56         while (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
  57
  58         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
  59                            RADEON_PPLL_ATOMIC_UPDATE_W,
  60                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
  61 }
  62
  63 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
  64 {
  65         struct drm_radeon_private *dev_priv = dev->dev_private;
  66         int i = 0;
  67
  68
  69         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
  70            the cause yet, but this workaround will mask the problem for now.
  71            Other chips usually will pass at the very first test, so the
  72            workaround shouldn't have any effect on them. */
  73         for (i = 0;
  74              (i < 10000 &&
  75               RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
  76              i++);
  77 }
  78
  79 static void radeon_pll2_write_update(struct drm_device *dev)
  80 {
  81         struct drm_radeon_private *dev_priv = dev->dev_private;
  82
  83         while (RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
  84
  85         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
  86                            RADEON_P2PLL_ATOMIC_UPDATE_W,
  87                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
  88 }
  89
  90 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
  91                                        uint16_t fb_div)
  92 {
  93         unsigned int vcoFreq;
  94
  95         if (!ref_div)
  96                 return 1;
  97
  98         vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
  99
 100         /*
 101          * This is horribly crude: the VCO frequency range is divided into
 102          * 3 parts, each part having a fixed PLL gain value.
 103          */
 104         if (vcoFreq >= 30000)
 105                 /*
 106                  * [300..max] MHz : 7
 107                  */
 108                 return 7;
 109         else if (vcoFreq >= 18000)
 110                 /*
 111                  * [180..300) MHz : 4
 112                  */
 113                 return 4;
 114         else
 115                 /*
 116                  * [0..180) MHz : 1
 117                  */
 118                 return 1;
 119 }
 120
 121 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 122 {
 123         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 124         struct drm_device *dev = crtc->dev;
 125         struct drm_radeon_private *dev_priv = dev->dev_private;
 126         uint32_t mask;
 127
 128         DRM_DEBUG("\n");
 129
 130         mask = radeon_crtc->crtc_id ?
 131                 (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) :
 132                 (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS);
 133
 134         switch(mode) {
 135         case DRM_MODE_DPMS_ON:
 136                 if (radeon_crtc->crtc_id)
 137                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, 0, ~mask);
 138                 else {
 139                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 140                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 141                 }
 142                 break;
 143         case DRM_MODE_DPMS_STANDBY:
 144                 if (radeon_crtc->crtc_id)
 145                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask);
 146                 else {
 147                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 148                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS), ~mask);
 149                 }
 150                 break;
 151         case DRM_MODE_DPMS_SUSPEND:
 152                 if (radeon_crtc->crtc_id)
 153                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask);
 154                 else {
 155                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 156                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS), ~mask);
 157                 }
 158                 break;
 159         case DRM_MODE_DPMS_OFF:
 160                 if (radeon_crtc->crtc_id)
 161                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
 162                 else {
 163                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~RADEON_CRTC_DISP_REQ_EN_B);
 164                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 165                 }
 166                 break;
 167         }
 168
 169         if (mode != DRM_MODE_DPMS_OFF) {
 170                 radeon_crtc_load_lut(crtc);
 171         }
 172 }
 173
 174 static bool radeon_set_crtc1_base(struct drm_crtc *crtc, int x, int y)
 175 {
 176         struct drm_device *dev = crtc->dev;
 177         struct drm_radeon_private *dev_priv = dev->dev_private;
 178         struct radeon_framebuffer *radeon_fb;
 179         struct drm_radeon_gem_object *obj_priv;
 180         uint32_t base;
 181         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 182         uint32_t crtc_pitch;
 183
 184         DRM_DEBUG("\n");
 185
 186         radeon_fb = to_radeon_framebuffer(crtc->fb);
 187
 188         obj_priv = radeon_fb->obj->driver_private;
 189
 190         crtc_offset = obj_priv->bo->offset;
 191
 192         crtc_offset_cntl = 0;
 193
 194         /* TODO tiling */
 195         if (0) {
 196                 if (radeon_is_r300(dev_priv))
 197                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 198                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 199                                              R300_CRTC_MACRO_TILE_EN);
 200                 else
 201                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 202         } else {
 203                 if (radeon_is_r300(dev_priv))
 204                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 205                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 206                                               R300_CRTC_MACRO_TILE_EN);
 207                 else
 208                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 209         }
 210
 211         base = obj_priv->bo->offset;
 212
 213         /* TODO more tiling */
 214         if (0) {
 215                 if (radeon_is_r300(dev_priv)) {
 216                         crtc_tile_x0_y0 = x | (y << 16);
 217                         base &= ~0x7ff;
 218                 } else {
 219                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 220                         int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
 221                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 222                         crtc_offset_cntl |= (y % 16);
 223                 }
 224         } else {
 225                 int offset = y * crtc->fb->pitch + x;
 226                 switch (crtc->fb->bits_per_pixel) {
 227                 case 15:
 228                 case 16:
 229                         offset *= 2;
 230                         break;
 231                 case 24:
 232                         offset *= 3;
 233                         break;
 234                 case 32:
 235                         offset *= 4;
 236                         break;
 237                 default:
 238                         return false;
 239                 }
 240                 base += offset;
 241         }
 242
 243         base &= ~7;
 244
 245         /* update sarea TODO */
 246
 247         crtc_offset = base;
 248
 249         crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
 250                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 251                        (crtc->fb->bits_per_pixel * 8));
 252         crtc_pitch |= crtc_pitch << 16;
 253
 254         DRM_DEBUG("mc_fb_location: 0x%x\n", dev_priv->fb_location);
 255
 256         RADEON_WRITE(RADEON_DISPLAY_BASE_ADDR, dev_priv->fb_location);
 257
 258         if (radeon_is_r300(dev_priv))
 259                 RADEON_WRITE(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 260         RADEON_WRITE(RADEON_CRTC_OFFSET_CNTL, crtc_offset_cntl);
 261         RADEON_WRITE(RADEON_CRTC_OFFSET, crtc_offset);
 262         RADEON_WRITE(RADEON_CRTC_PITCH, crtc_pitch);
 263
 264         return true;
 265 }
 266
 267 static bool radeon_set_crtc1_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 268 {
 269         struct drm_device *dev = crtc->dev;
 270         struct drm_radeon_private *dev_priv = dev->dev_private;
 271         int format;
 272         int hsync_start;
 273         int hsync_wid;
 274         int vsync_wid;
 275         uint32_t crtc_gen_cntl;
 276         uint32_t crtc_ext_cntl;
 277         uint32_t crtc_h_total_disp;
 278         uint32_t crtc_h_sync_strt_wid;
 279         uint32_t crtc_v_total_disp;
 280         uint32_t crtc_v_sync_strt_wid;
 281         uint32_t disp_merge_cntl;
 282
 283         DRM_DEBUG("\n");
 284
 285         switch (crtc->fb->bits_per_pixel) {
 286
 287         case 15:      /*  555 */
 288                 format = 3;
 289                 break;
 290         case 16:      /*  565 */
 291                 format = 4;
 292                 break;
 293         case 24:      /*  RGB */
 294                 format = 5;
 295                 break;
 296         case 32:      /* xRGB */
 297                 format = 6;
 298                 break;
 299         default:
 300                 return false;
 301         }
 302
 303         crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
 304                          | RADEON_CRTC_EN
 305                          | (format << 8)
 306                          | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 307                             ? RADEON_CRTC_DBL_SCAN_EN
 308                             : 0)
 309                          | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 310                             ? RADEON_CRTC_CSYNC_EN
 311                             : 0)
 312                          | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 313                             ? RADEON_CRTC_INTERLACE_EN
 314                             : 0));
 315
 316         crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 317         crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 318                           RADEON_CRTC_VSYNC_DIS |
 319                           RADEON_CRTC_HSYNC_DIS |
 320                           RADEON_CRTC_DISPLAY_DIS);
 321
 322         disp_merge_cntl = RADEON_READ(RADEON_DISP_MERGE_CNTL);
 323         disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 324
 325         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 326                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 327
 328         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 329         if (!hsync_wid)
 330                 hsync_wid = 1;
 331         hsync_start = mode->crtc_hsync_start - 8;
 332
 333         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 334                                 | ((hsync_wid & 0x3f) << 16)
 335                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 336                                    ? RADEON_CRTC_H_SYNC_POL
 337                                    : 0));
 338
 339         /* This works for double scan mode. */
 340         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 341                              | ((mode->crtc_vdisplay - 1) << 16));
 342
 343         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 344         if (!vsync_wid)
 345                 vsync_wid = 1;
 346
 347         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 348                                 | ((vsync_wid & 0x1f) << 16)
 349                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 350                                    ? RADEON_CRTC_V_SYNC_POL
 351                                    : 0));
 352
 353         /* TODO -> Dell Server */
 354         if (0) {
 355                 uint32_t disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
 356                 uint32_t tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
 357                 uint32_t dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2);
 358                 uint32_t crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
 359
 360                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
 361                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 362
 363                 /* For CRT on DAC2, don't turn it on if BIOS didn't
 364                    enable it, even it's detected.
 365                 */
 366                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 367                 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
 368                 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 369
 370                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 371                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 372                 RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 373                 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 374         }
 375
 376         RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl |
 377                      RADEON_CRTC_DISP_REQ_EN_B);
 378
 379         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl,
 380                        RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_DISPLAY_DIS);
 381
 382         RADEON_WRITE(RADEON_CRTC_H_TOTAL_DISP, crtc_h_total_disp);
 383         RADEON_WRITE(RADEON_CRTC_H_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 384         RADEON_WRITE(RADEON_CRTC_V_TOTAL_DISP, crtc_v_total_disp);
 385         RADEON_WRITE(RADEON_CRTC_V_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 386
 387         RADEON_WRITE(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 388
 389         RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 390
 391         return true;
 392 }
 393
 394 static void radeon_set_pll1(struct drm_crtc *crtc, struct drm_display_mode *mode)
 395 {
 396         struct drm_device *dev = crtc->dev;
 397         struct drm_radeon_private *dev_priv = dev->dev_private;
 398         struct drm_encoder *encoder;
 399         uint32_t feedback_div = 0;
 400         uint32_t reference_div = 0;
 401         uint32_t post_divider = 0;
 402         uint32_t freq = 0;
 403         uint8_t pll_gain;
 404         int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV;
 405         bool use_bios_divs = false;
 406         /* PLL registers */
 407         uint32_t ppll_ref_div = 0;
 408         uint32_t ppll_div_3 = 0;
 409         uint32_t htotal_cntl = 0;
 410         uint32_t vclk_ecp_cntl;
 411
 412         struct radeon_pll *pll = &dev_priv->mode_info.p1pll;
 413
 414         struct {
 415                 int divider;
 416                 int bitvalue;
 417         } *post_div, post_divs[]   = {
 418                 /* From RAGE 128 VR/RAGE 128 GL Register
 419                  * Reference Manual (Technical Reference
 420                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 421                  * 3-17 (PLL_DIV_[3:0]).
 422                  */
 423                 {  1, 0 },              /* VCLK_SRC                 */
 424                 {  2, 1 },              /* VCLK_SRC/2               */
 425                 {  4, 2 },              /* VCLK_SRC/4               */
 426                 {  8, 3 },              /* VCLK_SRC/8               */
 427                 {  3, 4 },              /* VCLK_SRC/3               */
 428                 { 16, 5 },              /* VCLK_SRC/16              */
 429                 {  6, 6 },              /* VCLK_SRC/6               */
 430                 { 12, 7 },              /* VCLK_SRC/12              */
 431                 {  0, 0 }
 432         };
 433
 434         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 435                 if (encoder->crtc == crtc) {
 436                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 437                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 438                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 439                                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 440
 441                                 if (radeon_encoder->use_bios_dividers) {
 442                                         ppll_ref_div = radeon_encoder->panel_ref_divider;
 443                                         ppll_div_3   = (radeon_encoder->panel_fb_divider |
 444                                                         (radeon_encoder->panel_post_divider << 16));
 445                                         htotal_cntl  = 0;
 446                                         use_bios_divs = true;
 447                                 } else
 448                                         pll_flags |= RADEON_PLL_USE_REF_DIV;
 449                         }
 450                 }
 451         }
 452
 453         DRM_DEBUG("\n");
 454
 455         if (!use_bios_divs) {
 456                 radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, pll_flags);
 457
 458                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 459                         if (post_div->divider == post_divider)
 460                                 break;
 461                 }
 462
 463                 if (!post_div->divider) {
 464                         post_div = &post_divs[0];
 465                 }
 466
 467                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 468                           (unsigned)freq,
 469                           feedback_div,
 470                           reference_div,
 471                           post_divider);
 472
 473                 ppll_ref_div   = reference_div;
 474 #if defined(__powerpc__) && (0) /* TODO */
 475                 /* apparently programming this otherwise causes a hang??? */
 476                 if (info->MacModel == RADEON_MAC_IBOOK)
 477                         state->ppll_div_3 = 0x000600ad;
 478                 else
 479 #endif
 480                         ppll_div_3     = (feedback_div | (post_div->bitvalue << 16));
 481                 htotal_cntl    = mode->htotal & 0x7;
 482
 483         }
 484
 485         vclk_ecp_cntl = (RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL) &
 486                          ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
 487
 488         pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.p1pll.reference_freq,
 489                                            ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 490                                            ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);
 491
 492         if (dev_priv->flags & RADEON_IS_MOBILITY) {
 493                 /* A temporal workaround for the occational blanking on certain laptop panels.
 494                    This appears to related to the PLL divider registers (fail to lock?).
 495                    It occurs even when all dividers are the same with their old settings.
 496                    In this case we really don't need to fiddle with PLL registers.
 497                    By doing this we can avoid the blanking problem with some panels.
 498                 */
 499                 if ((ppll_ref_div == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 500                     (ppll_div_3 == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_DIV_3) &
 501                                            (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 502                         RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
 503                                        RADEON_PLL_DIV_SEL,
 504                                        ~(RADEON_PLL_DIV_SEL));
 505                         radeon_pll_errata_after_index(dev_priv);
 506                         return;
 507                 }
 508         }
 509
 510         RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
 511                            RADEON_VCLK_SRC_SEL_CPUCLK,
 512                            ~(RADEON_VCLK_SRC_SEL_MASK));
 513         RADEON_WRITE_PLL_P(dev_priv,
 514                            RADEON_PPLL_CNTL,
 515                            RADEON_PPLL_RESET
 516                            | RADEON_PPLL_ATOMIC_UPDATE_EN
 517                            | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 518                            | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 519                            ~(RADEON_PPLL_RESET
 520                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 521                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 522                              | RADEON_PPLL_PVG_MASK));
 523
 524         RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
 525                        RADEON_PLL_DIV_SEL,
 526                        ~(RADEON_PLL_DIV_SEL));
 527         radeon_pll_errata_after_index(dev_priv);
 528
 529         if (radeon_is_r300(dev_priv) ||
 530             (dev_priv->chip_family == CHIP_RS300) ||
 531             (dev_priv->chip_family == CHIP_RS400) ||
 532             (dev_priv->chip_family == CHIP_RS480)) {
 533                 if (ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 534                         /* When restoring console mode, use saved PPLL_REF_DIV
 535                          * setting.
 536                          */
 537                         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 538                                            ppll_ref_div,
 539                                            0);
 540                 } else {
 541                         /* R300 uses ref_div_acc field as real ref divider */
 542                         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 543                                            (ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 544                                            ~R300_PPLL_REF_DIV_ACC_MASK);
 545                 }
 546         } else {
 547                 RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 548                                    ppll_ref_div,
 549                                    ~RADEON_PPLL_REF_DIV_MASK);
 550         }
 551
 552         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
 553                            ppll_div_3,
 554                            ~RADEON_PPLL_FB3_DIV_MASK);
 555
 556         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
 557                            ppll_div_3,
 558                            ~RADEON_PPLL_POST3_DIV_MASK);
 559
 560         radeon_pll_write_update(dev);
 561         radeon_pll_wait_for_read_update_complete(dev);
 562
 563         RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL_CNTL, htotal_cntl);
 564
 565         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_CNTL,
 566                            0,
 567                            ~(RADEON_PPLL_RESET
 568                              | RADEON_PPLL_SLEEP
 569                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 570                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 571
 572         DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 573                   ppll_ref_div,
 574                   ppll_div_3,
 575                   (unsigned)htotal_cntl,
 576                   RADEON_READ_PLL(dev_priv, RADEON_PPLL_CNTL));
 577         DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
 578                   ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 579                   ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
 580                   (ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 581
 582         mdelay(50); /* Let the clock to lock */
 583
 584         RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
 585                            RADEON_VCLK_SRC_SEL_PPLLCLK,
 586                            ~(RADEON_VCLK_SRC_SEL_MASK));
 587
 588         /*RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);*/
 589
 590 }
 591
 592 static bool radeon_set_crtc2_base(struct drm_crtc *crtc, int x, int y)
 593 {
 594         struct drm_device *dev = crtc->dev;
 595         struct drm_radeon_private *dev_priv = dev->dev_private;
 596         struct radeon_framebuffer *radeon_fb;
 597         struct drm_radeon_gem_object *obj_priv;
 598         uint32_t base;
 599         uint32_t crtc2_offset, crtc2_offset_cntl, crtc2_tile_x0_y0 = 0;
 600         uint32_t crtc2_pitch;
 601
 602         DRM_DEBUG("\n");
 603
 604         radeon_fb = to_radeon_framebuffer(crtc->fb);
 605
 606         obj_priv = radeon_fb->obj->driver_private;
 607
 608         crtc2_offset = obj_priv->bo->offset;
 609
 610         crtc2_offset_cntl = 0;
 611
 612         /* TODO tiling */
 613         if (0) {
 614                 if (radeon_is_r300(dev_priv))
 615                         crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 616                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 617                                               R300_CRTC_MACRO_TILE_EN);
 618                 else
 619                         crtc2_offset_cntl |= RADEON_CRTC_TILE_EN;
 620         } else {
 621                 if (radeon_is_r300(dev_priv))
 622                         crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 623                                                R300_CRTC_MICRO_TILE_BUFFER_DIS |
 624                                                R300_CRTC_MACRO_TILE_EN);
 625                 else
 626                         crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 627         }
 628
 629         base = obj_priv->bo->offset;
 630
 631         /* TODO more tiling */
 632         if (0) {
 633                 if (radeon_is_r300(dev_priv)) {
 634                         crtc2_tile_x0_y0 = x | (y << 16);
 635                         base &= ~0x7ff;
 636                 } else {
 637                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 638                         int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
 639                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 640                         crtc2_offset_cntl |= (y % 16);
 641                 }
 642         } else {
 643                 int offset = y * crtc->fb->pitch + x;
 644                 switch (crtc->fb->bits_per_pixel) {
 645                 case 15:
 646                 case 16:
 647                         offset *= 2;
 648                         break;
 649                 case 24:
 650                         offset *= 3;
 651                         break;
 652                 case 32:
 653                         offset *= 4;
 654                         break;
 655                 default:
 656                         return false;
 657                 }
 658                 base += offset;
 659         }
 660
 661         base &= ~7;
 662
 663         /* update sarea TODO */
 664
 665         crtc2_offset = base;
 666
 667         crtc2_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
 668                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 669                        (crtc->fb->bits_per_pixel * 8));
 670         crtc2_pitch |= crtc2_pitch << 16;
 671
 672         RADEON_WRITE(RADEON_DISPLAY2_BASE_ADDR, dev_priv->fb_location);
 673
 674         if (radeon_is_r300(dev_priv))
 675                 RADEON_WRITE(R300_CRTC2_TILE_X0_Y0, crtc2_tile_x0_y0);
 676         RADEON_WRITE(RADEON_CRTC2_OFFSET_CNTL, crtc2_offset_cntl);
 677         RADEON_WRITE(RADEON_CRTC2_OFFSET, crtc2_offset);
 678         RADEON_WRITE(RADEON_CRTC2_PITCH, crtc2_pitch);
 679
 680         return true;
 681 }
 682
 683 static bool radeon_set_crtc2_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 684 {
 685         struct drm_device *dev = crtc->dev;
 686         struct drm_radeon_private *dev_priv = dev->dev_private;
 687         int format;
 688         int hsync_start;
 689         int hsync_wid;
 690         int vsync_wid;
 691         uint32_t crtc2_gen_cntl;
 692         uint32_t crtc2_h_total_disp;
 693         uint32_t crtc2_h_sync_strt_wid;
 694         uint32_t crtc2_v_total_disp;
 695         uint32_t crtc2_v_sync_strt_wid;
 696         uint32_t disp2_merge_cntl;
 697         uint32_t fp_h2_sync_strt_wid;
 698         uint32_t fp_v2_sync_strt_wid;
 699
 700         DRM_DEBUG("\n");
 701
 702         switch (crtc->fb->bits_per_pixel) {
 703
 704         case 15:      /*  555 */
 705                 format = 3;
 706                 break;
 707         case 16:      /*  565 */
 708                 format = 4;
 709                 break;
 710         case 24:      /*  RGB */
 711                 format = 5;
 712                 break;
 713         case 32:      /* xRGB */
 714                 format = 6;
 715                 break;
 716         default:
 717                 return false;
 718         }
 719
 720         crtc2_h_total_disp =
 721                 ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 722                  | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 723
 724         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 725         if (!hsync_wid)
 726                 hsync_wid = 1;
 727         hsync_start = mode->crtc_hsync_start - 8;
 728
 729         crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
 730                                  | ((hsync_wid & 0x3f) << 16)
 731                                  | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 732                                     ? RADEON_CRTC_H_SYNC_POL
 733                                     : 0));
 734
 735         /* This works for double scan mode. */
 736         crtc2_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 737                               | ((mode->crtc_vdisplay - 1) << 16));
 738
 739         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 740         if (!vsync_wid)
 741                 vsync_wid = 1;
 742
 743         crtc2_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 744                                  | ((vsync_wid & 0x1f) << 16)
 745                                  | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 746                                     ? RADEON_CRTC2_V_SYNC_POL
 747                                     : 0));
 748
 749         /* check to see if TV DAC is enabled for another crtc and keep it enabled */
 750         if (RADEON_READ(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
 751                 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
 752         else
 753                 crtc2_gen_cntl = 0;
 754
 755         crtc2_gen_cntl |= (RADEON_CRTC2_EN
 756                            | (format << 8)
 757                            | RADEON_CRTC2_VSYNC_DIS
 758                            | RADEON_CRTC2_HSYNC_DIS
 759                            | RADEON_CRTC2_DISP_DIS
 760                            | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 761                               ? RADEON_CRTC2_DBL_SCAN_EN
 762                               : 0)
 763                            | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 764                               ? RADEON_CRTC2_CSYNC_EN
 765                               : 0)
 766                            | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 767                               ? RADEON_CRTC2_INTERLACE_EN
 768                               : 0));
 769
 770         disp2_merge_cntl = RADEON_READ(RADEON_DISP2_MERGE_CNTL);
 771         disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 772
 773         fp_h2_sync_strt_wid = crtc2_h_sync_strt_wid;
 774         fp_v2_sync_strt_wid = crtc2_v_sync_strt_wid;
 775
 776         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,
 777                      crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
 778                      RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
 779                      RADEON_CRTC2_DISP_REQ_EN_B);
 780
 781         RADEON_WRITE(RADEON_CRTC2_H_TOTAL_DISP,    crtc2_h_total_disp);
 782         RADEON_WRITE(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
 783         RADEON_WRITE(RADEON_CRTC2_V_TOTAL_DISP,    crtc2_v_total_disp);
 784         RADEON_WRITE(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
 785
 786         RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID,   fp_h2_sync_strt_wid);
 787         RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID,   fp_v2_sync_strt_wid);
 788
 789         RADEON_WRITE(RADEON_DISP2_MERGE_CNTL,      disp2_merge_cntl);
 790
 791         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,        crtc2_gen_cntl);
 792
 793         return true;
 794
 795 }
 796
 797 static void radeon_set_pll2(struct drm_crtc *crtc, struct drm_display_mode *mode)
 798 {
 799         struct drm_device *dev = crtc->dev;
 800         struct drm_radeon_private *dev_priv = dev->dev_private;
 801         struct drm_encoder *encoder;
 802         uint32_t feedback_div = 0;
 803         uint32_t reference_div = 0;
 804         uint32_t post_divider = 0;
 805         uint32_t freq = 0;
 806         uint8_t pll_gain;
 807         int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV;
 808         bool use_bios_divs = false;
 809         /* PLL2 registers */
 810         uint32_t p2pll_ref_div = 0;
 811         uint32_t p2pll_div_0 = 0;
 812         uint32_t htotal_cntl2 = 0;
 813         uint32_t pixclks_cntl;
 814
 815         struct radeon_pll *pll = &dev_priv->mode_info.p2pll;
 816
 817         struct {
 818                 int divider;
 819                 int bitvalue;
 820         } *post_div, post_divs[]   = {
 821                 /* From RAGE 128 VR/RAGE 128 GL Register
 822                  * Reference Manual (Technical Reference
 823                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 824                  * 3-17 (PLL_DIV_[3:0]).
 825                  */
 826                 {  1, 0 },              /* VCLK_SRC                 */
 827                 {  2, 1 },              /* VCLK_SRC/2               */
 828                 {  4, 2 },              /* VCLK_SRC/4               */
 829                 {  8, 3 },              /* VCLK_SRC/8               */
 830                 {  3, 4 },              /* VCLK_SRC/3               */
 831                 {  6, 6 },              /* VCLK_SRC/6               */
 832                 { 12, 7 },              /* VCLK_SRC/12              */
 833                 {  0, 0 }
 834         };
 835
 836         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 837                 if (encoder->crtc == crtc) {
 838                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 839                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 840                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 841                                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 842
 843                                 if (radeon_encoder->use_bios_dividers) {
 844                                         p2pll_ref_div = radeon_encoder->panel_ref_divider;
 845                                         p2pll_div_0   = (radeon_encoder->panel_fb_divider |
 846                                                         (radeon_encoder->panel_post_divider << 16));
 847                                         htotal_cntl2  = 0;
 848                                         use_bios_divs = true;
 849                                 } else
 850                                         pll_flags |= RADEON_PLL_USE_REF_DIV;
 851                         }
 852                 }
 853         }
 854
 855         DRM_DEBUG("\n");
 856
 857         if (!use_bios_divs) {
 858                 radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, pll_flags);
 859
 860                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 861                         if (post_div->divider == post_divider)
 862                                 break;
 863                 }
 864
 865                 if (!post_div->divider) {
 866                         post_div = &post_divs[0];
 867                 }
 868
 869                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 870                           (unsigned)freq,
 871                           feedback_div,
 872                           reference_div,
 873                           post_divider);
 874
 875                 p2pll_ref_div    = reference_div;
 876                 p2pll_div_0      = (feedback_div | (post_div->bitvalue << 16));
 877                 htotal_cntl2     = mode->htotal & 0x7;
 878
 879         }
 880
 881         pixclks_cntl     = ((RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL) &
 882                              ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 883                             RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 884
 885         pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.p2pll.reference_freq,
 886                                            p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 887                                            p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);
 888
 889
 890         RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
 891                            RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 892                            ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 893
 894         RADEON_WRITE_PLL_P(dev_priv,
 895                            RADEON_P2PLL_CNTL,
 896                            RADEON_P2PLL_RESET
 897                            | RADEON_P2PLL_ATOMIC_UPDATE_EN
 898                            | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 899                            ~(RADEON_P2PLL_RESET
 900                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 901                              | RADEON_P2PLL_PVG_MASK));
 902
 903
 904         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
 905                            p2pll_ref_div,
 906                            ~RADEON_P2PLL_REF_DIV_MASK);
 907
 908         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
 909                            p2pll_div_0,
 910                            ~RADEON_P2PLL_FB0_DIV_MASK);
 911
 912         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
 913                            p2pll_div_0,
 914                            ~RADEON_P2PLL_POST0_DIV_MASK);
 915
 916         radeon_pll2_write_update(dev);
 917         radeon_pll2_wait_for_read_update_complete(dev);
 918
 919         RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL2_CNTL, htotal_cntl2);
 920
 921         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_CNTL,
 922                            0,
 923                            ~(RADEON_P2PLL_RESET
 924                              | RADEON_P2PLL_SLEEP
 925                              | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 926
 927         DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 928                   (unsigned)p2pll_ref_div,
 929                   (unsigned)p2pll_div_0,
 930                   (unsigned)htotal_cntl2,
 931                   RADEON_READ_PLL(dev_priv, RADEON_P2PLL_CNTL));
 932         DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
 933                   (unsigned)p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 934                   (unsigned)p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
 935                   (unsigned)((p2pll_div_0 &
 936                               RADEON_P2PLL_POST0_DIV_MASK) >>16));
 937
 938         mdelay(50); /* Let the clock to lock */
 939
 940         RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
 941                            RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 942                            ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 943
 944         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
 945
 946 }
 947
 948 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
 949                                    struct drm_display_mode *mode,
 950                                    struct drm_display_mode *adjusted_mode)
 951 {
 952         return true;
 953 }
 954
 955 void radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y)
 956 {
 957         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 958
 959         switch(radeon_crtc->crtc_id) {
 960         case 0:
 961                 radeon_set_crtc1_base(crtc, x, y);
 962                 break;
 963         case 1:
 964                 radeon_set_crtc2_base(crtc, x, y);
 965                 break;
 966
 967         }
 968 }
 969
 970 static void radeon_crtc_mode_set(struct drm_crtc *crtc,
 971                                  struct drm_display_mode *mode,
 972                                  struct drm_display_mode *adjusted_mode,
 973                                  int x, int y)
 974 {
 975         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 976
 977         DRM_DEBUG("\n");
 978
 979         /* TODO TV */
 980
 981         radeon_crtc_set_base(crtc, x, y);
 982
 983         switch(radeon_crtc->crtc_id) {
 984         case 0:
 985                 radeon_set_crtc1_timing(crtc, adjusted_mode);
 986                 radeon_set_pll1(crtc, adjusted_mode);
 987                 break;
 988         case 1:
 989                 radeon_set_crtc2_timing(crtc, adjusted_mode);
 990                 radeon_set_pll2(crtc, adjusted_mode);
 991                 break;
 992
 993         }
 994 }
 995
 996 static void radeon_crtc_prepare(struct drm_crtc *crtc)
 997 {
 998         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 999 }
1000
1001 static void radeon_crtc_commit(struct drm_crtc *crtc)
1002 {
1003         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1004 }
1005
1006 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1007         .dpms = radeon_crtc_dpms,
1008         .mode_fixup = radeon_crtc_mode_fixup,
1009         .mode_set = radeon_crtc_mode_set,
1010         .mode_set_base = radeon_crtc_set_base,
1011         .prepare = radeon_crtc_prepare,
1012         .commit = radeon_crtc_commit,
1013 };
1014
1015
1016 void radeon_legacy_init_crtc(struct drm_device *dev,
1017                                struct radeon_crtc *radeon_crtc)
1018 {
1019         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1020 }