linux-core/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #include "drm_crtc_helper.h"
  31
  32 void radeon_restore_common_regs(struct drm_device *dev)
  33 {
  34         /* don't need this yet */
  35 }
  36
  37 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
  38 {
  39         struct drm_radeon_private *dev_priv = dev->dev_private;
  40         int i = 0;
  41
  42         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
  43            the cause yet, but this workaround will mask the problem for now.
  44            Other chips usually will pass at the very first test, so the
  45            workaround shouldn't have any effect on them. */
  46         for (i = 0;
  47              (i < 10000 &&
  48               RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
  49              i++);
  50 }
  51
  52 static void radeon_pll_write_update(struct drm_device *dev)
  53 {
  54         struct drm_radeon_private *dev_priv = dev->dev_private;
  55
  56         while (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
  57
  58         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
  59                            RADEON_PPLL_ATOMIC_UPDATE_W,
  60                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
  61 }
  62
  63 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
  64 {
  65         struct drm_radeon_private *dev_priv = dev->dev_private;
  66         int i = 0;
  67
  68
  69         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
  70            the cause yet, but this workaround will mask the problem for now.
  71            Other chips usually will pass at the very first test, so the
  72            workaround shouldn't have any effect on them. */
  73         for (i = 0;
  74              (i < 10000 &&
  75               RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
  76              i++);
  77 }
  78
  79 static void radeon_pll2_write_update(struct drm_device *dev)
  80 {
  81         struct drm_radeon_private *dev_priv = dev->dev_private;
  82
  83         while (RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
  84
  85         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
  86                            RADEON_P2PLL_ATOMIC_UPDATE_W,
  87                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
  88 }
  89
  90 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
  91                                        uint16_t fb_div)
  92 {
  93         unsigned int vcoFreq;
  94
  95         if (!ref_div)
  96                 return 1;
  97
  98         vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
  99
 100         /*
 101          * This is horribly crude: the VCO frequency range is divided into
 102          * 3 parts, each part having a fixed PLL gain value.
 103          */
 104         if (vcoFreq >= 30000)
 105                 /*
 106                  * [300..max] MHz : 7
 107                  */
 108                 return 7;
 109         else if (vcoFreq >= 18000)
 110                 /*
 111                  * [180..300) MHz : 4
 112                  */
 113                 return 4;
 114         else
 115                 /*
 116                  * [0..180) MHz : 1
 117                  */
 118                 return 1;
 119 }
 120
 121 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 122 {
 123         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 124         struct drm_device *dev = crtc->dev;
 125         struct drm_radeon_private *dev_priv = dev->dev_private;
 126         uint32_t mask;
 127
 128         DRM_DEBUG("\n");
 129
 130         mask = radeon_crtc->crtc_id ?
 131                 (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) :
 132                 (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS);
 133
 134         switch(mode) {
 135         case DRM_MODE_DPMS_ON:
 136                 if (radeon_crtc->crtc_id)
 137                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, 0, ~mask);
 138                 else {
 139                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 140                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 141                 }
 142                 break;
 143         case DRM_MODE_DPMS_STANDBY:
 144                 if (radeon_crtc->crtc_id)
 145                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask);
 146                 else {
 147                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 148                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS), ~mask);
 149                 }
 150                 break;
 151         case DRM_MODE_DPMS_SUSPEND:
 152                 if (radeon_crtc->crtc_id)
 153                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask);
 154                 else {
 155                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 156                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS), ~mask);
 157                 }
 158                 break;
 159         case DRM_MODE_DPMS_OFF:
 160                 if (radeon_crtc->crtc_id)
 161                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
 162                 else {
 163                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~RADEON_CRTC_DISP_REQ_EN_B);
 164                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 165                 }
 166                 break;
 167         }
 168
 169         if (mode != DRM_MODE_DPMS_OFF) {
 170                 radeon_crtc_load_lut(crtc);
 171         }
 172 }
 173
 174 static bool radeon_set_crtc1_base(struct drm_crtc *crtc, int x, int y)
 175 {
 176         struct drm_device *dev = crtc->dev;
 177         struct drm_radeon_private *dev_priv = dev->dev_private;
 178         struct radeon_framebuffer *radeon_fb;
 179         struct drm_radeon_gem_object *obj_priv;
 180         uint32_t base;
 181         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 182         uint32_t crtc_pitch;
 183
 184         DRM_DEBUG("\n");
 185
 186         radeon_fb = to_radeon_framebuffer(crtc->fb);
 187
 188         obj_priv = radeon_fb->obj->driver_private;
 189
 190         crtc_offset = obj_priv->bo->offset;
 191
 192         crtc_offset_cntl = 0;
 193
 194         /* TODO tiling */
 195         if (0) {
 196                 if (radeon_is_r300(dev_priv))
 197                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 198                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 199                                              R300_CRTC_MACRO_TILE_EN);
 200                 else
 201                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 202         } else {
 203                 if (radeon_is_r300(dev_priv))
 204                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 205                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 206                                               R300_CRTC_MACRO_TILE_EN);
 207                 else
 208                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 209         }
 210
 211         base = obj_priv->bo->offset;
 212
 213         /* TODO more tiling */
 214         if (0) {
 215                 if (radeon_is_r300(dev_priv)) {
 216                         crtc_tile_x0_y0 = x | (y << 16);
 217                         base &= ~0x7ff;
 218                 } else {
 219                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 220                         int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
 221                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 222                         crtc_offset_cntl |= (y % 16);
 223                 }
 224         } else {
 225                 int offset = y * crtc->fb->pitch + x;
 226                 switch (crtc->fb->bits_per_pixel) {
 227                 case 15:
 228                 case 16:
 229                         offset *= 2;
 230                         break;
 231                 case 24:
 232                         offset *= 3;
 233                         break;
 234                 case 32:
 235                         offset *= 4;
 236                         break;
 237                 default:
 238                         return false;
 239                 }
 240                 base += offset;
 241         }
 242
 243         base &= ~7;
 244
 245         /* update sarea TODO */
 246
 247         crtc_offset = base;
 248
 249         crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
 250                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 251                        (crtc->fb->bits_per_pixel * 8));
 252         crtc_pitch |= crtc_pitch << 16;
 253
 254         DRM_DEBUG("mc_fb_location: 0x%x\n", dev_priv->fb_location);
 255
 256         RADEON_WRITE(RADEON_DISPLAY_BASE_ADDR, dev_priv->fb_location);
 257
 258         if (radeon_is_r300(dev_priv))
 259                 RADEON_WRITE(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 260         RADEON_WRITE(RADEON_CRTC_OFFSET_CNTL, crtc_offset_cntl);
 261         RADEON_WRITE(RADEON_CRTC_OFFSET, crtc_offset);
 262         RADEON_WRITE(RADEON_CRTC_PITCH, crtc_pitch);
 263
 264         return true;
 265 }
 266
 267 static bool radeon_set_crtc1_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 268 {
 269         struct drm_device *dev = crtc->dev;
 270         struct drm_radeon_private *dev_priv = dev->dev_private;
 271         int format;
 272         int hsync_start;
 273         int hsync_wid;
 274         int vsync_wid;
 275         uint32_t crtc_gen_cntl;
 276         uint32_t crtc_ext_cntl;
 277         uint32_t crtc_h_total_disp;
 278         uint32_t crtc_h_sync_strt_wid;
 279         uint32_t crtc_v_total_disp;
 280         uint32_t crtc_v_sync_strt_wid;
 281         uint32_t disp_merge_cntl;
 282
 283         DRM_DEBUG("\n");
 284
 285         switch (crtc->fb->bits_per_pixel) {
 286
 287         case 15:      /*  555 */
 288                 format = 3;
 289                 break;
 290         case 16:      /*  565 */
 291                 format = 4;
 292                 break;
 293         case 24:      /*  RGB */
 294                 format = 5;
 295                 break;
 296         case 32:      /* xRGB */
 297                 format = 6;
 298                 break;
 299         default:
 300                 return false;
 301         }
 302
 303         crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
 304                          | RADEON_CRTC_EN
 305                          | (format << 8)
 306                          | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 307                             ? RADEON_CRTC_DBL_SCAN_EN
 308                             : 0)
 309                          | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 310                             ? RADEON_CRTC_CSYNC_EN
 311                             : 0)
 312                          | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 313                             ? RADEON_CRTC_INTERLACE_EN
 314                             : 0));
 315
 316         crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 317         crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 318                           RADEON_CRTC_VSYNC_DIS |
 319                           RADEON_CRTC_HSYNC_DIS |
 320                           RADEON_CRTC_DISPLAY_DIS);
 321
 322         disp_merge_cntl = RADEON_READ(RADEON_DISP_MERGE_CNTL);
 323         disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 324
 325         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 326                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 327
 328         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 329         if (!hsync_wid)
 330                 hsync_wid = 1;
 331         hsync_start = mode->crtc_hsync_start - 8;
 332
 333         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 334                                 | ((hsync_wid & 0x3f) << 16)
 335                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 336                                    ? RADEON_CRTC_H_SYNC_POL
 337                                    : 0));
 338
 339         /* This works for double scan mode. */
 340         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 341                              | ((mode->crtc_vdisplay - 1) << 16));
 342
 343         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 344         if (!vsync_wid)
 345                 vsync_wid = 1;
 346
 347         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 348                                 | ((vsync_wid & 0x1f) << 16)
 349                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 350                                    ? RADEON_CRTC_V_SYNC_POL
 351                                    : 0));
 352
 353         /* TODO -> Dell Server */
 354         if (0) {
 355                 uint32_t disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
 356                 uint32_t tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
 357                 uint32_t dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2);
 358                 uint32_t crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
 359
 360                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
 361                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 362
 363                 /* For CRT on DAC2, don't turn it on if BIOS didn't
 364                    enable it, even it's detected.
 365                 */
 366                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 367                 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
 368                 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 369
 370                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 371                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 372                 RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 373                 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 374         }
 375
 376         RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl |
 377                      RADEON_CRTC_DISP_REQ_EN_B);
 378
 379         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl,
 380                        RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_DISPLAY_DIS);
 381
 382         RADEON_WRITE(RADEON_CRTC_H_TOTAL_DISP, crtc_h_total_disp);
 383         RADEON_WRITE(RADEON_CRTC_H_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 384         RADEON_WRITE(RADEON_CRTC_V_TOTAL_DISP, crtc_v_total_disp);
 385         RADEON_WRITE(RADEON_CRTC_V_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 386
 387         RADEON_WRITE(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 388
 389         RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 390
 391         return true;
 392 }
 393
 394 static void radeon_set_pll1(struct drm_crtc *crtc, struct drm_display_mode *mode)
 395 {
 396         struct drm_device *dev = crtc->dev;
 397         struct drm_radeon_private *dev_priv = dev->dev_private;
 398         struct drm_encoder *encoder;
 399         uint32_t feedback_div = 0;
 400         uint32_t reference_div = 0;
 401         uint32_t post_divider = 0;
 402         uint32_t freq = 0;
 403         uint8_t pll_gain;
 404         int pll_flags = RADEON_PLL_LEGACY;
 405         bool use_bios_divs = false;
 406         /* PLL registers */
 407         uint32_t ppll_ref_div = 0;
 408         uint32_t ppll_div_3 = 0;
 409         uint32_t htotal_cntl = 0;
 410         uint32_t vclk_ecp_cntl;
 411
 412         struct radeon_pll *pll = &dev_priv->mode_info.p1pll;
 413
 414         struct {
 415                 int divider;
 416                 int bitvalue;
 417         } *post_div, post_divs[]   = {
 418                 /* From RAGE 128 VR/RAGE 128 GL Register
 419                  * Reference Manual (Technical Reference
 420                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 421                  * 3-17 (PLL_DIV_[3:0]).
 422                  */
 423                 {  1, 0 },              /* VCLK_SRC                 */
 424                 {  2, 1 },              /* VCLK_SRC/2               */
 425                 {  4, 2 },              /* VCLK_SRC/4               */
 426                 {  8, 3 },              /* VCLK_SRC/8               */
 427                 {  3, 4 },              /* VCLK_SRC/3               */
 428                 { 16, 5 },              /* VCLK_SRC/16              */
 429                 {  6, 6 },              /* VCLK_SRC/6               */
 430                 { 12, 7 },              /* VCLK_SRC/12              */
 431                 {  0, 0 }
 432         };
 433
 434         if (mode->clock > 120000) /* range limits??? */
 435                 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 436         else
 437                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 438
 439         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 440                 if (encoder->crtc == crtc) {
 441                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 442                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 443                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 444                                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 445
 446                                 if (radeon_encoder->use_bios_dividers) {
 447                                         ppll_ref_div = radeon_encoder->panel_ref_divider;
 448                                         ppll_div_3   = (radeon_encoder->panel_fb_divider |
 449                                                         (radeon_encoder->panel_post_divider << 16));
 450                                         htotal_cntl  = 0;
 451                                         use_bios_divs = true;
 452                                 } else
 453                                         pll_flags |= RADEON_PLL_USE_REF_DIV;
 454                         }
 455                 }
 456         }
 457
 458         DRM_DEBUG("\n");
 459
 460         if (!use_bios_divs) {
 461                 radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, pll_flags);
 462
 463                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 464                         if (post_div->divider == post_divider)
 465                                 break;
 466                 }
 467
 468                 if (!post_div->divider) {
 469                         post_div = &post_divs[0];
 470                 }
 471
 472                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 473                           (unsigned)freq,
 474                           feedback_div,
 475                           reference_div,
 476                           post_divider);
 477
 478                 ppll_ref_div   = reference_div;
 479 #if defined(__powerpc__) && (0) /* TODO */
 480                 /* apparently programming this otherwise causes a hang??? */
 481                 if (info->MacModel == RADEON_MAC_IBOOK)
 482                         state->ppll_div_3 = 0x000600ad;
 483                 else
 484 #endif
 485                         ppll_div_3     = (feedback_div | (post_div->bitvalue << 16));
 486                 htotal_cntl    = mode->htotal & 0x7;
 487
 488         }
 489
 490         vclk_ecp_cntl = (RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL) &
 491                          ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
 492
 493         pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.p1pll.reference_freq,
 494                                            ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 495                                            ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);
 496
 497         if (dev_priv->flags & RADEON_IS_MOBILITY) {
 498                 /* A temporal workaround for the occational blanking on certain laptop panels.
 499                    This appears to related to the PLL divider registers (fail to lock?).
 500                    It occurs even when all dividers are the same with their old settings.
 501                    In this case we really don't need to fiddle with PLL registers.
 502                    By doing this we can avoid the blanking problem with some panels.
 503                 */
 504                 if ((ppll_ref_div == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 505                     (ppll_div_3 == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_DIV_3) &
 506                                            (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 507                         RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
 508                                        RADEON_PLL_DIV_SEL,
 509                                        ~(RADEON_PLL_DIV_SEL));
 510                         radeon_pll_errata_after_index(dev_priv);
 511                         return;
 512                 }
 513         }
 514
 515         RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
 516                            RADEON_VCLK_SRC_SEL_CPUCLK,
 517                            ~(RADEON_VCLK_SRC_SEL_MASK));
 518         RADEON_WRITE_PLL_P(dev_priv,
 519                            RADEON_PPLL_CNTL,
 520                            RADEON_PPLL_RESET
 521                            | RADEON_PPLL_ATOMIC_UPDATE_EN
 522                            | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 523                            | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 524                            ~(RADEON_PPLL_RESET
 525                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 526                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 527                              | RADEON_PPLL_PVG_MASK));
 528
 529         RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
 530                        RADEON_PLL_DIV_SEL,
 531                        ~(RADEON_PLL_DIV_SEL));
 532         radeon_pll_errata_after_index(dev_priv);
 533
 534         if (radeon_is_r300(dev_priv) ||
 535             (dev_priv->chip_family == CHIP_RS300) ||
 536             (dev_priv->chip_family == CHIP_RS400) ||
 537             (dev_priv->chip_family == CHIP_RS480)) {
 538                 if (ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 539                         /* When restoring console mode, use saved PPLL_REF_DIV
 540                          * setting.
 541                          */
 542                         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 543                                            ppll_ref_div,
 544                                            0);
 545                 } else {
 546                         /* R300 uses ref_div_acc field as real ref divider */
 547                         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 548                                            (ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 549                                            ~R300_PPLL_REF_DIV_ACC_MASK);
 550                 }
 551         } else {
 552                 RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 553                                    ppll_ref_div,
 554                                    ~RADEON_PPLL_REF_DIV_MASK);
 555         }
 556
 557         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
 558                            ppll_div_3,
 559                            ~RADEON_PPLL_FB3_DIV_MASK);
 560
 561         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
 562                            ppll_div_3,
 563                            ~RADEON_PPLL_POST3_DIV_MASK);
 564
 565         radeon_pll_write_update(dev);
 566         radeon_pll_wait_for_read_update_complete(dev);
 567
 568         RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL_CNTL, htotal_cntl);
 569
 570         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_CNTL,
 571                            0,
 572                            ~(RADEON_PPLL_RESET
 573                              | RADEON_PPLL_SLEEP
 574                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 575                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 576
 577         DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 578                   ppll_ref_div,
 579                   ppll_div_3,
 580                   (unsigned)htotal_cntl,
 581                   RADEON_READ_PLL(dev_priv, RADEON_PPLL_CNTL));
 582         DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
 583                   ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 584                   ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
 585                   (ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 586
 587         mdelay(50); /* Let the clock to lock */
 588
 589         RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
 590                            RADEON_VCLK_SRC_SEL_PPLLCLK,
 591                            ~(RADEON_VCLK_SRC_SEL_MASK));
 592
 593         /*RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);*/
 594
 595 }
 596
 597 static bool radeon_set_crtc2_base(struct drm_crtc *crtc, int x, int y)
 598 {
 599         struct drm_device *dev = crtc->dev;
 600         struct drm_radeon_private *dev_priv = dev->dev_private;
 601         struct radeon_framebuffer *radeon_fb;
 602         struct drm_radeon_gem_object *obj_priv;
 603         uint32_t base;
 604         uint32_t crtc2_offset, crtc2_offset_cntl, crtc2_tile_x0_y0 = 0;
 605         uint32_t crtc2_pitch;
 606
 607         DRM_DEBUG("\n");
 608
 609         radeon_fb = to_radeon_framebuffer(crtc->fb);
 610
 611         obj_priv = radeon_fb->obj->driver_private;
 612
 613         crtc2_offset = obj_priv->bo->offset;
 614
 615         crtc2_offset_cntl = 0;
 616
 617         /* TODO tiling */
 618         if (0) {
 619                 if (radeon_is_r300(dev_priv))
 620                         crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 621                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 622                                               R300_CRTC_MACRO_TILE_EN);
 623                 else
 624                         crtc2_offset_cntl |= RADEON_CRTC_TILE_EN;
 625         } else {
 626                 if (radeon_is_r300(dev_priv))
 627                         crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 628                                                R300_CRTC_MICRO_TILE_BUFFER_DIS |
 629                                                R300_CRTC_MACRO_TILE_EN);
 630                 else
 631                         crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 632         }
 633
 634         base = obj_priv->bo->offset;
 635
 636         /* TODO more tiling */
 637         if (0) {
 638                 if (radeon_is_r300(dev_priv)) {
 639                         crtc2_tile_x0_y0 = x | (y << 16);
 640                         base &= ~0x7ff;
 641                 } else {
 642                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 643                         int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
 644                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 645                         crtc2_offset_cntl |= (y % 16);
 646                 }
 647         } else {
 648                 int offset = y * crtc->fb->pitch + x;
 649                 switch (crtc->fb->bits_per_pixel) {
 650                 case 15:
 651                 case 16:
 652                         offset *= 2;
 653                         break;
 654                 case 24:
 655                         offset *= 3;
 656                         break;
 657                 case 32:
 658                         offset *= 4;
 659                         break;
 660                 default:
 661                         return false;
 662                 }
 663                 base += offset;
 664         }
 665
 666         base &= ~7;
 667
 668         /* update sarea TODO */
 669
 670         crtc2_offset = base;
 671
 672         crtc2_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
 673                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 674                        (crtc->fb->bits_per_pixel * 8));
 675         crtc2_pitch |= crtc2_pitch << 16;
 676
 677         RADEON_WRITE(RADEON_DISPLAY2_BASE_ADDR, dev_priv->fb_location);
 678
 679         if (radeon_is_r300(dev_priv))
 680                 RADEON_WRITE(R300_CRTC2_TILE_X0_Y0, crtc2_tile_x0_y0);
 681         RADEON_WRITE(RADEON_CRTC2_OFFSET_CNTL, crtc2_offset_cntl);
 682         RADEON_WRITE(RADEON_CRTC2_OFFSET, crtc2_offset);
 683         RADEON_WRITE(RADEON_CRTC2_PITCH, crtc2_pitch);
 684
 685         return true;
 686 }
 687
 688 static bool radeon_set_crtc2_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_radeon_private *dev_priv = dev->dev_private;
 692         int format;
 693         int hsync_start;
 694         int hsync_wid;
 695         int vsync_wid;
 696         uint32_t crtc2_gen_cntl;
 697         uint32_t crtc2_h_total_disp;
 698         uint32_t crtc2_h_sync_strt_wid;
 699         uint32_t crtc2_v_total_disp;
 700         uint32_t crtc2_v_sync_strt_wid;
 701         uint32_t disp2_merge_cntl;
 702         uint32_t fp_h2_sync_strt_wid;
 703         uint32_t fp_v2_sync_strt_wid;
 704
 705         DRM_DEBUG("\n");
 706
 707         switch (crtc->fb->bits_per_pixel) {
 708
 709         case 15:      /*  555 */
 710                 format = 3;
 711                 break;
 712         case 16:      /*  565 */
 713                 format = 4;
 714                 break;
 715         case 24:      /*  RGB */
 716                 format = 5;
 717                 break;
 718         case 32:      /* xRGB */
 719                 format = 6;
 720                 break;
 721         default:
 722                 return false;
 723         }
 724
 725         crtc2_h_total_disp =
 726                 ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 727                  | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 728
 729         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 730         if (!hsync_wid)
 731                 hsync_wid = 1;
 732         hsync_start = mode->crtc_hsync_start - 8;
 733
 734         crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
 735                                  | ((hsync_wid & 0x3f) << 16)
 736                                  | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 737                                     ? RADEON_CRTC_H_SYNC_POL
 738                                     : 0));
 739
 740         /* This works for double scan mode. */
 741         crtc2_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 742                               | ((mode->crtc_vdisplay - 1) << 16));
 743
 744         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 745         if (!vsync_wid)
 746                 vsync_wid = 1;
 747
 748         crtc2_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 749                                  | ((vsync_wid & 0x1f) << 16)
 750                                  | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 751                                     ? RADEON_CRTC2_V_SYNC_POL
 752                                     : 0));
 753
 754         /* check to see if TV DAC is enabled for another crtc and keep it enabled */
 755         if (RADEON_READ(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
 756                 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
 757         else
 758                 crtc2_gen_cntl = 0;
 759
 760         crtc2_gen_cntl |= (RADEON_CRTC2_EN
 761                            | (format << 8)
 762                            | RADEON_CRTC2_VSYNC_DIS
 763                            | RADEON_CRTC2_HSYNC_DIS
 764                            | RADEON_CRTC2_DISP_DIS
 765                            | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 766                               ? RADEON_CRTC2_DBL_SCAN_EN
 767                               : 0)
 768                            | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 769                               ? RADEON_CRTC2_CSYNC_EN
 770                               : 0)
 771                            | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 772                               ? RADEON_CRTC2_INTERLACE_EN
 773                               : 0));
 774
 775         disp2_merge_cntl = RADEON_READ(RADEON_DISP2_MERGE_CNTL);
 776         disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 777
 778         fp_h2_sync_strt_wid = crtc2_h_sync_strt_wid;
 779         fp_v2_sync_strt_wid = crtc2_v_sync_strt_wid;
 780
 781         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,
 782                      crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
 783                      RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
 784                      RADEON_CRTC2_DISP_REQ_EN_B);
 785
 786         RADEON_WRITE(RADEON_CRTC2_H_TOTAL_DISP,    crtc2_h_total_disp);
 787         RADEON_WRITE(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
 788         RADEON_WRITE(RADEON_CRTC2_V_TOTAL_DISP,    crtc2_v_total_disp);
 789         RADEON_WRITE(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
 790
 791         RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID,   fp_h2_sync_strt_wid);
 792         RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID,   fp_v2_sync_strt_wid);
 793
 794         RADEON_WRITE(RADEON_DISP2_MERGE_CNTL,      disp2_merge_cntl);
 795
 796         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,        crtc2_gen_cntl);
 797
 798         return true;
 799
 800 }
 801
 802 static void radeon_set_pll2(struct drm_crtc *crtc, struct drm_display_mode *mode)
 803 {
 804         struct drm_device *dev = crtc->dev;
 805         struct drm_radeon_private *dev_priv = dev->dev_private;
 806         struct drm_encoder *encoder;
 807         uint32_t feedback_div = 0;
 808         uint32_t reference_div = 0;
 809         uint32_t post_divider = 0;
 810         uint32_t freq = 0;
 811         uint8_t pll_gain;
 812         int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV;
 813         bool use_bios_divs = false;
 814         /* PLL2 registers */
 815         uint32_t p2pll_ref_div = 0;
 816         uint32_t p2pll_div_0 = 0;
 817         uint32_t htotal_cntl2 = 0;
 818         uint32_t pixclks_cntl;
 819
 820         struct radeon_pll *pll = &dev_priv->mode_info.p2pll;
 821
 822         struct {
 823                 int divider;
 824                 int bitvalue;
 825         } *post_div, post_divs[]   = {
 826                 /* From RAGE 128 VR/RAGE 128 GL Register
 827                  * Reference Manual (Technical Reference
 828                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 829                  * 3-17 (PLL_DIV_[3:0]).
 830                  */
 831                 {  1, 0 },              /* VCLK_SRC                 */
 832                 {  2, 1 },              /* VCLK_SRC/2               */
 833                 {  4, 2 },              /* VCLK_SRC/4               */
 834                 {  8, 3 },              /* VCLK_SRC/8               */
 835                 {  3, 4 },              /* VCLK_SRC/3               */
 836                 {  6, 6 },              /* VCLK_SRC/6               */
 837                 { 12, 7 },              /* VCLK_SRC/12              */
 838                 {  0, 0 }
 839         };
 840
 841         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 842                 if (encoder->crtc == crtc) {
 843                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 844                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 845                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 846                                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 847
 848                                 if (radeon_encoder->use_bios_dividers) {
 849                                         p2pll_ref_div = radeon_encoder->panel_ref_divider;
 850                                         p2pll_div_0   = (radeon_encoder->panel_fb_divider |
 851                                                         (radeon_encoder->panel_post_divider << 16));
 852                                         htotal_cntl2  = 0;
 853                                         use_bios_divs = true;
 854                                 } else
 855                                         pll_flags |= RADEON_PLL_USE_REF_DIV;
 856                         }
 857                 }
 858         }
 859
 860         DRM_DEBUG("\n");
 861
 862         if (!use_bios_divs) {
 863                 radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, pll_flags);
 864
 865                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 866                         if (post_div->divider == post_divider)
 867                                 break;
 868                 }
 869
 870                 if (!post_div->divider) {
 871                         post_div = &post_divs[0];
 872                 }
 873
 874                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 875                           (unsigned)freq,
 876                           feedback_div,
 877                           reference_div,
 878                           post_divider);
 879
 880                 p2pll_ref_div    = reference_div;
 881                 p2pll_div_0      = (feedback_div | (post_div->bitvalue << 16));
 882                 htotal_cntl2     = mode->htotal & 0x7;
 883
 884         }
 885
 886         pixclks_cntl     = ((RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL) &
 887                              ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 888                             RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 889
 890         pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.p2pll.reference_freq,
 891                                            p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 892                                            p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);
 893
 894
 895         RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
 896                            RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 897                            ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 898
 899         RADEON_WRITE_PLL_P(dev_priv,
 900                            RADEON_P2PLL_CNTL,
 901                            RADEON_P2PLL_RESET
 902                            | RADEON_P2PLL_ATOMIC_UPDATE_EN
 903                            | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 904                            ~(RADEON_P2PLL_RESET
 905                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 906                              | RADEON_P2PLL_PVG_MASK));
 907
 908
 909         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
 910                            p2pll_ref_div,
 911                            ~RADEON_P2PLL_REF_DIV_MASK);
 912
 913         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
 914                            p2pll_div_0,
 915                            ~RADEON_P2PLL_FB0_DIV_MASK);
 916
 917         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
 918                            p2pll_div_0,
 919                            ~RADEON_P2PLL_POST0_DIV_MASK);
 920
 921         radeon_pll2_write_update(dev);
 922         radeon_pll2_wait_for_read_update_complete(dev);
 923
 924         RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL2_CNTL, htotal_cntl2);
 925
 926         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_CNTL,
 927                            0,
 928                            ~(RADEON_P2PLL_RESET
 929                              | RADEON_P2PLL_SLEEP
 930                              | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 931
 932         DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 933                   (unsigned)p2pll_ref_div,
 934                   (unsigned)p2pll_div_0,
 935                   (unsigned)htotal_cntl2,
 936                   RADEON_READ_PLL(dev_priv, RADEON_P2PLL_CNTL));
 937         DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
 938                   (unsigned)p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 939                   (unsigned)p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
 940                   (unsigned)((p2pll_div_0 &
 941                               RADEON_P2PLL_POST0_DIV_MASK) >>16));
 942
 943         mdelay(50); /* Let the clock to lock */
 944
 945         RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
 946                            RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 947                            ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 948
 949         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
 950
 951 }
 952
 953 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
 954                                    struct drm_display_mode *mode,
 955                                    struct drm_display_mode *adjusted_mode)
 956 {
 957         return true;
 958 }
 959
 960 void radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y)
 961 {
 962         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 963
 964         switch(radeon_crtc->crtc_id) {
 965         case 0:
 966                 radeon_set_crtc1_base(crtc, x, y);
 967                 break;
 968         case 1:
 969                 radeon_set_crtc2_base(crtc, x, y);
 970                 break;
 971
 972         }
 973 }
 974
 975 static void radeon_crtc_mode_set(struct drm_crtc *crtc,
 976                                  struct drm_display_mode *mode,
 977                                  struct drm_display_mode *adjusted_mode,
 978                                  int x, int y)
 979 {
 980         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 981
 982         DRM_DEBUG("\n");
 983
 984         /* TODO TV */
 985
 986         radeon_crtc_set_base(crtc, x, y);
 987
 988         switch(radeon_crtc->crtc_id) {
 989         case 0:
 990                 radeon_set_crtc1_timing(crtc, adjusted_mode);
 991                 radeon_set_pll1(crtc, adjusted_mode);
 992                 break;
 993         case 1:
 994                 radeon_set_crtc2_timing(crtc, adjusted_mode);
 995                 radeon_set_pll2(crtc, adjusted_mode);
 996                 break;
 997
 998         }
 999 }
1000
1001 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1002 {
1003         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1004 }
1005
1006 static void radeon_crtc_commit(struct drm_crtc *crtc)
1007 {
1008         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1009 }
1010
1011 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1012         .dpms = radeon_crtc_dpms,
1013         .mode_fixup = radeon_crtc_mode_fixup,
1014         .mode_set = radeon_crtc_mode_set,
1015         .mode_set_base = radeon_crtc_set_base,
1016         .prepare = radeon_crtc_prepare,
1017         .commit = radeon_crtc_commit,
1018 };
1019
1020
1021 void radeon_legacy_init_crtc(struct drm_device *dev,
1022                                struct radeon_crtc *radeon_crtc)
1023 {
1024         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1025 }